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/openrisc/trunk/rtos/ecos-2.0/packages/hal/mn10300/arch
- from Rev 27 to Rev 174
- ↔ Reverse comparison
Rev 27 → Rev 174
/v2_0/cdl/hal_mn10300.cdl
0,0 → 1,93
# ==================================================================== |
# |
# hal_mn10300.cdl |
# |
# MN10300 architectural HAL package configuration data |
# |
# ==================================================================== |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
# ==================================================================== |
######DESCRIPTIONBEGIN#### |
# |
# Author(s): jskov |
# Original data: bartv, nickg |
# Contributors: dmoseley |
# Date: 1999-11-02 |
# |
#####DESCRIPTIONEND#### |
# |
# ==================================================================== |
|
cdl_package CYGPKG_HAL_MN10300 { |
display "MN10300 architecture" |
parent CYGPKG_HAL |
hardware |
include_dir cyg/hal |
define_header hal_mn10300.h |
description " |
The MN10300 architecture HAL package provides generic |
support for this processor architecture. It is also |
necessary to select a specific target platform HAL |
package." |
|
cdl_interface CYGINT_HAL_MN10300_VARIANT { |
display "Number of variant implementations in this configuration" |
requires 1 == CYGINT_HAL_MN10300_VARIANT |
} |
|
cdl_interface CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP { |
display "Implementations of hal_mn10300_mem_real_region_top()" |
} |
|
cdl_option CYGDBG_HAL_MN10300_DEBUG_GDB_CTRLC_SUPPORT { |
display "Architecture GDB CTRLC support" |
calculated { CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT || CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT } |
active_if { CYGINT_HAL_DEBUG_GDB_CTRLC_UNSUPPORTED == 0 } |
description " |
If either the CTRLC or BREAK support options in hal.h are set |
then set our own option to turn on shared generic support for |
control C handling." |
} |
|
compile hal_misc.c hal_syscall.c context.S mn10300_stub.c |
|
make { |
<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S |
$(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $< |
@echo $@ ": \\" > $(notdir $@).deps |
@tail +2 vectors.tmp >> $(notdir $@).deps |
@echo >> $(notdir $@).deps |
@rm vectors.tmp |
} |
} |
/v2_0/include/mn10300_stub.h
0,0 → 1,145
#ifndef CYGONCE_HAL_MN10300_STUB_H |
#define CYGONCE_HAL_MN10300_STUB_H |
//======================================================================== |
// |
// mn10300_stub.h |
// |
// MN10300-specific definitions for generic stub |
// |
//======================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//======================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): Red Hat, jskov |
// Contributors: Red Hat, jskov, dmoseley |
// Date: 1998-11-06 |
// Purpose: |
// Description: MN10300-specific definitions for generic stub |
// Usage: |
// |
//####DESCRIPTIONEND#### |
// |
//======================================================================== |
|
#ifdef __cplusplus |
extern "C" { |
#endif |
|
#if defined(CYGPKG_HAL_MN10300_AM33) && (CYGHWR_HAL_MN10300_AM33_REVISION == 2) |
#define NUMREGS 64 |
#else |
#define NUMREGS 32 |
#endif |
|
#define REGSIZE( _x_ ) (4) |
|
typedef unsigned long target_register_t; |
|
enum regnames { |
D0, D1, D2, D3, A0, A1, A2, A3, |
SP, PC, MDR, PSW, LIR, LAR |
#ifdef CYGPKG_HAL_MN10300_AM33 |
, MDRQ, |
R0, R1, R2, R3, R4, R5, R6, R7, |
SSP, MSP, USP, MCRH, MCRL, MCVF |
#if CYGHWR_HAL_MN10300_AM33_REVISION == 2 |
// FPU registers for AM33/2.00 |
, FP_START, FPCR=FP_START, |
XXXX1, XXXX2, // unused |
FS0, FS1, FS2, FS3, FS4, FS5, FS6, FS7, |
FS8, FS9, FS10, FS11, FS12, FS13, FS14, FS15, |
FS16, FS17, FS18, FS19, FS20, FS21, FS22, FS23, |
FS24, FS25, FS26, FS27, FS28, FS29, FS30, FS31, FP_END=FS31, |
#endif |
#endif |
}; |
|
typedef enum regnames regnames_t; |
|
/* Given a trap value TRAP, return the corresponding signal. */ |
extern int __computeSignal (unsigned int trap_number); |
|
/* Return the SPARC trap number corresponding to the last-taken trap. */ |
extern int __get_trap_number (void); |
|
/* Return the currently-saved value corresponding to register REG. */ |
extern target_register_t get_register (regnames_t reg); |
|
/* Store VALUE in the register corresponding to WHICH. */ |
extern void put_register (regnames_t which, target_register_t value); |
|
/* Set the currently-saved pc register value to PC. This also updates NPC |
as needed. */ |
#if !defined(SET_PC_PROTOTYPE_EXISTS) && !defined(set_pc) |
#define SET_PC_PROTOTYPE_EXISTS |
extern void set_pc (target_register_t pc); |
#endif |
|
/* Set things up so that the next user resume will execute one instruction. |
This may be done by setting breakpoints or setting a single step flag |
in the saved user registers, for example. */ |
#ifndef __single_step |
void __single_step (void); |
#endif |
|
/* Clear the single-step state. */ |
void __clear_single_step (void); |
|
/* If the breakpoint we hit is in the breakpoint() instruction, return a |
non-zero value. */ |
#ifndef __is_breakpoint_function |
extern int __is_breakpoint_function (void); |
#endif |
|
/* Skip the current instruction. */ |
extern void __skipinst (void); |
|
extern void __install_breakpoints (void); |
|
extern void __clear_breakpoints (void); |
|
extern void __install_breakpoint_list (void); |
|
extern void __clear_breakpoint_list (void); |
|
extern int __is_bsp_syscall(void); |
|
extern int hal_syscall_handler(void); |
|
#ifdef __cplusplus |
} /* extern "C" */ |
#endif |
|
#endif // ifndef CYGONCE_HAL_MN10300_STUB_H |
/v2_0/include/hal_io.h
0,0 → 1,150
#ifndef CYGONCE_HAL_HAL_IO_H |
#define CYGONCE_HAL_HAL_IO_H |
|
//============================================================================= |
// |
// hal_io.h |
// |
// HAL device IO register support. |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, dmoseley |
// Date: 1998-02-17 |
// Purpose: Define IO register support |
// Description: The macros defined here provide the HAL APIs for handling |
// device IO control registers. |
// |
// Usage: |
// #include <cyg/hal/hal_io.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#ifndef __ASSEMBLER__ |
#include <cyg/infra/cyg_type.h> |
#include <cyg/hal/plf_io.h> |
#endif |
|
//----------------------------------------------------------------------------- |
// IO Register address. |
// This type is for recording the address of an IO register. |
|
#ifndef __ASSEMBLER__ |
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER; |
#endif |
|
//----------------------------------------------------------------------------- |
// BYTE Register access. |
// Individual and vectorized access to 8 bit registers. |
|
#define HAL_READ_UINT8( _register_, _value_ ) \ |
((_value_) = *((volatile CYG_BYTE *)(_register_))) |
|
#define HAL_WRITE_UINT8( _register_, _value_ ) \ |
(*((volatile CYG_BYTE *)(_register_)) = (_value_)) |
|
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \ |
} |
|
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \ |
} |
|
|
//----------------------------------------------------------------------------- |
// 16 bit access. |
// Individual and vectorized access to 16 bit registers. |
|
#define HAL_READ_UINT16( _register_, _value_ ) \ |
((_value_) = *((volatile CYG_WORD16 *)(_register_))) |
|
#define HAL_WRITE_UINT16( _register_, _value_ ) \ |
(*((volatile CYG_WORD16 *)(_register_)) = (_value_)) |
|
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \ |
} |
|
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
} |
|
//----------------------------------------------------------------------------- |
// 32 bit access. |
// Individual and vectorized access to 32 bit registers. |
|
#define HAL_READ_UINT32( _register_, _value_ ) \ |
((_value_) = *((volatile CYG_WORD32 *)(_register_))) |
|
#define HAL_WRITE_UINT32( _register_, _value_ ) \ |
(*((volatile CYG_WORD32 *)(_register_)) = (_value_)) |
|
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \ |
} |
|
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \ |
{ \ |
cyg_count32 _i_,_j_; \ |
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \ |
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \ |
} |
|
//----------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_HAL_HAL_IO_H |
// End of hal_io.h |
/v2_0/include/basetype.h
0,0 → 1,81
#ifndef CYGONCE_HAL_BASETYPE_H |
#define CYGONCE_HAL_BASETYPE_H |
|
//============================================================================= |
// |
// basetype.h |
// |
// Standard types for this architecture. |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors:nickg |
// Date: 1997-09-08 |
// Purpose: Define architecture base types. |
// Usage: Included by "cyg_type.h", do not use directly |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
//----------------------------------------------------------------------------- |
// Characterize the architecture |
|
#define CYG_BYTEORDER CYG_LSBFIRST // Little endian |
|
//----------------------------------------------------------------------------- |
// MN10300 usually uses labels with underscores. So when defining a label |
// in asm or linker scripts, we need to add one. |
|
#define CYG_LABEL_DEFN(_name_) _##_name_ |
|
//----------------------------------------------------------------------------- |
// MN10300 only requires four byte alignment |
|
#define CYGARC_ALIGNMENT 4 |
#define CYGARC_P2ALIGNMENT 2 |
|
//----------------------------------------------------------------------------- |
// Define the standard variable sizes |
|
// The MN10300 architecture uses the default definitions of the base types, |
// so we do not need to define any here. |
|
//----------------------------------------------------------------------------- |
#endif // CYGONCE_HAL_BASETYPE_H |
// End of basetype.h |
/v2_0/include/arch.inc
0,0 → 1,201
#ifndef CYGONCE_HAL_ARCH_INC |
#define CYGONCE_HAL_ARCH_INC |
##============================================================================= |
## |
## arch.inc |
## |
## MN10300 assembler header file |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): nickg |
## Contributors: nickg, dmoseley |
## Date: 1997-10-16 |
## Purpose: Architecture definitions. |
## Description: This file contains various definitions and macros that are |
## useful for writing assembly code for the MN10300 CPU family. |
## Usage: |
## #include <cyg/hal/arch.inc> |
## ... |
## |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/hal.h> |
|
#include <cyg/hal/variant.inc> |
|
##----------------------------------------------------------------------------- |
## CPU specific macros. These provide a common assembler interface to |
## operations that may have CPU specific implementations on different |
## variants of the architecture. |
|
#ifndef CYGPKG_HAL_MN10300_CPU_INIT_DEFINED |
# Initialize CPU |
.macro hal_cpu_init |
# Set up the PSW |
mov 0x0700,d0 |
mov d0,psw |
.endm |
#endif |
|
# Enable interrupts |
.macro hal_cpu_int_enable |
or 0x0800,psw |
.endm |
|
# Disable interrupts |
.macro hal_cpu_int_disable |
and 0xF7ff,psw |
.endm |
|
# Merge the interrupt enable state of the status register in |
# \sr with the current sr. |
.macro hal_cpu_int_merge sr |
movm [d3],(sp) |
and 0x00000F00,\sr # isolate IE and IM bits |
hal_cpu_get_psw d3 |
and 0xfffff0ff,d3 |
or \sr,d3 |
hal_cpu_set_psw d3 |
movm (sp),[d3] |
.endm |
|
# Enable further exception processing, and disable |
# interrupt processing. |
.macro hal_cpu_except_enable |
.endm |
|
# Return from exception. |
.macro hal_cpu_eret pc,sr |
.endm |
|
##----------------------------------------------------------------------------- |
# Default interrupt decoding macros. |
|
#ifndef CYGPKG_HAL_MN10300_INTC_DEFINED |
|
#ifndef CYGPKG_HAL_MN10300_INTC_INIT_DEFINED |
# initialize all interrupts to disabled |
.macro hal_intc_init |
.endm |
#endif |
|
#endif |
|
#ifndef CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED |
.macro hal_intc_decode dreg,areg,dreg1 |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
# MMU macros. |
|
#ifndef CYGPKG_HAL_MN10300_MMU_DEFINED |
|
.macro hal_mmu_init |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
# MEMC macros. |
|
#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED |
|
.macro hal_memc_init |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Cache macros. |
|
#ifndef CYGPKG_HAL_MN10300_CACHE_DEFINED |
|
.macro hal_cache_init |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Diagnostics macros. |
|
#ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED |
|
.macro hal_diag_init |
.endm |
|
.macro hal_diag_excpt_start |
.endm |
|
.macro hal_diag_intr_start |
.endm |
|
.macro hal_diag_restore |
.endm |
|
.macro hal_diag_data |
.endm |
#endif |
|
#------------------------------------------------------------------------------ |
# Timer initialization. |
|
#ifndef CYGPKG_HAL_MN10300_TIMER_DEFINED |
|
.macro hal_timer_init |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
# Monitor initialization. |
|
#ifndef CYGPKG_HAL_MN10300_MON_DEFINED |
|
.macro hal_mon_init |
.endm |
|
#endif |
|
#------------------------------------------------------------------------------ |
#endif // ifndef CYGONCE_HAL_ARCH_INC |
# end of arch.inc |
/v2_0/include/hal_intr.h
0,0 → 1,346
#ifndef CYGONCE_HAL_HAL_INTR_H |
#define CYGONCE_HAL_HAL_INTR_H |
//========================================================================== |
// |
// hal_intr.h |
// |
// HAL Interrupt and clock support |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jlarmour |
// Date: 1999-02-18 |
// Purpose: Define Interrupt support |
// Description: The macros defined here provide the HAL APIs for handling |
// interrupts and the clock. |
// Usage: |
// #include <cyg/hal/hal_intr.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> |
#include <cyg/hal/hal_io.h> |
|
#include <cyg/hal/var_intr.h> |
|
//-------------------------------------------------------------------------- |
// Static data used by HAL |
|
// ISR tables |
externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT]; |
externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT]; |
externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT]; |
|
// VSR table |
externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT]; |
|
// MN10300 interrupt control registers, mapped by linker script. |
externC volatile cyg_uint16 mn10300_interrupt_control[]; |
|
//-------------------------------------------------------------------------- |
// Default ISR |
// The #define is used to test whether this routine exists, and to allow |
// us to call it. |
|
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data); |
|
#define HAL_DEFAULT_ISR hal_default_isr |
|
//-------------------------------------------------------------------------- |
// Interrupt state storage |
|
typedef cyg_uint32 CYG_INTERRUPT_STATE; |
|
//-------------------------------------------------------------------------- |
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
|
// Routine to execute DSRs using separate interrupt stack |
externC void hal_interrupt_stack_call_pending_DSRs(void); |
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \ |
hal_interrupt_stack_call_pending_DSRs() |
|
// these are offered solely for stack usage testing |
// if they are not defined, then there is no interrupt stack. |
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base |
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack |
// use them to declare these extern however you want: |
// extern char HAL_INTERRUPT_STACK_BASE[]; |
// extern char HAL_INTERRUPT_STACK_TOP[]; |
// is recommended |
|
#endif |
|
//-------------------------------------------------------------------------- |
// Interrupt control macros |
|
#define HAL_DISABLE_INTERRUPTS(_old_) \ |
asm volatile ( \ |
"mov psw,%0;" \ |
"mov 0xF7FF,d0;" \ |
"and %0,d0;" \ |
"mov d0,psw;" \ |
"and 0x0800,%0;" \ |
: "=d"(_old_) \ |
: \ |
: "d0" \ |
); |
|
#define HAL_ENABLE_INTERRUPTS() \ |
asm volatile ( \ |
"mov psw,d0;" \ |
"or 0x0800,d0;" \ |
"mov d0,psw;" \ |
: \ |
: \ |
: "d0" \ |
); |
|
#define HAL_RESTORE_INTERRUPTS(_old_) \ |
asm volatile ( \ |
"mov psw,d1;" \ |
"and 0xF7FF,d1;" \ |
"or %0,d1;" \ |
"mov d1,psw;" \ |
: \ |
: "d"(_old_) \ |
: "d1" \ |
); |
|
#define HAL_QUERY_INTERRUPTS(_old_) \ |
asm volatile ( \ |
"mov psw,%0;" \ |
"and 0x0800,%0;" \ |
: "=d"(_old_) \ |
); |
|
//-------------------------------------------------------------------------- |
// Translate a vector number into an ISR table index. |
// If we have chained interrupts we have just a single ISR per priority |
// level. On the MN103000 there are several interrupts per controller, |
// so we have to decode to one of 100 vectors. On the MN103002 there is |
// only one interrupt per controller, so we can have just one ISR per |
// controller, except for the NMI vectors which occupy the first 3 slots. |
|
#ifndef HAL_TRANSLATE_VECTOR |
|
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN) |
|
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \ |
{ \ |
if( _vector_ <= CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR ) \ |
(_index_) = (_vector_); \ |
else \ |
{ \ |
/* ICRs are 16 bit regs at 32 bit spacing */ \ |
cyg_ucount16 _ix_ = ((_vector_)>>2)<<1; \ |
\ |
/* read the appropriate interrupt control register */ \ |
cyg_uint16 _icr_ = mn10300_interrupt_control[_ix_]; \ |
\ |
/* extract interrupt priority level */ \ |
_index_ = CYGNUM_HAL_INTERRUPT_RESERVED_3 + ((_icr_ >> 12) & 0x7); \ |
} \ |
} |
|
#else |
|
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_) |
|
#endif |
|
#endif |
|
//-------------------------------------------------------------------------- |
// Interrupt and VSR attachment macros |
|
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \ |
CYG_MACRO_START \ |
cyg_uint32 _index_; \ |
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \ |
\ |
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
(_state_) = 0; \ |
else \ |
(_state_) = 1; \ |
CYG_MACRO_END |
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \ |
CYG_MACRO_START \ |
cyg_uint32 _index_; \ |
HAL_TRANSLATE_VECTOR(_vector_,_index_); \ |
\ |
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \ |
{ \ |
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \ |
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \ |
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \ |
} \ |
CYG_MACRO_END |
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \ |
CYG_MACRO_START \ |
cyg_uint32 _index_; \ |
HAL_TRANSLATE_VECTOR(_vector_,_index_); \ |
\ |
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \ |
{ \ |
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \ |
hal_interrupt_data[_index_] = 0; \ |
hal_interrupt_objects[_index_] = 0; \ |
} \ |
CYG_MACRO_END |
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \ |
*((CYG_ADDRESS *)_pvsr_) = hal_vsr_table[_vector_]; |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \ |
if( _poldvsr_ != NULL ) \ |
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \ |
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; |
|
|
//-------------------------------------------------------------------------- |
// Interrupt controller access |
// Read interrupt control registers back after writing to them. This |
// ensures that the written value is not sitting in the store buffers |
// when interrupts are re-enabled. |
#define HAL_INTERRUPT_MASK( _vector_ ) \ |
{ \ |
/* ICRs are 16 bit regs at 32 bit spacing */ \ |
cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \ |
\ |
/* read the appropriate interrupt control register */ \ |
cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \ |
\ |
/* clear interrupt enable bit for this vector */ \ |
_icr_ &= ~(0x0100<<((_vector_)&3)); \ |
\ |
/* restore the interrupt control register */ \ |
mn10300_interrupt_control[_index_] = _icr_; \ |
_icr_ = mn10300_interrupt_control[_index_]; \ |
} |
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \ |
{ \ |
/* ICRs are 16 bit regs at 32 bit spacing */ \ |
cyg_ucount16 _index_ = (_vector_>>2)<<1; \ |
\ |
/* read the appropriate interrupt control register */ \ |
cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \ |
\ |
/* set interrupt enable bit for this vector */ \ |
_icr_ |= (0x0100<<(_vector_&3)); \ |
\ |
/* restore the interrupt control register */ \ |
mn10300_interrupt_control[_index_] = _icr_; \ |
_icr_ = mn10300_interrupt_control[_index_]; \ |
} |
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \ |
{ \ |
/* ICRs are 16 bit regs at 32 bit spacing */ \ |
cyg_ucount16 _index_ = ((_vector_)>>2)<<1; \ |
\ |
/* read the appropriate interrupt control register */ \ |
cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \ |
\ |
/* clear interrupt request bit for this vector */ \ |
_icr_ &= ~(0x0010<<((_vector_)&3)); \ |
\ |
/* set interrupt detect bit for this vector */ \ |
_icr_ |= (0x0001<<((_vector_)&3)); \ |
\ |
/* restore the interrupt control register */ \ |
mn10300_interrupt_control[_index_] = _icr_; \ |
_icr_ = mn10300_interrupt_control[_index_]; \ |
} |
|
#if !defined(HAL_INTERRUPT_CONFIGURE) |
|
#error HAL_INTERRUPT_CONFIGURE not defined by variant |
|
#endif |
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \ |
{ \ |
/* ICRs are 16 bit regs at 32 bit spacing */ \ |
cyg_ucount16 _index_ = (_vector_>>2)<<1; \ |
\ |
/* read the appropriate interrupt control register */ \ |
cyg_uint16 _icr_ = mn10300_interrupt_control[_index_]; \ |
\ |
/* set interrupt level for this group of vectors */ \ |
_icr_ &= 0x0FFF; \ |
_icr_ |= (_level_)<<12; \ |
\ |
/* restore the interrupt control register */ \ |
mn10300_interrupt_control[_index_] = _icr_; \ |
_icr_ = mn10300_interrupt_control[_index_]; \ |
} |
|
//-------------------------------------------------------------------------- |
// Clock control. |
// This is almost all handled in the var_intr.h. |
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY |
#define HAL_CLOCK_LATENCY(_pvalue_) HAL_CLOCK_READ(_pvalue_) |
#endif |
|
//-------------------------------------------------------------------------- |
// Memory region top |
// |
#if CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP |
|
externC cyg_uint8 *hal_mn10300_mem_real_region_top( cyg_uint8 *_regionend_ ); |
|
# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \ |
hal_mn10300_mem_real_region_top( _regionend_ ) |
#endif |
|
|
//-------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_HAL_HAL_INTR_H |
// EOF hal_intr.h |
/v2_0/include/hal_arch.h
0,0 → 1,370
#ifndef CYGONCE_HAL_HAL_ARCH_H |
#define CYGONCE_HAL_HAL_ARCH_H |
//========================================================================== |
// |
// hal_arch.h |
// |
// Architecture specific abstractions |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, dmoseley |
// Date: 1999-02-18 |
// Purpose: Define architecture abstractions |
// Usage: #include <cyg/hal/hal_arch.h> |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================== |
|
#include <pkgconf/hal.h> |
#include <cyg/infra/cyg_type.h> |
|
#include <cyg/hal/var_arch.h> |
|
//-------------------------------------------------------------------------- |
// Exception handling function. |
// This function is defined by the kernel according to this prototype. It is |
// invoked from the HAL to deal with any CPU exceptions that the HAL does |
// not want to deal with itself. It usually invokes the kernel's exception |
// delivery mechanism. |
|
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data ); |
|
//-------------------------------------------------------------------------- |
// Bit manipulation routines |
|
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask); |
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask); |
|
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask); |
|
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask); |
|
//-------------------------------------------------------------------------- |
// Context Initialization |
// Initialize the context of a thread. |
// Arguments: |
// _sp_ name of variable containing current sp, will be written with new sp |
// _thread_ thread object address, passed as argument to entry point |
// _entry_ entry point address. |
// _id_ bit pattern used in initializing registers, for debugging. |
|
#ifndef HAL_THREAD_INIT_CONTEXT_EXTRA |
#define HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_) |
#endif |
|
#define HAL_THREAD_INIT_CONTEXT( _sp_, _thread_, _entry_, _id_ ) \ |
{ \ |
register HAL_SavedRegisters *_regs_; \ |
_regs_ = (HAL_SavedRegisters *)(((CYG_ADDRWORD)(_sp_)&~15) - \ |
sizeof(HAL_SavedRegisters)*2); \ |
HAL_THREAD_INIT_CONTEXT_EXTRA(_regs_, _id_); \ |
_regs_->d0 = (CYG_WORD)(_thread_); \ |
_regs_->d1 = (_id_)|0xddd1; \ |
_regs_->d2 = (_id_)|0xddd2; \ |
_regs_->d3 = (_id_)|0xddd3; \ |
_regs_->a0 = (_id_)|0xaaa0; \ |
_regs_->a1 = (_id_)|0xaaa1; \ |
_regs_->a2 = (_id_)|0xaaa2; \ |
_regs_->a3 = (_id_)|0xaaa3; \ |
_regs_->mdr = 0; \ |
_regs_->lir = 0; \ |
_regs_->lar = 0; \ |
_regs_->psw = 0x0000F00; \ |
_regs_->pc = (CYG_WORD)(_entry_); \ |
_sp_ = (CYG_ADDRESS)_regs_; \ |
} |
|
//-------------------------------------------------------------------------- |
// Context switch macros. |
// The arguments are pointers to locations where the stack pointer |
// of the current thread is to be stored, and from where the sp of the |
// next thread is to be fetched. |
|
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from ); |
externC void hal_thread_load_context( CYG_ADDRESS to ) |
__attribute__ ((noreturn)); |
|
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \ |
hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \ |
(CYG_ADDRESS)_fspptr_); |
|
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \ |
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ ); |
|
//-------------------------------------------------------------------------- |
// Execution reorder barrier. |
// When optimizing the compiler can reorder code. In multithreaded systems |
// where the order of actions is vital, this can sometimes cause problems. |
// This macro may be inserted into places where reordering should not happen. |
|
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" ) |
|
//-------------------------------------------------------------------------- |
// Breakpoint support |
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to |
// happen if executed. |
// HAL_BREAKINST is the value of the breakpoint instruction and |
// HAL_BREAKINST_SIZE is its size in bytes. |
// HAL_BREAKINST_TYPE is the type. |
|
#define HAL_BREAKPOINT(_label_) \ |
asm volatile (" .globl _" #_label_ ";" \ |
"_"#_label_":" \ |
".byte 0xFF" \ |
); |
|
#define HAL_BREAKINST 0xFF |
|
#define HAL_BREAKINST_SIZE 1 |
|
#define HAL_BREAKINST_TYPE cyg_uint8 |
|
//-------------------------------------------------------------------------- |
// Thread register state manipulation for GDB support. |
|
// Translate a stack pointer as saved by the thread context macros above into |
// a pointer to a HAL_SavedRegisters structure. |
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \ |
(_regs_) = (HAL_SavedRegisters *)(_sp_) |
|
#ifndef HAL_GET_GDB_EXTRA_REGISTERS |
#define HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ) |
#endif |
#ifndef HAL_SET_GDB_EXTRA_REGISTERS |
#define HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ) |
#endif |
|
|
// Copy a set of registers from a HAL_SavedRegisters structure into a |
// GDB ordered array. |
// |
// The CYGMON version should differ by also handling SP and PSW |
// since we will be using a different stack. |
#ifdef CYGPKG_CYGMON |
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ |
{ \ |
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
\ |
_regval_[0] = (_regs_)->d0; \ |
_regval_[1] = (_regs_)->d1; \ |
_regval_[2] = (_regs_)->d2; \ |
_regval_[3] = (_regs_)->d3; \ |
_regval_[4] = (_regs_)->a0; \ |
_regval_[5] = (_regs_)->a1; \ |
_regval_[6] = (_regs_)->a2; \ |
_regval_[7] = (_regs_)->a3; \ |
\ |
_regval_[8] = (_regs_)->sp; \ |
_regval_[9] = (_regs_)->pc; \ |
_regval_[10] = (_regs_)->mdr; \ |
_regval_[11] = (_regs_)->psw; \ |
\ |
_regval_[12] = (_regs_)->lar; \ |
_regval_[13] = (_regs_)->lir; \ |
HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \ |
} |
#else |
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \ |
{ \ |
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
\ |
_regval_[0] = (_regs_)->d0; \ |
_regval_[1] = (_regs_)->d1; \ |
_regval_[2] = (_regs_)->d2; \ |
_regval_[3] = (_regs_)->d3; \ |
_regval_[4] = (_regs_)->a0; \ |
_regval_[5] = (_regs_)->a1; \ |
_regval_[6] = (_regs_)->a2; \ |
_regval_[7] = (_regs_)->a3; \ |
\ |
_regval_[8] = (_regs_)->sp = (CYG_ADDRWORD)(_regs_) + \ |
sizeof(HAL_SavedRegisters); \ |
_regval_[9] = (_regs_)->pc; \ |
_regval_[10] = (_regs_)->mdr; \ |
_regval_[11] = (_regs_)->psw; \ |
\ |
_regval_[12] = (_regs_)->lar; \ |
_regval_[13] = (_regs_)->lir; \ |
HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \ |
} |
#endif |
|
// Copy a GDB ordered array into a HAL_SavedRegisters structure. |
// |
// The CYGMON version should differ by also handling SP and PSW |
// since we will be using a different stack. |
#ifdef CYGPKG_CYGMON |
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ |
{ \ |
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
\ |
(_regs_)->d0 = _regval_[0]; \ |
(_regs_)->d1 = _regval_[1]; \ |
(_regs_)->d2 = _regval_[2]; \ |
(_regs_)->d3 = _regval_[3]; \ |
(_regs_)->a0 = _regval_[4]; \ |
(_regs_)->a1 = _regval_[5]; \ |
(_regs_)->a2 = _regval_[6]; \ |
(_regs_)->a3 = _regval_[7]; \ |
\ |
(_regs_)->sp = _regval_[8]; \ |
(_regs_)->pc = _regval_[9]; \ |
(_regs_)->mdr = _regval_[10]; \ |
(_regs_)->psw = _regval_[11]; \ |
\ |
(_regs_)->lar = _regval_[12]; \ |
(_regs_)->lir = _regval_[13]; \ |
\ |
HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \ |
} |
#else |
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \ |
{ \ |
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \ |
\ |
(_regs_)->d0 = _regval_[0]; \ |
(_regs_)->d1 = _regval_[1]; \ |
(_regs_)->d2 = _regval_[2]; \ |
(_regs_)->d3 = _regval_[3]; \ |
(_regs_)->a0 = _regval_[4]; \ |
(_regs_)->a1 = _regval_[5]; \ |
(_regs_)->a2 = _regval_[6]; \ |
(_regs_)->a3 = _regval_[7]; \ |
\ |
(_regs_)->pc = _regval_[9]; \ |
(_regs_)->mdr = _regval_[10]; \ |
\ |
(_regs_)->lar = _regval_[12]; \ |
(_regs_)->lir = _regval_[13]; \ |
\ |
/* We do not allow the SP or PSW to be set. Changing the SP will \ |
* mess up the saved state. No PSW is saved on thread context \ |
* switches, so there is nowhere to save it to. \ |
*/ \ |
\ |
HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \ |
} |
#endif |
|
//------------------------------------------------------------------------- |
// HAL setjmp |
// Note: These definitions are repeated in context.S. If changes are required |
// remember to update both sets. |
|
#define CYGARC_JMP_BUF_SP 0 |
#define CYGARC_JMP_BUF_D2 1 |
#define CYGARC_JMP_BUF_D3 2 |
#define CYGARC_JMP_BUF_A2 3 |
#define CYGARC_JMP_BUF_A3 4 |
#define CYGARC_JMP_BUF_LR 5 |
|
#define CYGARC_JMP_BUF_SIZE 6 |
|
typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE]; |
|
externC int hal_setjmp(hal_jmp_buf env); |
externC void hal_longjmp(hal_jmp_buf env, int val); |
|
//------------------------------------------------------------------------- |
// Idle thread code. |
// This macro is called in the idle thread loop, and gives the HAL the |
// chance to insert code. Typical idle thread behaviour might be to halt the |
// processor. |
|
externC void hal_idle_thread_action(cyg_uint32 loop_count); |
|
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_) |
|
//----------------------------------------------------------------------------- |
// Minimal and sensible stack sizes: the intention is that applications |
// will use these to provide a stack size in the first instance prior to |
// proper analysis. Idle thread stack should be this big. |
|
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES. |
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING. |
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES! |
|
// We define quite large stack needs for SPARClite, for it requires 576 |
// bytes (144 words) to process an interrupt and thread-switch, and |
// momentarily, but needed in case of recursive interrupts, it needs 208 |
// words - if a sequence of saves to push out other regsets is interrupted. |
|
// This is not a config option because it should not be adjusted except |
// under "enough rope" sort of disclaimers. |
|
// Worst case stack frame size: return link + 4 args + 4 pushed registers. |
#define CYGNUM_HAL_STACK_FRAME_SIZE (40) |
|
// Stack needed for a context switch: |
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (60) |
|
// Interrupt + call to ISR, interrupt_end() and the DSR |
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (128) |
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
|
// An interrupt stack which is large enough for all possible interrupt |
// conditions (and only used for that purpose) exists. "User" stacks |
// can be much smaller |
|
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \ |
CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \ |
CYGNUM_HAL_STACK_FRAME_SIZE*16) |
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048) |
|
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
|
// No separate interrupt stack exists. Make sure all threads contain |
// a stack sufficiently large. |
|
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096) |
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096) |
|
#endif |
|
//-------------------------------------------------------------------------- |
// Macros for switching context between two eCos instances (jump from |
// code in ROM to code in RAM or vice versa). |
#define CYGARC_HAL_SAVE_GP() |
#define CYGARC_HAL_RESTORE_GP() |
|
//-------------------------------------------------------------------------- |
#endif // CYGONCE_HAL_HAL_ARCH_H |
// EOF hal_arch.h |
/v2_0/include/hal_cache.h
0,0 → 1,196
#ifndef CYGONCE_HAL_CACHE_H |
#define CYGONCE_HAL_CACHE_H |
|
//============================================================================= |
// |
// hal_cache.h |
// |
// HAL cache control API |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg |
// Date: 1998-02-17 |
// Purpose: Cache control API |
// Description: The macros defined here provide the HAL APIs for handling |
// cache control operations. |
// Usage: |
// #include <cyg/hal/hal_cache.h> |
// ... |
// |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
#include <cyg/infra/cyg_type.h> |
|
#if !defined(CYG_HAL_MN10300_AM31_SIM) |
|
#include <cyg/hal/var_cache.h> |
|
#else |
|
//============================================================================= |
// MN10300 Simulator |
|
//----------------------------------------------------------------------------- |
// Cache dimensions |
|
// Data cache |
#define HAL_DCACHE_SIZE 4096 // Size of data cache in bytes |
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line |
#define HAL_DCACHE_WAYS 2 // Associativity of the cache |
|
// Instruction cache |
#define HAL_ICACHE_SIZE 4096 // Size of cache in bytes |
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line |
#define HAL_ICACHE_WAYS 2 // Associativity of the cache |
|
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS)) |
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS)) |
|
//----------------------------------------------------------------------------- |
// Global control of data cache |
|
// Enable the data cache |
#define HAL_DCACHE_ENABLE() |
|
// Disable the data cache |
#define HAL_DCACHE_DISABLE() |
|
// Invalidate the entire cache |
#define HAL_DCACHE_INVALIDATE_ALL() |
|
// Synchronize the contents of the cache with memory. |
#define HAL_DCACHE_SYNC() |
|
// Set the data cache refill burst size |
//#define HAL_DCACHE_BURST_SIZE(_size_) |
|
// Set the data cache write mode |
//#define HAL_DCACHE_WRITE_MODE( _mode_ ) |
|
// Load the contents of the given address range into the data cache |
// and then lock the cache so that it stays there. |
//#define HAL_DCACHE_LOCK(_base_, _size_) |
|
// Undo a previous lock operation |
//#define HAL_DCACHE_UNLOCK(_base_, _size_) |
|
// Unlock entire cache |
//#define HAL_DCACHE_UNLOCK_ALL() |
|
//----------------------------------------------------------------------------- |
// Data cache line control |
|
// Allocate cache lines for the given address range without reading its |
// contents from memory. |
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ ) |
|
// Write dirty cache lines to memory and invalidate the cache entries |
// for the given address range. |
//#define HAL_DCACHE_FLUSH( _base_ , _size_ ) |
|
// Invalidate cache lines in the given range without writing to memory. |
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) |
|
// Write dirty cache lines to memory for the given address range. |
//#define HAL_DCACHE_STORE( _base_ , _size_ ) |
|
// Preread the given range into the cache with the intention of reading |
// from it later. |
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ ) |
|
// Preread the given range into the cache with the intention of writing |
// to it later. |
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ ) |
|
// Allocate and zero the cache lines associated with the given range. |
//#define HAL_DCACHE_ZERO( _base_ , _size_ ) |
|
//----------------------------------------------------------------------------- |
// Global control of Instruction cache |
|
// Enable the instruction cache |
#define HAL_ICACHE_ENABLE() |
|
// Disable the instruction cache |
#define HAL_ICACHE_DISABLE() |
|
// Invalidate the entire cache |
#define HAL_ICACHE_INVALIDATE_ALL() |
|
// Synchronize the contents of the cache with memory. |
#define HAL_ICACHE_SYNC() |
|
// Set the instruction cache refill burst size |
//#define HAL_ICACHE_BURST_SIZE(_size_) |
|
// Load the contents of the given address range into the instruction cache |
// and then lock the cache so that it stays there. |
//#define HAL_ICACHE_LOCK(_base_, _size_) |
|
// Undo a previous lock operation |
//#define HAL_ICACHE_UNLOCK(_base_, _size_) |
|
// Unlock entire cache |
//#define HAL_ICACHE_UNLOCK_ALL() |
|
//----------------------------------------------------------------------------- |
// Instruction cache line control |
|
// Invalidate cache lines in the given range without writing to memory. |
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) |
|
#endif |
|
|
//----------------------------------------------------------------------------- |
// Check that a supported configuration has actually defined some macros. |
|
#ifndef HAL_DCACHE_ENABLE |
|
#error Unsupported MN10300 configuration |
|
#endif |
|
//----------------------------------------------------------------------------- |
#endif // ifndef CYGONCE_HAL_CACHE_H |
// End of hal_cache.h |
/v2_0/src/hal_syscall.c
0,0 → 1,106
//============================================================================= |
// |
// hal_syscall.c |
// |
// |
// |
//============================================================================= |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//============================================================================= |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): msalter |
// Contributors:msalter |
// Date: 2000-11-5 |
// Purpose: |
// Description: |
// |
// |
// |
//####DESCRIPTIONEND#### |
// |
//============================================================================= |
|
#include <pkgconf/hal.h> |
|
#ifdef CYGPKG_REDBOOT |
#include <pkgconf/redboot.h> |
#endif |
|
#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS) |
|
#include <cyg/hal/hal_stub.h> // Our header |
#include <cyg/hal/hal_arch.h> // HAL_BREAKINST |
#include <cyg/hal/hal_cache.h> // HAL_xCACHE_x |
#include <cyg/hal/hal_intr.h> // interrupt disable/restore |
|
#include <cyg/hal/hal_if.h> // ROM calling interface |
#include <cyg/hal/hal_misc.h> // Helper functions |
|
extern CYG_ADDRWORD __do_syscall(CYG_ADDRWORD func, // syscall function number |
CYG_ADDRWORD arg1, CYG_ADDRWORD arg2, // up to four args. |
CYG_ADDRWORD arg3, CYG_ADDRWORD arg4, |
CYG_ADDRWORD *retval, // syscall return value |
CYG_ADDRWORD *sig); // signal to return (or 0) |
|
#define SYS_exit 1 |
#define SYS_interrupt 1000 |
|
int |
hal_syscall_handler(void) |
{ |
CYG_ADDRWORD func, arg1, arg2, arg3, arg4; |
CYG_ADDRWORD err, sig; |
|
func = get_register(D0); |
arg1 = get_register(D1); |
arg2 = get_register(D2); |
arg3 = get_register(D3); |
arg4 = 0; |
|
if (func == SYS_interrupt) { |
// A console interrupt landed us here. |
// Invoke the debug agent so as to cause a SIGINT. |
return SIGINT; |
} |
|
if (__do_syscall(func, arg1, arg2, arg3, arg4, &err, &sig)) { |
put_register(D0, err); |
return (int)sig; |
} |
|
return SIGTRAP; |
} |
|
#endif // CYGSEM_REDBOOT_BSP_SYSCALLS |
/v2_0/src/hal_misc.c
0,0 → 1,301
/*========================================================================== |
// |
// hal_misc.c |
// |
// HAL miscellaneous functions |
// |
//========================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//========================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): nickg |
// Contributors: nickg, jlarmour, dmoseley |
// Date: 1999-02-18 |
// Purpose: HAL miscellaneous functions |
// Description: This file contains miscellaneous functions provided by the |
// HAL. |
// |
//####DESCRIPTIONEND#### |
// |
//========================================================================*/ |
|
#include <pkgconf/hal.h> |
|
#include <cyg/infra/cyg_type.h> |
#include <cyg/infra/cyg_trac.h> |
|
#include <cyg/hal/hal_arch.h> |
|
#include <cyg/hal/hal_intr.h> |
|
#include <cyg/hal/hal_cache.h> |
|
#if 0 |
void trace( CYG_ADDRWORD tag, CYG_ADDRWORD a1, CYG_ADDRWORD a2) |
{ |
CYG_ADDRWORD **pp = (CYG_ADDRWORD **)0x48100000; |
CYG_ADDRWORD *ix = (CYG_ADDRWORD *)0x4810000C; |
CYG_ADDRWORD *p = *pp; |
*p++ = tag; |
*ix = *ix + 1; |
*p++ = *ix; |
*p++ = a1; |
*p++ = a2; |
*pp = p; |
} |
#endif |
|
/*------------------------------------------------------------------------*/ |
|
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
cyg_bool cyg_hal_stop_constructors; |
#endif |
|
void |
cyg_hal_invoke_constructors(void) |
{ |
typedef void (*pfunc) (void); |
extern pfunc _CTOR_LIST__[]; |
extern pfunc _CTOR_END__[]; |
|
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
static pfunc *p = &_CTOR_END__[-1]; |
|
cyg_hal_stop_constructors = 0; |
for (; p >= _CTOR_LIST__; p--) { |
(*p) (); |
if (cyg_hal_stop_constructors) { |
p--; |
break; |
} |
} |
#else |
pfunc *p; |
|
for (p = &_CTOR_END__[-1]; p >= _CTOR_LIST__; p--) |
(*p) (); |
#endif |
|
} // cyg_hal_invoke_constructors() |
|
/*------------------------------------------------------------------------*/ |
/* Determine the index of the ls bit of the supplied mask. */ |
|
cyg_uint32 |
hal_lsbit_index(cyg_uint32 mask) |
{ |
cyg_uint32 n = mask; |
|
static const signed char tab[64] = |
{ -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10, |
4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11, |
5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0, |
0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0 |
}; |
|
n &= ~(n-1UL); |
n = (n<<16)-n; |
n = (n<<6)+n; |
n = (n<<4)+n; |
|
return tab[n>>26]; |
} |
|
/*------------------------------------------------------------------------*/ |
/* Determine the index of the ms bit of the supplied mask. */ |
|
cyg_uint32 |
hal_msbit_index(cyg_uint32 mask) |
{ |
cyg_uint32 x = mask; |
cyg_uint32 w; |
|
/* Phase 1: make word with all ones from that one to the right */ |
x |= x >> 16; |
x |= x >> 8; |
x |= x >> 4; |
x |= x >> 2; |
x |= x >> 1; |
|
/* Phase 2: calculate number of "1" bits in the word */ |
w = (x & 0x55555555) + ((x >> 1) & 0x55555555); |
w = (w & 0x33333333) + ((w >> 2) & 0x33333333); |
w = w + (w >> 4); |
w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F); |
return (cyg_uint32)((w + (w >> 16)) & 0xFF) - 1; |
} |
|
/*------------------------------------------------------------------------*/ |
/* First level C exception handler. */ |
|
externC void __handle_exception (void); |
|
externC HAL_SavedRegisters *_hal_registers; |
|
externC void* volatile __mem_fault_handler; |
|
externC cyg_uint32 |
cyg_hal_exception_handler(HAL_SavedRegisters *regs, CYG_WORD32 isr) |
{ |
CYG_WORD vector = regs->vector; |
|
#if defined(CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR) && defined(CYGNUM_HAL_EXCEPTION_JTAG) |
if( vector == CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR ) |
{ |
// Translate vector number via ISR bits into the full |
// set. |
vector = CYGNUM_HAL_EXCEPTION_JTAG+hal_lsbit_index( isr ); |
|
regs->vector = vector; |
} |
#endif |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
|
// If we caught an exception inside the stubs, see if we were expecting it |
// and if so jump to the saved address |
if (__mem_fault_handler) { |
regs->pc = (CYG_ADDRWORD)__mem_fault_handler; |
return 0; // Caught an exception inside stubs |
} |
|
// Set the pointer to the registers of the current exception |
// context. At entry the GDB stub will expand the |
// HAL_SavedRegisters structure into a (bigger) register array. |
_hal_registers = regs; |
|
__handle_exception(); |
|
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) |
|
if( vector == CYGNUM_HAL_EXCEPTION_WATCHDOG ) |
{ |
// Special case the watchdog timer exception, look for an |
// ISR for it and call it if present. Otherwise pass on to |
// the exception system. |
|
cyg_uint32 (*isr)(CYG_ADDRWORD,CYG_ADDRWORD); |
cyg_uint32 index; |
|
HAL_TRANSLATE_VECTOR( CYGNUM_HAL_INTERRUPT_WATCHDOG, index ); |
|
isr = (cyg_uint32 (*)(CYG_ADDRWORD,CYG_ADDRWORD)) |
(hal_interrupt_handlers[index]); |
|
if( isr != 0 ) |
{ |
isr(CYGNUM_HAL_INTERRUPT_WATCHDOG, |
hal_interrupt_data[CYGNUM_HAL_INTERRUPT_WATCHDOG] |
); |
return 0; |
} |
} |
|
#if defined(CYGPKG_HAL_EXCEPTIONS) |
|
// We should decode the vector and pass a more appropriate |
// value as the second argument. For now we simply pass a |
// pointer to the saved registers. We should also divert |
// breakpoint and other debug vectors into the debug stubs. |
|
cyg_hal_deliver_exception( vector, (CYG_ADDRWORD)regs ); |
|
#endif |
|
#endif |
|
return 0; |
} |
|
/*------------------------------------------------------------------------*/ |
/* default ISR */ |
|
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT |
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
{ |
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) && \ |
defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ |
defined(HAL_CTRLC_ISR) |
|
#ifndef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN |
if( vector == CYGHWR_HAL_GDB_PORT_VECTOR ) |
#endif |
{ |
cyg_uint32 result = HAL_CTRLC_ISR( vector, data ); |
if( result != 0 ) return result; |
} |
|
#endif |
|
CYG_TRACE1(true, "Interrupt: %d", vector); |
CYG_FAIL("Spurious Interrupt!!!"); |
return 0; |
} |
|
#else // CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT |
|
#include <cyg/hal/plf_io.h> |
externC cyg_uint32 hal_arch_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data) |
{ |
#if defined(CYGDBG_HAL_MN10300_DEBUG_GDB_CTRLC_SUPPORT) && \ |
defined(CYGHWR_HAL_GDB_PORT_VECTOR) && \ |
defined(HAL_CTRLC_ISR) |
|
#if defined(CYGSEM_HAL_USE_ROM_MONITOR_CygMon) |
#if defined(HAL_DIAG_IRQ_CHECK) |
{ |
cyg_uint32 ret; |
/* let ROM monitor handle unexpected interrupts */ |
HAL_DIAG_IRQ_CHECK(vector, ret); |
if (ret<=0) |
return ret; |
} |
#endif // def HAL_DIAG_IRQ_CHECK |
#endif // def CYGSEM_HAL_USE_ROM_MONITOR_CygMon |
#endif |
|
return 0; |
} |
#endif |
|
/*------------------------------------------------------------------------*/ |
/* Idle thread activity. */ |
|
externC void hal_idle_thread_action(cyg_uint32 loop_count) |
{ |
} |
|
/*------------------------------------------------------------------------*/ |
/* End of hal_misc.c */ |
/v2_0/src/context.S
0,0 → 1,154
##============================================================================= |
## |
## context.S |
## |
## MN10300 context switch code |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): nickg |
## Contributors: nickg |
## Date: 1998-04-27 |
## Purpose: MN10300 context switch code |
## Description: This file contains implementations of the thread context |
## switch routines. It also contains the longjmp() and setjmp() |
## routines. |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/hal.h> |
|
#include <cyg/hal/arch.inc> |
|
#------------------------------------------------------------------------------ |
# hal_thread_switch_context |
# Switch thread contexts |
# D0 = address of sp of next thread to execute |
# D1 = address of sp save location of current thread |
|
.global _hal_thread_switch_context |
_hal_thread_switch_context: |
add -8,sp # space for SP and PSW |
mov d2,a0 # move d2->a0 since PSW can only be |
# saved to a data register |
hal_cpu_get_psw d2 # save PSW to d2 |
mov d2,(4,sp) # store in stack loc |
mov a0,d2 # retrieve old d2 value |
hal_cpu_save_all # save entire register set |
mov d1,a2 # move save loc addr to A2 |
mov sp,(0,a2) # store SP in save location |
|
# Now load the destination thread by dropping through |
# to hal_thread_load_context |
|
#------------------------------------------------------------------------------ |
# hal_thread_load_context |
# Load thread context |
# D0 = address of sp of next thread to execute |
# Note that this function is also the second half of hal_thread_switch_context |
# and is simply dropped into from it. |
|
.global _hal_thread_load_context |
_hal_thread_load_context: |
|
mov d0,a2 # move next sp loc to a2 |
mov (0,a2),sp # load SP with new value |
hal_cpu_load_all # load whole register set |
mov (4,sp),d1 # retrieve saved PSW |
hal_cpu_set_psw d1 # and restore it |
add 8,sp # skip saved SP and PSW |
ret [],0 # and return |
|
##----------------------------------------------------------------------------- |
## HAL longjmp(), setjmp() implementations |
## These implementations omit the usual movm [d2,d3,a2,a3],(sp) |
## Which is the first instruction of all C compiled functions. |
## Note: These definitions are repeated in hal_arch.h. If changes are required |
## remember to update both sets. |
|
#define CYGARC_JMP_BUF_SP 0 |
#define CYGARC_JMP_BUF_D2 1 |
#define CYGARC_JMP_BUF_D3 2 |
#define CYGARC_JMP_BUF_A2 3 |
#define CYGARC_JMP_BUF_A3 4 |
#define CYGARC_JMP_BUF_LR 5 |
|
#define CYGARC_JMP_BUF_SIZE 6 |
|
|
# This just preserves the callee save registers |
# namely a2,a3,d2,d3 |
# setjmp cannot use movm to do this as we need to keep |
# the sp underneath all live data at all times. |
.globl _hal_setjmp |
_hal_setjmp: # d0=env |
mov d0,a0 # env |
mov d2,(CYGARC_JMP_BUF_D2*4,a0) |
mov d3,(CYGARC_JMP_BUF_D3*4,a0) |
mov a2,(CYGARC_JMP_BUF_A2*4,a0) |
mov a3,(CYGARC_JMP_BUF_A3*4,a0) |
mov mdr,d1 # link saved by call (also in (0,sp)) |
mov d1,(CYGARC_JMP_BUF_LR*4,a0) |
mov sp,a1 |
mov a1,(CYGARC_JMP_BUF_SP*4,a0) # a1==(caller''s sp) |
clr d0 # return 0 |
ret [],0 |
|
# longjmp returns to caller of setjmp |
# after restoring callee save registers |
.globl _hal_longjmp |
_hal_longjmp: |
mov d0,a0 |
mov (CYGARC_JMP_BUF_D2*4,a0),d2 |
mov (CYGARC_JMP_BUF_D3*4,a0),d3 |
mov (CYGARC_JMP_BUF_A2*4,a0),a2 |
mov (CYGARC_JMP_BUF_A3*4,a0),a3 |
mov (CYGARC_JMP_BUF_LR*4,a0),d0 |
## mov d0,mdr |
mov (CYGARC_JMP_BUF_SP*4,a0),a1 # stashed (caller''s sp) |
mov a1,sp |
mov d0,(0,sp) # put link on stack |
mov d1,d0 # return arg1 |
ret [],0 # this ignores (0,sp) and does pc=mdr |
|
|
#------------------------------------------------------------------------------ |
# end of context.S |
|
|
/v2_0/src/vectors.S
0,0 → 1,842
##============================================================================= |
## |
## vectors.S |
## |
## MN10300 exception vectors |
## |
##============================================================================= |
#####ECOSGPLCOPYRIGHTBEGIN#### |
## ------------------------------------------- |
## This file is part of eCos, the Embedded Configurable Operating System. |
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
## |
## eCos is free software; you can redistribute it and/or modify it under |
## the terms of the GNU General Public License as published by the Free |
## Software Foundation; either version 2 or (at your option) any later version. |
## |
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
## WARRANTY; without even the implied warranty of MERCHANTABILITY or |
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
## for more details. |
## |
## You should have received a copy of the GNU General Public License along |
## with eCos; if not, write to the Free Software Foundation, Inc., |
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
## |
## As a special exception, if other files instantiate templates or use macros |
## or inline functions from this file, or you compile this file and link it |
## with other works to produce a work based on this file, this file does not |
## by itself cause the resulting work to be covered by the GNU General Public |
## License. However the source code for this file must still be made available |
## in accordance with section (3) of the GNU General Public License. |
## |
## This exception does not invalidate any other reasons why a work based on |
## this file might be covered by the GNU General Public License. |
## |
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
## at http://sources.redhat.com/ecos/ecos-license/ |
## ------------------------------------------- |
#####ECOSGPLCOPYRIGHTEND#### |
##============================================================================= |
#######DESCRIPTIONBEGIN#### |
## |
## Author(s): nickg |
## Contributors: nickg, dmoseley, dhowells |
## Date: 1997-10-16 |
## Purpose: MN10300 exception vectors |
## Description: This file defines the code placed into the exception |
## vectors. It also contains the first level default VSRs |
## that save and restore state for both exceptions and |
## interrupts. |
## |
######DESCRIPTIONEND#### |
## |
##============================================================================= |
|
#include <pkgconf/hal.h> |
|
#ifdef CYGPKG_REDBOOT |
#include <pkgconf/redboot.h> |
#endif |
|
#ifdef CYGPKG_KERNEL |
|
#include <pkgconf/kernel.h> |
|
#endif |
|
#include <cyg/hal/arch.inc> |
#include <cyg/hal/basetype.h> |
|
|
##----------------------------------------------------------------------------- |
|
// .file "vectors.S" |
|
#ifdef CYGPKG_CYGMON |
##----------------------------------------------------------------------------- |
## Macros for Stack handling when running Cygmon |
|
.macro hal_cygmon_switch_app_stack |
# |
# Switch to interrupt stack to handle exception |
# |
|
# First, save some scratch registers |
mov a2(a2_save) |
mov a3,(a3_save) |
|
# Copy the exception frame |
mov __cygmon_interrupt_stack-8,a2 |
mov (sp),a3 // Copy over the saved EPSW |
mov a3,(a2) |
mov (4,sp),a3 // Copy over the saved PC |
mov a3,(4,a2) |
|
# Save the pre-exception sp in the register image |
add -4,a2 # space for SP |
mov sp,a3 |
add 8,a3 # adjust for exception frame |
mov a3,(a2) |
|
# Actually switch the stack |
mov a2,sp |
|
# Now, restore the scratch registers |
mov (a2_save),a2 |
mov (a3_save),a3 |
.endm |
|
.macro hal_cygmon_restore_app_stack |
// For cygmon we are switching stacks immediately on exception. |
// We must wait until the very end before restoring the original stack. |
|
# Save some scratch registers |
mov a2,(a2_save) |
mov a3,(a3_save) |
|
# We need to restore the application stack pointer, but we also |
# need to restore the exception frame. |
mov (sp),a2 |
add 4,sp // remove saved sp |
add -8,a2 // adjust for exception frame |
|
mov (sp),a3 // Copy the saved EPSW |
mov a3,(a2) |
mov (4,sp),a3 // Copy the saved PC |
mov a3,(4,a2) |
mov a2,sp // Restore the frame-adjusted SP |
|
# Restore the scratch registers |
mov (a2_save),a2 |
mov (a3_save),a3 |
.endm |
|
#endif // CYGPKG_CYGMON |
|
##----------------------------------------------------------------------------- |
#define EXCEPTION_HANDLER(VECTOR,NAME,HANDLER) .org VECTOR; \ |
NAME##_vector: \ |
jmp HANDLER |
|
.section ".vectors","ax" |
|
.globl reset_vector |
|
.org 0x000 |
reset_vector: |
# Reset vector |
jmp _start |
|
EXCEPTION_HANDLER(0x008, nmi ,__nmi) |
EXCEPTION_HANDLER(0x010, trap ,__trap) |
EXCEPTION_HANDLER(0x100, ins_tlb_miss_exception ,__unknown) |
EXCEPTION_HANDLER(0x108, data_tlb_miss_exception ,__unknown) |
EXCEPTION_HANDLER(0x110, ins_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x118, data_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x160, priv_ins_exception ,__unknown) |
EXCEPTION_HANDLER(0x168, unimpl_ins_exception ,__unknown) |
EXCEPTION_HANDLER(0x170, unimpl_ext_ins_exception ,__unknown) |
EXCEPTION_HANDLER(0x180, misalignment_exception ,__unknown) |
EXCEPTION_HANDLER(0x188, bus_error ,__unknown) |
EXCEPTION_HANDLER(0x190, illegal_ins_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x198, illegal_data_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x1a0, iospace_ins_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x1a8, priv_space_ins_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x1b0, priv_space_data_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x1b8, data_space_ins_access_exception ,__unknown) |
EXCEPTION_HANDLER(0x1c0, fpu_disabled_exception ,__unknown) |
EXCEPTION_HANDLER(0x1c8, fpu_unimplemented_exception ,__unknown) |
EXCEPTION_HANDLER(0x1d0, fpu_operation_exception ,__unknown) |
EXCEPTION_HANDLER(0x200, double_fault ,__unknown) |
EXCEPTION_HANDLER(0x240, wdt_overflow ,__unknown) |
EXCEPTION_HANDLER(0x248, nmi_pin ,__nmi) |
EXCEPTION_HANDLER(0x280, maskable_int0 ,__unknown) |
EXCEPTION_HANDLER(0x288, maskable_int1 ,__unknown) |
EXCEPTION_HANDLER(0x290, maskable_int2 ,__unknown) |
EXCEPTION_HANDLER(0x298, maskable_int3 ,__unknown) |
EXCEPTION_HANDLER(0x2a0, maskable_int4 ,__unknown) |
EXCEPTION_HANDLER(0x2a8, maskable_int5 ,__unknown) |
EXCEPTION_HANDLER(0x2b0, maskable_int6 ,__unknown) |
|
// We need to put the syscall handler at 0x300 |
// For cygmon, we will use the am33 "syscall 0" as the syscall trap. |
EXCEPTION_HANDLER(0x300, syscall0 ,__nmi) |
EXCEPTION_HANDLER(0x308, syscall1 ,__unknown) |
EXCEPTION_HANDLER(0x310, syscall2 ,__unknown) |
EXCEPTION_HANDLER(0x318, syscall3 ,__unknown) |
EXCEPTION_HANDLER(0x320, syscall4 ,__unknown) |
EXCEPTION_HANDLER(0x328, syscall5 ,__unknown) |
EXCEPTION_HANDLER(0x330, syscall6 ,__unknown) |
EXCEPTION_HANDLER(0x338, syscall7 ,__unknown) |
EXCEPTION_HANDLER(0x340, syscall8 ,__unknown) |
EXCEPTION_HANDLER(0x348, syscall9 ,__unknown) |
EXCEPTION_HANDLER(0x350, syscalla ,__unknown) |
EXCEPTION_HANDLER(0x358, syscallb ,__unknown) |
EXCEPTION_HANDLER(0x360, syscallc ,__unknown) |
EXCEPTION_HANDLER(0x368, syscalld ,__unknown) |
EXCEPTION_HANDLER(0x370, syscalle ,__unknown) |
EXCEPTION_HANDLER(0x378, syscallf ,__unknown) |
|
##----------------------------------------------------------------------------- |
## unknown interrupt or exception vector |
__unknown: |
#ifdef CYG_HAL_HANDLE_UNKNOWN_INT_DEFINED |
hal_handle_unknown_int |
#endif |
|
##----------------------------------------------------------------------------- |
## NMI vector |
|
.globl __nmi |
__nmi: |
#ifdef CYGPKG_CYGMON |
hal_cygmon_switch_app_stack |
#else |
add -4,sp # space for SP |
#endif |
hal_cpu_save_all # push all registers |
mov (_hal_vsr_table+28),a0 |
jmp (a0) |
|
##----------------------------------------------------------------------------- |
## Trap vector |
|
.globl __trap |
__trap: |
#ifdef CYGPKG_CYGMON |
add -4,sp # space for PSW |
hal_cygmon_switch_app_stack |
#else |
add -8,sp # space for SP and PSW |
#endif |
hal_cpu_save_all # push all registers |
mov (_hal_vsr_table+32),a0 |
jmp (a0) |
|
##----------------------------------------------------------------------------- |
## Macro to define a hardware VSR |
|
.macro hardware_vector name |
.globl __hardware_vector_\name |
__hardware_vector_\name: |
#ifdef CYGPKG_CYGMON |
hal_cygmon_switch_app_stack |
#else |
add -4,sp # space for SP |
#endif |
hal_cpu_save_all |
mov \name,d0 # d0 = vector id |
mov d0,(0,sp) # save in dummy stack loc |
mov _hal_vsr_table,a0 # a0 = vsr table |
add \name<<2,a0 # a0 = &required vsr |
mov (a0),a0 # a0 = required vsr |
jmp (a0) # go there |
.endm |
|
##----------------------------------------------------------------------------- |
## Hardware Vectors. These are pointed to by the registers in |
## mn10300_interrupt_vectors and must be in the range 0x4000XXXX. |
|
hardware_vector 0 |
hardware_vector 1 |
hardware_vector 2 |
hardware_vector 3 |
hardware_vector 4 |
hardware_vector 5 |
hardware_vector 6 |
|
##----------------------------------------------------------------------------- |
## Startup code |
|
.text |
|
.globl _start |
_start: |
|
#ifdef HAL_EARLY_INIT |
HAL_EARLY_INIT |
#endif |
# set up stack |
|
mov __interrupt_stack,a0 |
sub 8,a0 |
mov a0,sp |
|
# Initialize hardware |
hal_cpu_init |
hal_mmu_init |
hal_memc_init |
hal_diag_init |
hal_intc_init |
hal_cache_init |
hal_timer_init |
hal_mon_init |
|
#ifdef CYG_HAL_STARTUP_ROM |
|
# Copy data from ROM to RAM |
|
mov __rom_data_start,a0 |
mov __ram_data_end,a1 |
mov __ram_data_start,a2 |
|
cmp a2,a1 |
beq 8f |
1: |
movbu (a0),d0 |
movbu d0,(a2) |
inc a0 |
inc a2 |
cmp a2,a1 |
bne 1b |
8: |
|
#endif |
|
# Clear BSS |
mov __bss_start,a0 |
mov __bss_end,a1 |
|
cmp a0,a1 |
beq 8f |
clr d0 |
1: |
movbu d0,(a0) |
inc a0 |
cmp a0,a1 |
bne 1b |
8: |
|
# Call variant and platform HAL |
# initialization routines. |
|
.extern _hal_variant_init |
call _hal_variant_init,[],0 |
|
.extern _hal_platform_init |
call _hal_platform_init,[],0 |
|
# Call constructors |
|
.extern _cyg_hal_invoke_constructors |
call _cyg_hal_invoke_constructors,[],0 |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
.extern _initialize_stub |
call _initialize_stub,[],0 |
#endif |
|
#ifdef CYGDBG_HAL_MIPS_DEBUG_GDB_CTRLC_SUPPORT |
.extern hal_ctrlc_isr_init |
call hal_ctrlc_isr_init,[],0 |
#endif |
|
# Call cyg_start |
clr d0 |
mov d0,(4,sp) |
|
.extern _cyg_start |
call _cyg_start,[],0 |
|
9: |
bra 9b # Loop if we return |
|
##----------------------------------------------------------------------------- |
## The following macros are defined depending on whether the HAL is configured |
## to support the kernel or not. |
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT |
|
.extern _cyg_scheduler_sched_lock |
|
# Increment the scheduler lock |
|
.macro increment_sched_lock reg=d0 |
mov (_cyg_scheduler_sched_lock),\reg |
inc \reg |
mov \reg,(_cyg_scheduler_sched_lock) |
.endm |
|
#else |
|
.macro increment_sched_lock reg=d0 |
.endm |
|
#endif |
|
##----------------------------------------------------------------------------- |
## Default interrupt VSR |
|
.text |
.globl __default_interrupt_vsr |
__default_interrupt_vsr: |
|
# We come here with all the registers pushed |
# onto the stack. |
|
hal_diag_intr_start |
|
increment_sched_lock |
|
#if defined(CYGPKG_CYGMON) |
// For Cygmon, we saved this back when we originally switched stacks. |
mov (sp),a2 # A2 = saved thread state |
#elif defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK) |
# Increment interrupt nesting counter |
mov __interrupt_stack,a0 # A0 = interrupt stack top |
mov sp,a2 # A2 = SP |
cmp __interrupt_stack_base,a2 # compare with base of stack |
blt 1f # if lt switch to int stack |
cmp a0,a2 # compare sp with stack top |
ble 8f # if le already on istack |
1: |
mov a0,sp # switch to new SP |
8: |
movm [a2],(sp) # save old SP |
|
#else |
mov sp,a2 # A2 = saved thread state |
#endif |
|
# Here A2 -> saved thread state on the threads own |
# stack. We will be executing either on the same stack |
# or on the interrupt stack, depending on config options. |
|
hal_intc_decode d3,a3,d0 |
|
# Here D3 contains the table byte offset of the vector to |
# call. |
|
#if defined(CYGPKG_KERNEL_INSTRUMENT) && defined(CYGDBG_KERNEL_INSTRUMENT_INTR) |
|
# Call cyg_instrument to record that this interrupt is being raised. |
|
.extern _cyg_instrument |
add -16,sp # make space for return link + args |
mov 0x0301,d0 # d0 = type = INTR,RAISE |
mov (0,a2),d1 # d1 = arg1 = vector |
mov d3,(12,sp) # (12,sp) = arg2 = table offset |
calls _cyg_instrument # call instrumentation |
add 16,sp # pop space |
|
#endif |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
.extern _cyg_hal_gdb_isr |
add -16,sp # make space for return link + args |
mov (0,a2),d0 # d0 = vector |
mov (SAVED_CONTEXT_PC_OFFSET,a2),d1 # d1 = pc |
calls _cyg_hal_gdb_isr # call GDB isr function |
cmp 0x00,d0 # Call ISR proper? |
beq 2f # (d0 is 0 when skipping |
# to avoid DSR call) |
add 16,sp # pop space |
#endif |
|
#ifdef CYGSEM_HAL_COMMON_INTERRUPTS_ALLOW_NESTING |
|
# To allow nested interrupts, we set the IE bit. We do |
# not touch the IPL bits, so only higher priority interrupts |
# will be nested on top of us. Also, new interrupts will not |
# be delivered until the ISR calls |
# Cyg_Interrupt::acknowledge_interrupt(). At some future point |
# we may want to do the ack stuff here to allow immediate nesting. |
|
or 0x0800,psw |
|
#endif |
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT) |
|
# If we have Ctrl-C support enabled, save a pointer to the |
# saved CPU state here so we can plant a breakpoint there if |
# this is a ^C. |
|
.extern _hal_saved_interrupt_state |
mov a2,(_hal_saved_interrupt_state) |
|
#endif |
|
mov _hal_interrupt_handlers,a0 # a0 = isr table |
mov (d3,a0),a0 # a0 = isr |
|
mov _hal_interrupt_data,a1 # a1 = data table |
mov (d3,a1),d1 # d1 = isr data |
|
mov (0,a2),d0 # d0 = vector. (d3 is... |
# ...adjusted for table reads) |
|
add -16,sp # make space for return link |
|
calls (a0) # call isr |
|
# on return d0 bit 1 will indicate whether a DSR is |
# to be posted. Pass this together with a pointer to |
# the interrupt object we have just used to the |
# interrupt tidy up routine. |
|
# D3 is defined to be saved across procedure calls, and |
# should still contain the vector byte index. Similarly, |
# A2 should still point to the saved machine state. |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT |
# If interrupt was caused by GDB, the ISR call above |
# is skipped by jumping here. |
2: |
#endif |
|
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK) && !defined(CYGPKG_CYGMON) |
|
# If we are returning from the last nested interrupt, move back |
# to the thread stack. interrupt_end() must be called on the |
# thread stack since it potentially causes a context switch. |
|
add 16,sp # pop call frame from int stack |
movm (sp),[a3] # pop old sp |
mov a3,sp # put in SP |
|
add -16,sp # make call frame for call |
|
#endif |
|
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT |
|
# We only need to call _interrupt_end() when there is a kernel |
# present to do any tidying up. |
|
# Using the vector offset in D3, get the interrupt object pointer |
# into D1. |
mov _hal_interrupt_objects,a0 # a0 = object table |
mov (d3,a0),d1 # d1 = object |
|
# Even when this is not the last nested interrupt, we must call |
# _interrupt_end() to post the DSR and decrement the scheduler |
# lock. |
|
mov a2,(12,sp) # arg3 = saved state. |
|
calls _interrupt_end # call interrupt end fn |
#endif |
|
add 16,sp # pop return link |
|
# show_interrupts |
|
hal_diag_restore |
|
hal_cpu_load_all |
#ifdef CYGPKG_CYGMON |
hal_cygmon_restore_app_stack |
#else |
add 4,sp |
#endif |
rti # and return |
|
##----------------------------------------------------------------------------- |
## Execute pending DSRs on the interrupt stack with interrupts enabled. |
## Note: this can only be called from code running on a thread stack |
|
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK |
.extern _cyg_interrupt_call_pending_DSRs |
.global _hal_interrupt_stack_call_pending_DSRs |
|
_hal_interrupt_stack_call_pending_DSRs: |
movm [d2,a2],(sp) # save some work regs |
mov __interrupt_stack,a0 # interrupt stack pointer |
mov sp,a2 # save current SP |
mov a0,sp # set SP to interrupt stack |
hal_cpu_get_psw d2 # save PSW |
hal_cpu_int_enable # enable interrupts |
|
# Call kernel code to invoke DSRs. |
calls _cyg_interrupt_call_pending_DSRs |
|
# On return the old SP in a2 and the old PSW in d2 will |
# have been preserved by the calling conventions. |
|
hal_cpu_int_merge d2 # Restore previous PSW |
mov a2,sp # restore old SP |
movm (sp),[d2,a2] # Retrieve old work regs |
ret [],0 # and return |
|
#endif |
|
##----------------------------------------------------------------------------- |
## Default NMI VSR |
|
.globl _cyg_hal_exception_handler |
|
.text |
.globl __default_nmi_vsr |
__default_nmi_vsr: |
|
# We come here with all the registers saved |
# on the stack. |
|
#ifdef CYG_HAL_DIAG_EXCPT_END |
hal_diag_excpt_start |
#endif |
|
# Decode the cause of the NMI and cancel all the bits in all |
# the registers. We need to clear any bits set in the ISR and |
# then clear any bits set in the NMICR. Note that we can only |
# access the ISR if the DCR:DE bit is set. |
|
movhu (NMICR),d0 # D0 = NMI Control register |
|
movhu (DCR),d1 # D1 = Debug Control Register |
mov d1,d2 # D2 = copy of DCR |
movhu (ISR),d3 # D3 = Interrupt Status Register |
|
or DCR_DE,d1 # Set DE bit |
movhu d1,(DCR) |
|
movhu d3,(ISR) # clear ISR bits |
|
movhu d2,(DCR) # restore DCR to original value |
|
movhu d0,(NMICR) # clear NMI bits |
and 0x7,d0 # LS 3 bits only |
|
mov hal_lsbit_table,a0 |
movbu (d0,a0),d1 # D1 = NMI code |
## 0 = NMI |
## 1 = Watchdog |
## 2 = System Error |
|
add 9,d1 # offset into exception number space |
|
#if defined(CYGPKG_CYGMON) || defined(CYGSEM_REDBOOT_BSP_SYSCALLS) |
# Check to see if this was a syscall. |
# If so, set d1 appropriately |
#define TBR 0xC0000024 |
mov (TBR), d0 |
and 0x00FFFFFF, d0 |
cmp 0x300, d0 |
bne 0f |
|
# This was apparently a syscall. |
mov SIGSYSCALL, d1 |
|
0: |
#endif |
hal_cpu_clear_nmid |
|
mov d1,(sp) # save initial vector in spare save slot |
|
mov sp,a1 # a1 = saved state |
|
mov a1,d0 # d0 = arg1 = saved state |
|
add -16,sp # return link + args |
mov d3,d1 # d1 = arg2 = ISR value |
|
calls _cyg_hal_exception_handler # call C code |
|
add 16,sp # pop args |
|
#ifdef CYG_HAL_DIAG_EXCPT_END |
hal_diag_excpt_end |
#endif |
|
hal_cpu_load_all |
|
#ifdef CYGPKG_CYGMON |
hal_cygmon_restore_app_stack |
#else |
add 4,sp |
#endif |
|
rti |
|
.globl hal_lsbit_table |
hal_lsbit_table: |
.byte 0, 0, 1, 0 |
.byte 2, 0, 1, 0 |
.byte 3, 0, 1, 0 |
.byte 2, 0, 1, 0 |
|
#ifdef CYGPKG_CYGMON |
.section ".bss" |
d0_save: |
.long 0 |
d1_save: |
.long 0 |
d2_save: |
.long 0 |
d3_save: |
.long 0 |
a0_save: |
.long 0 |
a1_save: |
.long 0 |
a2_save: |
.long 0 |
a3_save: |
.long 0 |
sp_save: |
.long 0 |
#endif |
|
##----------------------------------------------------------------------------- |
## Default TRAP VSR |
|
.text |
.globl __default_trap_vsr |
__default_trap_vsr: |
|
#ifdef CYG_HAL_DIAG_EXCPT_END |
hal_diag_excpt_start |
#endif |
|
# We come here with all the registers saved |
# on the stack. |
mov 8,d1 |
mov d1,(sp) # set the VSR vector number |
mov sp,a1 # a1 = saved state |
mov a1,d0 # d0 = arg1 = saved state |
|
add -16,sp # return link + arg |
mov 3,d1 # d1 = arg2 = ISR value (3 == TRAP trap) |
calls _cyg_hal_exception_handler # call C code |
add 16,sp # pop args |
|
#ifdef CYG_HAL_DIAG_EXCPT_END |
hal_diag_excpt_end |
#endif |
hal_cpu_load_all |
#ifdef CYGPKG_CYGMON |
hal_cygmon_restore_app_stack |
add 4,sp |
#else |
add 8,sp |
#endif |
rets |
|
##----------------------------------------------------------------------------- |
## VSR table. The VSRs pointed to by this table are called from the stubs |
## connected to the hardware. |
|
#ifndef CYG_HAL_MN10300_VSR_TABLE_DEFINED |
|
.data |
|
.globl _hal_vsr_table |
_hal_vsr_table: |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_interrupt_vsr |
.long __default_nmi_vsr |
.long __default_trap_vsr |
|
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
|
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
.long __default_nmi_vsr |
#endif |
|
##----------------------------------------------------------------------------- |
## Interrupt tables |
|
.data |
|
.extern _hal_default_isr |
|
.globl _hal_interrupt_handlers |
_hal_interrupt_handlers: |
.rept CYG_ISR_TABLE_SIZE |
.long _hal_default_isr |
.endr |
|
.globl _hal_interrupt_data |
_hal_interrupt_data: |
.rept CYG_ISR_TABLE_SIZE |
.long 0 |
.endr |
|
.globl _hal_interrupt_objects |
_hal_interrupt_objects: |
.rept CYG_ISR_TABLE_SIZE |
.long 0 |
.endr |
|
|
##----------------------------------------------------------------------------- |
## Temporary interrupt stack |
|
.section ".bss" |
|
.balign 16 |
.global _cyg_interrupt_stack_base |
_cyg_interrupt_stack_base: |
__interrupt_stack_base: |
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE |
.byte 0 |
.endr |
.balign 16 |
.global _cyg_interrupt_stack |
_cyg_interrupt_stack: |
__interrupt_stack: |
|
#ifdef CYGPKG_CYGMON |
.balign 16 |
.global __cygmon_interrupt_stack_base |
__cygmon_interrupt_stack_base: |
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE |
.byte 0 |
.endr |
.balign 16 |
.global __cygmon_interrupt_stack |
__cygmon_interrupt_stack: |
#endif |
|
.long 0,0,0,0,0,0,0,0 |
|
##----------------------------------------------------------------------------- |
|
.data |
hal_diag_data |
|
##----------------------------------------------------------------------------- |
## end of vectors.S |
|
/v2_0/src/mn10300_stub.c
0,0 → 1,478
//======================================================================== |
// |
// mn10300_stub.c |
// |
// Helper functions for mn10300 stub |
// |
//======================================================================== |
//####ECOSGPLCOPYRIGHTBEGIN#### |
// ------------------------------------------- |
// This file is part of eCos, the Embedded Configurable Operating System. |
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc. |
// |
// eCos is free software; you can redistribute it and/or modify it under |
// the terms of the GNU General Public License as published by the Free |
// Software Foundation; either version 2 or (at your option) any later version. |
// |
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY |
// WARRANTY; without even the implied warranty of MERCHANTABILITY or |
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
// for more details. |
// |
// You should have received a copy of the GNU General Public License along |
// with eCos; if not, write to the Free Software Foundation, Inc., |
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. |
// |
// As a special exception, if other files instantiate templates or use macros |
// or inline functions from this file, or you compile this file and link it |
// with other works to produce a work based on this file, this file does not |
// by itself cause the resulting work to be covered by the GNU General Public |
// License. However the source code for this file must still be made available |
// in accordance with section (3) of the GNU General Public License. |
// |
// This exception does not invalidate any other reasons why a work based on |
// this file might be covered by the GNU General Public License. |
// |
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc. |
// at http://sources.redhat.com/ecos/ecos-license/ |
// ------------------------------------------- |
//####ECOSGPLCOPYRIGHTEND#### |
//======================================================================== |
//#####DESCRIPTIONBEGIN#### |
// |
// Author(s): Red Hat, jskov |
// Contributors: Red Hat, jskov, dmoseley |
// Date: 1998-11-06 |
// Purpose: |
// Description: Helper functions for mn10300 stub |
// Usage: |
// |
//####DESCRIPTIONEND#### |
// |
//======================================================================== |
|
#include <stddef.h> |
|
#include <pkgconf/hal.h> |
|
#ifdef CYGPKG_REDBOOT |
#include <pkgconf/redboot.h> |
#endif |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
|
#include <cyg/hal/hal_stub.h> |
#include <cyg/hal/hal_arch.h> |
#include <cyg/hal/hal_intr.h> |
|
#ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT |
#include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id |
#endif |
|
/*---------------------------------------------------------------------- |
* Asynchronous interrupt support |
*/ |
|
typedef unsigned char t_inst; |
|
static struct |
{ |
t_inst *targetAddr; |
t_inst savedInstr; |
} asyncBuffer; |
|
/* Called to asynchronously interrupt a running program. |
Must be passed address of instruction interrupted. |
This is typically called in response to a debug port |
receive interrupt. |
*/ |
|
void |
install_async_breakpoint(void *pc) |
{ |
asyncBuffer.targetAddr = pc; |
asyncBuffer.savedInstr = *(t_inst *)pc; |
*(t_inst *)pc = (t_inst)HAL_BREAKINST; |
__instruction_cache(CACHE_FLUSH); |
__data_cache(CACHE_FLUSH); |
} |
|
/*--------------------------------------------------------------------*/ |
/* Given a trap value TRAP, return the corresponding signal. */ |
|
int __computeSignal (unsigned int trap_number) |
{ |
if (asyncBuffer.targetAddr != NULL) |
{ |
/* BP installed by serial driver to stop running program */ |
*asyncBuffer.targetAddr = asyncBuffer.savedInstr; |
__instruction_cache(CACHE_FLUSH); |
__data_cache(CACHE_FLUSH); |
asyncBuffer.targetAddr = NULL; |
return SIGINT; |
} |
#ifdef SIGSYSCALL |
switch (trap_number) |
{ |
case SIGSYSCALL: |
/* System call */ |
return SIGSYSCALL; |
} |
#endif |
return SIGTRAP; |
} |
|
/*--------------------------------------------------------------------*/ |
/* Return the trap number corresponding to the last-taken trap. */ |
|
int __get_trap_number (void) |
{ |
// The vector is not not part of the GDB register set so get it |
// directly from the save context. |
return _hal_registers->vector; |
} |
|
#if defined(CYGSEM_REDBOOT_BSP_SYSCALLS) |
int __is_bsp_syscall(void) |
{ |
return __get_trap_number() == SIGSYS; |
} |
#endif |
|
/*--------------------------------------------------------------------*/ |
/* Set the currently-saved pc register value to PC. This also updates NPC |
as needed. */ |
|
void set_pc (target_register_t pc) |
{ |
put_register (PC, pc); |
} |
|
|
/*---------------------------------------------------------------------- |
* Single-step support. Lifted from CygMon. |
*/ |
|
#define NUM_SS_BPTS 2 |
static target_register_t break_mem [NUM_SS_BPTS] = {0, 0}; |
static unsigned char break_mem_data [NUM_SS_BPTS]; |
|
/* Set a single-step breakpoint at ADDR. Up to two such breakpoints |
can be set; WHICH specifies which one to set (0 or 1). */ |
|
static void |
set_single_bp (int which, unsigned char *addr) |
{ |
if (0 == break_mem[which]) { |
break_mem[which] = (target_register_t) addr; |
break_mem_data[which] = *addr; |
*addr = HAL_BREAKINST; |
} |
} |
|
/* Clear any single-step breakpoint(s) that may have been set. */ |
|
void __clear_single_step (void) |
{ |
int x; |
for (x = 0; x < NUM_SS_BPTS; x++) |
{ |
unsigned char* addr = (unsigned char*) break_mem[x]; |
if (addr) { |
*addr = break_mem_data[x]; |
break_mem[x] = 0; |
} |
} |
} |
|
/* Read a 16-bit displacement from address 'p'. The |
value is stored little-endian. */ |
|
static short |
read_disp16(unsigned char *p) |
{ |
return (short)(p[0] | (p[1] << 8)); |
} |
|
/* Read a 32-bit displacement from address 'p'. The |
value is stored little-endian. */ |
|
static int |
read_disp32(unsigned char *p) |
{ |
return (int)(p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); |
} |
|
|
/* Get the contents of An register. */ |
|
static unsigned int |
get_areg (int n) |
{ |
switch (n) |
{ |
case 0: |
return get_register (A0); |
case 1: |
return get_register (A1); |
case 2: |
return get_register (A2); |
case 3: |
return get_register (A3); |
} |
return 0; |
} |
|
|
/* Table of instruction sizes, indexed by first byte of instruction, |
used to determine the address of the next instruction for single stepping. |
If an entry is zero, special code must handle the case (for example, |
branches or multi-byte opcodes). */ |
|
static char opcode_size[256] = |
{ |
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
/*------------------------------------------------*/ |
/* 0 */ 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, 1, 3, 3, 3, |
/* 1 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
/* 2 */ 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, |
/* 3 */ 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, |
/* 4 */ 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, 2, 2, |
/* 5 */ 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, |
/* 6 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
/* 7 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
/* 8 */ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, |
/* 9 */ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, |
/* a */ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, |
/* b */ 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, 1, 1, 1, 1, 2, |
/* c */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 2, 2, |
/* d */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, |
/* e */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
/* f */ 0, 2, 2, 2, 2, 2, 2, 1, 0, 3, 0, 4, 0, 6, 7, 1 |
}; |
|
/* Set breakpoint(s) to simulate a single step from the current PC. */ |
|
void __single_step (void) |
{ |
unsigned char *pc = (unsigned char *) get_register (PC); |
unsigned int opcode; |
int displ; |
|
opcode = *pc; |
|
/* Check the table for the simple cases. */ |
displ = opcode_size[opcode]; |
if (displ != 0) |
{ |
set_single_bp (0, pc + displ); |
return; |
} |
|
/* Handle the more complicated cases. */ |
switch (opcode) |
{ |
case 0xc0: |
case 0xc1: |
case 0xc2: |
case 0xc3: |
case 0xc4: |
case 0xc5: |
case 0xc6: |
case 0xc7: |
case 0xc8: |
case 0xc9: |
case 0xca: |
/* |
* bxx (d8,PC) |
*/ |
displ = *((signed char *)pc + 1); |
set_single_bp (0, pc + 2); |
if (displ < 0 || displ > 2) |
set_single_bp (1, pc + displ); |
break; |
|
case 0xd0: |
case 0xd1: |
case 0xd2: |
case 0xd3: |
case 0xd4: |
case 0xd5: |
case 0xd6: |
case 0xd7: |
case 0xd8: |
case 0xd9: |
case 0xda: |
/* |
* lxx (d8,PC) |
*/ |
if (pc != (unsigned char*) get_register (LAR)) |
set_single_bp (0, (unsigned char *) get_register (LAR)); |
set_single_bp (1, pc + 1); |
break; |
|
case 0xdb: |
/* |
* setlb requires special attention. It loads the next four instruction |
* bytes into the LIR register, so we can't insert a breakpoint in any |
* of those locations. |
*/ |
set_single_bp (0, pc + 5); |
break; |
|
case 0xcc: |
case 0xcd: |
/* |
* jmp (d16,PC) or call (d16,PC) |
*/ |
displ = read_disp16((char *)(pc + 1)); |
set_single_bp (0, pc + displ); |
break; |
|
case 0xdc: |
case 0xdd: |
/* |
* jmp (d32,PC) or call (d32,PC) |
*/ |
displ = read_disp32((char *)(pc + 1)); |
set_single_bp (0, pc + displ); |
break; |
|
case 0xde: |
/* |
* retf |
*/ |
set_single_bp (0, (unsigned char *) get_register (MDR)); |
break; |
|
case 0xdf: |
/* |
* ret |
*/ |
displ = *((char *)pc + 2); |
set_single_bp (0, (unsigned char *) read_disp32 ((unsigned char *) |
get_register (SP) + displ)); |
break; |
|
case 0xf0: |
/* |
* Some branching 2-byte instructions. |
*/ |
opcode = *(pc + 1); |
if (opcode >= 0xf0 && opcode <= 0xf7) |
{ |
/* jmp (An) / calls (An) */ |
set_single_bp (0, (unsigned char *) get_areg (opcode & 3)); |
|
} |
else if (opcode == 0xfc) |
{ |
/* rets */ |
set_single_bp (0, (unsigned char *) read_disp32 ((unsigned char *) |
get_register (SP))); |
|
} |
else if (opcode == 0xfd) |
{ |
/* rti */ |
set_single_bp (0, (unsigned char *) read_disp32 ((unsigned char *) |
get_register (SP) + 4)); |
|
} |
else |
set_single_bp (0, pc + 2); |
|
break; |
|
case 0xf8: |
/* |
* Some branching 3-byte instructions. |
*/ |
opcode = *(pc + 1); |
if (opcode >= 0xe8 && opcode <= 0xeb) |
{ |
displ = *((signed char *)pc + 2); |
set_single_bp (0, pc + 3); |
if (displ < 0 || displ > 3) |
set_single_bp (1, pc + displ); |
|
} |
else |
set_single_bp (0, pc + 3); |
break; |
|
case 0xfa: |
opcode = *(pc + 1); |
if (opcode == 0xff) |
{ |
/* calls (d16,PC) */ |
displ = read_disp16((char *)(pc + 2)); |
set_single_bp (0, pc + displ); |
} |
else |
set_single_bp (0, pc + 4); |
break; |
|
case 0xfc: |
opcode = *(pc + 1); |
if (opcode == 0xff) |
{ |
/* calls (d32,PC) */ |
displ = read_disp32((char *)(pc + 2)); |
set_single_bp (0, pc + displ); |
} |
else |
set_single_bp (0, pc + 6); |
break; |
|
} |
} |
|
void __install_breakpoints (void) |
{ |
/* NOP since single-step HW exceptions are used instead of |
breakpoints. */ |
|
/* Install the breakpoints in the breakpoint list */ |
__install_breakpoint_list(); |
} |
|
void __clear_breakpoints (void) |
{ |
__clear_breakpoint_list(); |
} |
|
|
/* If the breakpoint we hit is in the breakpoint() instruction, return a |
non-zero value. */ |
|
int |
__is_breakpoint_function () |
{ |
return get_register (PC) == (target_register_t)&CYG_LABEL_NAME(_breakinst); |
} |
|
|
/* Skip the current instruction. */ |
|
void __skipinst (void) |
{ |
unsigned char *pc = (char *) get_register (PC); |
|
switch (*pc) |
{ |
case 0xff: // breakpoint instruction |
pc++; |
break; |
case 0xf0: // Assume syscall trap (0xf0, 0x20) |
pc += 2; |
break; |
default: |
pc++; // Assume all other instructions |
break; // are one byte |
} |
|
put_register (PC, (target_register_t) pc); |
} |
|
#endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS |
/v2_0/ChangeLog
0,0 → 1,913
2003-01-31 Mark Salter <msalter@redhat.com> |
|
* src/hal_syscall.c (hal_syscall_handler): Let generic syscall code |
handle exit. |
|
2002-12-06 Mark Salter <msalter@redhat.com> |
|
* cdl/hal_mn10300.cdl: Add CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP. |
* include/hal_intr.h: Support CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP. |
|
2002-04-29 Jonathan Larmour <jlarmour@redhat.com> |
|
* src/vectors.S: |
Don't use .file as it can confuse debugging since the .file |
doesn't contain the path and therefore the debugger will never |
know where it lives! This conflicts with using -Wa,--gstabs. |
|
2002-04-15 Jonathan Larmour <jlarmour@redhat.com> |
|
* src/hal_syscall.c (hal_syscall_handler): Add extra sig argument to |
__do_syscall. |
|
2001-11-16 Nick Garnett <nickg@redhat.com> |
|
* src/hal_misc.c (hal_msbit_index): Fixed this function so that it |
actually works! |
|
2001-10-16 David Howells <dhowells@redhat.com> |
|
* src/hal_syscall.c: mustn't increment the return address by 4. |
* cdl/hal_mn10300.cdl: moved the RTC configuration previously |
added to the ASB2305 platform. |
|
2001-10-16 David Howells <dhowells@redhat.com> |
|
* src/vectors.S: conditionally call diagnostic macros on entry and |
exit to default NMI handler and make inclusion of RedBoot header |
file conditional. |
|
2001-10-15 David Howells <dhowells@redhat.com> |
|
* include/mn10300_stub.h: added syscall handling. |
* src/hal_syscall.c: ditto |
* src/mn10300_stub.c: ditto |
* src/vectors.S: ditto |
* cdl/hal_mn10300.cdl: added RTC configuration. |
|
2001-07-27 David Howells <dhowells@redhat.com> |
|
* include/mn10300_stub.h: set NUMREGS to be the correct value to |
keep gdb happy. |
* include/hal_io.h: refer to plf_io.h |
* include/arch.inc: note presence of the ASB2305 platform |
* src/vectors.S: Adjusted exception handling to be able to cope |
with AM33v2 exceptions. |
|
2001-01-18 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: Added underscore to reference to |
cyg_scheduler_sched_lock, since CYGBLD_ATTRIB_ASM_ALIAS() now adds |
one automatically. |
|
2000-11-30 Drew Moseley <dmoseley@redhat.com> |
|
* include/hal_arch.h: Handle Cygmon interrupt stack. ie For |
Cygmon we must switch to a new stack immediately on exception to |
make sure that we don't modify the application stack at all since |
GDB may be using it. |
* src/vectors.S: Ditto. |
|
2000-10-20 Jesper Skov <jskov@redhat.com> |
|
* src/hal_misc.c: Update __mem_fault_handler declaration. |
|
2000-09-04 Jonathan Larmour <jlarmour@redhat.com> |
|
* include/basetype.h (CYGARC_ALIGNMENT): mn10300 has 4 byte alignment |
(CYGARC_P2ALIGNMENT): Likewise |
|
2000-08-29 Jonathan Larmour <jlarmour@redhat.co.uk> |
|
* src/vectors.S (__default_nmi_vsr): Fix quoting in comment problem |
|
2000-08-15 Drew Moseley <dmoseley@redhat.com> |
|
* src/mn10300_stub.c (__is_breakpoint_function): Prepend an _ to |
breakinst. Apparently the symbol generation has changed requiring |
this. |
|
2000-08-14 Drew Moseley <dmoseley@redhat.com> |
|
* src/vectors.S: Use some generic MN10300 code rather than AM33-specific. |
|
* include/mn10300_stub.h: Some cleanups of AM33/2.00 includes. |
|
* src/mn10300_stub.c (__computeSignal): Make sure SIGSYSCALL is |
defined before returning it. |
|
2000-08-12 Drew Moseley <dmoseley@redhat.com> |
|
* include/mn10300_stub.h: More rearranging of GDB regnames. |
|
2000-08-11 Drew Moseley <dmoseley@redhat.com> |
|
* include/mn10300_stub.h: Rearranged regnames to correspond to |
what GDB is expecting. |
|
* include/arch.inc: Fixed error in declaration of hal_intc_decode. |
|
2000-08-10 Drew Moseley <dmoseley@redhat.com> |
|
* src/vectors.S: Added syscall handling. |
Added HAL_EARLY_INIT. |
Added CTRLC_SUPPORT. |
Added CYGMON support. |
|
* src/mn10300_stub.c: Added breakpoint list handling. |
Added syscall handling. |
|
* src/hal_misc.c (cyg_hal_exception_handler): Added support for |
exceptions caused by the stubs which are passed transparently |
back. |
Also added VIRTUAL_VECTOR support. |
|
* include/hal_arch.h: Added HAL_BREAKINST_TYPE. |
Added Cygmon support. |
|
* include/arch.inc: Added AM33/2.00 board support. |
|
* include/mn10300_stub.h: Added AM33/2.00 support. |
|
* cdl/hal_mn10300.cdl: Added option for CTRLC_SUPPORT. |
* include/pkgconf/hal_mn10300.h: Ditto. |
|
2000-06-21 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h: Added underscores to label in |
HAL_BREAKINST(). |
|
* include/basetype.h: |
Removed definition of CYG_LABEL_NAME() and added one for |
CYG_LABEL_DEFN(). |
|
2000-06-08 Jesper Skov <jskov@redhat.com> |
|
* include/hal_arch.h (CYGARC_HAL_SAVE_GP, CYGARC_HAL_RESTORE_GP): |
Added. |
|
2000-03-20 Jonathan Larmour <jlarmour@redhat.co.uk> |
|
* src/vectors.S (__default_interrupt_vsr): Pass variant-specific PC |
offset from register context into cyg_hal_gdb_isr() |
|
* include/hal_arch.h: Move HAL_SavedRegisters into variant HALs |
|
2000-03-19 Jonathan Larmour <jlarmour@redhat.co.uk> |
|
* include/mn10300_stub.h: Make C++ safe |
|
2000-02-16 Jesper Skov <jskov@redhat.com> |
|
* cdl/hal_mn10300.cdl: remove fix me. |
|
1999-11-09 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/hal_intr.h (HAL_RESTORE_INTERRUPTS): Ensure we restore the |
old state exactly, including "restoring" by disabling interrupts |
Requested by Matsushita in case 102544 |
|
1999-12-02 John Dallaway <jld@cygnus.co.uk> |
|
* cdl/hal_mn10300.cdl: |
|
Use the <PACKAGE> token in custom rules. |
|
1999-12-01 John Dallaway <jld@cygnus.co.uk> |
|
* cdl/hal_mn10300.cdl: |
|
Use the <PREFIX> token in custom rules. |
|
1999-11-04 John Dallaway <jld@cygnus.co.uk> |
|
* cdl/hal_mn10300.cdl: |
|
Output custom rule dependency information to .deps files in |
the current directory. |
|
Dispense with the need to create a 'src' sub-directory. |
|
1999-11-03 Jesper Skov <jskov@cygnus.co.uk> |
|
* cdl/hal_mn10300.cdl: Added. |
|
1999-09-10 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/hal_cache.h: Change CYG_HAL_MN10300_SIM to |
CYG_HAL_MN10300_AM31_SIM |
Only include var_cache.h when not sim |
|
1999-08-18 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c (cyg_hal_exception_handler): |
Use CYGNUM_HAL_EXCEPTION_WATCHDOG rather than |
CYGNUM_HAL_INTERRUPT_WATCHDOG in test for watchdog exceptions. |
|
1999-08-17 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/arch.inc: Modified hal_cpu_int_merge to avoid corrupting |
any registers other than the one passed as an argument. |
|
1999-08-16 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/arch.inc: rename CYGPKG_HAL_MN10300_AM32_STDEVAL1 to |
CYGPKG_HAL_MN10300_AM31_STDEVAL1 |
|
1999-08-13 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/arch.inc: Moved AM33 trace address to uncached memory |
window. |
|
* src/vectors.S (_start): Tidied away some superfluous trace |
code. |
|
1999-08-12 Nick Garnett <nickg@cygnus.co.uk> |
|
Imported following changed from development branch. |
|
1999-08-11 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: Removed debug code. |
|
* include/hal_intr.h: Made mn10300_interrupt_control[] unsized |
since it is different sizes on different variants. |
|
* include/arch.inc: |
Changed hal_cpu_int_merge so that both the IE and IPL bits are |
changed across a thread switch. |
Some minor tweaks to trace code for AM32. |
|
1999-08-10 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/pkgconf/hal_mn10300.h: |
Move CYGPKG_HAL_MN10300's "target mn10300" under the variant |
packages instead. |
Add CYGPKG_HAL_MN10300_VARIANTS |
|
1999-07-30 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: Added default ISR. |
|
* src/vectors.S: |
Added Ctrl-C support. Extended VSR table to include new |
exceptions. Install default ISR by default. |
|
* src/mn10300_stub.c: |
Added asynchronous breakpoint support. |
[Later] Tidied up install_async_breakpoint() and fixed indirection |
bug. |
|
* include/hal_intr.h: |
Added default ISR. Removed HAL_INTERRUPT_CONFIGURE(), this is now |
variant-specific. |
|
1999-07-27 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Some reorganization to make code more generic. |
Some diagnostic macros added. |
Note: some trace/debug code has been left in place temporarily, |
this will be removed eventually. |
|
* include/mn10300_stub.h: Added extra regnames for AM33. |
|
* include/hal_arch.h: |
Added macros to get and set extra registers for AM33. |
* include/arch.inc: |
Changed all *_MIPS_* to *_MN10300_*. |
Added some temporary trace/debug macros. |
|
1999-07-16 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: |
* include/hal_arch.h: |
Added hal_idle_thread_action(); |
|
* include/arch.inc: Made hal_cpu_init definition optional. |
|
1999-07-08 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Moved some code to variant specific macros. Now pass ISR register |
to cyg_hal_exception_handler() to enable further decoding. |
|
* src/hal_misc.c (cyg_hal_exception_handler): |
Added extra argument to pass ISR register value. Now decodes ISR |
value to specify extra exceptions. |
|
1999-07-07 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_intr.h: |
Added HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() macro to support |
calling of DSRs on the interrupt stack. |
|
* include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): |
Initialize the PSW to enable all interrupts on entry to thread. |
|
* include/arch.inc: |
Added implementations of CPU control macros. |
|
* src/context.S: |
Added code to preserve PSW across context switches. |
|
* src/vectors.S: |
Implemented mechanism to call DSRs on the interrupt stack. |
Refined condition for defining VSR table here. |
|
1999-06-30 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/context.S: |
* src/vectors.S: |
Use hal_cpu_save_all and hal_cpu_load_all macros to save and |
restore CPU register sets. |
|
* include/hal_arch.h: |
Modified HAL_THREAD_INIT_CONTEXT_EXTRA() to take some arguments. |
|
1999-06-29 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h: |
Added code in preparation for AM33 port. |
Added include of variant header. |
|
* include/hal_cache.h: |
* include/hal_intr.h: |
* src/vectors.S: |
* src/hal_misc.c: |
Extensive changes to convert to new HAL organization. These mostly |
involve moving variant and platform specific stuff out to the |
appropriate headers in the variant and platform directories. |
|
* src/PKGconf.mak: |
* src/mn10300.ld (removed): |
Moved build of target.ld to variant directory. |
|
* include/arch.inc: |
Added this file to contain architecture specific macros. |
|
1999-06-08 Jesper Skov <jskov@cygnus.co.uk> |
|
* src/hal_misc.c (cyg_hal_dcache_store): Only define for HW target. |
|
1999-06-07 Jesper Skov <jskov@cygnus.co.uk> |
PR 20136 |
* src/hal_misc.c (cyg_hal_dcache_store): |
* include/hal_cache.h (HAL_DCACHE_STORE): |
DCACHE store operation needs 4 register variables. Put it in a |
separate function to ensure registers are availble. |
|
1999-05-21 Hugo Tyson <hmt@masala.cygnus.co.uk> |
|
* include/hal_intr.h: Define HAL_INTERRUPT_STACK_BASE and |
HAL_INTERRUPT_STACK_TOP so that stack usage macros in |
kernel/.../stackmon.hxx can work. |
|
* src/vectors.S (cyg_interrupt_stack_base): Define this symbol for |
the interrupt stack and its friend for the stack top so that we |
can publish them with nice names. |
|
1999-05-13 Hugo Tyson <hmt@cygnus.co.uk> |
|
* include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align stack |
(rather conservatively) before use. |
|
1999-04-28 Bart Veer <bartv@cygnus.co.uk> |
|
* src/PKGconf.mak: |
Remove the -n argument to tail, it does not appear to be required |
on any supported host and causes problems with some |
implementations of tail. |
|
1999-04-20 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/hal_cache.h: |
(HAL_DCACHE_IS_ENABLED) (HAL_ICACHE_IS_ENABLED): Add these new macros |
(HAL_DCACHE_DISABLE) (HAL_ICACHE_DISABLE): Make variables register |
variables |
Ensure the cache has finished its operation before exitting. |
(HAL_DCACHE_INVALIDATE_ALL) (HAL_ICACHE_INVALIDATE_ALL): Make |
variables register variables. |
Re-enable cache if it was enabled on entry. |
(HAL_DCACHE_WRITE_MODE): Make variables register variables. |
Re-enable data cache if it was enabled on entry. |
Ensure the cache has finished its operation before exitting. |
(HAL_DCACHE_STORE): Make variables register variables. |
Re-enable data cache if it was enabled on entry. |
|
These fix PR19887 |
|
1999-04-15 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/mn10300.ld: Define __bss_end at the end of the BSS |
* src/vectors.S (_start): Use __bss_end rather than _end when clearing |
BSS |
These fix PR 19750 |
|
1999-04-15 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/hal_misc.c: |
* src/vectors.S: |
Separate parts of cyg_hal_invoke_constructors() out into new functions |
cyg_hal_enable_caches() and cyg_hal_debug_init() so that |
cyg_hal_invoke_constructors() can be called again safely if |
necessary |
Fix for PR19642 |
|
1999-04-14 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/PKGconf.mak (EXTRAS): Don't generate extras.o here any more |
But do define EXTRAS every time for the linker script. |
|
1999-04-09 Jesper Skov <jskov@cygnus.co.uk> |
|
* src/mn10300_stub.c: |
Moved get_register and put_register to hal_stub.c. |
|
1999-04-08 John Dallaway <jld@cygnus.co.uk> |
|
* src/*.ld: Revised SECTION_* macro arguments to |
avoid padded output sections (PR 19787) |
|
1999-03-31 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h (HAL_THREAD_INIT_CONTEXT): Align initial SP |
to a 4 byte boundary. Fixes PR 19695. |
|
* include/hal_cache.h: Added include of hal.h and a test that a |
valid set of macros have been added. |
|
1999-03-26 Gary Thomas <gthomas@cygnus.co.uk> |
|
* include/hal_arch.h (CYGNUM_HAL_STACK_SIZE_MINIMUM): Be a little |
more generous since this stack should allow at least a kernel API |
call which could be at least 4 levels deep. |
|
1999-03-23 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h: |
Modified stack size definitions to be more accurate. |
|
1999-03-22 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/mn10300_stub.h: Update copyright |
|
* src/mn10300_stub.c: Update copyright |
|
1999-03-22 Hugo Tyson <hmt@cygnus.co.uk> |
|
* include/hal_arch.h: |
Use CYGNUM_HAL_STACK_SIZE_TYPICAL for the stack size instead of |
CYGNUM_HAL_MINIMUM_STACK_SIZE. |
|
1999-03-19 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: |
* src/vectors.S: |
Fixed problem with taking breakpoints after watchdog interrupts |
and memory access exceptions. See the comments in |
__default_nmi_vsr in vector.S for details. |
|
1999-03-17 John Dallaway <jld@cygnus.co.uk> |
|
* src/PKGconf.mak: Remove dependence on echo '-e' switch. |
|
1999-03-12 Gary Thomas <gthomas@cygnus.co.uk> |
|
* include/hal_arch.h: Add definition of 'CYGNUM_HAL_MINIMUM_STACK_SIZE' |
|
1999-03-10 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/hal_intr.h (HAL_INTERRUPT_ATTACH): Added. |
|
1999-03-08 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/mn10300.ld: |
Added alignment before definition of __DEVTAB__. |
|
1999-03-05 Gary Thomas <gthomas@cygnus.co.uk> |
|
* src/PKGconf.mak: |
* src/mn10300.ld: Clean up I/O package changes. |
|
1999-03-04 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/mn10300.ld: |
Unconditionalize use of libextras.a and add to GROUP() |
|
1999-02-25 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: |
Now tests for whether the kernel is present before trying to use |
patch_dbg_syscalls(). |
|
* include/hal_intr.h (HAL_INTERRUPT_CONFIGURE): fixed some compile |
bugs in this macro. |
|
* src/vectors.S: |
Changed label used to access scheduler lock to one that is not |
mangled by C++. This is intended to make support for interrupt |
handling in non-kernel configurations easier. |
|
1999-02-20 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* include/hal_arch.h: |
Rename deliver_exception() -> cyg_hal_deliver_exception() |
QA improvements |
|
* include/hal_intr.h: |
Reorganise vector/interrupt/exception names according to purpose |
QA improvements |
|
* src/hal_misc.c: |
Rename deliver_exception() -> cyg_hal_deliver_exception() |
Rename CYG_VECTOR_* according to hal_intr.h changes above |
QA improvements |
|
* src/vectors.S: |
Rename exception_handler() -> cyg_hal_exception_handler() |
|
1999-02-16 Jesper Skov <jskov@cygnus.co.uk> |
|
* src/vectors.S: Changed set_debug_traps to initialize_stub. |
|
* src/mn10300_stub.c: |
* include/mn10300_stub.h: |
Cleaned up to only include arch specific stub code. |
|
1999-02-15 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/basetype.h: Added CYG_LABEL_NAME macro. |
|
1999-02-11 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_cache.h (HAL_DCACHE_STORE): |
Added "register" keywords to the variables used in this macro. If |
these are not in registers then when the cache is disabled, they |
can be stranded in the cache and the random values in main memory |
are used instead. This is only a problem when optimization is |
disabled; under optimization the compiler puts these variables |
into registers as a matter of course. |
Fixes PR 19165. |
(HAL_DCACHE_SYNC): Divide cache size by number of ways to |
calculate correct size to pass to HAL_DCACHE_STORE(). |
|
1999-02-05 John Dallaway <jld@cygnus.co.uk> |
|
* src/mn10300.ld: Add LMA_EQ_VMA macro definition. |
|
1999-02-01 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_cache.h: Fixed implementation of HAL_DCACHE_STORE() so |
that it now works, and changed implementation of HAL_DCACHE_SYNC() |
to use it. |
Fixes PR 18577 and is a better fix to 18849. |
|
1999-01-27 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_intr.h: |
* src/vectors.S: |
Allow for NMI vectors in ISR table when using chained |
interrupts. This largely consists of moving the interrupt vector |
slots up by 3 entries. |
|
1999-01-26 Hugo Tyson <hmt@masala.cygnus.co.uk> |
|
* src/mn10300.ld: |
Add copyright notice. (Though these files will later be generated |
by a tool and so not copyright, these default setups are.) |
|
1999-01-25 Jesper Skov <jskov@cygnus.co.uk> |
|
* src/mn10300_stub.c (__build_t_packet): Rewrote fix me text. Added PR |
number, but otherwise left the note. |
|
1999-01-25 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_cache.h (HAL_DCACHE_SYNC): Add implementation of |
this macro to enable test programs to work. |
Fixes PR 18849. |
|
1999-01-21 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/hal_misc.c (cyg_hal_invoke_constructors): |
Add code to deal with CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG |
Tidy up and update description header |
Shorten needlessly long lines |
Remove all traces of non-CYG_KERNEL_USE_INIT_PRIORITY code |
|
1999-01-14 John Dallaway <jld@cygnus.co.uk> |
|
* src/mn10300.ld: do not define _hal_vsr_table for minimal |
simulator builds |
|
1999-01-13 Gary Thomas <gthomas@cygnus.co.uk> |
|
* include/basetype.h: CYG_DOUBLE_BYTEORDER now in <infra/cyg_type.h> |
|
1999-01-13 John Dallaway <jld@cygnus.co.uk> |
|
* src/mn10300.ld: define FOLLOWING () macro to simplify |
hand editing of linker script fragments |
|
1999-01-12 Gary Thomas <gthomas@cygnus.co.uk> |
|
* include/basetype.h (CYG_DOUBLE_BYTEORDER): Define ordering |
for words within doubles. |
|
1999-01-12 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: Altered call to patch_dbg_syscalls() to pass |
pointer to base of vector rather than a single vector entry. |
|
1999-01-12 John Dallaway <jld@cygnus.co.uk> |
|
* src/mn10300.ld: new linker script for MLT |
* src/PKGconf.mak: add mn10300.ld rules for MLT |
|
1998-12-15 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/hal_arch.h: |
* src/context.S (_hal_setjmp, _hal_longjmp): |
Added CYGARC definitions for jmpbuf entries. |
|
1998-12-10 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/hal_cache.h (HAL_DCACHE_UNLOCK_ALL, |
HAL_ICACHE_UNLOCK_ALL): Added. |
|
1998-11-25 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/hal_arch.h (HAL_REORDER_BARRIER): Changed to same form |
as on the other archs. |
|
1998-11-18 Gary Thomas <gthomas@cygnus.co.uk> |
|
* include/hal_intr.h: Add support for interrupt latency |
measurement, controlled by CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY. |
|
1998-11-09 Jesper Skov <jskov@cygnus.co.uk> |
|
* src/vectors.S (__default_interrupt_vsr): Added GDB break |
support. |
Added call to GDB initialization during startup. |
|
* src/mn10300_stub.c: Changed instruction word type. |
|
1998-11-06 Jesper Skov <jskov@lassi.cygnus.co.uk> |
|
* src/PKGconf.mak: |
Added stub to object list. |
|
* include/mn10300_stub.h: |
* src/mn10300_stub.c: |
Added GDB stub. |
|
* src/hal_misc.c (exception_handler): Added GDB stub call. |
|
1998-11-06 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/basetype.h (CYG_BYTEORDER): Fixed comment. |
|
1998-11-16 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_cache.h: |
Added volatile keyword to appropriate places to prevent compiler |
optimizing out cache control register access. |
|
1998-10-21 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_intr.h (HAL_CLOCK_READ): |
Fixed this macro to return correct value. |
|
1998-10-16 Bart Veer <bartv@cygnus.co.uk> |
|
* src/vectors.S (__interrupt_stack): |
Made the interrupt stack size configurable. |
|
1998-10-16 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: |
Enabled caches by default. |
|
1998-10-13 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/hal_misc.c: |
Altered ifdefs to allow builds without kernel. |
|
Thu Sep 24 18:14:19 1998 Jesper Skov <jskov@cygnus.co.uk> |
|
* include/hal_intr.h: Read the interrupt control registers back |
after writing to them to ensure that the value is not sitting in |
the store buffer. |
Also put _ around variable names in HAL_INTERRUPT_CONFIGURE for |
consistency. |
|
1998-09-24 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_intr.h: |
Inverted mask for level in HAL_INTERRUPT_SET_LEVEL(). |
|
* src/vectors.S: |
Added correct implementations of decode_interrupt macro for |
chained interrupt processing. |
Modified call to cyg_instrument() to pass table offset as well as |
vector number. |
Include <pkgconf/kernel.h> to allow call to cyg_instrument() to be |
enabled. |
|
1998-09-14 Bart Veer <bartv@cygnus.co.uk> |
|
* src/PKGconf.mak: |
Made vectors.o dependent on the various files that can contain |
makefile variables or rules. This is needed after changes to |
pkgconf.tcl for PRs 17195 and 17286. |
|
Mon Sep 14 11:08:40 1998 Jesper Skov <jskov@lassi.cygnus.co.uk> |
PR 17230 |
|
* include/hal_intr.h: |
* src/vectors.S: |
Replaced CYGIMP_KERNEL_INTERRUPTS_CHAIN with new |
CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN. |
|
1998-09-12 Bart Veer <bartv@cygnus.co.uk> |
|
* include/pkgconf/hal_mn10300.h: |
Added missing descriptions (PR 17184) |
|
* src/hal_misc.c (exception_handler): |
Sort out exception handling options (PR 16953) |
|
Thu Sep 10 20:24:02 1998 Hugo Tyson <hmt@cygnus.co.uk> |
|
* src/vectors.S (__default_interrupt_vsr): |
Fix a bug. Wrong offset when restoring the PSW tends to screw |
things up rather. |
|
Thu Sep 10 15:12:21 1998 Jesper Skov <jskov@lassi.cygnus.co.uk> |
PR 17153 |
|
* src/vectors.S (__default_interrupt_vsr): Pass correct vector |
value to isr. |
|
1998-09-09 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h: |
Removed distinction between interrupt and thread switch contexts |
in HAL_SavedRegisters. Modified appropriate macros to reflect this. |
|
* src/hal_misc.c (cyg_hal_invoke_constructors): |
Added call to patch_dbg_syscalls() for Cygmon hosted builds. |
|
* src/context.S (_hal_thread_switch_context): |
Adjust thread context so that it has the same structure as the |
state saved by interrupt and exception handlers. This makes |
supporting thread-aware debugging easier. |
|
* src/vectors.S: |
Moved nmi and trap vectors to correct slots in vsr table. |
Now place arg3 of interrupt_end() in correct stack slot. |
|
1998-09-04 Bart Veer <bartv@cygnus.co.uk> |
|
* src/vectors.S (__default_interrupt_vsr): |
Fixed type in configuration option name. |
|
Thu Sep 3 15:15:57 1998 Tim Goodwin <tgoodwin@cygnus.co.uk> |
|
* hal/mn10300/arch/current/src/PKGconf.mak |
* hal/mn10300/arch/current/src/makefile |
* hal/mn10300/arch/current/tests/PKGconf.mak |
|
s/panx/mn10300/g |
|
1998-09-03 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Fixed offset bug in __trap. |
Changed conditionals on runtime initialisation of VSR table to not |
do it in simulated targets. |
|
1998-09-02 Bart Veer <bartv@cygnus.co.uk> |
|
* include/pkgconf/hal_mn10300.h: |
New header file for architecture-specific configuration options |
|
* tests/PKGconf.mak: |
* src/PKGconf.mak: |
Sort out package naming conventions. |
|
1998-09-02 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Moved NMI and TRAP VSRs down 1 word to match cygmon's use of the |
vector table. This may need to change back in the future. |
|
1998-09-01 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_intr.h: |
Added CYG_VSR_COUNT, CYG_EXCEPTION_COUNT and CYG_ISR_COUNT. |
Modified HAL_TRANSLATE_VECTOR() for mn103002 to provide slots |
for the NMI vectors at start of hal_interrupt_* tables. |
|
* src/hal_misc.c (exception_handler): |
Added support for decoding NMI vectors and for calling watchdog |
ISR if present. |
|
* src/vectors.S: |
Modified behaviour of __default_nmi_vsr to support watchdog timer |
properly. |
Fixed indirection bug in __nmi and __trap. |
Modified offsets in hal_interrupt_* tables to provide slots for |
NMI vectors at start in mn103002. |
|
1998-08-28 Bart Veer <bartv@cygnus.co.uk> |
|
* src/vectors.S, src/context.S, src/hal_misc.c, include/hal_intr.h: |
Updated for new kernel configuration option symbol names |
|
Fri Aug 28 10:09:03 1998 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/hal_misc.c: |
rename __main() to cyg_hal_invoke_constructors() and remove |
initialised test |
|
* src/vectors.S (_start): |
Change call of __main() to cyg_hal_invoke_constructors(), and call |
of main() to cyg_start() |
|
1998-08-25 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Now pass pointer to saved registers as third argument to |
interrupt_end(). |
|
* include/hal_arch.h: |
Added macros to support GDB. |
|
1998-08-21 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_cache.h: |
Now includes cyg_type.h rather than ktypes.h. |
|
* src/hal_misc.c: |
Added calls to turn the caches on. But disabled them |
since they interact poorly with Cygmon (Cygmon does not |
flush the caches when setting/clearing breakpoints). |
|
Wed Aug 19 18:19:32 1998 Jonathan Larmour <jlarmour@cygnus.co.uk> |
|
* src/hal_misc.c (__main): |
Add void to function prototypes to silence warnings |
|
1998-08-18 Nick Garnett <nickg@cygnus.co.uk> |
|
* include/hal_arch.h: |
* include/hal_intr.h: |
Now includes cyg_type.h rather than ktypes.h. |
|
* src/context.S: |
* src/vectors.S: |
* src/hal_misc.c: |
Now uses hal.h rather than kernel.h. |
|
1998-08-17 Nick Garnett <nickg@cygnus.co.uk> |
|
* src/vectors.S: |
Reorgnized ifdefs to better support kernel porting. |
|
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