OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/ecos-2.0/packages/hal/mn10300/asb2305/v2_0/src
    from Rev 27 to Rev 174
    ↔ Reverse comparison
  •

Rev 27 → Rev 174

/ser_asb.c
0,0 → 1,506
//=============================================================================
//
// ser_asb.c
//
// Simple driver for the serial controllers on the AM33 ASB305 board
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors:dmoseley, nickg, gthomas
// Date: 2001-05-18
// Description: Simple driver for the ASB2305 debug serial port
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#if defined(CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS > 0
 
/*---------------------------------------------------------------------------*/
/* From serial_16550.h */
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x78
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x3C
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x1E
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x14
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x0A
#endif
 
#ifndef CYG_DEVICE_SERIAL_BAUD_MSB
#error Missing/incorrect serial baud rate defined - CDL error?
#endif
 
/*---------------------------------------------------------------------------*/
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x0C // line control register, read/write
#define CYG_DEV_MCR 0x10 // modem control register, read/write
#define CYG_DEV_LSR 0x14 // line status register, read
#define CYG_DEV_MSR 0x18 // modem status register, read
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
#define LSR_WAIT_FOR(STATE) do { cyg_uint8 lsr; do { HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); } while (!(lsr&SIO_LSR_##STATE)); } while(0)
#define LSR_QUERY(STATE) ({ cyg_uint8 lsr; HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); (lsr&SIO_LSR_##STATE); })
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS
#define FLOWCTL_QUERY(LINE) ({ cyg_uint8 msr; HAL_READ_UINT8(base+CYG_DEV_MSR, msr); (msr&SIO_MSR_##LINE); })
#define FLOWCTL_WAIT_FOR(LINE) do { cyg_uint8 msr; do { HAL_READ_UINT8(base+CYG_DEV_MSR, msr); } while (!(msr&SIO_MSR_##LINE)); } while(0)
#define FLOWCTL_CLEAR(LINE) do { cyg_uint8 mcr; HAL_READ_UINT8(base+CYG_DEV_MCR,mcr); mcr &= ~SIO_MCR_##LINE; HAL_WRITE_UINT8(base+CYG_DEV_MCR, mcr); } while (0);
#define FLOWCTL_SET(LINE) do { cyg_uint8 mcr; HAL_READ_UINT8(base+CYG_DEV_MCR,mcr); mcr |= SIO_MCR_##LINE; HAL_WRITE_UINT8(base+CYG_DEV_MCR, mcr); } while (0);
 
#else
#define FLOWCTL_QUERY(LINE) 1
#define FLOWCTL_WAIT_FOR(LINE) do { ; } while(0)
#define FLOWCTL_CLEAR(LINE) do { ; } while(0)
#define FLOWCTL_SET(LINE) do { ; } while(0)
 
#endif
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
static channel_data_t asb2305_serial_channels[] = {
{ (cyg_uint8*)0xA6FB0000, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_0_RX }
};
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(const void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lcr;
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
lcr |= SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO
 
FLOWCTL_CLEAR(DTR);
FLOWCTL_CLEAR(RTS);
}
 
static void
cyg_hal_plf_serial_putc_aux(cyg_uint8* base, char c)
{
LSR_WAIT_FOR(THRE);
 
FLOWCTL_WAIT_FOR(CTS);
 
HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
CYGARC_HAL_SAVE_GP();
 
FLOWCTL_SET(DTR);
 
cyg_hal_plf_serial_putc_aux(base,c);
 
FLOWCTL_CLEAR(DTR);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 
if (!LSR_QUERY(DR))
return false;
 
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
/* see if there's some cached data in the FIFO */
if (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)) {
/* there isn't - open the flood gates */
FLOWCTL_WAIT_FOR(DSR);
FLOWCTL_SET(RTS);
 
while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
FLOWCTL_CLEAR(RTS);
}
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
CYGARC_HAL_SAVE_GP();
 
FLOWCTL_SET(DTR);
 
while(__len-- > 0)
cyg_hal_plf_serial_putc_aux(__ch_data, *__buf++);
 
FLOWCTL_CLEAR(DTR);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
#define TM0MD 0xD4003000
#define TM0BR 0xD4003010
#define TM0BC 0xD4003020
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
#if 1
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint8 last, val;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
/* see if there's any cached data in the FIFO */
res = cyg_hal_plf_serial_getc_nonblock(__ch_data,ch);
if (!res) {
/* there isn't - open the flood gates */
delay_count = chan->msec_timeout * 125; // want delay in 8uS steps
 
HAL_WRITE_UINT8(TM0BR,200); // IOCLK is 25MHz, we want 125KHz
HAL_WRITE_UINT8(TM0MD,0x40); // stop and load
HAL_WRITE_UINT8(TM0MD,0x80); // set source to be IOCLK and go
HAL_READ_UINT8(TM0BC,last);
 
while (delay_count>0 && !FLOWCTL_QUERY(DSR)) {
HAL_READ_UINT8(TM0BC,val);
if (val==last) continue;
if (val>last)
delay_count--; // count the underflows
last = val;
}
if (delay_count==0)
goto timeout;
 
FLOWCTL_SET(RTS);
 
while (delay_count>0 && !LSR_QUERY(DR)) {
HAL_READ_UINT8(TM0BC,val);
if (val==last) continue;
if (val>last)
delay_count--; // count the underflows
last = val;
}
 
FLOWCTL_CLEAR(RTS);
 
if (LSR_QUERY(DR)) {
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
res = true;
}
 
timeout:
HAL_WRITE_UINT8(TM0MD,0x00); // stop h/w timer
}
 
CYGARC_HAL_RESTORE_GP();
return res;
 
#else
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
/* see if there's some cached data in the FIFO */
res = cyg_hal_plf_serial_getc_nonblock(__ch_data,ch);
if (!res) {
/* there isn't - open the flood gates */
delay_count = chan->msec_timeout * 1000; // want delay in uS steps
 
for (; delay_count>0 && !FLOWCTL_QUERY(DSR); delay_count--)
CYGACC_CALL_IF_DELAY_US(1);
if (delay_count==0)
goto timeout;
 
FLOWCTL_SET(RTS);
 
for (; delay_count>0 && !LSR_QUERY(DR); delay_count--)
CYGACC_CALL_IF_DELAY_US(1);
 
FLOWCTL_CLEAR(RTS);
 
if (LSR_QUERY(DR)) {
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
res = true;
}
 
}
 
timeout:
CYGARC_HAL_RESTORE_GP();
return res;
#endif
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
 
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
char c;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
cyg_drv_interrupt_acknowledge(chan->isr_vector);
 
*__ctrlc = 0;
HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
if ( (lsr & SIO_LSR_DR) != 0 ) {
 
HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(asb2305_serial_channels[0].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel(&asb2305_serial_channels[0]);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &asb2305_serial_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
 
#if defined(CYGNUM_HAL_AM33_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_SERIAL_CHANNELS > 0
cyg_hal_am33_serial_init(1);
#endif
}
 
#endif // defined(CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS > 0
 
/*---------------------------------------------------------------------------*/
/* End of ser_asb.c */
/plf_stub.c
0,0 → 1,202
//=============================================================================
//
// plf_stub.c
//
// Platform specific code for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors:dmoseley
// Date: 2001-05-17
// Purpose: Platform specific code for GDB stub support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/hal_io.h> // HAL IO macros
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
#include <cyg/hal/hal_intr.h> // HAL interrupt macros
 
/*---------------------------------------------------------------------------*/
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x0C // line control register, read/write
#define CYG_DEV_MCR 0x10 // modem control register, read/write
#define CYG_DEV_LSR 0x14 // line status register, read
#define CYG_DEV_MSR 0x18 // modem status register, read
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
#define SERIAL0BASE 0x86FB0000
 
//---------------------------------------------------------------------------
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
// This ISR is called from the interrupt handler. This should only
// happen when there is no serial driver, so the code shouldn't mess
// anything up.
int cyg_hal_gdb_isr(cyg_uint32 vector, target_register_t pc)
{
if ( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX == vector ) {
cyg_uint8 c;
 
HAL_READ_UINT8(SERIAL0BASE+CYG_DEV_RBR,c);
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SERIAL_0_RX);
 
if( 3 == c )
{
// Ctrl-C: set a breakpoint at PC so GDB will display the
// correct program context when stopping rather than the
// interrupt handler.
cyg_hal_gdb_interrupt (pc);
 
// Interrupt handled. Don't call ISR proper. At return
// from the VSR, execution will stop at the breakpoint
// just set.
return 0;
}
}
 
// Not caused by GDB. Call ISR proper.
return 1;
}
#endif
 
//-----------------------------------------------------------------------------
 
void hal_asb_platform_init(void)
{
extern CYG_ADDRESS hal_virtual_vector_table[64];
extern void init_thread_syscall( void *);
extern void install_async_breakpoint(void *epc);
// void (*oldvsr)(void);
extern void _default_trap_vsr(void);
 
// Ensure that the breakpoint VSR points to the default VSR. This will pass
// it on to the stubs.
// HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, _default_trap_vsr, &oldvsr );
 
// Install async breakpoint handler into vector table.
hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint;
 
#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT)
// Only include this code if we do not have a kernel. Otherwise
// the kernel supplies the functionality for the app we are linked
// with.
 
// Prepare for application installation of thread info function in
// vector table.
hal_virtual_vector_table[15] = 0;
init_thread_syscall( (void *)&hal_virtual_vector_table[15] );
 
#endif
}
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
/*------------------------------------------------------------------------*/
/* Reset support */
 
#define RSTCTR 0xc0001004
#define CHIPRST 0x01
void cyg_hal_plf_reset(void)
{
// Unfortunately this only resets the MN103E010
// A full board reset is not done. ie If the boot block select switched,
// and a Cygmon reset called the switch change will not occur. AFAICT
// the only way to notice that change is to use the Reset switch on the
// board.
HAL_WRITE_UINT8(RSTCTR, 0x00);
HAL_WRITE_UINT8(RSTCTR, CHIPRST);
 
// Just in case.
while (1) ;
}
 
 
//-----------------------------------------------------------------------------
// End of plf_stub.c
/hal_diag.c
0,0 → 1,215
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley (based on the original by jskov)
// Contributors:nickg, jskov, dmoseley
// Date: 2000-08-11
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#warning HAL_DIAG has only been verified using CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>
 
#warning GET HAL_DIAG STUFF WORKING
 
/*---------------------------------------------------------------------------*/
/* Select default diag channel to use */
 
//#define CYG_KERNEL_DIAG_SERIAL
//#define CYG_KERNEL_DIAG_BUFFER
//#define CYG_KERNEL_DIAG_GDB
 
#if !defined(CYG_KERNEL_DIAG_SERIAL) && defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
# define CYG_KERNEL_DIAG_SERIAL
# define CYG_KERNEL_DIAG_GDB
#else
# define CYG_KERNEL_DIAG_SERIAL
#endif
 
/*---------------------------------------------------------------------------*/
 
externC void diag_write_string (const char*);
 
#if defined(CYG_KERNEL_DIAG_SERIAL)
extern void cyg_hal_plf_comms_init(void);
extern void cyg_hal_plf_serial_putc(void*, cyg_uint8);
extern cyg_uint8 cyg_hal_plf_serial_getc(void*);
#endif
 
#if defined(CYG_KERNEL_DIAG_BUFFER)
char hal_diag_buffer[10000];
int hal_diag_buffer_pos;
#endif
 
void hal_diag_init(void)
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_comms_init();
#endif
 
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer_pos = 0;
#endif
}
 
#ifdef CYG_KERNEL_DIAG_GDB
static void gdb_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
while (1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
hal_diag_write_char_serial('$');
hal_diag_write_char_serial('O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
hal_diag_write_char_serial(h);
hal_diag_write_char_serial(l);
csum += h;
csum += l;
}
hal_diag_write_char_serial('#');
hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
hal_diag_write_char_serial(hex[csum&0xF]);
 
{
char c1;
 
hal_diag_read_char_serial( &c1 );
 
if( c1 == '+' ) break;
 
if( cyg_hal_is_break( &c1, 1 ) )
cyg_hal_user_break( NULL );
}
}
pos = 0;
}
}
#endif // CYG_KERNEL_DIAG_GDB
 
void hal_diag_write_char(char c)
{
unsigned long __state;
 
HAL_DISABLE_INTERRUPTS(__state);
 
if(c == '\n')
{
#if defined (CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, '\r');
cyg_hal_plf_serial_putc(NULL, '\n');
#endif
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer[hal_diag_buffer_pos++] = c;
if (hal_diag_buffer_pos >= sizeof(hal_diag_buffer) )
hal_diag_buffer_pos = 0;
#endif
#if defined(CYG_KERNEL_DIAG_GDB)
gdb_diag_write_char(c);
#endif
}
else if (c == '\r')
{
// Ignore '\r'
}
else
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, c);
#endif
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer[hal_diag_buffer_pos++] = c;
if (hal_diag_buffer_pos >= sizeof(hal_diag_buffer) )
hal_diag_buffer_pos = 0;
#endif
#if defined(CYG_KERNEL_DIAG_GDB)
gdb_diag_write_char(c);
#endif
}
 
HAL_RESTORE_INTERRUPTS(__state);
}
 
void hal_diag_read_char(char *c)
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_getc(c);
#endif
}
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/plf_misc.c
0,0 → 1,273
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley (based on the original by nickg)
// Contributors: nickg, jlarmour, dmoseley
// Date: 2000-08-11
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // architectural definitions
 
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_cache.h> // Cache handling
 
#include <cyg/hal/hal_if.h>
 
#include <cyg/hal/plf_io.h>
 
const cyg_uint8 hal_diag_digits[] = {
0x81, // 0
0xf3, // 1
0x49, // 2
0x61, // 3
0x33, // 4
0x25, // 5
0x05, // 6
0xf1, // 7
0x01, // 8
0x21, // 9
0x11, // A
0x07, // B
0x8d, // C
0x43, // D
0x0d, // E
0x1d // F
};
 
const char hal_diag_hex_digits[] = "0123456789ABCDEF";
 
cyg_uint32 hal_led_old_display = 0x5f17ffff; /* "rh " */
 
/*------------------------------------------------------------------------*/
/* LED support */
cyg_uint8 cyg_hal_plf_led_val(CYG_WORD hexdig)
{
return hal_diag_digits[(hexdig & 0xF)];
}
 
/*------------------------------------------------------------------------*/
 
#include CYGHWR_MEMORY_LAYOUT_H
#if defined(CYGPKG_CYGMON)
extern unsigned long cygmon_memsize;
#endif
 
void hal_platform_init(void)
{
*(cyg_uint8*)(&hal_led_old_display) = cyg_hal_plf_led_val(8);
HAL_WRITE_UINT32(HAL_LED_ADDRESS,hal_led_old_display);
 
#if defined(CYG_HAL_STARTUP_ROM)
// Note that the hardware seems to come up with the
// caches containing random data. Hence they must be
// invalidated before being enabled.
// However, we only do this if we are in ROM. If we are
// in RAM, then we leave the caches in the state chosen
// by the ROM monitor. If we enable them when the monitor
// is not expecting it, we can end up breaking things if the
// monitor is not doing cache flushes.
 
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
#endif
 
#if defined(CYGPKG_CYGMON)
cygmon_memsize = 16 * 1024 * 1024 - 0x200; // 16 MB - 0x200 (for _hal_vsr_table and _hal_virtual_vector_table)
#endif
 
// Set up eCos/ROM interfaces
hal_if_init();
#if defined(CYGPKG_KERNEL) && \
defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
{
extern CYG_ADDRESS hal_virtual_vector_table[32];
extern void patch_dbg_syscalls(void * vector);
patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) );
}
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
{
static void hal_ctrlc_isr_init(void);
hal_ctrlc_isr_init();
}
#endif
 
// Make sure the TBR points at the base of ROM
#if 0
{
#define TBR 0xC0000024
cyg_uint32 TBR_val;
HAL_READ_UINT32(TBR, TBR_val);
TBR_val = (TBR_val & 0x00FFFFFF) | 0x90000000; //(CYGMEM_REGION_rom & 0xFF000000);
HAL_WRITE_UINT32(TBR, TBR_val);
}
#endif
 
// Make sure the MTBR points at the base of ROM
#if 0
{
#define mTBR 0xC0000028
cyg_uint32 mTBR_val;
HAL_READ_UINT32(mTBR, mTBR_val);
mTBR_val = (mTBR_val & 0x00FFFFFF) | (CYGMEM_REGION_rom & 0xFF000000);
HAL_WRITE_UINT32(mTBR, mTBR_val);
}
#endif
}
 
/*------------------------------------------------------------------------*/
/* Functions to support the detection and execution of a user provoked */
/* program break. These are usually called from interrupt routines. */
 
/*------------------------------------------------------------------------*/
/* Control C ISR support */
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
 
#if CYGHWR_HAL_MN10300_AM33_STB_GDB_PORT == 0
 
// We use serial0 on AM33
#define SERIAL_CR ((volatile cyg_uint16 *)0xd4002000)
#define SERIAL_ICR ((volatile cyg_uint8 *) 0xd4002004)
#define SERIAL_TXR ((volatile cyg_uint8 *) 0xd4002008)
#define SERIAL_RXR ((volatile cyg_uint8 *) 0xd4002009)
#define SERIAL_SR ((volatile cyg_uint16 *)0xd400200c)
 
// Timer 1 provided baud rate divisor
#define TIMER_MD ((volatile cyg_uint8 *)0xd4003000)
#define TIMER_BR ((volatile cyg_uint8 *)0xd4003010)
#define TIMER_CR ((volatile cyg_uint8 *)0xd4003020)
 
#define SIO_LSTAT_TRDY 0x20
#define SIO_LSTAT_RRDY 0x10
 
#else
 
#error Unsupported GDB port
 
#endif
 
struct Hal_SavedRegisters *hal_saved_interrupt_state;
 
static void hal_ctrlc_isr_init(void)
{
// cyg_uint16 cr;
 
// HAL_READ_UINT16( SERIAL_CR, cr );
// cr |= LCR_RXE;
// HAL_WRITE_UINT16( SERIAL_CR, cr );
HAL_INTERRUPT_SET_LEVEL( CYGHWR_HAL_GDB_PORT_VECTOR, 4 );
HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR );
}
 
cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
char c;
cyg_uint16 sr;
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
 
HAL_READ_UINT16( SERIAL_SR, sr );
 
if( sr & SIO_LSTAT_RRDY )
{
HAL_READ_UINT8( SERIAL_RXR, c);
 
if( cyg_hal_is_break( &c , 1 ) )
cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
 
}
return 1;
}
 
#endif
 
void hal_arch_funcall_new_stack(void (*func)(void), void* stack_base, cyg_uint32 stack_size)
{
register cyg_uint32 stack_top = (cyg_uint32)stack_base + stack_size;
register cyg_uint32 old_stack;
asm volatile (" mov sp, %0" : "=r" (old_stack) : );
asm volatile (" mov %0, sp" : : "r" (stack_top) );
func();
asm volatile (" mov %0, sp" : : "r" (old_stack) );
}
 
/*------------------------------------------------------------------------*/
/* Syscall support */
#ifdef CYGPKG_CYGMON
// Cygmon provides syscall handling for this board
#include <cyg/hal/hal_stub.h>
int __get_syscall_num (void)
{
return SIGSYS;
}
#endif
 
/*------------------------------------------------------------------------*/
/* flash write-protect support */
int plf_flash_query_soft_wp(void *addr, int len)
{
if (((unsigned long)addr & 0xFC000000UL) == 0x84000000UL)
return !(*(cyg_uint8*)0xA6FA0000 & 0x02); // system flash
else
return 0; // boot prom
}
 
/*------------------------------------------------------------------------*/
/* End of plf_misc.c */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.