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    from Rev 27 to Rev 174
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Rev 27 → Rev 174

/cdl/hal_mn10300_am33_asb2305.cdl
0,0 → 1,324
# ====================================================================
#
# hal_mn10300_am33_asb2305.cdl
#
# AM33-2/ASB2305 board HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): dhowells
# Original data: dmoseley. nick, bartv
# Contributors:
# Date: 2001-05-17
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_MN10300_AM33_ASB2305 {
display "Panasonic ASB2305 Evaluation Board"
parent CYGPKG_HAL_MN10300
requires CYGPKG_HAL_MN10300_AM33
requires { CYGHWR_HAL_MN10300_AM33_REVISION == 2 }
define_header hal_mn10300_am33_asb2305.h
include_dir cyg/hal
description "
The ASB2305 HAL package should be used when targetting the
actual hardware for the Panasonic ASB2305 Evaluation Board
with the MN103E010 microcontroller."
 
compile hal_diag.c plf_stub.c plf_misc.c ser_asb.c
 
implements CYGINT_HAL_DEBUG_GDB_STUBS
implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
implements CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP
 
requires CYGSEM_HAL_UNCACHED_FLASH_ACCESS == 1;
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_mn10300_am33.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_mn10300_am33_asb2305.h>"
puts $::cdl_system_header "#define HAL_PLATFORM_BOARD \"Panasonic ASB2305\""
puts $::cdl_system_header "#define HAL_PLATFORM_EXTRA \"\""
puts $::cdl_system_header "#define HAL_PLATFORM_CPU \"MN103E010 AM33/2.0\""
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM" "ROM"}
default_value {"ROM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
This determines whether the stored .data section will need copying
to RAM before it can be used."
}
 
cdl_component CYG_HAL_ROM_SLOT {
display "ROM slot in which residing"
flavor data
legal_values {"BootPROM" "SysFlash"}
default_value {"BootPROM"}
no_define
define -file system.h CYG_HAL_ROM_SLOT
description "
This specifies which ROM slot the program resides in (and is booted
from."
}
 
cdl_option CYG_HAL_FULL_RAM {
display "Use all of RAM for RAM startup"
flavor bool
default_value 0
description "
This specifies whether or not RAM startup configurations use all of
RAM. This should be true when using the MEI debugger to load the RAM
startup program when no monitor is installed on the board."
}
 
cdl_option CYGHWR_HAL_MN10300_PROCESSOR_OSC_DEFAULT {
display "Processor clock rate"
calculated 33333333
flavor data
}
 
cdl_option CYGHWR_HAL_MN10300_PLATFORM_VSR_TABLE_BASE {
display "ASB2305 VSR table base address"
flavor data
default_value 0x8C000000
description "
Base address of the VSR table on ASB2305 board."
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
parent CYGPKG_NONE
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "mn10300-elf" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-mam33-2 -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -Wp,-Wno-paste -g -O2 -fno-builtin -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-mam33 -g -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
display "Build GDB stub ROM image"
default_value 0
requires { CYG_HAL_STARTUP == "ROM" }
requires CYGSEM_HAL_ROM_MONITOR
requires CYGBLD_BUILD_COMMON_GDB_STUBS
requires CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
requires ! CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
requires ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
requires ! CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
no_define
description "
This option enables the building of the GDB stubs for the
board. The common HAL controls takes care of most of the
build process, but the final conversion from ELF image to
binary data is handled by the platform CDL, allowing
relocation of the data if necessary."
 
make -priority 320 {
<PREFIX>/bin/gdb_module.bin : <PREFIX>/bin/gdb_module.img
$(OBJCOPY) -O binary $< $@
}
}
}
 
cdl_option CYGNUM_HAL_BREAKPOINT_LIST_SIZE {
display "Number of breakpoints supported by the HAL."
flavor data
default_value 25
description "
This option determines the number of breakpoints supported by the HAL."
}
 
cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
display "Diagnostic serial port RTS/CTS flow control"
flavor bool
default_value 0
description "
The ASB2305 debug serial port RTS/CTS flow control setting."
}
 
cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL0 {
display "ASB2305 uses AM33 SERIAL0"
flavor bool
default_value 1
description "
Enable this option if AM33 SERIAL0 is to be used as a virtual vector
communications channel."
}
 
cdl_option CYGSEM_HAL_AM33_PLF_USES_SERIAL1 {
display "ASB2305 uses AM33 SERIAL1"
flavor bool
default_value 0
description "
Enable this option if AM33 SERIAL1 is to be used as a virtual vector
communications channel."
}
 
cdl_option CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS {
display "ASB2305 has one comm channels."
flavor data
default_value 1
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { CYG_HAL_STARTUP == "RAM" ? \
CYG_HAL_FULL_RAM ? "mn10300_am33_asb2305_fullram" : \
"mn10300_am33_asb2305_ram" : \
CYG_HAL_ROM_SLOT == "BootPROM" ? "mn10300_am33_asb2305_rom" : \
"mn10300_am33_asb2305_flash" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { CYG_HAL_STARTUP == "RAM" ? \
CYG_HAL_FULL_RAM ? "<pkgconf/mlt_mn10300_am33_asb2305_fullram.ldi>" : \
"<pkgconf/mlt_mn10300_am33_asb2305_ram.ldi>" : \
CYG_HAL_ROM_SLOT == "BootPROM" ? "<pkgconf/mlt_mn10300_am33_asb2305_rom.ldi>" : \
"<pkgconf/mlt_mn10300_am33_asb2305_flash.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { CYG_HAL_STARTUP == "RAM" ? \
CYG_HAL_FULL_RAM ? "<pkgconf/mlt_mn10300_am33_asb2305_fullram.h>" : \
"<pkgconf/mlt_mn10300_am33_asb2305_ram.h>" : \
CYG_HAL_ROM_SLOT == "BootPROM" ? "<pkgconf/mlt_mn10300_am33_asb2305_rom.h>" : \
"<pkgconf/mlt_mn10300_am33_asb2305_flash.h>" }
}
}
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor booldata
legal_values { "GDB_stubs" }
default_value { CYG_HAL_STARTUP == "RAM" ? "GDB_stubs" : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
description "
Support can be enabled for boot ROMs or ROM monitors which contain
GDB stubs. This support changes various eCos semantics such as
the encoding of diagnostic output, and the overriding of hardware
interrupt vectors."
}
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
display "Behave as a ROM monitor"
flavor bool
default_value 1
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "ROM" }
description "
Enable this option if this program is to be used as a ROM monitor,
i.e. applications will be loaded into RAM on the board, and this
ROM monitor may process exceptions or interrupts generated from the
application. This enables features such as utilizing a separate
interrupt stack when exceptions are generated."
}
 
cdl_component CYGPKG_REDBOOT_HAL_OPTIONS {
display "Redboot HAL options"
flavor none
no_define
parent CYGPKG_REDBOOT
active_if CYGPKG_REDBOOT
description "
This option lists the target's requirements for a valid Redboot
configuration."
cdl_option CYGBLD_BUILD_REDBOOT_BIN {
display "Build Redboot ROM binary image"
active_if CYGBLD_BUILD_REDBOOT
default_value 1
no_define
description "This option enables the conversion of the Redboot ELF
image to a binary image suitable for ROM programming."
make -priority 325 {
<PREFIX>/bin/redboot.bin : <PREFIX>/bin/redboot.elf
$(OBJCOPY) --strip-debug $< $(@:.bin=.img)
$(OBJCOPY) -O srec $< $(@:.bin=.srec)
$(OBJCOPY) -O binary $< $@
}
}
}
}
/include/plf_intr.h
0,0 → 1,112
#ifndef CYGONCE_HAL_PLF_INTR_H
#define CYGONCE_HAL_PLF_INTR_H
 
//==========================================================================
//
// plf_intr.h
//
// ASB2305 Interrupt and clock support
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors: nickg, jskov,
// gthomas, jlarmour, dmoseley
// Date: 2001-05-17
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock for the AM33-2 ASB2305 board.
//
// Usage:
// #include <cyg/hal/plf_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#if CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL==0
#define CYGNUM_HAL_INTERRUPT_DEBUG_UART CYGNUM_HAL_INTERRUPT_SERIAL_1_RX
#elif CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL==1
#define CYGNUM_HAL_INTERRUPT_DEBUG_UART CYGNUM_HAL_INTERRUPT_SERIAL_0_RX
#else
#error UNKNOWN DEBUG CHANNEL
#endif
 
extern void cyg_plf_hal_delay_us(cyg_int32 usecs);
#define HAL_DELAY_US cyg_plf_hal_delay_us
 
//--------------------------------------------------------------------------
// Control-C support.
 
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
 
# define CYGHWR_HAL_GDB_PORT_VECTOR CYGNUM_HAL_INTERRUPT_SERIAL_1_RX
 
externC cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
 
#define HAL_CTRLC_ISR hal_ctrlc_isr
 
#endif
 
//--------------------------------------------------------------------------
// Function call support with a new stack.
// This will emulate thread creation using a new stack
//
#define HAL_ARCH_FUNCALL_NEW_STACK(func, base, size) hal_arch_funcall_new_stack(func, base, size)
extern void hal_arch_funcall_new_stack(void (*func)(void), void* stack_base, cyg_uint32 stack_size);
 
 
//----------------------------------------------------------------------------
// Reset.
#ifndef CYGHWR_HAL_RESET_DEFINED
extern void cyg_hal_plf_reset( void );
#define CYGHWR_HAL_RESET_DEFINED
#define HAL_PLATFORM_RESET() cyg_hal_plf_reset()
 
#define HAL_PLATFORM_RESET_ENTRY 0x40000000
 
#endif // CYGHWR_HAL_RESET_DEFINED
 
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
/include/plf_stub.h
0,0 → 1,103
#ifndef CYGONCE_HAL_PLF_STUB_H
#define CYGONCE_HAL_PLF_STUB_H
 
//=============================================================================
//
// plf_stub.h
//
// Platform header for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors:dmoseley
// Date: 2001-05-17
// Purpose: Platform HAL stub support for AM33-20/ASB2305 boards.
// Usage: #include <cyg/hal/plf_stub.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_mn10300_am33_asb2305.h>
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/infra/cyg_type.h> // CYG_UNUSED_PARAM
 
#include <cyg/hal/mn10300_stub.h> // architecture stub support
 
//----------------------------------------------------------------------------
// Define some platform specific communication details. This is mostly
// handled by hal_if now, but we need to make sure the comms tables are
// properly initialized.
 
externC void cyg_hal_plf_comms_init(void);
 
#define HAL_STUB_PLATFORM_INIT_SERIAL() cyg_hal_plf_comms_init()
#define HAL_STUB_PLATFORM_GET_CHAR() cyg_hal_plf_serial_getc(0)
#define HAL_STUB_PLATFORM_PUT_CHAR(c) cyg_hal_plf_serial_putc(0, (c))
#define HAL_STUB_PLATFORM_SET_BAUD_RATE(baud) cyg_hal_plf_serial_setbaud(0, (baud))
#define HAL_STUB_PLATFORM_INTERRUPTIBLE (&hal_asb_interruptible)
#define HAL_STUB_PLATFORM_INIT_BREAK_IRQ() CYG_EMPTY_STATEMENT
 
//----------------------------------------------------------------------------
// Stub initializer.
 
externC void hal_asb_platform_init(void);
 
#define HAL_STUB_PLATFORM_INIT() hal_asb_platform_init()
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
//-----------------------------------------------------------------------------
// Syscall support.
#ifdef CYGPKG_CYGMON
// Cygmon provides syscall handling for this board
#define SIGSYSCALL SIGSYS
extern int __get_syscall_num (void);
#endif
 
//-----------------------------------------------------------------------------
// Register validity checking.
#ifdef CYGPKG_CYGMON
#define CYGHWR_REGISTER_VALIDITY_CHECKING
#endif
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_PLF_STUB_H
// End of plf_stub.h
/include/pkgconf/mlt_mn10300_am33_asb2305_rom.h
0,0 → 1,25
// eCos memory layout - Fri Oct 20 08:28:05 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_rom (0x80000000)
#define CYGMEM_REGION_rom_SIZE (0x400000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#define CYGMEM_REGION_ram (0x90000000)
#define CYGMEM_REGION_ram_SIZE (0x04000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x94000000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x80000)
/include/pkgconf/mlt_mn10300_am33_asb2305_flash.h
0,0 → 1,25
// eCos memory layout - Fri Oct 20 08:28:05 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_rom (0x84000000)
#define CYGMEM_REGION_rom_SIZE (0x1000000)
#define CYGMEM_REGION_rom_ATTR (CYGMEM_REGION_ATTR_R)
#define CYGMEM_REGION_ram (0x90000000)
#define CYGMEM_REGION_ram_SIZE (0x04000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x94000000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x80000)
/include/pkgconf/mlt_mn10300_am33_asb2305_rom.ldi
0,0 → 1,29
// eCos memory layout - Fri Oct 20 08:28:05 2000 -*- c -*-
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
rom : ORIGIN = 0x80000000, LENGTH = 0x00400000
ram : ORIGIN = 0x90000000, LENGTH = 0x04000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0x80000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, 0x90000000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x9C000000; . = CYG_LABEL_DEFN(__pci_window) + 0x80000;
SECTIONS_END
}
 
/include/pkgconf/mlt_mn10300_am33_asb2305_flash.ldi
0,0 → 1,29
// eCos memory layout - Fri Oct 20 08:28:05 2000 -*- c -*-
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
rom : ORIGIN = 0x84000000, LENGTH = 0x01000000
ram : ORIGIN = 0x90000000, LENGTH = 0x04000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (rom, 0x84000000, LMA_EQ_VMA)
SECTION_text (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (rom, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, 0x90000000, FOLLOWING (.gcc_except_table))
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x9C000000; . = CYG_LABEL_DEFN(__pci_window) + 0x80000;
SECTIONS_END
}
 
/include/pkgconf/mlt_mn10300_am33_asb2305_ram.h
0,0 → 1,22
// eCos memory layout - Fri Oct 20 08:28:43 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x90020000)
#define CYGMEM_REGION_ram_SIZE (0x03fe0000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x94000000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x80000)
/include/pkgconf/mlt_mn10300_am33_asb2305_ram.ldi
0,0 → 1,28
// eCos memory layout - Fri Oct 20 08:28:43 2000 -*- c -*-
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x90020000, LENGTH = 0x03fe0000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (ram, 0x90020000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x9C000000; . = CYG_LABEL_DEFN(__pci_window) + 0x80000;
SECTIONS_END
}
 
/include/pkgconf/mlt_mn10300_am33_asb2305_flash.mlt
0,0 → 1,14
version 0
region rom 84000000 1000000 1 !
region ram 90000000 4000000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 84000000 84000000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 0 0 1 data !
section data 0 1 1 1 1 1 0 0 90000000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 80000 1 0 0 1 0 1 0 9c000000 9c000000 !
/include/pkgconf/mlt_mn10300_am33_asb2305_fullram.h
0,0 → 1,22
// eCos memory layout - Fri Oct 20 08:28:43 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x90000000)
#define CYGMEM_REGION_ram_SIZE (0x04000000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x94000000 - (size_t) CYG_LABEL_NAME (__heap1))
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__pci_window) [];
#endif
#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
#define CYGMEM_SECTION_pci_window_SIZE (0x80000)
/include/pkgconf/mlt_mn10300_am33_asb2305_rom.mlt
0,0 → 1,14
version 0
region rom 80000000 400000 1 !
region ram 90000000 4000000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 80000000 80000000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 0 0 1 data !
section data 0 1 1 1 1 1 0 0 90000000 bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 80000 1 0 0 1 0 1 0 9c000000 9c000000 !
/include/pkgconf/mlt_mn10300_am33_asb2305_fullram.ldi
0,0 → 1,28
// eCos memory layout - Fri Oct 20 08:28:43 2000 -*- c -*-
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x90000000, LENGTH = 0x04000000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (ram, 0x90000000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
CYG_LABEL_DEFN(__pci_window) = 0x9C000000; . = CYG_LABEL_DEFN(__pci_window) + 0x80000;
SECTIONS_END
}
 
/include/pkgconf/mlt_mn10300_am33_asb2305_ram.mlt
0,0 → 1,13
version 0
region ram 90020000 3fe0000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 90020000 90020000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 80000 1 0 0 1 0 1 0 9c000000 9c000000 !
/include/pkgconf/mlt_mn10300_am33_asb2305_fullram.mlt
0,0 → 1,13
version 0
region ram 90000000 4000000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 90000000 90000000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 4 0 1 0 1 0 1 bss bss !
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
section pci_window 80000 1 0 0 1 0 1 0 9c000000 9c000000 !
/include/platform.inc
0,0 → 1,520
#ifndef CYGONCE_HAL_PLATFORM_INC
#define CYGONCE_HAL_PLATFORM_INC
##=============================================================================
##
## platform.inc
##
## ASB2305 board assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): dhowells
## Contributors:dmoseley
## Date: 2001-05-17
## Purpose: ASB2305 board definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the ASB2305 board.
## Usage:
## #include <cyg/hal/platform.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/plf_io.h>
 
#------------------------------------------------------------------------------
# Diagnostics macros.
 
#include <cyg/hal/hal_io.h>
 
.macro hal_diag_data
hal_diag_intr_count: .long 0
.endm
 
#define HAL_EARLY_INIT hal_early_init
.macro hal_early_init
# turn on the sofware status LED
movbu (0xDB000008),d0
or 0x80,d0
movbu d0,(0xDB000008)
movhu (0xDB000000),d0
and 0x3FFF,d0
or 0x4000,d0
movhu d0,(0xDB000000)
 
# enable system flash memory write
movbu (0xDB000008),d0
and 0xdf,d0
movbu d0,(0xDB000008)
movhu (0xDB000000),d0
and 0xF3FF,d0
or 0x0400,d0
movhu d0,(0xDB000000)
 
.endm
 
.macro hal_diag_init
mov 0x5f17ff7f,d0 # 'rh -'
mov d0,(_hal_led_old_display)
mov d0,(HAL_LED_ADDRESS)
.endm
 
#define CYGPKG_HAL_MN10300_DIAG_DEFINED
 
.macro hal_handle_unknown_int
mov _hal_diag_digits,a2
mov (0xC0000024),d0 // Get TBR
mov 0x6D00,d1 // 7-seg LED: =ABC
mov d0,d2 // 0xnnnnnAnn
lsr 8,d2
and 0xf,d2
movbu (a2,d2),d2
or d2,d1
asl 8,d1
mov d0,d2 // 0xnnnnnnBn
lsr 4,d2
and 0xf,d2
movbu (a2,d2),d2
or d2,d1
asl 8,d1
and 0xf,d0 // 0xnnnnnnnC
movbu (a2,d0),d2
or d2,d1
mov (_hal_led_old_display),d0
and 0x00010000,d0
or d1,d0
mov d0,(_hal_led_old_display)
mov d0,(HAL_LED_ADDRESS)
.endm
#define CYG_HAL_HANDLE_UNKNOWN_INT_DEFINED
 
.macro hal_diag_excpt_start
hal_handle_unknown_int
.endm
 
.macro hal_diag_excpt_end
mov 0x5f17ff01,d0
mov d0,(_hal_led_old_display)
mov d0,(HAL_LED_ADDRESS)
.endm
#define CYG_HAL_DIAG_EXCPT_END
 
.macro hal_diag_intr_start
mov (hal_diag_intr_count),d1
inc d1
cmp 100,d1
bne x\@
clr d1
mov (_hal_led_old_display),d0
xor 0x00010000,d0
mov d0,(_hal_led_old_display)
mov d0,(HAL_LED_ADDRESS)
x\@:
mov d1,(hal_diag_intr_count)
.endm
 
.macro hal_diag_restore
.endm
 
.macro hal_diag_led val
movm [d2,d3,a2],(sp)
0: mov _hal_diag_digits,a2
mov \val,d2
and 0xf,d2
add d2,a2
movbu (a2),d3
mov (_hal_led_old_display),d2
asl 8,d2
or d3,d2
mov d2,(HAL_LED_ADDRESS)
mov d2,(_hal_led_old_display)
movm (sp),[d2,d3,a2]
.endm
 
.macro hal_cpu_stop
// mov 0x10,d0
// movhu d0,(0xC0000040) // enter STOP mode (register CPUM)
.endm
#define CYG_HAL_CPU_STOP_DEFINED
 
#------------------------------------------------------------------------------
# MEMC macros.
 
#ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
 
// These settings follow the recommended settings in the
// "MN103E010 Evaluation Board User's Guide"
 
#define BCCR 0xC0002000
#define BCCR_INIT 0x12040580
 
#define SBBASE0 0xD8C00100
#define SBBASE0_INIT_SYSFL 0x8000FE01
#define SBBASE0_INIT_BPROM 0x8400FE01
#define SBBASE1 0xD8C00110
#define SBBASE1_INIT_SYSFL 0x8400FE01
#define SBBASE1_INIT_BPROM 0x8000FE01
#define SBBASE2 0xD8C00120
#define SBBASE2_INIT 0x8600FF81
#define SBBASE3 0xD8C00130
#define SBBASE3_INIT 0x8680FF81
#define SBBASE4 0xD8C00140
#define SBBASE4_INIT 0x9800F801
#define SBBASE5 0xD8C00150
#define SBBASE5_INIT 0x00000000
#define SBBASE6 0xD8C00160
#define SBBASE6_INIT 0x00000000
#define SBBASE7 0xD8C00170
#define SBBASE7_INIT 0x00000000
 
#define SBCTRL00 0xD8C00200
#define SBCTRL00_INIT 0x21111000
#define SBCTRL10 0xD8C00210
#define SBCTRL10_INIT 0x21111000
#define SBCTRL20 0xD8C00220
#define SBCTRL20_INIT 0x21111000
#define SBCTRL30 0xD8C00230
#define SBCTRL30_INIT 0x11111000
#define SBCTRL40 0xD8C00240
#define SBCTRL40_INIT 0x00140000
#define SBCTRL50 0xD8C00250
#define SBCTRL50_INIT 0x22100000
#define SBCTRL60 0xD8C00260
#define SBCTRL60_INIT 0x22100000
#define SBCTRL70 0xD8C00270
#define SBCTRL70_INIT 0x22100000
 
#define SBCTRL01 0xD8C00204
#define SBCTRL01_INIT 0x00100200
#define SBCTRL11 0xD8C00214
#define SBCTRL11_INIT 0x00100200
#define SBCTRL21 0xD8C00224
#define SBCTRL21_INIT 0x00100200
#define SBCTRL31 0xD8C00234
#define SBCTRL31_INIT 0x00100100
#define SBCTRL41 0xD8C00244
#define SBCTRL41_INIT 0x11011100
#define SBCTRL51 0xD8C00254
#define SBCTRL51_INIT 0x00001100
#define SBCTRL61 0xD8C00264
#define SBCTRL61_INIT 0x00001100
#define SBCTRL71 0xD8C00274
#define SBCTRL71_INIT 0x00001100
 
#define SBCTRL02 0xD8C00208
#define SBCTRL02_INIT 0x00000004
#define SBCTRL12 0xD8C00218
#define SBCTRL12_INIT 0x04000004
#define SBCTRL22 0xD8C00228
#define SBCTRL22_INIT 0x00000004
#define SBCTRL32 0xD8C00238
#define SBCTRL32_INIT 0x00000002
#define SBCTRL42 0xD8C00248
#define SBCTRL42_INIT 0x01000001
#define SBCTRL52 0xD8C00258
#define SBCTRL52_INIT 0x0000000F
#define SBCTRL62 0xD8C00268
#define SBCTRL62_INIT 0x0000000F
#define SBCTRL72 0xD8C00278
#define SBCTRL72_INIT 0x0000000F
 
#define SDBASE0 0xDA000008
#define SDBASE1 0xDA00000C
#define SDRAMBUS 0xDA000000
 
// 16MB SDRAM
#define SDBASE0_8M_INIT 0x9000FF81
#define SDBASE1_8M_INIT 0x9080FF81
#define SDRAMBUS_8M_INIT 0xA8990654
 
// 32MB SDRAM
#define SDBASE0_16M_INIT 0x9000FF01
#define SDBASE1_16M_INIT 0x9100FF01
#define SDRAMBUS_16M_INIT 0xA89a0654
 
// 64MB SDRAM
#define SDBASE0_32M_INIT 0x9000fe01
#define SDBASE1_32M_INIT 0x9200fe01
#define SDRAMBUS_32M_INIT 0xa89b0654
 
.macro hal_memc_init
mov BCCR,a0
mov BCCR_INIT,d0
mov d0,(a0)
 
// reduce the span of the ROM banks first
mov (SBBASE0),d0
btst 1,d0
beq 0f
mov 0x8000FE01,d0
mov d0,(SBBASE0)
0:
mov (SBBASE1),d0
btst 1,d0
beq 0f
mov 0x8000FE01,d0
mov d0,(SBBASE1)
0:
// memory bank 2
mov SBBASE2_INIT,d0
mov d0,(SBBASE2)
mov SBCTRL20_INIT,d0
mov d0,(SBCTRL20)
mov SBCTRL21_INIT,d0
mov d0,(SBCTRL21)
mov SBCTRL22_INIT,d0
mov d0,(SBCTRL22)
 
// memory bank 3
mov SBBASE3_INIT,d0
mov d0,(SBBASE3)
mov SBCTRL30_INIT,d0
mov d0,(SBCTRL30)
mov SBCTRL31_INIT,d0
mov d0,(SBCTRL31)
mov SBCTRL32_INIT,d0
mov d0,(SBCTRL32)
 
// memory bank 4
mov SBBASE4_INIT,d0
mov d0,(SBBASE4)
mov SBCTRL40_INIT,d0
mov d0,(SBCTRL40)
mov SBCTRL41_INIT,d0
mov d0,(SBCTRL41)
mov SBCTRL42_INIT,d0
mov d0,(SBCTRL42)
 
// memory bank 5
#if SBBASE5_INIT != 0
mov SBBASE5_INIT,d0
mov d0,(SBBASE5)
mov SBCTRL50_INIT,d0
mov d0,(SBCTRL50)
mov SBCTRL51_INIT,d0
mov d0,(SBCTRL51)
mov SBCTRL52_INIT,d0
mov d0,(SBCTRL52)
#endif
 
// memory bank 6
#if SBBASE6_INIT != 0
mov SBBASE6_INIT,d0
mov d0,(SBBASE6)
mov SBCTRL60_INIT,d0
mov d0,(SBCTRL60)
mov SBCTRL61_INIT,d0
mov d0,(SBCTRL61)
mov SBCTRL62_INIT,d0
mov d0,(SBCTRL62)
#endif
 
// memory bank 7
#if SBBASE7_INIT != 0
mov SBBASE7_INIT,d0
mov d0,(SBBASE7)
mov SBCTRL70_INIT,d0
mov d0,(SBCTRL70)
mov SBCTRL71_INIT,d0
mov d0,(SBCTRL71)
mov SBCTRL72_INIT,d0
mov d0,(SBCTRL72)
#endif
 
#ifndef CYG_HAL_STARTUP_RAM
 
// Setup for 64MB initially and determine final mem config below.
mov SDRAMBUS,a0
mov (a0),d0
and 0xfffffffb,d0 // disable refresh
mov d0,(a0)
 
mov SDBASE0,a0
mov SDBASE0_32M_INIT,d0
mov d0,(a0)
mov SDBASE1,a0
mov SDBASE1_32M_INIT,d0
mov d0,(a0)
mov SDRAMBUS,a0
mov SDRAMBUS_32M_INIT,d0
mov d0,(a0)
 
mov 0x1000,d0
0:
sub 1,d0
bne 0b
 
// Check for 16MB and 32MB shadowing to determine actual amount of
// memory installed. This assumes 8M, 16M, or 32M configs.
mov 0,d0
mov d0,(0x90800000)
mov d0,(0x91000000)
mov 0xaaaaaaaa,d0
mov d0,(0x90000000)
mov (0x90800000),d1
cmp d0,d1
bne 1f
 
// 16MB installed
mov SDRAMBUS,a0
mov (a0),d0
and 0xfffffffb,d0 // disable refresh
mov d0,(a0)
mov SDBASE0,a1
mov SDBASE0_8M_INIT,d1
mov d1,(a1)
mov SDBASE1,a1
mov SDBASE1_8M_INIT,d1
mov d1,(a1)
mov SDRAMBUS_8M_INIT,d0
mov d0,(a0)
jmp 2f
1:
mov (0x91000000),d1
cmp d0,d1
bne 2f
 
// 32MB installed
mov SDRAMBUS,a0
mov (a0),d0
and 0xfffffffb,d0 // disable refresh
mov d0,(a0)
mov SDBASE0,a1
mov SDBASE0_16M_INIT,d1
mov d1,(a1)
mov SDBASE1,a1
mov SDBASE1_16M_INIT,d1
mov d1,(a1)
mov SDRAMBUS_16M_INIT,d0
mov d0,(a0)
2:
#endif // ! CYG_HAL_STARTUP_RAM
 
// now the ROMs need putting into the right place
// - this is tricky because when we're booting from the system flash,
// it has had its base address pre-swapped by the CPU
// - we need to copy a small piece of code to the SRAM and execute it
// there
 
// display on the LEDs
mov 0x7e7e7e7e,d0 # '-.-.-.-.'
mov d0,(HAL_LED_ADDRESS)
 
// copy the ROM address adjustor to the SRAM
add -4,sp
call __hal_plf_base_ref,[],0 // note we can't address ourselves directly yet
__hal_plf_base_ref:
movm (sp),[a3]
mov a3,a0
add __hal_plf_rom_swap_start-__hal_plf_base_ref,a0
add __hal_plf_rom_swap_end-__hal_plf_base_ref,a3
mov 0x8C000000,a1
0: movbu (a0),d0
movbu d0,(a1)
inc a0
inc a1
cmp a0,a3
bcc 0b
mov 0x8C000000,a1
jmp (a1)
 
////////////////////////////////////////////////////////////////
__hal_plf_rom_swap_start:
// put boot PROM at 0x80000000, and system flash at 0x84000000
mov SBBASE0_INIT_BPROM,d0
mov d0,(SBBASE0)
 
mov SBBASE1_INIT_BPROM,d0
mov d0,(SBBASE1)
 
// memory bank 0
mov SBCTRL00_INIT,d0
mov d0,(SBCTRL00)
mov SBCTRL01_INIT,d0
mov d0,(SBCTRL01)
mov SBCTRL02_INIT,d0
mov d0,(SBCTRL02)
 
// memory bank 1
mov SBCTRL10_INIT,d0
mov d0,(SBCTRL10)
mov SBCTRL11_INIT,d0
mov d0,(SBCTRL11)
mov SBCTRL12_INIT,d0
mov d0,(SBCTRL12)
 
// jump forward so we start running from the 80000000/84000000 base address
mov __hal_plf_rom_swap_reentry,a0
jmp (a0)
__hal_plf_rom_swap_end:
////////////////////////////////////////////////////////////////
 
__hal_plf_rom_swap_reentry:
// clear the on-CPU 16Kb SRAM
clr d0
mov 16384/4-4,d1
mov 0x8C000000,a0
0:
mov d0,(a0,d1)
sub 4,d1
bnc 0b
 
.endm
 
#define CYGPKG_HAL_MN10300_MEMC_DEFINED
 
#endif
 
 
//-----------------------------------------------------------------------------
// Syscall support.
#if defined(CYGPKG_CYGMON) || defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
// Cygmon provides syscall handling for this board
// These must be kept in sync with the rest of the tree.
#define SIGSYS 12
#define SIGSYSCALL SIGSYS
#endif
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLATFORM_INC
# end of platform.inc
/include/hal_diag.h
0,0 → 1,92
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
//=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors:jskov, nickg, dmoseley
// Date: 2000-08-11
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#if defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#include <cyg/hal/hal_if.h>
 
#define HAL_DIAG_INIT() hal_if_diag_init()
#define HAL_DIAG_WRITE_CHAR(_c_) hal_if_diag_write_char(_c_)
#define HAL_DIAG_READ_CHAR(_c_) hal_if_diag_read_char(&_c_)
 
#else // everything by steam
 
//-----------------------------------------------------------------------------
// functions implemented in hal_diag.c
 
externC void hal_diag_init(void);
 
externC void hal_diag_write_char(char c);
 
externC void hal_diag_read_char(char *c);
 
//-----------------------------------------------------------------------------
 
#define HAL_DIAG_INIT() hal_diag_init()
 
#define HAL_DIAG_WRITE_CHAR(_c_) hal_diag_write_char(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) hal_diag_read_char(&_c_)
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
//-----------------------------------------------------------------------------
// end of hal_diag.h
#endif // CYGONCE_HAL_HAL_DIAG_H
/include/plf_io.h
0,0 → 1,344
#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H
 
//=============================================================================
//
// plf_io.h
//
// Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors: dmoseley
// Date: 2001-05-17
// Purpose: ASB2305 platform IO support
// Description:
// Usage: #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#ifndef __ASSEMBLER__
#include <cyg/hal/hal_intr.h>
#endif
 
#ifdef __ASSEMBLER__
#define HAL_REG_8(x) x
#define HAL_REG_16(x) x
#define HAL_REG_32(x) x
#else
#define HAL_REG_8(x) (volatile cyg_uint8*)(x)
#define HAL_REG_16(x) (volatile cyg_uint16*)(x)
#define HAL_REG_32(x) (volatile cyg_uint32*)(x)
#endif
 
# define CYGARC_UNCACHED_ADDRESS(x) ((x)|0x20000000)
 
//-----------------------------------------------------------------------------
 
/* ASB GPIO Registers */
#define HAL_GPIO_BASE 0xDB000000
 
#define HAL_GPIO_0_MODE_OFFSET 0x0000
#define HAL_GPIO_0_IN_OFFSET 0x0004
#define HAL_GPIO_0_OUT_OFFSET 0x0008
#define HAL_GPIO_1_MODE_OFFSET 0x0100
#define HAL_GPIO_1_IN_OFFSET 0x0104
#define HAL_GPIO_1_OUT_OFFSET 0x0108
#define HAL_GPIO_2_MODE_OFFSET 0x0200
#define HAL_GPIO_2_IN_OFFSET 0x0204
#define HAL_GPIO_2_OUT_OFFSET 0x0208
#define HAL_GPIO_3_MODE_OFFSET 0x0300
#define HAL_GPIO_3_IN_OFFSET 0x0304
#define HAL_GPIO_3_OUT_OFFSET 0x0308
#define HAL_GPIO_4_MODE_OFFSET 0x0400
#define HAL_GPIO_4_IN_OFFSET 0x0404
#define HAL_GPIO_4_OUT_OFFSET 0x0408
#define HAL_GPIO_5_MODE_OFFSET 0x0500
#define HAL_GPIO_5_IN_OFFSET 0x0504
#define HAL_GPIO_5_OUT_OFFSET 0x0508
 
#define HAL_GPIO_0_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_0_MODE_OFFSET)
#define HAL_GPIO_0_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_IN_OFFSET)
#define HAL_GPIO_0_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_0_OUT_OFFSET)
#define HAL_GPIO_1_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_1_MODE_OFFSET)
#define HAL_GPIO_1_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_IN_OFFSET)
#define HAL_GPIO_1_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_1_OUT_OFFSET)
#define HAL_GPIO_2_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_2_MODE_OFFSET)
#define HAL_GPIO_2_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_IN_OFFSET)
#define HAL_GPIO_2_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_2_OUT_OFFSET)
#define HAL_GPIO_3_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_3_MODE_OFFSET)
#define HAL_GPIO_3_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_IN_OFFSET)
#define HAL_GPIO_3_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_3_OUT_OFFSET)
#define HAL_GPIO_4_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_4_MODE_OFFSET)
#define HAL_GPIO_4_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_IN_OFFSET)
#define HAL_GPIO_4_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_4_OUT_OFFSET)
#define HAL_GPIO_5_MODE HAL_REG_16 (HAL_GPIO_BASE + HAL_GPIO_5_MODE_OFFSET)
#define HAL_GPIO_5_IN HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_IN_OFFSET)
#define HAL_GPIO_5_OUT HAL_REG_8 (HAL_GPIO_BASE + HAL_GPIO_5_OUT_OFFSET)
 
//-----------------------------------------------------------------------------
#define HAL_LED_ADDRESS 0xA6F90000
#define HAL_GPIO_MODE_ALL_OUTPUT 0x5555
 
 
#ifdef __ASSEMBLER__
 
# include <cyg/hal/platform.inc>
# define DEBUG_DISPLAY(hexdig) hal_diag_led hexdig
# define DEBUG_DELAY() \
mov 0x20000, d0; \
0: sub 1, d0; \
bne 0b; \
nop
 
#else
 
extern cyg_uint8 cyg_hal_plf_led_val(CYG_WORD hexdig);
# define DEBUG_DISPLAY(hexdig) HAL_WRITE_UINT8(HAL_LED_ADDRESS, cyg_hal_plf_led_val(hexdig))
# define DEBUG_DELAY() \
{ \
volatile int i = 0x80000; \
while (--i) ; \
}
 
#endif
 
//-----------------------------------------------------------------------------
// PCI access stuff
 
// Compute address necessary to access PCI config space for the given
// bus and device.
#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
(0x80000000 | ((__bus) << 16) | ((__devfn) << 8) | ((__offset) & ~3))
 
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_READ_UINT8(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_READ_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
} \
} while(0)
 
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_READ_UINT16(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_READ_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
} \
} while(0)
 
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_READ_UINT32(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_READ_UINT32(0xBFFFFFFC,(__val)); \
} \
} while(0)
 
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_WRITE_UINT8(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_WRITE_UINT8(0xBFFFFFFC + ((__offset)&3),(__val)); \
} \
} while(0)
 
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_WRITE_UINT16(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_WRITE_UINT16(0xBFFFFFFC + ((__offset)&2),(__val)); \
} \
} while(0)
 
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
do { \
if ((__bus)==0 && (__devfn)==0) { \
HAL_WRITE_UINT32(0xBE040000+(__offset),(__val)); \
} \
else { \
HAL_WRITE_UINT32(0xBFFFFFF8,HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset)); \
HAL_WRITE_UINT32(0xBFFFFFFC,(__val)); \
} \
} while(0)
 
// Initialize the PCI bus.
#define HAL_PCI_INIT() \
do { \
cyg_uint32 devfn; \
cyg_uint16 word; \
\
/* we need to set up the bridge _now_ or we won't be able to access the */ \
/* PCI config registers */ \
HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
\
HAL_PCI_CFG_WRITE_UINT16(0,0,CYG_PCI_CFG_STATUS, 0xF800); \
HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_LATENCY_TIMER, 0x10); \
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_BAR_0, 0x80000000); \
HAL_PCI_CFG_WRITE_UINT8 (0,0,CYG_PCI_CFG_INT_LINE, 1); \
HAL_PCI_CFG_WRITE_UINT32(0,0,0x48, 0x98000000); \
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x41, 0x00); \
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x42, 0x01); \
HAL_PCI_CFG_WRITE_UINT8 (0,0,0x44, 0x01); \
HAL_PCI_CFG_WRITE_UINT32(0,0,0x50, 0x00000001); \
HAL_PCI_CFG_WRITE_UINT32(0,0,0x58, 0x00000002); \
HAL_PCI_CFG_WRITE_UINT32(0,0,0x5C, 0x00000001); \
\
/* we also need to set up the PCI-PCI bridge (no BIOS, you see) */ \
devfn = 3<<3 | 0; \
\
/* IO: 0x00010000-0x0001ffff */ \
HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_BASE, 0x01); \
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_BASE_UPPER16, 0x0001); \
HAL_PCI_CFG_WRITE_UINT8 (0,devfn,CYG_PCI_CFG_IO_LIMIT, 0xF1); \
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_IO_LIMIT_UPPER16, 0x0001); \
\
HAL_PCI_CFG_READ_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
word |= CYG_PCI_CFG_COMMAND_SERR | CYG_PCI_CFG_COMMAND_PARITY; \
word |= CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_IO | CYG_PCI_CFG_COMMAND_MASTER; \
HAL_PCI_CFG_WRITE_UINT32(0,0,CYG_PCI_CFG_COMMAND,word); \
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_BASE, 0x1000); \
HAL_PCI_CFG_WRITE_UINT16(0,devfn,CYG_PCI_CFG_MEM_LIMIT, 0x1000); \
} while(0)
 
 
//-----------------------------------------------------------------------------
// Resources
 
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY 0x10000000
#define HAL_PCI_ALLOC_BASE_IO 0x1000
 
// This is where the PCI spaces are mapped in the CPU's address space.
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
#define HAL_PCI_PHYSICAL_IO_BASE 0xBE000000
 
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
/* Interrupt assignment as 21285 sees them. (From */ \
/* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_RESERVED_170, /* INTC# */ \
CYGNUM_HAL_INTERRUPT_RESERVED_169, /* INTB# */ \
CYGNUM_HAL_INTERRUPT_EXTERNAL_1, /* INTA# */ \
CYGNUM_HAL_INTERRUPT_RESERVED_171}; /* INTD# */ \
\
/* The PCI lines from the different slots are wired like this */ \
/* on the PCI backplane: */ \
/* pin6A pin7B pin7A pin8B */ \
/* System Slot INTA# INTB# INTC# INTD# */ \
/* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
/* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
/* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
/* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
/* */ \
/* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
/* */ \
/* Devsel signals are wired to, resulting in device IDs: */ \
/* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
/* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
/* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
/* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
/* */ \
/* (From PCI Development Backplane, 3.2.1 General) */ \
/* */ \
/* The observant reader will notice that the array does not */ \
/* match the table of how interrupts are wired. The array */ \
/* does however match observed behavior of the hardware: */ \
/* */ \
/* Observed interrupts with an Intel ethernet card */ \
/* put in the slots in turn and set to generate interrupts: */ \
/* slot 1/intA# (dev 8): caused host INTB# */ \
/* slot 2/intA# (dev 7): caused host INTC# */ \
/* slot 3/intA# (dev 6): caused host INTD# */ \
/* slot 4/intA# (dev 5): caused host INTA# */ \
\
__vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
 
 
//-----------------------------------------------------------------------------
// Bus address translation macros
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
CYG_MACRO_START \
(__bus_addr) = (CYG_ADDRESS)((cyg_uint32)(__cpu_addr)&~0x20000000); \
CYG_MACRO_END
 
#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
CYG_MACRO_START \
(__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
/src/ser_asb.c
0,0 → 1,506
//=============================================================================
//
// ser_asb.c
//
// Simple driver for the serial controllers on the AM33 ASB305 board
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors:dmoseley, nickg, gthomas
// Date: 2001-05-18
// Description: Simple driver for the ASB2305 debug serial port
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP macros
#include <cyg/hal/hal_io.h> // IO macros
#include <cyg/hal/hal_if.h> // interface API
#include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
#include <cyg/hal/hal_misc.h> // Helper functions
#include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
 
#if defined(CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS > 0
 
/*---------------------------------------------------------------------------*/
/* From serial_16550.h */
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x78
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x3C
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x1E
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x14
#endif
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
#define CYG_DEVICE_SERIAL_BAUD_MSB 0x00
#define CYG_DEVICE_SERIAL_BAUD_LSB 0x0A
#endif
 
#ifndef CYG_DEVICE_SERIAL_BAUD_MSB
#error Missing/incorrect serial baud rate defined - CDL error?
#endif
 
/*---------------------------------------------------------------------------*/
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x0C // line control register, read/write
#define CYG_DEV_MCR 0x10 // modem control register, read/write
#define CYG_DEV_LSR 0x14 // line status register, read
#define CYG_DEV_MSR 0x18 // modem status register, read
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
#define LSR_WAIT_FOR(STATE) do { cyg_uint8 lsr; do { HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); } while (!(lsr&SIO_LSR_##STATE)); } while(0)
#define LSR_QUERY(STATE) ({ cyg_uint8 lsr; HAL_READ_UINT8(base+CYG_DEV_LSR, lsr); (lsr&SIO_LSR_##STATE); })
 
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS
#define FLOWCTL_QUERY(LINE) ({ cyg_uint8 msr; HAL_READ_UINT8(base+CYG_DEV_MSR, msr); (msr&SIO_MSR_##LINE); })
#define FLOWCTL_WAIT_FOR(LINE) do { cyg_uint8 msr; do { HAL_READ_UINT8(base+CYG_DEV_MSR, msr); } while (!(msr&SIO_MSR_##LINE)); } while(0)
#define FLOWCTL_CLEAR(LINE) do { cyg_uint8 mcr; HAL_READ_UINT8(base+CYG_DEV_MCR,mcr); mcr &= ~SIO_MCR_##LINE; HAL_WRITE_UINT8(base+CYG_DEV_MCR, mcr); } while (0);
#define FLOWCTL_SET(LINE) do { cyg_uint8 mcr; HAL_READ_UINT8(base+CYG_DEV_MCR,mcr); mcr |= SIO_MCR_##LINE; HAL_WRITE_UINT8(base+CYG_DEV_MCR, mcr); } while (0);
 
#else
#define FLOWCTL_QUERY(LINE) 1
#define FLOWCTL_WAIT_FOR(LINE) do { ; } while(0)
#define FLOWCTL_CLEAR(LINE) do { ; } while(0)
#define FLOWCTL_SET(LINE) do { ; } while(0)
 
#endif
 
//-----------------------------------------------------------------------------
typedef struct {
cyg_uint8* base;
cyg_int32 msec_timeout;
int isr_vector;
} channel_data_t;
 
static channel_data_t asb2305_serial_channels[] = {
{ (cyg_uint8*)0xA6FB0000, 1000, CYGNUM_HAL_INTERRUPT_SERIAL_0_RX }
};
 
//-----------------------------------------------------------------------------
 
static void
cyg_hal_plf_serial_init_channel(const void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 lcr;
 
// 8-1-no parity.
HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
 
HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
lcr |= SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
lcr &= ~SIO_LCR_DLAB;
HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07); // Enable & clear FIFO
 
FLOWCTL_CLEAR(DTR);
FLOWCTL_CLEAR(RTS);
}
 
static void
cyg_hal_plf_serial_putc_aux(cyg_uint8* base, char c)
{
LSR_WAIT_FOR(THRE);
 
FLOWCTL_WAIT_FOR(CTS);
 
HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
}
 
void
cyg_hal_plf_serial_putc(void *__ch_data, char c)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
CYGARC_HAL_SAVE_GP();
 
FLOWCTL_SET(DTR);
 
cyg_hal_plf_serial_putc_aux(base,c);
 
FLOWCTL_CLEAR(DTR);
 
CYGARC_HAL_RESTORE_GP();
}
 
static cyg_bool
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 
if (!LSR_QUERY(DR))
return false;
 
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
 
return true;
}
 
cyg_uint8
cyg_hal_plf_serial_getc(void* __ch_data)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
cyg_uint8 ch;
CYGARC_HAL_SAVE_GP();
 
/* see if there's some cached data in the FIFO */
if (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch)) {
/* there isn't - open the flood gates */
FLOWCTL_WAIT_FOR(DSR);
FLOWCTL_SET(RTS);
 
while (!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
 
FLOWCTL_CLEAR(RTS);
}
 
CYGARC_HAL_RESTORE_GP();
return ch;
}
 
static void
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
cyg_uint32 __len)
{
cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
CYGARC_HAL_SAVE_GP();
 
FLOWCTL_SET(DTR);
 
while(__len-- > 0)
cyg_hal_plf_serial_putc_aux(__ch_data, *__buf++);
 
FLOWCTL_CLEAR(DTR);
 
CYGARC_HAL_RESTORE_GP();
}
 
static void
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
{
CYGARC_HAL_SAVE_GP();
 
while(__len-- > 0)
*__buf++ = cyg_hal_plf_serial_getc(__ch_data);
 
CYGARC_HAL_RESTORE_GP();
}
 
#define TM0MD 0xD4003000
#define TM0BR 0xD4003010
#define TM0BC 0xD4003020
 
cyg_bool
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
{
#if 1
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_uint8 last, val;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
/* see if there's any cached data in the FIFO */
res = cyg_hal_plf_serial_getc_nonblock(__ch_data,ch);
if (!res) {
/* there isn't - open the flood gates */
delay_count = chan->msec_timeout * 125; // want delay in 8uS steps
 
HAL_WRITE_UINT8(TM0BR,200); // IOCLK is 25MHz, we want 125KHz
HAL_WRITE_UINT8(TM0MD,0x40); // stop and load
HAL_WRITE_UINT8(TM0MD,0x80); // set source to be IOCLK and go
HAL_READ_UINT8(TM0BC,last);
 
while (delay_count>0 && !FLOWCTL_QUERY(DSR)) {
HAL_READ_UINT8(TM0BC,val);
if (val==last) continue;
if (val>last)
delay_count--; // count the underflows
last = val;
}
if (delay_count==0)
goto timeout;
 
FLOWCTL_SET(RTS);
 
while (delay_count>0 && !LSR_QUERY(DR)) {
HAL_READ_UINT8(TM0BC,val);
if (val==last) continue;
if (val>last)
delay_count--; // count the underflows
last = val;
}
 
FLOWCTL_CLEAR(RTS);
 
if (LSR_QUERY(DR)) {
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
res = true;
}
 
timeout:
HAL_WRITE_UINT8(TM0MD,0x00); // stop h/w timer
}
 
CYGARC_HAL_RESTORE_GP();
return res;
 
#else
int delay_count;
channel_data_t* chan = (channel_data_t*)__ch_data;
cyg_uint8* base = chan->base;
cyg_bool res;
CYGARC_HAL_SAVE_GP();
 
/* see if there's some cached data in the FIFO */
res = cyg_hal_plf_serial_getc_nonblock(__ch_data,ch);
if (!res) {
/* there isn't - open the flood gates */
delay_count = chan->msec_timeout * 1000; // want delay in uS steps
 
for (; delay_count>0 && !FLOWCTL_QUERY(DSR); delay_count--)
CYGACC_CALL_IF_DELAY_US(1);
if (delay_count==0)
goto timeout;
 
FLOWCTL_SET(RTS);
 
for (; delay_count>0 && !LSR_QUERY(DR); delay_count--)
CYGACC_CALL_IF_DELAY_US(1);
 
FLOWCTL_CLEAR(RTS);
 
if (LSR_QUERY(DR)) {
HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
res = true;
}
 
}
 
timeout:
CYGARC_HAL_RESTORE_GP();
return res;
#endif
}
 
static int
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
{
static int irq_state = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
int ret = 0;
CYGARC_HAL_SAVE_GP();
 
switch (__func) {
case __COMMCTL_IRQ_ENABLE:
irq_state = 1;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
 
HAL_INTERRUPT_UNMASK(chan->isr_vector);
break;
case __COMMCTL_IRQ_DISABLE:
ret = irq_state;
irq_state = 0;
 
HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
 
HAL_INTERRUPT_MASK(chan->isr_vector);
break;
case __COMMCTL_DBG_ISR_VECTOR:
ret = chan->isr_vector;
break;
case __COMMCTL_SET_TIMEOUT:
{
va_list ap;
 
va_start(ap, __func);
 
ret = chan->msec_timeout;
chan->msec_timeout = va_arg(ap, cyg_uint32);
 
va_end(ap);
}
default:
break;
}
CYGARC_HAL_RESTORE_GP();
return ret;
}
 
static int
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
{
int res = 0;
channel_data_t* chan = (channel_data_t*)__ch_data;
char c;
cyg_uint8 lsr;
CYGARC_HAL_SAVE_GP();
 
cyg_drv_interrupt_acknowledge(chan->isr_vector);
 
*__ctrlc = 0;
HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
if ( (lsr & SIO_LSR_DR) != 0 ) {
 
HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
if( cyg_hal_is_break( &c , 1 ) )
*__ctrlc = 1;
 
res = CYG_ISR_HANDLED;
}
 
CYGARC_HAL_RESTORE_GP();
return res;
}
 
static void
cyg_hal_plf_serial_init(void)
{
hal_virtual_comm_table_t* comm;
int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 
// Disable interrupts.
HAL_INTERRUPT_MASK(asb2305_serial_channels[0].isr_vector);
 
// Init channels
cyg_hal_plf_serial_init_channel(&asb2305_serial_channels[0]);
 
// Setup procs in the vector table
 
// Set channel 0
CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
comm = CYGACC_CALL_IF_CONSOLE_PROCS();
CYGACC_COMM_IF_CH_DATA_SET(*comm, &asb2305_serial_channels[0]);
CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
 
// Restore original console
CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
}
 
void
cyg_hal_plf_comms_init(void)
{
static int initialized = 0;
 
if (initialized)
return;
 
initialized = 1;
 
cyg_hal_plf_serial_init();
 
#if defined(CYGNUM_HAL_AM33_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_SERIAL_CHANNELS > 0
cyg_hal_am33_serial_init(1);
#endif
}
 
#endif // defined(CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS) && CYGNUM_HAL_AM33_PLF_SERIAL_CHANNELS > 0
 
/*---------------------------------------------------------------------------*/
/* End of ser_asb.c */
/src/plf_stub.c
0,0 → 1,202
//=============================================================================
//
// plf_stub.c
//
// Platform specific code for GDB stub support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dhowells
// Contributors:dmoseley
// Date: 2001-05-17
// Purpose: Platform specific code for GDB stub support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/hal_io.h> // HAL IO macros
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
#include <cyg/hal/hal_stub.h>
#include <cyg/hal/hal_intr.h> // HAL interrupt macros
 
/*---------------------------------------------------------------------------*/
// Define the serial registers.
#define CYG_DEV_RBR 0x00 // receiver buffer register, read, dlab = 0
#define CYG_DEV_THR 0x00 // transmitter holding register, write, dlab = 0
#define CYG_DEV_DLL 0x00 // divisor latch (LS), read/write, dlab = 1
#define CYG_DEV_IER 0x04 // interrupt enable register, read/write, dlab = 0
#define CYG_DEV_DLM 0x04 // divisor latch (MS), read/write, dlab = 1
#define CYG_DEV_IIR 0x08 // interrupt identification register, read, dlab = 0
#define CYG_DEV_FCR 0x08 // fifo control register, write, dlab = 0
#define CYG_DEV_LCR 0x0C // line control register, read/write
#define CYG_DEV_MCR 0x10 // modem control register, read/write
#define CYG_DEV_LSR 0x14 // line status register, read
#define CYG_DEV_MSR 0x18 // modem status register, read
 
// Interrupt Enable Register
#define SIO_IER_RCV 0x01
#define SIO_IER_XMT 0x02
#define SIO_IER_LS 0x04
#define SIO_IER_MS 0x08
 
// The line status register bits.
#define SIO_LSR_DR 0x01 // data ready
#define SIO_LSR_OE 0x02 // overrun error
#define SIO_LSR_PE 0x04 // parity error
#define SIO_LSR_FE 0x08 // framing error
#define SIO_LSR_BI 0x10 // break interrupt
#define SIO_LSR_THRE 0x20 // transmitter holding register empty
#define SIO_LSR_TEMT 0x40 // transmitter register empty
#define SIO_LSR_ERR 0x80 // any error condition
 
// The modem status register bits.
#define SIO_MSR_DCTS 0x01 // delta clear to send
#define SIO_MSR_DDSR 0x02 // delta data set ready
#define SIO_MSR_TERI 0x04 // trailing edge ring indicator
#define SIO_MSR_DDCD 0x08 // delta data carrier detect
#define SIO_MSR_CTS 0x10 // clear to send
#define SIO_MSR_DSR 0x20 // data set ready
#define SIO_MSR_RI 0x40 // ring indicator
#define SIO_MSR_DCD 0x80 // data carrier detect
 
// The line control register bits.
#define SIO_LCR_WLS0 0x01 // word length select bit 0
#define SIO_LCR_WLS1 0x02 // word length select bit 1
#define SIO_LCR_STB 0x04 // number of stop bits
#define SIO_LCR_PEN 0x08 // parity enable
#define SIO_LCR_EPS 0x10 // even parity select
#define SIO_LCR_SP 0x20 // stick parity
#define SIO_LCR_SB 0x40 // set break
#define SIO_LCR_DLAB 0x80 // divisor latch access bit
 
// Modem Control Register
#define SIO_MCR_DTR 0x01
#define SIO_MCR_RTS 0x02
#define SIO_MCR_INT 0x08 // Enable interrupts
 
#define SERIAL0BASE 0x86FB0000
 
//---------------------------------------------------------------------------
 
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
// This ISR is called from the interrupt handler. This should only
// happen when there is no serial driver, so the code shouldn't mess
// anything up.
int cyg_hal_gdb_isr(cyg_uint32 vector, target_register_t pc)
{
if ( CYGNUM_HAL_INTERRUPT_SERIAL_0_RX == vector ) {
cyg_uint8 c;
 
HAL_READ_UINT8(SERIAL0BASE+CYG_DEV_RBR,c);
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SERIAL_0_RX);
 
if( 3 == c )
{
// Ctrl-C: set a breakpoint at PC so GDB will display the
// correct program context when stopping rather than the
// interrupt handler.
cyg_hal_gdb_interrupt (pc);
 
// Interrupt handled. Don't call ISR proper. At return
// from the VSR, execution will stop at the breakpoint
// just set.
return 0;
}
}
 
// Not caused by GDB. Call ISR proper.
return 1;
}
#endif
 
//-----------------------------------------------------------------------------
 
void hal_asb_platform_init(void)
{
extern CYG_ADDRESS hal_virtual_vector_table[64];
extern void init_thread_syscall( void *);
extern void install_async_breakpoint(void *epc);
// void (*oldvsr)(void);
extern void _default_trap_vsr(void);
 
// Ensure that the breakpoint VSR points to the default VSR. This will pass
// it on to the stubs.
// HAL_VSR_SET( CYGNUM_HAL_VECTOR_BREAKPOINT, _default_trap_vsr, &oldvsr );
 
// Install async breakpoint handler into vector table.
hal_virtual_vector_table[35] = (CYG_ADDRESS)install_async_breakpoint;
 
#if !defined(CYGPKG_KERNEL) && defined(CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT)
// Only include this code if we do not have a kernel. Otherwise
// the kernel supplies the functionality for the app we are linked
// with.
 
// Prepare for application installation of thread info function in
// vector table.
hal_virtual_vector_table[15] = 0;
init_thread_syscall( (void *)&hal_virtual_vector_table[15] );
 
#endif
}
#endif // ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 
/*------------------------------------------------------------------------*/
/* Reset support */
 
#define RSTCTR 0xc0001004
#define CHIPRST 0x01
void cyg_hal_plf_reset(void)
{
// Unfortunately this only resets the MN103E010
// A full board reset is not done. ie If the boot block select switched,
// and a Cygmon reset called the switch change will not occur. AFAICT
// the only way to notice that change is to use the Reset switch on the
// board.
HAL_WRITE_UINT8(RSTCTR, 0x00);
HAL_WRITE_UINT8(RSTCTR, CHIPRST);
 
// Just in case.
while (1) ;
}
 
 
//-----------------------------------------------------------------------------
// End of plf_stub.c
/src/hal_diag.c
0,0 → 1,215
//=============================================================================
//
// hal_diag.c
//
// HAL diagnostic output code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley (based on the original by jskov)
// Contributors:nickg, jskov, dmoseley
// Date: 2000-08-11
// Purpose: HAL diagnostic output
// Description: Implementations of HAL diagnostic output support.
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#if !defined(CYGSEM_HAL_VIRTUAL_VECTOR_DIAG)
 
#warning HAL_DIAG has only been verified using CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
#include <cyg/infra/cyg_type.h> // base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_diag.h>
#include <cyg/hal/hal_intr.h>
 
#warning GET HAL_DIAG STUFF WORKING
 
/*---------------------------------------------------------------------------*/
/* Select default diag channel to use */
 
//#define CYG_KERNEL_DIAG_SERIAL
//#define CYG_KERNEL_DIAG_BUFFER
//#define CYG_KERNEL_DIAG_GDB
 
#if !defined(CYG_KERNEL_DIAG_SERIAL) && defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
# define CYG_KERNEL_DIAG_SERIAL
# define CYG_KERNEL_DIAG_GDB
#else
# define CYG_KERNEL_DIAG_SERIAL
#endif
 
/*---------------------------------------------------------------------------*/
 
externC void diag_write_string (const char*);
 
#if defined(CYG_KERNEL_DIAG_SERIAL)
extern void cyg_hal_plf_comms_init(void);
extern void cyg_hal_plf_serial_putc(void*, cyg_uint8);
extern cyg_uint8 cyg_hal_plf_serial_getc(void*);
#endif
 
#if defined(CYG_KERNEL_DIAG_BUFFER)
char hal_diag_buffer[10000];
int hal_diag_buffer_pos;
#endif
 
void hal_diag_init(void)
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_comms_init();
#endif
 
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer_pos = 0;
#endif
}
 
#ifdef CYG_KERNEL_DIAG_GDB
static void gdb_diag_write_char(char c)
{
static char line[100];
static int pos = 0;
 
// No need to send CRs
if( c == '\r' ) return;
 
line[pos++] = c;
 
if( c == '\n' || pos == sizeof(line) )
{
while (1)
{
static char hex[] = "0123456789ABCDEF";
cyg_uint8 csum = 0;
int i;
hal_diag_write_char_serial('$');
hal_diag_write_char_serial('O');
csum += 'O';
for( i = 0; i < pos; i++ )
{
char ch = line[i];
char h = hex[(ch>>4)&0xF];
char l = hex[ch&0xF];
hal_diag_write_char_serial(h);
hal_diag_write_char_serial(l);
csum += h;
csum += l;
}
hal_diag_write_char_serial('#');
hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
hal_diag_write_char_serial(hex[csum&0xF]);
 
{
char c1;
 
hal_diag_read_char_serial( &c1 );
 
if( c1 == '+' ) break;
 
if( cyg_hal_is_break( &c1, 1 ) )
cyg_hal_user_break( NULL );
}
}
pos = 0;
}
}
#endif // CYG_KERNEL_DIAG_GDB
 
void hal_diag_write_char(char c)
{
unsigned long __state;
 
HAL_DISABLE_INTERRUPTS(__state);
 
if(c == '\n')
{
#if defined (CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, '\r');
cyg_hal_plf_serial_putc(NULL, '\n');
#endif
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer[hal_diag_buffer_pos++] = c;
if (hal_diag_buffer_pos >= sizeof(hal_diag_buffer) )
hal_diag_buffer_pos = 0;
#endif
#if defined(CYG_KERNEL_DIAG_GDB)
gdb_diag_write_char(c);
#endif
}
else if (c == '\r')
{
// Ignore '\r'
}
else
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_putc(NULL, c);
#endif
#if defined(CYG_KERNEL_DIAG_BUFFER)
hal_diag_buffer[hal_diag_buffer_pos++] = c;
if (hal_diag_buffer_pos >= sizeof(hal_diag_buffer) )
hal_diag_buffer_pos = 0;
#endif
#if defined(CYG_KERNEL_DIAG_GDB)
gdb_diag_write_char(c);
#endif
}
 
HAL_RESTORE_INTERRUPTS(__state);
}
 
void hal_diag_read_char(char *c)
{
#if defined(CYG_KERNEL_DIAG_SERIAL)
cyg_hal_plf_serial_getc(c);
#endif
}
 
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 
/*---------------------------------------------------------------------------*/
/* End of hal_diag.c */
/src/plf_misc.c
0,0 → 1,273
//==========================================================================
//
// plf_misc.c
//
// HAL platform miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dmoseley (based on the original by nickg)
// Contributors: nickg, jlarmour, dmoseley
// Date: 2000-08-11
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h> // Base types
#include <cyg/infra/cyg_trac.h> // tracing macros
#include <cyg/infra/cyg_ass.h> // assertion macros
 
#include <cyg/hal/hal_arch.h> // architectural definitions
 
#include <cyg/hal/hal_intr.h> // Interrupt handling
 
#include <cyg/hal/hal_cache.h> // Cache handling
 
#include <cyg/hal/hal_if.h>
 
#include <cyg/hal/plf_io.h>
 
const cyg_uint8 hal_diag_digits[] = {
0x81, // 0
0xf3, // 1
0x49, // 2
0x61, // 3
0x33, // 4
0x25, // 5
0x05, // 6
0xf1, // 7
0x01, // 8
0x21, // 9
0x11, // A
0x07, // B
0x8d, // C
0x43, // D
0x0d, // E
0x1d // F
};
 
const char hal_diag_hex_digits[] = "0123456789ABCDEF";
 
cyg_uint32 hal_led_old_display = 0x5f17ffff; /* "rh " */
 
/*------------------------------------------------------------------------*/
/* LED support */
cyg_uint8 cyg_hal_plf_led_val(CYG_WORD hexdig)
{
return hal_diag_digits[(hexdig & 0xF)];
}
 
/*------------------------------------------------------------------------*/
 
#include CYGHWR_MEMORY_LAYOUT_H
#if defined(CYGPKG_CYGMON)
extern unsigned long cygmon_memsize;
#endif
 
void hal_platform_init(void)
{
*(cyg_uint8*)(&hal_led_old_display) = cyg_hal_plf_led_val(8);
HAL_WRITE_UINT32(HAL_LED_ADDRESS,hal_led_old_display);
 
#if defined(CYG_HAL_STARTUP_ROM)
// Note that the hardware seems to come up with the
// caches containing random data. Hence they must be
// invalidated before being enabled.
// However, we only do this if we are in ROM. If we are
// in RAM, then we leave the caches in the state chosen
// by the ROM monitor. If we enable them when the monitor
// is not expecting it, we can end up breaking things if the
// monitor is not doing cache flushes.
 
HAL_ICACHE_INVALIDATE_ALL();
HAL_ICACHE_ENABLE();
HAL_DCACHE_INVALIDATE_ALL();
HAL_DCACHE_ENABLE();
#endif
 
#if defined(CYGPKG_CYGMON)
cygmon_memsize = 16 * 1024 * 1024 - 0x200; // 16 MB - 0x200 (for _hal_vsr_table and _hal_virtual_vector_table)
#endif
 
// Set up eCos/ROM interfaces
hal_if_init();
#if defined(CYGPKG_KERNEL) && \
defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs)
{
extern CYG_ADDRESS hal_virtual_vector_table[32];
extern void patch_dbg_syscalls(void * vector);
patch_dbg_syscalls( (void *)(&hal_virtual_vector_table[0]) );
}
#endif
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
{
static void hal_ctrlc_isr_init(void);
hal_ctrlc_isr_init();
}
#endif
 
// Make sure the TBR points at the base of ROM
#if 0
{
#define TBR 0xC0000024
cyg_uint32 TBR_val;
HAL_READ_UINT32(TBR, TBR_val);
TBR_val = (TBR_val & 0x00FFFFFF) | 0x90000000; //(CYGMEM_REGION_rom & 0xFF000000);
HAL_WRITE_UINT32(TBR, TBR_val);
}
#endif
 
// Make sure the MTBR points at the base of ROM
#if 0
{
#define mTBR 0xC0000028
cyg_uint32 mTBR_val;
HAL_READ_UINT32(mTBR, mTBR_val);
mTBR_val = (mTBR_val & 0x00FFFFFF) | (CYGMEM_REGION_rom & 0xFF000000);
HAL_WRITE_UINT32(mTBR, mTBR_val);
}
#endif
}
 
/*------------------------------------------------------------------------*/
/* Functions to support the detection and execution of a user provoked */
/* program break. These are usually called from interrupt routines. */
 
/*------------------------------------------------------------------------*/
/* Control C ISR support */
#if defined(CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT)
 
#if CYGHWR_HAL_MN10300_AM33_STB_GDB_PORT == 0
 
// We use serial0 on AM33
#define SERIAL_CR ((volatile cyg_uint16 *)0xd4002000)
#define SERIAL_ICR ((volatile cyg_uint8 *) 0xd4002004)
#define SERIAL_TXR ((volatile cyg_uint8 *) 0xd4002008)
#define SERIAL_RXR ((volatile cyg_uint8 *) 0xd4002009)
#define SERIAL_SR ((volatile cyg_uint16 *)0xd400200c)
 
// Timer 1 provided baud rate divisor
#define TIMER_MD ((volatile cyg_uint8 *)0xd4003000)
#define TIMER_BR ((volatile cyg_uint8 *)0xd4003010)
#define TIMER_CR ((volatile cyg_uint8 *)0xd4003020)
 
#define SIO_LSTAT_TRDY 0x20
#define SIO_LSTAT_RRDY 0x10
 
#else
 
#error Unsupported GDB port
 
#endif
 
struct Hal_SavedRegisters *hal_saved_interrupt_state;
 
static void hal_ctrlc_isr_init(void)
{
// cyg_uint16 cr;
 
// HAL_READ_UINT16( SERIAL_CR, cr );
// cr |= LCR_RXE;
// HAL_WRITE_UINT16( SERIAL_CR, cr );
HAL_INTERRUPT_SET_LEVEL( CYGHWR_HAL_GDB_PORT_VECTOR, 4 );
HAL_INTERRUPT_UNMASK( CYGHWR_HAL_GDB_PORT_VECTOR );
}
 
cyg_uint32 hal_ctrlc_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
char c;
cyg_uint16 sr;
HAL_INTERRUPT_ACKNOWLEDGE( CYGHWR_HAL_GDB_PORT_VECTOR );
 
HAL_READ_UINT16( SERIAL_SR, sr );
 
if( sr & SIO_LSTAT_RRDY )
{
HAL_READ_UINT8( SERIAL_RXR, c);
 
if( cyg_hal_is_break( &c , 1 ) )
cyg_hal_user_break( (CYG_ADDRWORD *)hal_saved_interrupt_state );
 
}
return 1;
}
 
#endif
 
void hal_arch_funcall_new_stack(void (*func)(void), void* stack_base, cyg_uint32 stack_size)
{
register cyg_uint32 stack_top = (cyg_uint32)stack_base + stack_size;
register cyg_uint32 old_stack;
asm volatile (" mov sp, %0" : "=r" (old_stack) : );
asm volatile (" mov %0, sp" : : "r" (stack_top) );
func();
asm volatile (" mov %0, sp" : : "r" (old_stack) );
}
 
/*------------------------------------------------------------------------*/
/* Syscall support */
#ifdef CYGPKG_CYGMON
// Cygmon provides syscall handling for this board
#include <cyg/hal/hal_stub.h>
int __get_syscall_num (void)
{
return SIGSYS;
}
#endif
 
/*------------------------------------------------------------------------*/
/* flash write-protect support */
int plf_flash_query_soft_wp(void *addr, int len)
{
if (((unsigned long)addr & 0xFC000000UL) == 0x84000000UL)
return !(*(cyg_uint8*)0xA6FA0000 & 0x02); // system flash
else
return 0; // boot prom
}
 
/*------------------------------------------------------------------------*/
/* End of plf_misc.c */
/ChangeLog
0,0 → 1,147
2002-12-13 Mark Salter <msalter@redhat.com>
 
* include/platform.inc: Fix memory size test. Reduce wait counts
for chip select 3 (16550 uart).
* misc/redboot_FLASH.ecm: Turn off hw flow control on 16550.
* misc/redboot_FULLRAM.ecm: Ditto.
* misc/redboot_RAM.ecm: Ditto.
* misc/redboot_ROM.ecm: Ditto.
 
* cdl/hal_mn10300_am33_asb2305.cdl: Add support for CPU serial ports.
* src/ser_asb.c: Support configurations no 16550 and with
builtin AM33 serial ports.
 
2002-12-06 Mark Salter <msalter@redhat.com>
 
* cdl/hal_mn10300_am33_asb2305.cdl (CYG_HAL_FULL_RAM): New option to
indicate if RAM startup should use all RAM. This allows a special
RAM startup to be built which may be loaded onto a bare board by
the MEI tools. This can be used to build an initial RedBoot which
is used to program the flash with the ROM startup RedBoot image.
Implement CYGINT_HAL_MN10300_MEM_REAL_REGION_TOP.
 
* misc/redboot_FULLRAM.ecm:
* include/pkgconf/mlt_mn10300_am33_asb2305_fullram.h:
* include/pkgconf/mlt_mn10300_am33_asb2305_fullram.ldi:
* include/pkgconf/mlt_mn10300_am33_asb2305_fullram.mlt: New files.
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.h:
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.ldi:
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.mlt: Move ram base
so that ROM based RedBoot can load it.
 
* include/platform.inc: Add SDRAM runtime sizing.
 
2002-11-19 Mark Salter <msalter@redhat.com>
 
* cdl/hal_mn10300_am33_asb2305.cdl: Remove virtual vector comm support.
Add option to select platform serial port for comm channels. Add rules
to build RedBoot srec amd img file.
 
2002-11-15 Mark Salter <msalter@redhat.com>
 
* cdl/hal_mn10300_am33_asb2305.cdl: Override default VSR placement.
Removed unused options. Set correct clock speed.
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.ldi: Remove unneeded
defines.
* include/pkgconf/mlt_mn10300_am33_asb2305_flash.ldi: Ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_rom.ldi: Ditto.
 
2002-11-14 Mark Salter <msalter@redhat.com>
 
* cdl/hal_mn10300_am33_asb2305.cdl: Remove RedBoot exec option. Now
provided in generic AM33 code. Ditto for RTC support.
* src/plf_misc.c: hal_delay_us now provided by AM33 package.
* src/redboot_cmds.c: Remove.
 
2002-08-02 Andrew Lunn <Andrew.Lunn@ascom.ch>
 
* cdl/hal_mn10300_am33_asb2305.cdl: Redboot exec command can now
be disabled by CDL
2001-10-18 David Howells <dhowells@redhat.com>
 
* cdl/hal_mn10300_am33_asb2305.cdl: change incorrect "BootFlash"
to "BootPROM" where specified.
* cdl/hal_mn10300_am33_asb2305.cdl: added support for booting
directly from the system flash.
* include/platform.inc: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_flash.mlt: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_flash.h: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_flash.ldi: ditto.
* misc/redboot_FLASH.ecm: ditto.
 
2001-10-16 David Howells <dhowells@redhat.com>
 
* include/plf_io.h: made the CPU access PCI registers through the
uncached memmap reflection.
* cdl/hal_mn10300_am33_asb2305.cdl: moved the RTC configuration
previously added to MN10300 arch to the ASB2305 platform.
* include/platform.inc: display exception code on entry to NMI
handler and clear it on exit.
 
2001-10-15 David Howells <dhowells@redhat.com>
 
* misc/redboot_RAM.ecm: forced ethernet to switch down to 10Mbps
and switched syscall support on.
* misc/redboot_ROM.ecm: ditto.
 
* include/platform.inc: improved LED driving upon exception.
* src/plf_misc.c: ditto.
 
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.mlt: PCI window moved.
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.h: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_ram.ldi: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_rom.mlt: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_rom.h: ditto.
* include/pkgconf/mlt_mn10300_am33_asb2305_rom.ldi: ditto.
 
2001-08-22 Gary Thomas <gthomas@redhat.com>
 
* src/redboot_cmds.c:
printf() is no longer a part of RedBoot. Thus all programs
must use diag_printf() and related functions instead.
 
2001-08-08 David Howells <dhowells@redhat.com>
 
* hal_mn10300_am33_asb2305.cdl: Generate binary RedBoot image
files as well as ELF ones.
 
2001-07-27 David Howells <dhowells@redhat.com>
 
* New platform inaugurated.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/misc/redboot_RAM.ecm
0,0 → 1,107
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware asb2305 ;
template redboot ;
package -hardware CYGPKG_HAL_MN10300 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33_ASB2305 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_MN10300 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
 
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MN10300_ASB2305 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
 
package CYGPKG_IO_FLASH v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MN10300_ASB2305 v2_0 ;
package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value RAM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGOPT_REDBOOT_FIS {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_MN10300_ASB2305_BANK {
user_value "BootPROM"
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL324D {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 {
user_value 1
};
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
user_value 115200
};
 
cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
user_value 0
};
 
cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
user_value 0
};
 
cdl_option CYGSEM_DEVS_ETH_AMD_PCNET_FORCE_10MBPS {
user_value 1
};
 
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
/misc/redboot_FULLRAM.ecm
0,0 → 1,111
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware asb2305 ;
template redboot ;
package -hardware CYGPKG_HAL_MN10300 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33_ASB2305 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_MN10300 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
 
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MN10300_ASB2305 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
 
package CYGPKG_IO_FLASH v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MN10300_ASB2305 v2_0 ;
package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value RAM
};
 
cdl_option CYG_HAL_FULL_RAM {
user_value 1
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGOPT_REDBOOT_FIS {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_MN10300_ASB2305_BANK {
user_value "BootPROM"
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL324D {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 {
user_value 1
};
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
user_value 115200
};
 
cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
user_value 0
};
 
cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
user_value 0
};
 
cdl_option CYGSEM_DEVS_ETH_AMD_PCNET_FORCE_10MBPS {
user_value 1
};
 
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
/misc/redboot_FLASH.ecm
0,0 → 1,103
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware asb2305 ;
template redboot ;
package -hardware CYGPKG_HAL_MN10300 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33_ASB2305 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_MN10300 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
 
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MN10300_ASB2305 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
 
package CYGPKG_IO_FLASH v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MN10300_ASB2305 v2_0 ;
package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYG_HAL_ROM_SLOT {
user_value "SysFlash"
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_MN10300_ASB2305_BANK {
user_value "BootPROM"
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL324D {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 {
user_value 1
};
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
user_value 115200
};
 
cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
user_value 0
};
 
cdl_option CYGSEM_DEVS_ETH_AMD_PCNET_FORCE_10MBPS {
user_value 1
};
 
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};
/misc/redboot_ROM.ecm
0,0 → 1,103
cdl_savefile_version 1;
cdl_savefile_command cdl_savefile_version {};
cdl_savefile_command cdl_savefile_command {};
cdl_savefile_command cdl_configuration { description hardware template package };
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
 
cdl_configuration eCos {
description "" ;
hardware asb2305 ;
template redboot ;
package -hardware CYGPKG_HAL_MN10300 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33_ASB2305 v2_0 ;
package -hardware CYGPKG_HAL_MN10300_AM33 v2_0 ;
package -hardware CYGPKG_IO_SERIAL_MN10300 v2_0 ;
package -hardware CYGPKG_IO_PCI v2_0 ;
package -hardware CYGPKG_DEVICES_WATCHDOG_MN10300_MN10300 v2_0 ;
package -template CYGPKG_HAL v2_0 ;
package -template CYGPKG_INFRA v2_0 ;
package -template CYGPKG_REDBOOT v2_0 ;
 
package CYGPKG_IO_ETH_DRIVERS v2_0 ;
package -hardware CYGPKG_DEVS_ETH_MN10300_ASB2305 v2_0 ;
package -hardware CYGPKG_DEVS_ETH_AMD_PCNET v2_0 ;
 
package CYGPKG_IO_FLASH v2_0 ;
package -hardware CYGPKG_DEVS_FLASH_MN10300_ASB2305 v2_0 ;
package CYGPKG_DEVS_FLASH_AMD_AM29XXXXX v2_0 ;
};
 
cdl_option CYGBLD_BUILD_GDB_STUBS {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
user_value 0
};
 
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
inferred_value 0
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT {
inferred_value 1
};
 
cdl_option CYGDBG_HAL_DEBUG_GDB_CTRLC_SUPPORT {
inferred_value 0
};
 
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
inferred_value 0 0
};
 
cdl_option CYGSEM_HAL_ROM_MONITOR {
inferred_value 1
};
 
cdl_component CYG_HAL_STARTUP {
user_value ROM
};
 
cdl_component CYGBLD_BUILD_REDBOOT {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_MN10300_ASB2305_BANK {
user_value "SysFlash"
};
 
cdl_option CYGSEM_IO_FLASH_SOFT_WRITE_PROTECT {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29DL324D {
user_value 1
};
 
cdl_option CYGHWR_DEVS_FLASH_AMD_AM29LV800 {
user_value 1
};
 
cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD {
user_value 115200
};
 
cdl_option CYGSEM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_RTSCTS {
user_value 0
};
 
cdl_option CYGSEM_DEVS_ETH_AMD_PCNET_FORCE_10MBPS {
user_value 1
};
 
cdl_option CYGSEM_REDBOOT_BSP_SYSCALLS {
user_value 1
};

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