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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/powerpc/mpc5xx/v2_0
    from Rev 27 to Rev 174
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Rev 27 → Rev 174

/cdl/hal_powerpc_mpc5xx.cdl
0,0 → 1,365
# ====================================================================
#
# hal_powerpc_mpc5xx.cdl
#
# PowerPC/MPC5xx variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): Bob Koninckx
# Contributors:
# Date: 2001-08-12
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_POWERPC_MPC5xx {
display "PowerPC 5xx variant HAL"
parent CYGPKG_HAL_POWERPC
hardware
include_dir cyg/hal
define_header hal_powerpc_mpc5xx.h
description "
The PowerPC 5xx variant HAL package provides generic support
for this processor variant. It is also necessary to
select a specific target platform HAL package."
 
cdl_interface CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED {
display "ROM monitor configuration is unsupported"
no_define
}
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
display "Work with a ROM monitor"
flavor bool
default_value { (CYG_HAL_STARTUP == "RAM" &&
!CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS &&
!CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED &&
!CYGSEM_HAL_POWERPC_COPY_VECTORS) ? 1 : 0 }
parent CYGPKG_HAL_ROM_MONITOR
requires { CYG_HAL_STARTUP == "RAM" }
requires ! CYGSEM_HAL_POWERPC_COPY_VECTORS
requires ! CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
requires ! CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED
description "
Allow coexistence with ROM monitor (GDB stubs) by
only initializing interrupt vectors on startup, thus leaving
exception handling to the ROM monitor."
}
 
#cdl_option CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP {
# calculated 0
#}
 
#cdl_option CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP {
# calculated 0
#}
 
# FIXME: the option above should be adjusted to select between monitor
# variants
cdl_option CYGSEM_HAL_USE_ROM_MONITOR_GDB_stubs {
display "Bad CDL workaround"
calculated 1
active_if CYGSEM_HAL_USE_ROM_MONITOR
}
 
 
# Note: This should be sub-variant specific to reduce memory use.
define_proc {
puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3f9800)"
puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
}
 
cdl_component CYGPKG_HAL_POWERPC_MPC555 {
display "PowerPC 555 microcontroller"
implements CYGINT_HAL_POWERPC_VARIANT
description "
The PowerPC 555 microcontroller. This is an embedded part that in
addition to the PowerPC processor core has built in peripherals
such as memory controllers, DMA controllers, serial ports and
timers/counters."
 
cdl_option CYGHWR_HAL_POWERPC_FPU {
display "Variant FPU support"
flavor bool
default_value 0
description "
Enable or disable hardware support for floating point operations."
}
 
cdl_option CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT {
display "Fully IEEE floating point compliant"
flavor bool
default_value 0
active_if CYGHWR_HAL_POWERPC_FPU
requires CYGHWR_HAL_POWERPC_FPU
description "
Generate a floating point exception when the limits of the
floating point unit are reached. A software envelope can then
be used to generate the correct IEEE result for e.g. denormalized
numbers. If not enabled, the hardware will generate more than acceptable
values for these situation."
}
 
cdl_option CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE {
display "Enable On Chip Debugging (OCD, BDM)"
flavor bool
default_value 0
description "
This option forces the startup code to leave the OCD registers
unchanged. This allows for debugging with a BDM debugger."
}
 
cdl_option CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE {
display "Enable internal flash"
flavor bool
default_value 0
description "
Enable or disable the internal flash on the MPC5xx micro."
}
 
cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IFLASH_DUAL_MAP {
display "Dual mapping of the internal flash"
default_value 1
active_if !CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE
requires !CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE
description "
This option allows to re-map the internal flash array to external RAM
memory."
}
 
cdl_option CYGHWR_HAL_POWERPC_DISABLE_MMU {
display "Disable Memory Management Unit (MMU)"
calculated 1
description "
The MPC5xx does not have an MMU, there is no use in enabling it."
}
 
cdl_option CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER {
display "IMB3 arbitration ISR"
flavor bool
default_value 1
description "
The MPC5XX maps all IMB3 interrupt levels above 7 to SIU interrupt
level 7. If more than one IMB3 module is used at an interrupt level
higher than 7, interrupt arbiters must be chained on this level. This
option allows to chain multiple interrupt arbiters on SIU level 7.
This can be done using the functions hal_mpc5xx_install_imb3_arbiter
and hal_mpc5xx_remove_imb3_arbiter"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB {
display "Time base interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT {
display "PIT interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_RTC {
display "RTC interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_PLL {
display "PLL interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE1 {
display "QUADC A, QUEUE 1 interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE2 {
display "QUADC A, QUEUE 2 interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1 {
display "QUADC B, QUEUE 1 interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2 {
display "QUADC B, QUEUE 2 interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI {
display "QSCI interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI {
display "QSPI interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A {
display "TOUCAN A interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B {
display "TOUCAN B interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A {
display "TPU A interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B {
display "TPU B interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A {
display "MIOS A interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
 
cdl_option CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B {
display "MIOS B interrupt source priority"
flavor data
legal_values 0 to 31
default_value 0
description "Time base interrupt source priority. O-6 are mapped to SIU levels 0-6.
7-31 are mapped to SIU level 7"
}
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_powerpc.h>"
}
 
compile var_intr.c var_misc.c variant.S
 
cdl_option CYGPKG_HAL_POWERPC_MPC5xx_TESTS {
display "PowerPC MPC5xx tests"
flavor data
no_define
calculated { "tests/intr0" }
 
description "
This option specifies the set of tests for the PowerPC MPC5xx HAL."
}
 
cdl_option CYGBLD_BUILD_VERSION_TOOL {
display "Build MPC5xx version dump tool"
default_value 0
requires { CYG_HAL_STARTUP == "RAM" }
no_define
description "This option enables the building of a tool which will print the version identifiers of the CPU."
make -priority 320 {
<PREFIX>/bin/mpc5xxrev : <PACKAGE>/src/mpc5xxrev.c
@sh -c "mkdir -p src $(dir $@)"
$(CC) -c $(INCLUDE_PATH) -Wp,-MD,deps.tmp -I$(dir $<) $(CFLAGS) -o src/mpc5xxrev.o $<
@echo $@ ": \\" > $(notdir $@).deps
@echo $(wildcard $(PREFIX)/lib/*) " \\" >> $(notdir $@).deps
@tail +2 deps.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm deps.tmp
$(CC) $(LDFLAGS) -L$(PREFIX)/lib -Ttarget.ld -o $@ src/mpc5xxrev.o
}
}
 
}
/tests/intr0.c
0,0 → 1,307
//=================================================================
//
// intr0.c
//
// Interrupt test 0
//
//=================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov
// Date: 1998-12-01
// Description: Simple test of MPC860 interrupt handling when the
// kernel has not been configured. Uses timer interrupts.
// Options:
//####DESCRIPTIONEND####
 
//#define DEBUG_PRINTFS
#ifdef DEBUG_PRINTFS
extern diag_printf( char *format, ... );
#endif
 
#include <pkgconf/hal.h>
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/ppc_regs.h>
 
#include <cyg/hal/hal_intr.h>
 
#include <cyg/infra/testcase.h>
 
#ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
 
#undef CHECK(b)
#define CHECK(b) CYG_TEST_CHECK(b,#b)
 
// Can't rely on Cyg_Interrupt class being defined.
#define Cyg_InterruptHANDLED 1
 
// This is the period between interrupts, measured in decrementer ticks.
// Period must be longer than the time required for setting up all the
// interrupt handlers.
#define PIT_PERIOD 5000
 
#ifdef CYGPKG_HAL_POWERPC_MBX
#define TB_PERIOD (PIT_PERIOD*384) // PTA period is 15.36 uS
#else
#define TB_PERIOD (PIT_PERIOD*32) // assuming 512/16 divisors
#endif
 
#define ID_RTC_SEC 12345
#define ID_RTC_ALR 23451
#define ID_PIT 34512
#define ID_TBA 45123
#define ID_TBB 51234
 
volatile cyg_uint32 count = 0;
 
// Time/PERIOD 0 1 2 3 4 5 6 7 8 9 10
// Interrupt PIT TBA PIT PIT TBB PIT PIT
// pit_count 0 0 0 1 1 2 2 3 3 4 4
// count 0 0 1 3 4 4 5 40 41 42
 
static cyg_uint32 count_verify_table[] = {1, 4, 5, 41, 42};
static int pit_count = 0;
 
// These are useful for debugging:
static cyg_uint32 count_actual_table[] = { -1, -1, -1, -1, -1};
static cyg_uint32 tbr_actual_table[] = { -1, -1, -1, -1, -1};
 
// Periodic timer ISR. Should be executing 5 times.
static cyg_uint32 isr_pit(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 verify_value;
 
CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
 
CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_PIT == vector, "Wrong vector!");
CYG_ASSERT (ID_PIT == data, "Wrong data!");
 
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_PIT);
 
count++;
 
count_actual_table[pit_count] = count;
{
cyg_uint32 tbl;
CYGARC_MFTB (TBL_R, tbl);
tbr_actual_table[pit_count] = tbl;
}
 
verify_value = count_verify_table[pit_count++];
 
#ifdef DEBUG_PRINTFS
diag_printf( "ISR_PIT executed %d of 5\n", pit_count );
#endif
 
CYG_ASSERT (count == verify_value, "Count wrong!");
 
// End of test when count is 42. Mask interrupts and print PASS text.
if (42 <= count || 5 == pit_count) {
HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
HAL_INTERRUPT_MASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
 
#ifdef DEBUG_PRINTFS
diag_printf( "INFO: Actual counts: %d %d %d %d %d\n",
count_actual_table[0],
count_actual_table[1],
count_actual_table[2],
count_actual_table[3],
count_actual_table[4] );
diag_printf( "INFO: Actuals tbrs: %d %d %d %d %d\n",
tbr_actual_table[0],
tbr_actual_table[1],
tbr_actual_table[2],
tbr_actual_table[3],
tbr_actual_table[4] );
#endif
if (42 == count && 5 == pit_count)
CYG_TEST_PASS_FINISH("Intr 0 OK");
else
CYG_TEST_FAIL_FINISH("Intr 0 Failed.");
}
 
return Cyg_InterruptHANDLED;
}
 
// TimeBase A ISR. Should be executing once.
static cyg_uint32 isr_tba(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
 
CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_A == vector, "Wrong vector!");
CYG_ASSERT (ID_TBA == data, "Wrong data!");
 
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
 
count = count * 3;
 
#ifdef DEBUG_PRINTFS
diag_printf( "ISR_TBA executed\n" );
#endif
 
return Cyg_InterruptHANDLED;
}
 
// TimeBase B ISR. Should be executing once.
static cyg_uint32 isr_tbb(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
CYG_UNUSED_PARAM(CYG_ADDRWORD, data);
 
CYG_ASSERT (CYGNUM_HAL_INTERRUPT_SIU_TB_B == vector, "Wrong vector!");
CYG_ASSERT (ID_TBB == data, "Wrong data!");
 
HAL_INTERRUPT_ACKNOWLEDGE (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
 
count = count * 8;
 
#ifdef DEBUG_PRINTFS
diag_printf( "ISR_TBB executed\n" );
#endif
 
return Cyg_InterruptHANDLED;
}
 
void intr0_main( void )
{
CYG_TEST_INIT();
 
#if 0
// The A.3 revision of the CPU I'm using at the moment generates a
// machine check exception when writing to IMM_RTCSC. Smells a
// bit like the "SIU4. Spurious External Bus Transaction Following
// PLPRCR Write." CPU errata. Have to find out for sure. Run real
// time clock interrupts on level 0
{
// Still to do.
}
#endif
 
// Run periodic timer interrupt on level 1
{
cyg_uint16 piscr;
 
// Attach pit arbiter.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL1,
&hal_arbitration_isr_pit, ID_PIT, 0);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL1);
 
// Attach pit isr.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_PIT, &isr_pit,
ID_PIT, 0);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_PIT, 1);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_PIT);
 
 
// Set period.
HAL_WRITE_UINT32 (CYGARC_REG_IMM_PITC,
(2*PIT_PERIOD) << CYGARC_REG_IMM_PITC_COUNT_SHIFT);
 
#ifdef DEBUG_PRINTFS
diag_printf( "PIT set to %d\n", 2*PIT_PERIOD );
#endif
// Enable.
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= CYGARC_REG_IMM_PISCR_PTE;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
}
 
// Run timebase interrupts on level 2
{
cyg_uint16 tbscr;
cyg_uint32 tbl;
 
// Attach tb arbiter.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_LVL2,
&hal_arbitration_isr_tb, ID_TBA, 0);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_LVL2);
 
// Attach tb isrs.
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_A, &isr_tba,
ID_TBA, 0);
HAL_INTERRUPT_ATTACH (CYGNUM_HAL_INTERRUPT_SIU_TB_B, &isr_tbb,
ID_TBB, 0);
HAL_INTERRUPT_SET_LEVEL (CYGNUM_HAL_INTERRUPT_SIU_TB_A, 2);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
HAL_INTERRUPT_UNMASK (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
 
// Set reference A & B registers.
CYGARC_MFTB (TBL_R, tbl);
tbl += TB_PERIOD*3;
HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF0, tbl);
tbl += TB_PERIOD*4;
HAL_WRITE_UINT32 (CYGARC_REG_IMM_TBREF1, tbl);
 
#ifdef DEBUG_PRINTFS
diag_printf( "TB initial %d, !1 %d !2 %d\n",
tbl - 7*TB_PERIOD,
tbl - 4*TB_PERIOD,
tbl - 0*TB_PERIOD );
#endif
// Enable.
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= (CYGARC_REG_IMM_TBSCR_REFA | CYGARC_REG_IMM_TBSCR_REFB |
CYGARC_REG_IMM_TBSCR_TBE);
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= CYGARC_REG_IMM_TBSCR_REFAE | CYGARC_REG_IMM_TBSCR_REFBE;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
}
 
HAL_ENABLE_INTERRUPTS();
 
for (;;);
}
 
externC void
cyg_start( void )
{
intr0_main();
}
 
#else // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
 
externC void
cyg_start( void )
{
CYG_TEST_INIT();
CYG_TEST_PASS_FINISH("N/A: CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE disabled");
}
 
#endif // ifdef CYGSEM_HAL_POWERPC_MPC860_CPM_ENABLE
 
// EOF intr0.c
/include/var_cache.h
0,0 → 1,177
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// Variant HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors:Bob Koninckx
// Date: 2001-12-11
// Purpose: Variant cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations on the MPC8xx variant CPUs.
// Usage: Is included via the architecture cache header:
// #include <cyg/hal/hal_cache.h>
// ...
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/ppc_regs.h>
 
#include <cyg/hal/plf_cache.h>
 
 
//-----------------------------------------------------------------------------
// MPC5xx has no data or instruction cache. This is going to be a relatively
// simple file
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Disable the data cache
#define HAL_DCACHE_DISABLE() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
_state_ = 0; \
CYG_MACRO_END
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
 
//#define HAL_DCACHE_LOCK(_base_, _size_)
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC() \
CYG_MACRO_START \
CYG_MACRO_END
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
_state_ = 0; \
CYG_MACRO_END
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/include/var_intr.h
0,0 → 1,2845
#ifndef CYGONCE_VAR_INTR_H
#define CYGONCE_VAR_INTR_H
//=============================================================================
//
// var_intr.h
//
// Variant HAL interrupt and clock support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors:Bob Koninckx
// Date: 2001-12-15
// Purpose: Variant interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock on the MPC5xx variant CPUs.
// Usage: Is included via the architecture interrupt header:
// #include <cyg/hal/hal_intr.h>
// ...
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/plf_intr.h>
 
#include <cyg/infra/cyg_type.h> // types
 
#include <cyg/hal/ppc_regs.h> // register definitions
 
#include <cyg/hal/hal_io.h> // io macros
#include <cyg/infra/cyg_ass.h> // CYG_FAIL
 
//-----------------------------------------------------------------------------
// Special IMB3 arbitration code
typedef struct t_hal_mpc5xx_arbitration_data {
cyg_uint32 priority;
CYG_ADDRWORD data;
cyg_uint32 (* arbiter)(CYG_ADDRWORD, CYG_ADDRWORD);
void * reserved;
} hal_mpc5xx_arbitration_data;
 
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
externC void
hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data *adata);
 
//-----------------------------------------------------------------------------
// Exception vectors.
 
// Additional exceptions on the MPC5xx CPUs
#define CYGNUM_HAL_VECTOR_RESERVED_F 15
#define CYGNUM_HAL_VECTOR_SW_EMUL 16
#define CYGNUM_HAL_VECTOR_RESERVED_11 17
#define CYGNUM_HAL_VECTOR_RESERVED_12 18
#define CYGNUM_HAL_VECTOR_ITLB_ERROR 19
#define CYGNUM_HAL_VECTOR_DTLB_ERROR 20
#define CYGNUM_HAL_VECTOR_RESERVED_15 21
#define CYGNUM_HAL_VECTOR_RESERVED_16 22
#define CYGNUM_HAL_VECTOR_RESERVED_17 23
#define CYGNUM_HAL_VECTOR_RESERVED_18 24
#define CYGNUM_HAL_VECTOR_RESERVED_19 25
#define CYGNUM_HAL_VECTOR_RESERVED_1A 26
#define CYGNUM_HAL_VECTOR_RESERVED_1B 27
#define CYGNUM_HAL_VECTOR_DATA_BP 28
#define CYGNUM_HAL_VECTOR_INSTRUCTION_BP 29
#define CYGNUM_HAL_VECTOR_PERIPHERAL_BP 30
#define CYGNUM_HAL_VECTOR_NMI 31
 
#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_NMI
 
// These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
#define CYGNUM_HAL_EXCEPTION_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MACHINE_CHECK CYGNUM_HAL_VECTOR_MACHINE_CHECK
#define CYGNUM_HAL_EXCEPTION_RESERVED_3 CYGNUM_HAL_VECTOR_RESERVED_3
#define CYGNUM_HAL_EXCEPTION_RESERVED_4 CYGNUM_HAL_VECTOR_RESERVED_4
#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS CYGNUM_HAL_VECTOR_ALIGNMENT
#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_FP_UNAVAILABLE
#define CYGNUM_HAL_EXCEPTION_RESERVED_A CYGNUM_HAL_VECTOR_RESERVED_A
#define CYGNUM_HAL_EXCEPTION_RESERVED_B CYGNUM_HAL_VECTOR_RESERVED_B
#define CYGNUM_HAL_EXCEPTION_SYSTEM_CALL CYGNUM_HAL_VECTOR_SYSTEM_CALL
#define CYGNUM_HAL_EXCEPTION_TRACE CYGNUM_HAL_VECTOR_TRACE
#define CYGNUM_HAL_EXCEPTION_FP_ASSIST CYGNUM_HAL_VECTOR_FP_ASSIST
#define CYGNUM_HAL_EXCEPTION_RESERVED_F CYGNUM_HAL_VECTOR_RESERVED_F
#define CYGNUM_HAL_EXCEPTION_SW_EMUL CYGNUM_HAL_VECTOR_SW_EMUL
#define CYGNUM_HAL_EXCEPTION_RESERVED_11 CYGNUM_HAL_VECTOR_RESERVED_11
#define CYGNUM_HAL_EXCEPTION_RESERVED_12 CYGNUM_HAL_VECTOR_RESERVED_12
#define CYGNUM_HAL_EXCEPTION_CODE_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_ITLB_ERROR
#define CYGNUM_HAL_EXCEPTION_DATA_TLBERROR_ACCESS CYGNUM_HAL_VECTOR_DTLB_ERROR
#define CYGNUM_HAL_EXCEPTION_RESERVED_15 CYGNUM_HAL_VECTOR_RESERVED_15
#define CYGNUM_HAL_EXCEPTION_RESERVED_16 CYGNUM_HAL_VECTOR_RESERVED_16
#define CYGNUM_HAL_EXCEPTION_RESERVED_17 CYGNUM_HAL_VECTOR_RESERVED_17
#define CYGNUM_HAL_EXCEPTION_RESERVED_18 CYGNUM_HAL_VECTOR_RESERVED_18
#define CYGNUM_HAL_EXCEPTION_RESERVED_19 CYGNUM_HAL_VECTOR_RESERVED_19
#define CYGNUM_HAL_EXCEPTION_RESERVED_1A CYGNUM_HAL_VECTOR_RESERVED_1A
#define CYGNUM_HAL_EXCEPTION_RESERVED_1B CYGNUM_HAL_VECTOR_RESERVED_1B
#define CYGNUM_HAL_EXCEPTION_DATA_BP CYGNUM_HAL_VECTOR_DATA_BP
#define CYGNUM_HAL_EXCEPTION_INSTRUCTION_BP CYGNUM_HAL_VECTOR_INSTRUCTION_BP
#define CYGNUM_HAL_EXCEPTION_PERIPHERAL_BP CYGNUM_HAL_VECTOR_PERIPHERAL_BP
#define CYGNUM_HAL_EXCEPTION_NMI CYGNUM_HAL_VECTOR_NMI
 
// decoded exception vectors (decoded program exception)
#define CYGNUM_HAL_EXCEPTION_TRAP (-1)
#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION (-2)
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION (-3)
#define CYGNUM_HAL_EXCEPTION_FPU (-4)
 
#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_RESERVED_0
#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_NMI
 
#define CYGHWR_HAL_EXCEPTION_VECTORS_DEFINED
 
//-----------------------------------------------------------------------------
// Interrupts
 
// The first level of external interrupts
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ0 1
#define CYGNUM_HAL_INTERRUPT_SIU_LVL0 2
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ1 3
#define CYGNUM_HAL_INTERRUPT_SIU_LVL1 4
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ2 5
#define CYGNUM_HAL_INTERRUPT_SIU_LVL2 6
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ3 7
#define CYGNUM_HAL_INTERRUPT_SIU_LVL3 8
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ4 9
#define CYGNUM_HAL_INTERRUPT_SIU_LVL4 10
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ5 11
#define CYGNUM_HAL_INTERRUPT_SIU_LVL5 12
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ6 13
#define CYGNUM_HAL_INTERRUPT_SIU_LVL6 14
#define CYGNUM_HAL_INTERRUPT_SIU_IRQ7 15
#define CYGNUM_HAL_INTERRUPT_SIU_LVL7 16
 
// Further decoded interrupts
#define CYGNUM_HAL_INTERRUPT_SIU_TB_A 17 // Time base reference A
#define CYGNUM_HAL_INTERRUPT_SIU_TB_B 18 // Time base reference B
#define CYGNUM_HAL_INTERRUPT_SIU_PIT 19 // Periodic interrupt timer
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC 20 // Real time clock once per second
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR 21 // Real time clock alarm
#define CYGNUM_HAL_INTERRUPT_SIU_COL 22 // Change of lock of the PLL
 
// Even further decoded interrupts
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1 23 // QUADCA queue 1 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1 24 // QUADCA queue 1 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2 25 // QUADCA queue 2 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2 26 // QUADCA queue 2 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1 27 // QUADCB queue 1 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1 28 // QUADCB queue 1 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2 29 // QUADCB queue 2 completion
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2 30 // QUADCB queue 2 pause
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX 31 // SCI 0 transmit
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC 32 // SCI 0 transmit complete
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX 33 // SCI 0 receiver full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE 34 // SCI 0 idle line detected
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX 35 // SCI 1 transmit
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC 36 // SCI 1 transmit complete
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX 37 // SCI 1 receiver full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE 38 // SCI 1 idle line detected
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF 39 // SCI 1 RX Queue top half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF 40 // SCI 1 RX Queue bottom half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE 41 // SCI 1 TX Queue top half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE 42 // SCI 1 TX Queue bottom half full
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI 43 // SPI finished
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF 44 // SPI Mode fault
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA 45 // SPI Halt Acknowledge
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF 46 // TOUCANA buss off
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR 47 // TOUCANA error
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU 48 // TOUCANA wake up
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0 49 // TOUCANA buffer 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1 50 // TOUCANA buffer 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2 51 // TOUCANA buffer 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3 52 // TOUCANA buffer 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4 53 // TOUCANA buffer 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5 54 // TOUCANA buffer 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6 55 // TOUCANA buffer 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7 56 // TOUCANA buffer 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8 57 // TOUCANA buffer 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9 58 // TOUCANA buffer 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10 59 // TOUCANA buffer 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11 60 // TOUCANA buffer 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12 61 // TOUCANA buffer 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13 62 // TOUCANA buffer 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14 63 // TOUCANA buffer 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15 64 // TOUCANA buffer 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF 65 // TOUCANB buss off
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR 66 // TOUCANB error
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU 67 // TOUCANB wake up
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0 68 // TOUCANB buffer 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1 69 // TOUCANB buffer 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2 70 // TOUCANB buffer 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3 71 // TOUCANB buffer 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4 72 // TOUCANB buffer 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5 73 // TOUCANB buffer 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6 74 // TOUCANB buffer 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7 75 // TOUCANB buffer 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8 76 // TOUCANB buffer 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9 77 // TOUCANB buffer 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10 78 // TOUCANB buffer 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11 79 // TOUCANB buffer 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12 80 // TOUCANB buffer 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13 81 // TOUCANB buffer 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14 82 // TOUCANB buffer 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15 83 // TOUCANB buffer 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0 84 // TPU A channel 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1 85 // TPU A channel 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2 86 // TPU A channel 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3 87 // TPU A channel 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4 88 // TPU A channel 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5 89 // TPU A channel 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6 90 // TPU A channel 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7 91 // TPU A channel 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8 92 // TPU A channel 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9 93 // TPU A channel 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10 94 // TPU A channel 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11 95 // TPU A channel 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12 96 // TPU A channel 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13 97 // TPU A channel 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14 98 // TPU A channel 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15 99 // TPU A channel 15
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0 100 // TPU B channel 0
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1 101 // TPU B channel 1
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2 102 // TPU B channel 2
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3 103 // TPU B channel 3
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4 104 // TPU B channel 4
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5 105 // TPU B channel 5
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6 106 // TPU B channel 6
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7 107 // TPU B channel 7
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8 108 // TPU B channel 8
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9 109 // TPU B channel 9
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10 110 // TPU B channel 10
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11 111 // TPU B channel 11
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12 112 // TPU B channel 12
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13 113 // TPU B channel 13
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14 114 // TPU B channel 14
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15 115 // TPU B channel 15
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0 116 // MIOS PWM0
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1 117 // MIOS PWM1
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2 118 // MIOS PWM2
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3 119 // MIOS PWM3
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6 120 // MIOS MCSM6
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11 121 // MIOS MDASM11
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12 122 // MIOS MDASM12
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13 123 // MIOS MDASM13
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14 124 // MIOS MDASM14
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15 125 // MIOS MDASM15
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16 126 // MIOS PWM16
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17 127 // MIOS PWM17
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18 128 // MIOS PWM18
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19 129 // MIOS PWM19
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22 130 // MIOS MCSM22
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27 131 // MIOS MDASM27
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28 132 // MIOS MDASM28
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29 133 // MIOS MDASM29
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30 134 // MIOS MDASM30
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31 135 // MIOS MDASM31
 
#define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_DECREMENTER
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31
 
//--------------------------------------------------------------------------
// Interrupt controller access
static __inline__ void
cyg_hal_interrupt_mask ( cyg_uint32 vector )
{
switch (vector) {
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
{
// SIU interrupt vectors
cyg_uint32 simask;
 
HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
simask &= ~(((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0)
>> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
{
// TimeBase A interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFAE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
{
// TimeBase B interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFBE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_PIT:
{
// Periodic Interrupt
cyg_uint16 piscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr &= ~(CYGARC_REG_IMM_PISCR_PIE);
piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
{
// Real Time Clock Second
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SIE);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
{
// Real Time Clock Alarm
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALE);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_COL:
{
// PLL change of lock
cyg_uint16 colir;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_COLIR, colir);
colir &= ~(CYGARC_REG_IMM_COLIR_COLIE);
colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_COLIR, colir);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
quacr1 &= ~(CYGARC_REG_IMM_QUACR1_CIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
quacr1 &= ~(CYGARC_REG_IMM_QUACR1_PIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
quacr2 &= ~(CYGARC_REG_IMM_QUACR2_CIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
quacr2 &= ~(CYGARC_REG_IMM_QUACR2_PIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
quacr1 &= ~(CYGARC_REG_IMM_QUACR1_CIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
quacr1 &= ~(CYGARC_REG_IMM_QUACR1_PIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
quacr2 &= ~(CYGARC_REG_IMM_QUACR2_CIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
{
cyg_uint16 quacr2;
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
quacr2 &= ~(CYGARC_REG_IMM_QUACR2_PIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TCIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_RIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_ILIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_TCIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_RIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 &= ~(CYGARC_REG_IMM_SCCxR1_ILIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QTHFI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QBHFI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QTHEI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr &= ~(CYGARC_REG_IMM_QSCI1CR_QBHEI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
{
cyg_uint16 spcr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
spcr2 &= ~(CYGARC_REG_IMM_SPCR2_SPIFIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
{
cyg_uint16 spcr3;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
spcr3 &= ~(CYGARC_REG_IMM_SPCR3_HMIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_ERRMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
{
cyg_uint16 tcnmcr;
HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
tcnmcr &= ~(CYGARC_REG_IMM_TCNMCR_WAKEMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
{
cyg_uint16 imask;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
imask &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
canctrl0 &= ~(CYGARC_REG_IMM_CANCTRL0_ERRMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
{
cyg_uint16 tcnmcr;
HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
tcnmcr &= ~(CYGARC_REG_IMM_TCNMCR_WAKEMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
{
cyg_uint16 imask;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
imask &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
{
cyg_uint16 cier;
HAL_READ_UINT16(CYGARC_REG_IMM_CIER_A, cier);
cier &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_A, cier);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
{
cyg_uint16 cier;
HAL_READ_UINT16(CYGARC_REG_IMM_CIER_B, cier);
cier &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_B, cier);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN0);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN3);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN6);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN11);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN12);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN13);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN14);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 &= ~(CYGARC_REG_IMM_MIOS1ER0_EN15);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN16);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN17);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN18);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN19);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN22);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN27);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN28);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN29);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN30);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 &= ~(CYGARC_REG_IMM_MIOS1ER1_EN31);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
default:
CYG_FAIL("Unknown Interrupt!!!");
break;
}
}
 
static __inline__ void
cyg_hal_interrupt_unmask ( cyg_uint32 vector )
{
switch (vector) {
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
{
// SIU interrupt vectors
cyg_uint32 simask;
 
HAL_READ_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
simask |= (((cyg_uint32) CYGARC_REG_IMM_SIMASK_IRM0)
>> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIMASK, simask);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_A :
{
// TimeBase A interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= (CYGARC_REG_IMM_TBSCR_REFAE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_TB_B :
{
// TimeBase B interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= (CYGARC_REG_IMM_TBSCR_REFBE);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent from clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_PIT:
{
// Periodic Interrupt
cyg_uint16 piscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= (CYGARC_REG_IMM_PISCR_PIE);
piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
{
// Real Time Clock Second
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc |= (CYGARC_REG_IMM_RTCSC_SIE);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
{
// Real Time Clock Alarm
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc |= (CYGARC_REG_IMM_RTCSC_ALE);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do what is asdked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_COL:
{
// PLL change of lock
cyg_uint16 colir;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_COLIR, colir);
colir |= (CYGARC_REG_IMM_COLIR_COLIE);
colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_COLIR, colir);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_A, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
quacr2 |= (CYGARC_REG_IMM_QUACR2_PIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_A, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
quacr1 |= (CYGARC_REG_IMM_QUACR1_CIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
{
cyg_uint16 quacr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
quacr1 |= (CYGARC_REG_IMM_QUACR1_PIE1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR1_B, quacr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
{
cyg_uint16 quacr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
quacr2 |= (CYGARC_REG_IMM_QUACR2_CIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
{
cyg_uint16 quacr2;
HAL_READ_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
quacr2 |= (CYGARC_REG_IMM_QUACR2_PIE2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUACR2_B, quacr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TCIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_RIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_ILIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC1R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_TCIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_RIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
{
cyg_uint16 sccxr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
sccxr1 |= (CYGARC_REG_IMM_SCCxR1_ILIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SCC2R1, sccxr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QTHFI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QBHFI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QTHEI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
{
cyg_uint16 qsci1cr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
qsci1cr |= (CYGARC_REG_IMM_QSCI1CR_QBHEI);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1CR, qsci1cr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
{
cyg_uint16 spcr2;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
spcr2 |= (CYGARC_REG_IMM_SPCR2_SPIFIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR2, spcr2);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
{
cyg_uint16 spcr3;
 
HAL_READ_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
spcr3 |= (CYGARC_REG_IMM_SPCR3_HMIE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPCR3, spcr3);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_ERRMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
{
cyg_uint16 tcnmcr;
HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
tcnmcr |= (CYGARC_REG_IMM_TCNMCR_WAKEMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_A, tcnmcr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
{
cyg_uint16 imask;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
imask |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_A, imask);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_BOFFMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
{
cyg_uint16 canctrl0;
HAL_READ_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
canctrl0 |= (CYGARC_REG_IMM_CANCTRL0_ERRMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B, canctrl0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
{
cyg_uint16 tcnmcr;
HAL_READ_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
tcnmcr |= (CYGARC_REG_IMM_TCNMCR_WAKEMSK);
HAL_WRITE_UINT16(CYGARC_REG_IMM_TCNMCR_B, tcnmcr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
{
cyg_uint16 imask;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
imask |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IMASK_B, imask);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
{
cyg_uint16 cier;
HAL_READ_UINT16(CYGARC_REG_IMM_CIER_A, cier);
cier |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_A, cier);
break;
}
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
{
cyg_uint16 cier;
HAL_READ_UINT16(CYGARC_REG_IMM_CIER_B, cier);
cier |= (((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CIER_B, cier);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN0);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN3);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN6);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN11);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN12);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN13);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN14);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
{
cyg_uint16 mios1er0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
mios1er0 |= (CYGARC_REG_IMM_MIOS1ER0_EN15);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER0, mios1er0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN16);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN17);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN18);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN19);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN22);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN27);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN28);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN29);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN30);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
{
cyg_uint16 mios1er1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
mios1er1 |= (CYGARC_REG_IMM_MIOS1ER1_EN31);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1ER1, mios1er1);
break;
}
 
default:
CYG_FAIL("Unknown Interrupt!!!");
break;
}
}
 
static __inline__ void
cyg_hal_interrupt_acknowledge ( cyg_uint32 vector )
{
switch (vector) {
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
{
// SIU interrupt vectors
cyg_uint32 sipend;
 
// When IRQx is configured as an edge interrupt it needs to be
// cleared. Write to INTx and IRQ/level bits are ignore so
// it's safe to do always.
HAL_READ_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
sipend |= (((cyg_uint32) CYGARC_REG_IMM_SIPEND_IRQ0)
>> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIPEND, sipend);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
{
// TimeBase A interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= CYGARC_REG_IMM_TBSCR_REFA;
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // Only acknowledge the requested one
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
{
// TimeBase B interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr |= CYGARC_REG_IMM_TBSCR_REFB;
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Only acknowledge the requested one.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_PIT:
{
// Periodic Interrupt
cyg_uint16 piscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr |= CYGARC_REG_IMM_PISCR_PS;
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
{
// Real Time Clock Second
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc |= CYGARC_REG_IMM_RTCSC_SEC;
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // Only acknowledge the requested one
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
{
// Real Time Clock Alarm
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc |= CYGARC_REG_IMM_RTCSC_ALR;
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Only acknowledge the requested one
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_COL:
{
cyg_uint16 colir;
 
HAL_READ_UINT16(CYGARC_REG_IMM_COLIR, colir);
colir |= CYGARC_REG_IMM_COLIR_COLIS;
HAL_WRITE_UINT16(CYGARC_REG_IMM_COLIR, colir);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_A, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_CF2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
{
cyg_uint16 quasr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
quasr0 &= ~(CYGARC_REG_IMM_QUASR0_PF2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUASR0_B, quasr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
// Nothing needs to be done here
break;
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
{
cyg_uint16 scxsr;
HAL_READ_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SC1SR, scxsr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
// nothing needs to be done here
break;
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
{
cyg_uint16 scxsr;
HAL_READ_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
scxsr &= ~(CYGARC_REG_IMM_SCxSR_IDLE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SC2SR, scxsr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
{
cyg_uint16 qsci1sr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHF);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
{
cyg_uint16 qsci1sr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHF);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
{
cyg_uint16 qsci1sr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QTHE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
{
cyg_uint16 qsci1sr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
qsci1sr &= ~(CYGARC_REG_IMM_QSCI1SR_QBHE);
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSCI1SR, qsci1sr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
{
cyg_uint16 spsr;
HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
spsr &= ~(CYGARC_REG_IMM_SPSR_SPIF);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
{
cyg_uint16 spsr;
HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
spsr &= ~(CYGARC_REG_IMM_SPSR_MODF);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
{
cyg_uint16 spsr;
HAL_READ_UINT16(CYGARC_REG_IMM_SPSR, spsr);
spsr &= ~(CYGARC_REG_IMM_SPSR_HALTA);
HAL_WRITE_UINT16(CYGARC_REG_IMM_SPSR, spsr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read the flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_BOFFINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read the flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_ERRINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // Read tthe flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_WAKEINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_A, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
{
cyg_uint16 iflag;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IFLAG_A, iflag); // Read the flag as a one
iflag &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IFLAG_A, iflag); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_BOFFINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_ERRINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
{
cyg_uint16 estat;
HAL_READ_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // Read the flag as a one
estat &= ~(CYGARC_REG_IMM_ESTAT_WAKEINT);
HAL_WRITE_UINT16(CYGARC_REG_IMM_ESTAT_B, estat); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
{
cyg_uint16 iflag;
 
HAL_READ_UINT16(CYGARC_REG_IMM_IFLAG_B, iflag); // Read the flag as a one
iflag &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_IFLAG_B, iflag); // And write it as a zero
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
{
cyg_uint16 cisr;
HAL_READ_UINT16(CYGARC_REG_IMM_CISR_A, cisr);
cisr &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CISR_A, cisr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
{
cyg_uint16 cisr;
HAL_READ_UINT16(CYGARC_REG_IMM_CISR_B, cisr);
cisr &= ~(((cyg_uint16)0x0001) << (vector - CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0));
HAL_WRITE_UINT16(CYGARC_REG_IMM_CISR_B, cisr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL0);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL1);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL2);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL3);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL6);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL11);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL12);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL13);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL14);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
{
cyg_uint16 mios1sr0;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
mios1sr0 &= ~(CYGARC_REG_IMM_MIOS1SR0_FL15);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR0, mios1sr0);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL16);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL17);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL18);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL19);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL22);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL27);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL28);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL29);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL30);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
{
cyg_uint16 mios1sr1;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
mios1sr1 &= ~(CYGARC_REG_IMM_MIOS1SR1_FL31);
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1SR1, mios1sr1);
break;
}
 
 
default:
CYG_FAIL("Unknown Interrupt!!!");
break;
}
}
 
static __inline__ void
cyg_hal_interrupt_configure ( cyg_uint32 vector,
cyg_bool level,
cyg_bool up )
{
switch (vector) {
// Only external interrupts can be fully configured in the true meaning of the word
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ1:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ2:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ3:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ4:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ5:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ6:
case CYGNUM_HAL_INTERRUPT_SIU_IRQ7:
{
// External interrupts
cyg_uint32 siel, bit;
 
CYG_ASSERT( level || !up, "Only falling edge is supported");
 
bit = (((cyg_uint32) CYGARC_REG_IMM_SIEL_ED0)
>> (vector - CYGNUM_HAL_INTERRUPT_SIU_IRQ0));
 
HAL_READ_UINT32 (CYGARC_REG_IMM_SIEL, siel);
siel &= ~bit;
if (!level) {
// Set edge detect bit.
siel |= bit;
}
HAL_WRITE_UINT32 (CYGARC_REG_IMM_SIEL, siel);
break;
}
 
// Attempts to configure all other interrupt sources should fail
default:
CYG_FAIL("Unknown Interrupt!!!");
break;
}
}
 
static __inline__ void
cyg_hal_interrupt_set_level ( cyg_uint32 vector, cyg_uint32 level )
{
if(vector < CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1)
{
// Note: highest priority has the lowest numerical value.
CYG_ASSERT( level >= CYGARC_SIU_PRIORITY_HIGH, "Invalid priority");
CYG_ASSERT( level <= CYGARC_SIU_PRIORITY_LOW, "Invalid priority");
}
else
{
CYG_ASSERT( level >= CYGARC_IMB3_PRIORITY_HIGH, "Invalid priority");
CYG_ASSERT( level <= CYGARC_IMB3_PRIORITY_LOW, "Invalid priority");
}
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_SIU_IRQ0 ... CYGNUM_HAL_INTERRUPT_SIU_LVL7:
// These cannot be configured.
break;
 
case CYGNUM_HAL_INTERRUPT_SIU_TB_A:
case CYGNUM_HAL_INTERRUPT_SIU_TB_B:
{
// TimeBase A+B interrupt
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
tbscr &= ~(CYGARC_REG_IMM_TBSCR_IRQMASK);
tbscr |= CYGARC_REG_IMM_TBSCR_IRQ0 >> level;
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFA); // Prevent fom clearing interrupt flags
tbscr &= ~(CYGARC_REG_IMM_TBSCR_REFB); // accidently. Just do what is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_PIT:
{
// Periodic Interrupt
cyg_uint16 piscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
piscr &= ~(CYGARC_REG_IMM_PISCR_IRQMASK);
piscr |= CYGARC_REG_IMM_PISCR_IRQ0 >> level;
piscr &= ~(CYGARC_REG_IMM_PISCR_PS); // Prevent from clearing interrupt flag.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC:
case CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR:
{
// Real Time Clock Second & Real Time Clock Alarm
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_IRQMASK);
rtcsc |= CYGARC_REG_IMM_RTCSC_IRQ0 >> level;
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_SEC); // Prevent from clearing interrupt flags
rtcsc &= ~(CYGARC_REG_IMM_RTCSC_ALR); // accidently. Just do wahat is asked.
HAL_WRITE_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
break;
}
 
case CYGNUM_HAL_INTERRUPT_SIU_COL:
{
cyg_uint16 colir;
HAL_READ_UINT16(CYGARC_REG_IMM_COLIR, colir);
colir &= ~(CYGARC_REG_IMM_COLIR_COLIRQ); // mask out the level
colir |= CYGARC_REG_IMM_COLIR_IRQ0 >> level; // and set the new level
colir &= ~(CYGARC_REG_IMM_COLIR_COLIS); // Prevent from clearing interrupt flag accidently.
HAL_WRITE_UINT16(CYGARC_REG_IMM_COLIR, colir);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1:
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1:
{
cyg_uint16 quadc64int;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL1);
quadc64int |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2:
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2:
{
cyg_uint16 quadc64int;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL2);
quadc64int |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_A, quadc64int);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1:
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1:
{
cyg_uint16 quadc64int;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL1);
quadc64int |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2:
case CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2:
{
cyg_uint16 quadc64int;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
quadc64int &= ~(CYGARC_REG_IMM_QUADC64INT_IRL2);
quadc64int |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QUADC64INT_B, quadc64int);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE:
case CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE:
{
cyg_uint16 qdsci_il;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QDSCI_IL_ILDSCI_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QDSCI_IL, qdsci_il);
qdsci_il &= ~(CYGARC_REG_IMM_QDSCI_IL_ILDSCI);
qdsci_il |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QDSCI_IL, qdsci_il);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI:
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF:
case CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA:
{
cyg_uint16 qspi_il;
cyg_uint16 the_level = level << CYGARC_REG_IMM_QSPI_IL_ILQSPI_SHIFT;
 
HAL_READ_UINT16(CYGARC_REG_IMM_QSPI_IL, qspi_il);
qspi_il &= ~(CYGARC_REG_IMM_QSPI_IL_ILQSPI);
qspi_il |= the_level;
HAL_WRITE_UINT16(CYGARC_REG_IMM_QSPI_IL, qspi_il);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15:
{
cyg_uint16 irl = (level % 8) << CYGARC_REG_IMM_CANICR_IRL_SHIFT;
cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_CANICR_ILBS_SHIFT;
cyg_uint16 canicr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_CANICR_A, canicr);
canicr &= ~(CYGARC_REG_IMM_CANICR_IRL);
canicr &= ~(CYGARC_REG_IMM_CANICR_ILBS);
canicr |= irl;
canicr |= ilsb;
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANICR_A, canicr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14:
case CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15:
{
cyg_uint16 irl = (level % 8) << CYGARC_REG_IMM_CANICR_IRL_SHIFT;
cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_CANICR_ILBS_SHIFT;
cyg_uint16 canicr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_CANICR_B, canicr);
canicr &= ~(CYGARC_REG_IMM_CANICR_IRL);
canicr &= ~(CYGARC_REG_IMM_CANICR_ILBS);
canicr |= irl;
canicr |= ilsb;
HAL_WRITE_UINT16(CYGARC_REG_IMM_CANICR_B, canicr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15:
{
cyg_uint16 cirl = (level % 8) << CYGARC_REG_IMM_TICR_CIRL_SHIFT;
cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_TICR_ILBS_SHIFT;
cyg_uint16 ticr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_TICR_A, ticr);
ticr &= ~(CYGARC_REG_IMM_TICR_CIRL);
ticr &= ~(CYGARC_REG_IMM_TICR_ILBS);
ticr |= cirl;
ticr |= ilsb;
HAL_WRITE_UINT16(CYGARC_REG_IMM_TICR_A, ticr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14:
case CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15:
{
cyg_uint16 cirl = (level % 8) << CYGARC_REG_IMM_TICR_CIRL_SHIFT;
cyg_uint16 ilsb = (level / 8) << CYGARC_REG_IMM_TICR_ILBS_SHIFT;
cyg_uint16 ticr;
 
HAL_READ_UINT16(CYGARC_REG_IMM_TICR_B, ticr);
ticr &= ~(CYGARC_REG_IMM_TICR_CIRL);
ticr &= ~(CYGARC_REG_IMM_TICR_ILBS);
ticr |= cirl;
ticr |= ilsb;
HAL_WRITE_UINT16(CYGARC_REG_IMM_TICR_B, ticr);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15:
{
cyg_uint16 lvl = (level % 8) << CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT;
cyg_uint16 tm = (level / 8) << CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT;
cyg_uint16 mios1lvl;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1LVL0, mios1lvl);
mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_LVL);
mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_TM);
mios1lvl |= lvl;
mios1lvl |= tm;
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1LVL0, mios1lvl);
break;
}
 
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30:
case CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31:
{
cyg_uint16 lvl = (level % 8) << CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT;
cyg_uint16 tm = (level / 8) << CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT;
cyg_uint16 mios1lvl;
 
HAL_READ_UINT16(CYGARC_REG_IMM_MIOS1LVL1, mios1lvl);
mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_LVL);
mios1lvl &= ~(CYGARC_REG_IMM_MIOS1LVL_TM);
mios1lvl |= lvl;
mios1lvl |= tm;
HAL_WRITE_UINT16(CYGARC_REG_IMM_MIOS1LVL1, mios1lvl);
break;
}
 
default:
CYG_FAIL("Unknown Interrupt!!!");
break;
}
}
// The decrementer interrupt cannnot be masked, configured or acknowledged.
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
cyg_hal_interrupt_mask ( (_vector_) ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
cyg_hal_interrupt_unmask ( (_vector_) ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
cyg_hal_interrupt_acknowledge ( (_vector_) ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
CYG_MACRO_START \
if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
cyg_hal_interrupt_configure ( (_vector_), (_level_), (_up_) ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
CYG_MACRO_START \
if (CYGNUM_HAL_INTERRUPT_DECREMENTER != (_vector_)) \
cyg_hal_interrupt_set_level ( (_vector_) , (_level_) ); \
CYG_MACRO_END
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
//--------------------------------------------------------------------------
// Interrupt arbiters
externC cyg_uint32 hal_arbitration_isr_tb (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_pit (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
externC cyg_uint32 hal_arbitration_isr_rtc (CYG_ADDRWORD vector,
CYG_ADDRWORD data);
 
//-----------------------------------------------------------------------------
// Symbols used by assembly code
#define CYGARC_VARIANT_DEFS \
DEFINE(CYGNUM_HAL_VECTOR_NMI, CYGNUM_HAL_VECTOR_NMI);
 
//-----------------------------------------------------------------------------
// Interrupt source priorities
// Maybe this is not the best way to do this. Fact remains that these priorities
// are not hard wired by the board layout, but are all software configurable. Not
// so easy to combine flexibility with generality
#define CYGNUM_HAL_INTERRUPT_SIU_TB_A_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB
#define CYGNUM_HAL_INTERRUPT_SIU_TB_B_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TB
#define CYGNUM_HAL_INTERRUPT_SIU_PIT_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_PIT
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_RTC
#define CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_RTC
#define CYGNUM_HAL_INTERRUPT_SIU_COL_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_PLL
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE1
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE1
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_CI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE2
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCA_PI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_A_QUEUE2
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE1
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_CI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
#define CYGNUM_HAL_INTERRUPT_IMB3_QUADCB_PI2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QUADC_B_QUEUE2
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_TXC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_RX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI0_IDLE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXC_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RX_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_IDLE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQTHF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_RXQBHF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQTHE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SCI1_TXQBHE_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSCI
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_FI_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_MODF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
#define CYGNUM_HAL_INTERRUPT_IMB3_SPI_HALTA_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_QSPI
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_BOFF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_ERR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_WU_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANA_B15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_BOFF_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_ERR_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_WU_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TOUCANB_B15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TOUCAN_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUA_CH15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_A
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH4_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH5_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH7_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH8_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH9_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH10_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_TPUB_CH15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_TPU_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM0_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM1_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM2_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM3_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM6_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM11_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM12_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM13_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM14_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM15_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_A
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM16_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM17_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM18_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MPWM19_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MMCSM22_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM27_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM28_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM29_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM30_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
#define CYGNUM_HAL_INTERRUPT_IMB3_MIOS_MDASM31_PRIORITY CYGNUM_HAL_ISR_SOURCE_PRIORITY_MIOS_B
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_INTR_H
// End of var_intr.h
/include/variant.inc
0,0 → 1,273
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## MPC5xx family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): Bob Koninckx
## Contributors:Bob Koninckx
## Date: 2001-12-15
## Purpose: MPC5xx family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the MPC5xx CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
##------------------------------------------------------------------------------
## Handle denormalized numbers etc in hardware, or use a software envelope to
## generate 100% IEEE correct results
#define FULL_IEEE_FLOATING_POINT_SUPPORT 29
 
#include <pkgconf/hal.h>
#include <cyg/hal/arch.inc>
 
##-----------------------------------------------------------------------------
## MPC5xx defined vectors
 
.macro hal_extra_vectors
# MPC5xx vectors
exception_vector software_emu
exception_vector reserved_01100
exception_vector reserved_01200
exception_vector instruction_tlb_error
exception_vector data_tlb_error
exception_vector reserved_01500
exception_vector reserved_01600
exception_vector reserved_01700
exception_vector reserved_01800
exception_vector reserved_01900
exception_vector reserved_01A00
exception_vector reserved_01B00
exception_vector data_breakpoint
exception_vector instruction_breakpoint
exception_vector peripheral_breakpoint
exception_vector NMI_port
.endm
##-----------------------------------------------------------------------------
## MPC5xx CPU initialization
##
## Initialize CPU to a post-reset state, ensuring the ground doesn''t
## shift under us while we try to set things up.
 
.macro hal_cpu_init
 
# Set up MSR
lwi r3,CYG_MSR
sync
mtmsr r3
sync
 
#ifndef CYGSEM_HAL_USE_ROM_MONITOR
#ifndef CYGSEM_HAL_POWERPC_MPC5XX_OCD_ENABLE
#ifdef CYGSEM_HAL_ROM_MONITOR
## Do not touch the DER register if OCD support is wanted.
## DER will be set with the OCD debugger in this case.
## Leave it untouched if co-existence with a ROM monitor
## is wanted as well.
## If we want to make a ROM monitor, we have to specify events
## that assert the FREEZE signal
## Single steps are implemented using hardware interrupts,
## breakpoints use program exceptions
lwi r3, 0x2082000f
 
#else
## Disable special MPC5xx "development support" for non
## debug loads.
lwi r3, 0x00000000
#endif
mtder r3
#endif
#endif
 
#ifdef CYGSEM_HAL_POWERPC_IEEE_FLOATING_POINT
mtfsb0 FULL_IEEE_FLOATING_POINT_SUPPORT
#else
mtfsb1 FULL_IEEE_FLOATING_POINT_SUPPORT
#endif
 
# Set up IMMR
lwi r3, 0x00000000
#ifdef CYGHWR_HAL_POWERPC_MPC5XX_IFLASH_ENABLE
lwi r4, CYGARC_REG_IMM_IMMR_FLEN
#else
lwi r4, 0x00000000
#endif
## We load the internal memory space to address zero
## Board specific initialization can then relocate this
## afterwards
or r3, r3, r4
mtspr CYGARC_REG_IMMR, r3
 
## Disable bursts. Again, board initialization can enable this
## afterwards.
li r0, 0
mtspr 560, r0
 
.endm
##-----------------------------------------------------------------------------
## MPC5xx exception state handling
.macro hal_variant_save regs
.endm
 
.macro hal_variant_load regs
.endm
##-----------------------------------------------------------------------------
## MPC5xx monitor initialization
 
#ifndef CYGPKG_HAL_PPC_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
 
.macro hal_mon_init
#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
# If we are starting up from ROM and want vectors in RAM
# or we are starting in RAM and NOT using a ROM monitor,
# copy exception handler code to 0.
lwi r3,rom_vectors # r3 = rom start
lwi r4,0 # r4 = ram start
lwi r5,rom_vectors_end # r5 = rom end
cmplw r3,r5 # skip if no vectors
beq 2f
 
subi r3,r3,4
subi r4,r4,4
subi r5,r5,4
1:
lwzu r0,4(r3) # get word from ROM
stwu r0,4(r4) # store in RAM
cmplw r3,r5 # compare
blt 1b # loop if not yet done
2:
#endif
 
# Next initialize the VSR table. This happens whether the
# vectors were copied to RAM or not.
 
# First fill with exception handlers
lwi r3,cyg_hal_default_exception_vsr
lwi r4,hal_vsr_table
subi r4,r4,4
li r5,CYGNUM_HAL_VSR_COUNT
1: stwu r3,4(r4)
subi r5,r5,1
cmpwi r5,0
bne 1b
 
# Then fill in the special vectors
lwi r3,cyg_hal_default_interrupt_vsr
lwi r4,hal_vsr_table
stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
.endm
 
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vectors,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
lwi r3,cyg_hal_default_interrupt_vsr
lwi r4,hal_vsr_table
stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
.endm
 
 
#else
 
.macro hal_mon_init
 
.endm
 
#endif
 
 
#define CYGPKG_HAL_PPC_MON_DEFINED
 
#endif // CYGPKG_HAL_PPC_MON_DEFINED
 
 
 
 
##-----------------------------------------------------------------------------
## Indicate that the ISR tables are defined in variant.S
#define CYG_HAL_PPC_ISR_TABLES_DEFINED
 
##-----------------------------------------------------------------------------
## MPC5xx interrupt handling.
 
#ifndef CYGPKG_HAL_POWERPC_INTC_DEFINED
 
## First level decoding of MPC5xx SIU interrupt controller.
 
# decode the interrupt
.macro hal_intc_decode dreg,state
lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
rlwinm. \dreg,\dreg,22,31,31 # isolate bit 21
beq 0f # done if decrementer (vec 0)
lwi \dreg,CYGARC_REG_IMM_SIVEC # if external, get SIU
lbz \dreg,0(\dreg) # vector.
srwi \dreg,\dreg,2
addi \dreg,\dreg,1 # Skip decrementer vector
0: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
slwi \dreg,\dreg,2 # convert to byte offset.
.endm
 
 
#define CYGPKG_HAL_POWERPC_INTC_DEFINED
#endif // CYGPKG_HAL_POWERPC_INTC_DEFINED
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/include/var_regs.h
0,0 → 1,958
#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H
 
//==========================================================================
//
// var_regs.h
//
// PowerPC 5xx variant CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors: Bob Koninckx
// Date: 2001-09-12
// Purpose: Provide MPC5xx register definitions
// Description: Provide MPC5xx register definitions
// The short difinitions (sans CYGARC_REG_) are exported only
// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage: Included via the acrhitecture register header:
// #include <cyg/hal/ppc_regs.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
//--------------------------------------------------------------------------
// Special purpose registers
//
#define CYGARC_REG_XER 1
#define CYGARC_REG_LR 8
#define CYGARC_REG_CTR 9
#define CYGARC_REG_EIE 80
#define CYGARC_REG_EID 81
#define CYGARC_REG_NRI 82
#define CYGARC_REG_CMPA 144
#define CYGARC_REG_CMPB 145
#define CYGARC_REG_CMPC 146
#define CYGARC_REG_CMPD 147
#define CYGARC_REG_ECR 148
#define CYGARC_REG_DER 149
#define CYGARC_REG_COUNTA 150
#define CYGARC_REG_COUNTB 151
#define CYGARC_REG_CMPE 152
#define CYGARC_REG_CMPF 153
#define CYGARC_REG_CMPG 154
#define CYGARC_REG_CMPH 155
#define CYGARC_REG_LCTRL1 156
#define CYGARC_REG_LCTRL2 157
#define CYGARC_REG_ICTRL 158
#define CYGARC_REG_BAR 159
#define CYGARC_REG_MI_GRA 528
#define CYGARC_REG_L2U_GRA 536
#define CYGARC_REG_BBCMCR 560
#define CYGARC_REG_L2U_MCR 568
#define CYGARC_REG_DPDR 630
#define CYGARC_REG_IMMR 638
#define CYGARC_REG_MI_RBA0 784
#define CYGARC_REG_MI_RBA1 785
#define CYGARC_REG_MI_RBA2 786
#define CYGARC_REG_MI_RBA3 787
#define CYGARC_REG_L2U_RBA0 792
#define CYGARC_REG_L2U_RBA1 793
#define CYGARC_REG_L2U_RBA2 794
#define CYGARC_REG_L2U_RBA3 795
#define CYGARC_REG_MI_RA0 816
#define CYGARC_REG_MI_RA1 817
#define CYGARC_REG_MI_RA2 818
#define CYGARC_REG_MI_RA3 819
#define CYGARC_REG_L2U_RA0 824
#define CYGARC_REG_L2U_RA1 825
#define CYGARC_REG_L2U_RA2 826
#define CYGARC_REG_L2U_RA3 827
#define CYGARC_REG_FPECR 1022
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
//# define XER CYGARC_REG_XER // Leave these out, they conflict with GDB stubs
//# define LR CYGARC_REG_LR // are not used anyway
# define CTR CYGARC_REG_CTR
# define EIE CYGARC_REG_EIE
# define EID CYGARC_REG_EID
# define NRI CYGARC_REG_NRI
# define CMPA CYGARC_REG_CMPA
# define CMPB CYGARC_REG_CMPB
# define CMPC CYGARC_REG_CMPC
# define CMPD CYGARC_REG_CMPD
# define ECR CYGARC_REG_ECR
# define DER CYGARC_REG_DER
# define COUNTA CYGARC_REG_COUNTA
# define COUNTB CYGARC_REG_COUNTB
# define CMPE CYGARC_REG_CMPE
# define CMPF CYGARC_REG_CMPF
# define CMPG CYGARC_REG_CMPG
# define CMPH CYGARC_REG_CMPH
# define LCTRL1 CYGARC_REG_LCTRL1
# define LCTRL2 CYGARC_REG_LCTRL2
# define ICTRL CYGARC_REG_ICTRL
# define BAR CYGARC_REG_BAR
# define MI_GRA CYGARC_REG_MI_GRA
# define L2U_GRA CYGARC_REG_L2U_GRA
# define BBCMCR CYGARC_REG_BBCMCR
# define L2U_MCR CYGARC_REG_L2U_MCR
# define DPDR CYGARC_REG_DPDR
# define IMMR CYGARC_REG_IMMR
# define MI_RBA0 CYGARC_REG_MI_RBA0
# define MI_RBA1 CYGARC_REG_MI_RBA1
# define MI_RBA2 CYGARC_REG_MI_RBA2
# define MI_RBA3 CYGARC_REG_MI_RBA3
# define L2U_RBA0 CYGARC_REG_L2U_RBA0
# define L2U_RBA1 CYGARC_REG_L2U_RBA1
# define L2U_RBA2 CYGARC_REG_L2U_RBA2
# define L2U_RBA3 CYGARC_REG_L2U_RBA3
# define MI_RA0 CYGARC_REG_MI_RA0
# define MI_RA1 CYGARC_REG_MI_RA1
# define MI_RA2 CYGARC_REG_MI_RA2
# define MI_RA3 CYGARC_REG_MI_RA3
# define L2U_RA0 CYGARC_REG_L2U_RA0
# define L2U_RA1 CYGARC_REG_L2U_RA1
# define L2U_RA2 CYGARC_REG_L2U_RA2
# define L2U_RA3 CYGARC_REG_L2U_RA3
# define FPECR CYGARC_REG_FPECR
#endif //#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//-----------------------------------------------------------------------------
// Development Support.
#define CYGARC_REG_DER 149
 
#define CYGARC_REG_ICTRL 158 // instruction support control reg
#define CYGARC_REG_ICTRL_SERSHOW 0x00000000 // serialized, show cycles
#define CYGARC_REG_ICTRL_NOSERSHOW 0x00000007 //non-serialized&no show cycles
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define DER CYGARC_REG_DER
 
#define ICTRL CYGARC_REG_ICTRL
#define ICTRL_SERSHOW CYGARC_REG_ICTRL_SERSHOW
#define ICTRL_NOSERSHOW CYGARC_REG_ICTRL_NOSERSHOW
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//-----------------------------------------------------------------------------
// Bit definitions
//-----------------------------------------------------------------------------
// The internal memory map register (IMMR)
#define CYGARC_REG_IMM_IMMR_PARTNUM 0xff000000 // part number mask (ro)
#define CYGARC_REG_IMM_IMMR_MASKNUM 0x00ff0000 // mask number mask (ro)
#define CYGARC_REG_IMM_IMMR_ISB 0x0000000e // internal space base
#define CYGARC_REG_IMM_IMMR_CLES 0x00000100 // core little endian swap
#define CYGARC_REG_IMM_IMMR_FLEN 0x00000800 // flash enable
 
//-----------------------------------------------------------------------------
// System protection control (SYPCR)
#define CYGARC_REG_IMM_SYPR_SWTC_MASK 0xffff0000
#define CYGARC_REG_IMM_SYPR_BMT_MASK 0x0000ff00
#define CYGARC_REG_IMM_SYPR_BME 0x00000080
#define CYGARC_REG_IMM_SYPR_SWF 0x00000008
#define CYGARC_REG_IMM_SYPR_SWE 0x00000004
#define CYGARC_REG_IMM_SYPR_SWRI 0x00000002
#define CYGARC_REG_IMM_SYPR_SWP 0x00000001
 
//-----------------------------------------------------------------------------
// Interrupt pend register (SIPEND)
#define CYGARC_REG_IMM_SIPEND_IRQ0 0x80000000 // External interrupt priority 0
#define CYGARC_REG_IMM_SIPEND_LVL0 0x40000000 // Internal interrupt level 0
#define CYGARC_REG_IMM_SIPEND_IRQ1 0x20000000 // External interrupt priority 1
#define CYGARC_REG_IMM_SIPEND_LVL1 0x10000000 // Internal interrupt level 1
#define CYGARC_REG_IMM_SIPEND_IRQ2 0x08000000 // External interrupt priority 2
#define CYGARC_REG_IMM_SIPEND_LVL2 0x04000000 // Internal interrupt level 2
#define CYGARC_REG_IMM_SIPEND_IRQ3 0x02000000 // External interrupt priority 3
#define CYGARC_REG_IMM_SIPEND_LVL3 0x01000000 // Internal interrupt level 3
#define CYGARC_REG_IMM_SIPEND_IRQ4 0x00800000 // External interrupt prioeity 4
#define CYGARC_REG_IMM_SIPEND_LVL4 0x00400000 // Internal interrupt level 4
#define CYGARC_REG_IMM_SIPEND_IRQ5 0x00200000 // External interrupt priority 5
#define CYGARC_REG_IMM_SIPEND_LVL5 0x00100000 // Internal interrupt level 5
#define CYGARC_REG_IMM_SIPEND_IRQ6 0x00080000 // External interrupt priority 6
#define CYGARC_REG_IMM_SIPEND_LVL6 0x00040000 // Internal interrupt level 6
#define CYGARC_REG_IMM_SIPEND_IRQ7 0x00020000 // External interrupt priority 7
#define CYGARC_REG_IMM_SIPEND_LVL7 0x00010000 // Internal interrupt level 7
 
//-----------------------------------------------------------------------------
// Interrupt mask register (SIMASK)
#define CYGARC_REG_IMM_SIMASK_IRM0 0x80000000 // External interrupt priority 0
#define CYGARC_REG_IMM_SIMASK_LVM0 0x40000000 // Internal interrupt level 0
#define CYGARC_REG_IMM_SIMASK_IRM1 0x20000000 // External interrupt priority 1
#define CYGARC_REG_IMM_SIMASK_LVM1 0x10000000 // Internal interrupt level 1
#define CYGARC_REG_IMM_SIMASK_IRM2 0x08000000 // External interrupt priority 2
#define CYGARC_REG_IMM_SIMASK_LVM2 0x04000000 // Internal interrupt level 2
#define CYGARC_REG_IMM_SIMASK_IRM3 0x02000000 // External interrupt priority 3
#define CYGARC_REG_IMM_SIMASK_LVM3 0x01000000 // Internal interrupt level 3
#define CYGARC_REG_IMM_SIMASK_IRM4 0x00800000 // External interrupt priority 4
#define CYGARC_REG_IMM_SIMASK_LVM4 0x00400000 // Internal interrupt level 4
#define CYGARC_REG_IMM_SIMASK_IRM5 0x00200000 // External interrupt priority 5
#define CYGARC_REG_IMM_SIMASK_LVM5 0x00100000 // Internal interrupt level 5
#define CYGARC_REG_IMM_SIMASK_IRM6 0x00080000 // External interrupt priority 6
#define CYGARC_REG_IMM_SIMASK_LVM6 0x00040000 // Internal interrupt level 6
#define CYGARC_REG_IMM_SIMASK_IRM7 0x00020000 // External interrupt priority 7
#define CYGARC_REG_IMM_SIMASK_LVM7 0x00010000 // Internal interrupt level 7
 
//-----------------------------------------------------------------------------
// Interrupt edge level register (CIEL)
#define CYGARC_REG_IMM_SIEL_ED0 0x80000000 // Falling edge external interrupt priority 0
#define CYGARC_REG_IMM_SIEL_WM0 0x40000000 // Wake-up mask external interrupt priority 0
#define CYGARC_REG_IMM_SIEL_ED1 0x20000000 // Falling edge external interrupt priority 1
#define CYGARC_REG_IMM_SIEL_WM1 0x10000000 // Wake-up mask external interrupt priority 1
#define CYGARC_REG_IMM_SIEL_ED2 0x08000000 // Falling edge external interrupt priority 2
#define CYGARC_REG_IMM_SIEL_WM2 0x04000000 // Wake-up mask external interrupt priority 2
#define CYGARC_REG_IMM_SIEL_ED3 0x02000000 // Falling edge external interrupt priority 3
#define CYGARC_REG_IMM_SIEL_WM3 0x01000000 // Wake-up mask external interrupt priority 3
#define CYGARC_REG_IMM_SIEL_ED4 0x00800000 // Falling edge external interrupt prioriry 4
#define CYGARC_REG_IMM_SIEL_WM4 0x00400000 // Wake-up mask external interrupt priority 4
#define CYGARC_REG_IMM_SIEL_ED5 0x00200000 // Falling edge external interrupt priority 5
#define CYGARC_REG_IMM_SIEL_WM5 0x00100000 // Wake-up mask external interrupt priority 5
#define CYGARC_REG_IMM_SIEL_ED6 0x00080000 // Falling edge external interrupt priority 6
#define CYGARC_REG_IMM_SIEL_WM6 0x00040000 // Wake-up mask external interrupt priority 6
#define CYGARC_REG_IMM_SIEL_ED7 0x00020000 // Falling edge external interrupt priority 7
#define CYGARC_REG_IMM_SIEL_WM7 0x00010000 // Wake-up mask external interrupt priority 7
 
//-----------------------------------------------------------------------------
// Memory controller
#define CYGARC_REG_IMM_BR_BA_MASK 0xffff8000 // base address
#define CYGARC_REG_IMM_BR_AT_MASK 0x00007000 // address type
#define CYGARC_REG_IMM_BR_PS_8 0x00000400 // port size 8 bits
#define CYGARC_REG_IMM_BR_PS_16 0x00000800 // port size 16 bits
#define CYGARC_REG_IMM_BR_PS_32 0x00000000 // port size 32 bits
#define CYGARC_REG_IMM_BR_WP 0x00000100 // write protect
#define CYGARC_REG_IMM_BR_WEBS 0x00000020 // write enable byte select
#define CYGARC_REG_IMM_BR_TBDIP 0x00000010 // toggle burst data in progress
#define CYGARC_REG_IMM_BR_LBDIP 0x00000008 // late burst data in progress
#define CYGARC_REG_IMM_BR_SETA 0x00000004 // externam transfer acknowledge
#define CYGARC_REG_IMM_BR_BI 0x00000002 // burst inhibit
#define CYGARC_REG_IMM_BR_V 0x00000001 // valid bit
 
#define CYGARC_REG_IMM_OR_AM 0xffff8000 // address mask
#define CYGARC_REG_IMM_OR_ATM 0x00007000 // address type mask
#define CYGARC_REG_IMM_OR_CSNT 0x00000800 // GPCM : chip select negatoion time
#define CYGARC_REG_IMM_OR_ACS_0 0x00000000 // GPCM : CS output immediately
#define CYGARC_REG_IMM_OR_ACS_4 0x00000400 // GPCM : CS output 1/4 clock cycle later
#define CYGARC_REG_IMM_OR_ACS_2 0x00000600 // GPCM : CS output 1/2 clock cycle later
#define CYGARC_REG_IMM_OR_SCY_MASK 0x000000f0 // cycle length in clocks
#define CYGARC_REG_IMM_OR_BSCY 0x0000000E // burst cycle length in clocks
#define CYGARC_REG_IMM_OR_TRLX 0x00000001 // timing relaxed
#define CYGARC_REG_IMM_OR_EHTR 0x00000100 // extended hold time on read
#define CYGARC_REG_IMM_OR_SCY_SHIFT 4
 
//-----------------------------------------------------------------------------
// Time base status and control (TBSCR)
#define CYGARC_REG_IMM_TBSCR_REFA 0x0080 // reference interrupt status A
#define CYGARC_REG_IMM_TBSCR_REFB 0x0040 // reference interrupt status B
#define CYGARC_REG_IMM_TBSCR_REFAE 0x0008 // reference interrupt enable A
#define CYGARC_REG_IMM_TBSCR_REFBE 0x0004 // reference interrupt enable B
#define CYGARC_REG_IMM_TBSCR_TBF 0x0002 // timebase freeze
#define CYGARC_REG_IMM_TBSCR_TBE 0x0001 // timebase enable
#define CYGARC_REG_IMM_TBSCR_IRQ0 0x8000 // highest interrupt level
#define CYGARC_REG_IMM_TBSCR_IRQMASK 0xff00 // irq priority mask
 
//-----------------------------------------------------------------------------
// Real time clock
#define CYGARC_REG_IMM_RTCSC_SEC 0x0080 // once per second interrupt
#define CYGARC_REG_IMM_RTCSC_ALR 0x0040 // alarm interrupt
#define CYGARC_REG_IMM_RTCSC_4M 0x0010 // source select
#define CYGARC_REG_IMM_RTCSC_SIE 0x0008 // second interrupt enable
#define CYGARC_REG_IMM_RTCSC_ALE 0x0004 // alarm interrupt enable
#define CYGARC_REG_IMM_RTCSC_RTF 0x0002 // real time clock freeze
#define CYGARC_REG_IMM_RTCSC_RTE 0x0001 // real time clock enable
#define CYGARC_REG_IMM_RTCSC_IRQ0 0x8000 // highest interrupt priority
#define CYGARC_REG_IMM_RTCSC_IRQMASK 0xff00 // irq priority mask
 
//-----------------------------------------------------------------------------
// Periodic interrupt status an control
#define CYGARC_REG_IMM_PISCR_PS 0x0080 // periodic interrupt status
#define CYGARC_REG_IMM_PISCR_PIE 0x0004 // periodic interrupt enable
#define CYGARC_REG_IMM_PISCR_PITF 0x0002 // periodic interrupt timer freeze
#define CYGARC_REG_IMM_PISCR_PTE 0x0001 // periodic timer enable
#define CYGARC_REG_IMM_PISCR_IRQ0 0x8000 // highest intetrupt priority
#define CYGARC_REG_IMM_PISCR_IRQMASK 0xff00 // irq priority mask
 
//-----------------------------------------------------------------------------
// Queued analog to digital convertor
#define CYGARC_REG_IMM_QUACR1_CIE1 0x8000
#define CYGARC_REG_IMM_QUACR1_PIE1 0x4000
#define CYGARC_REG_IMM_QUACR1_SSE1 0x2000
#define CYGARC_REG_IMM_QUACR1_MO1 0x1f00
#define CYGARC_REG_IMM_QUACR2_CIE2 0x8000
#define CYGARC_REG_IMM_QUACR2_PIE2 0x4000
#define CYGARC_REG_IMM_QUACR2_SSE2 0x2000
#define CYGARC_REG_IMM_QUACR2_MO2 0x1f00
#define CYGARC_REG_IMM_QUACR2_RESUME 0x0080
#define CYGARC_REG_IMM_QUACR2_BQ2 0x007f
#define CYGARC_REG_IMM_QUASR0_CF1 0x8000
#define CYGARC_REG_IMM_QUASR0_PF1 0x4000
#define CYGARC_REG_IMM_QUASR0_CF2 0x2000
#define CYGARC_REG_IMM_QUASR0_PF2 0x1000
#define CYGARC_REG_IMM_QUASR0_TOR1 0x0800
#define CYGARC_REG_IMM_QUASR0_TOR2 0x0400
#define CYGARC_REG_IMM_QUASR0_QS 0x03c0
#define CYGARC_REG_IMM_QUASR0_CWP 0x003f
#define CYGARC_REG_IMM_QUADC64INT_IRL1 0xf800
#define CYGARC_REG_IMM_QUADC64INT_IRL2 0x07c0
#define CYGARC_REG_IMM_QUADC64INT_IRL1_SHIFT 11
#define CYGARC_REG_IMM_QUADC64INT_IRL2_SHIFT 6
 
//-----------------------------------------------------------------------------
// PLL Change of lock
#define CYGARC_REG_IMM_COLIR_IRQ0 0x8000 // the highest interrupt priority
#define CYGARC_REG_IMM_COLIR_COLIRQ 0xff00 // interrupt priority mask
#define CYGARC_REG_IMM_COLIR_COLIS 0x0080 // change of lock detected
#define CYGARC_REG_IMM_COLIR_COLIE 0x0040 // change of lock interrupt enable
 
//-----------------------------------------------------------------------------
// SCI SPI registers
#define CYGARC_REG_IMM_SCCxR1_LOOPS 0x4000
#define CYGARC_REG_IMM_SCCxR1_WOMS 0x2000
#define CYGARC_REG_IMM_SCCxR1_ILT 0x1000
#define CYGARC_REG_IMM_SCCxR1_PT 0x0800
#define CYGARC_REG_IMM_SCCxR1_PE 0x0400
#define CYGARC_REG_IMM_SCCxR1_M 0x0200
#define CYGARC_REG_IMM_SCCxR1_WAKE 0x0100
#define CYGARC_REG_IMM_SCCxR1_TIE 0x0080
#define CYGARC_REG_IMM_SCCxR1_TCIE 0x0040
#define CYGARC_REG_IMM_SCCxR1_RIE 0x0020
#define CYGARC_REG_IMM_SCCxR1_ILIE 0x0010
#define CYGARC_REG_IMM_SCCxR1_TE 0x0008
#define CYGARC_REG_IMM_SCCxR1_RE 0x0004
#define CYGARC_REG_IMM_SCCxR1_RWU 0x0002
#define CYGARC_REG_IMM_SCCxR1_SBK 0x0001
#define CYGARC_REG_IMM_QSCI1CR_QTPNT 0xf000
#define CYGARC_REG_IMM_QSCI1CR_QTHFI 0x0800
#define CYGARC_REG_IMM_QSCI1CR_QBHFI 0x0400
#define CYGARC_REG_IMM_QSCI1CR_QTHEI 0x0200
#define CYGARC_REG_IMM_QSCI1CR_QBHEI 0x0100
#define CYGARC_REG_IMM_QSCI1CR_QTE 0x0040
#define CYGARC_REG_IMM_QSCI1CR_QRE 0x0020
#define CYGARC_REG_IMM_QSCI1CR_QTWE 0x0010
#define CYGARC_REG_IMM_QSCI1CR_QTSZ 0x000f
#define CYGARC_REG_IMM_SPCR1_SPE 0x8000
#define CYGARC_REG_IMM_SPCR1_DSCLK 0x7f00
#define CYGARC_REG_IMM_SPCR1_DTL 0x00ff
#define CYGARC_REG_IMM_SPCR2_SPIFIE 0x8000
#define CYGARC_REG_IMM_SPCR2_WREN 0x4000
#define CYGARC_REG_IMM_SPCR2_WRT0 0x2000
#define CYGARC_REG_IMM_SPCR2_ENDQP 0x1f00
#define CYGARC_REG_IMM_SPCR2_NEWQP 0x001f
#define CYGARC_REG_IMM_SPCR3_LOOPQ 0x0400
#define CYGARC_REG_IMM_SPCR3_HMIE 0x0200
#define CYGARC_REG_IMM_SPCR3_HALT 0x0100
#define CYGARC_REG_IMM_SPCR3_SPSR 0x00ff
#define CYGARC_REG_IMM_SCxSR_TDRE 0x0100
#define CYGARC_REG_IMM_SCxSR_TC 0x0080
#define CYGARC_REG_IMM_SCxSR_RDRF 0x0040
#define CYGARC_REG_IMM_SCxSR_RAF 0x0020
#define CYGARC_REG_IMM_SCxSR_IDLE 0x0010
#define CYGARC_REG_IMM_SCxSR_OR 0x0008
#define CYGARC_REG_IMM_SCxSR_NF 0x0004
#define CYGARC_REG_IMM_SCxSR_FE 0x0002
#define CYGARC_REG_IMM_SCxSR_PF 0x0001
#define CYGARC_REG_IMM_QSCI1SR_QOR 0x1000
#define CYGARC_REG_IMM_QSCI1SR_QTHF 0x0800
#define CYGARC_REG_IMM_QSCI1SR_QBHF 0x0400
#define CYGARC_REG_IMM_QSCI1SR_QTHE 0x0200
#define CYGARC_REG_IMM_QSCI1SR_QBHE 0x0100
#define CYGARC_REG_IMM_QSCI1SR_QRPNT 0x00f0
#define CYGARC_REG_IMM_QSCI1SR_QRPEND 0x000f
#define CYGARC_REG_IMM_SPSR_SPCR3 0xff00
#define CYGARC_REG_IMM_SPSR_SPIF 0x0080
#define CYGARC_REG_IMM_SPSR_MODF 0x0040
#define CYGARC_REG_IMM_SPSR_HALTA 0x0020
#define CYGARC_REG_IMM_SPSR_CPTQ 0x001f
#define CYGARC_REG_IMM_QDSCI_IL_ILDSCI 0x1f00
#define CYGARC_REG_IMM_QDSCI_IL_ILDSCI_SHIFT 8
#define CYGARC_REG_IMM_QSPI_IL_ILQSPI 0x001f
#define CYGARC_REG_IMM_QSPI_IL_ILQSPI_SHIFT 0
 
//-----------------------------------------------------------------------------
// TPU register settings
#define CYGARC_REG_IMM_TICR_CIRL 0x0700
#define CYGARC_REG_IMM_TICR_CIRL_SHIFT 8
#define CYGARC_REG_IMM_TICR_ILBS 0x00c0
#define CYGARC_REG_IMM_TICR_ILBS_SHIFT 6
 
//-----------------------------------------------------------------------------
// TOUCAN registers
#define CYGARC_REG_IMM_CANCTRL0_BOFFMSK 0x8000
#define CYGARC_REG_IMM_CANCTRL0_ERRMSK 0x4000
#define CYGARC_REG_IMM_CANCTRL0_RXMOD 0x0c00
#define CYGARC_REG_IMM_CANCTRL0_TXMOD 0x0300
#define CYGARC_REG_IMM_CANCTRL0_CANCTLL1 0x00ff
#define CYGARC_REG_IMM_TCNMCR_STOP 0x8000
#define CYGARC_REG_IMM_TCNMCR_FRZ 0x4000
#define CYGARC_REG_IMM_TCNMCR_HALT 0x1000
#define CYGARC_REG_IMM_TCNMCR_NOTRDY 0x0800
#define CYGARC_REG_IMM_TCNMCR_WAKEMSK 0x0400
#define CYGARC_REG_IMM_TCNMCR_SOFTRST 0x0200
#define CYGARC_REG_IMM_TCNMCR_FRZACK 0x0100
#define CYGARC_REG_IMM_TCNMCR_SUPV 0x0080
#define CYGARC_REG_IMM_TCNMCR_SELFWAKE 0x0040
#define CYGARC_REG_IMM_TCNMCR_APS 0x0020
#define CYGARC_REG_IMM_TCNMCR_STOPACK 0x0010
#define CYGARC_REG_IMM_ESTAT_BOFFINT 0x0004
#define CYGARC_REG_IMM_ESTAT_ERRINT 0x0002
#define CYGARC_REG_IMM_ESTAT_WAKEINT 0x0001
#define CYGARC_REG_IMM_CANICR_IRL 0x0700
#define CYGARC_REG_IMM_CANICR_IRL_SHIFT 8
#define CYGARC_REG_IMM_CANICR_ILBS 0x00c0
#define CYGARC_REG_IMM_CANICR_ILBS_SHIFT 6
 
//-----------------------------------------------------------------------------
// MIOS registers
#define CYGARC_REG_IMM_MIOS1ER0_EN15 0x8000
#define CYGARC_REG_IMM_MIOS1ER0_EN14 0x4000
#define CYGARC_REG_IMM_MIOS1ER0_EN13 0x2000
#define CYGARC_REG_IMM_MIOS1ER0_EN12 0x1000
#define CYGARC_REG_IMM_MIOS1ER0_EN11 0x0800
#define CYGARC_REG_IMM_MIOS1ER0_EN6 0x0040
#define CYGARC_REG_IMM_MIOS1ER0_EN3 0x0008
#define CYGARC_REG_IMM_MIOS1ER0_EN2 0x0004
#define CYGARC_REG_IMM_MIOS1ER0_EN1 0x0002
#define CYGARC_REG_IMM_MIOS1ER0_EN0 0x0001
#define CYGARC_REG_IMM_MIOS1ER1_EN31 0x8000
#define CYGARC_REG_IMM_MIOS1ER1_EN30 0x4000
#define CYGARC_REG_IMM_MIOS1ER1_EN29 0x2000
#define CYGARC_REG_IMM_MIOS1ER1_EN28 0x1000
#define CYGARC_REG_IMM_MIOS1ER1_EN27 0x0800
#define CYGARC_REG_IMM_MIOS1ER1_EN22 0x0040
#define CYGARC_REG_IMM_MIOS1ER1_EN19 0x0008
#define CYGARC_REG_IMM_MIOS1ER1_EN18 0x0004
#define CYGARC_REG_IMM_MIOS1ER1_EN17 0x0002
#define CYGARC_REG_IMM_MIOS1ER1_EN16 0x0001
#define CYGARC_REG_IMM_MIOS1SR0_FL15 0x8000
#define CYGARC_REG_IMM_MIOS1SR0_FL14 0x4000
#define CYGARC_REG_IMM_MIOS1SR0_FL13 0x2000
#define CYGARC_REG_IMM_MIOS1SR0_FL12 0x1000
#define CYGARC_REG_IMM_MIOS1SR0_FL11 0x0800
#define CYGARC_REG_IMM_MIOS1SR0_FL6 0x0040
#define CYGARC_REG_IMM_MIOS1SR0_FL3 0x0008
#define CYGARC_REG_IMM_MIOS1SR0_FL2 0x0004
#define CYGARC_REG_IMM_MIOS1SR0_FL1 0x0002
#define CYGARC_REG_IMM_MIOS1SR0_FL0 0x0001
#define CYGARC_REG_IMM_MIOS1SR1_FL31 0x8000
#define CYGARC_REG_IMM_MIOS1SR1_FL30 0x4000
#define CYGARC_REG_IMM_MIOS1SR1_FL29 0x2000
#define CYGARC_REG_IMM_MIOS1SR1_FL28 0x1000
#define CYGARC_REG_IMM_MIOS1SR1_FL27 0x0800
#define CYGARC_REG_IMM_MIOS1SR1_FL22 0x0040
#define CYGARC_REG_IMM_MIOS1SR1_FL19 0x0008
#define CYGARC_REG_IMM_MIOS1SR1_FL18 0x0004
#define CYGARC_REG_IMM_MIOS1SR1_FL17 0x0002
#define CYGARC_REG_IMM_MIOS1SR1_FL16 0x0001
#define CYGARC_REG_IMM_MIOS1LVL_LVL 0x0700
#define CYGARC_REG_IMM_MIOS1LVL_LVL_SHIFT 8
#define CYGARC_REG_IMM_MIOS1LVL_TM 0x00c0
#define CYGARC_REG_IMM_MIOS1LVL_TM_SHIFT 6
 
//-----------------------------------------------------------------------------
// Periodic interrupt timer count
#define CYGARC_REG_IMM_PITC_COUNT_SHIFT 16 // count is stored in bits 0-15
 
//-----------------------------------------------------------------------------
// System clock control
#define CYGARC_REG_IMM_SCCR_TBS 0x02000000 // Time base source
#define CYGARC_REG_IMM_SCCR_RTDIV 0x01000000 // rtc clock divide
#define CYGARC_REG_IMM_SCCR_RTSEL 0x00100000 // rtc clock select
 
//-------------------------------------
// TouCAN (CAN 2.0B Controller)
#define CYGARC_REG_IMM_CANICR_IRL 0x0700
#define CYGARC_REG_IMM_CANICR_IRL_SHIFT 8
#define CYGARC_REG_IMM_CANICR_ILBS 0x00c0
#define CYGARC_REG_IMM_CANICR_ILBS_SHIFT 6
 
#define CYGARC_REG_IMM_TCNMCR_STOP 0x8000
#define CYGARC_REG_IMM_TCNMCR_FRZ 0x4000
#define CYGARC_REG_IMM_TCNMCR_HALT 0x1000
#define CYGARC_REG_IMM_TCNMCR_NOTRDY 0x0800
#define CYGARC_REG_IMM_TCNMCR_WAKEMSK 0x0400
#define CYGARC_REG_IMM_TCNMCR_SOFTRST 0x0200
#define CYGARC_REG_IMM_TCNMCR_FRZACK 0x0100
#define CYGARC_REG_IMM_TCNMCR_SUPV 0x0080
#define CYGRAC_REG_IMM_TCNMCR_SELFWAKE 0x0040
#define CYGARC_REG_IMM_TCNMCR_APS 0x0020
#define CYGARC_REG_IMM_TCNMCR_STOPACK 0x0010
 
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_BOFFMSK 0x8000
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_ERRMSK 0x4000
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_RXMOD 0x0c00
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_TXMOD 0x0300
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_RXMOD_SHIFT 10
#define CYGARC_REG_IMM_CANCTRL0_CANCTRL1_TXMOD_SHIFT 8
 
#define CYGARC_REG_IMM_ESTAT_BITERR 0xc000
#define CYGARC_REG_IMM_ESTAT_ACKERR 0x2000
#define CYGARC_REG_IMM_ESTAT_CRCERR 0x1000
#define CYGARC_REG_IMM_ESTAT_FORMERR 0x0800
#define CYGARC_REG_IMM_ESTAT_STUFFERR 0x0400
#define CYGARC_REG_IMM_ESTAT_TXWARN 0x0200
#define CYGARC_REG_IMM_ESTAT_RXWARN 0x0100
#define CYGARC_REG_IMM_ESTAT_IDLE 0x0080
#define CYGARC_REG_IMM_ESTAT_TX_RX 0x0040
#define CYGARC_REG_IMM_ESTAT_FCS 0x0030
#define CYGARC_REG_IMM_ESTAT_BOFFINT 0x0004
#define CYGARC_REG_IMM_ESTAT_ERRINT 0x0002
#define CYGARC_REG_IMM_ESTAT_WAKEINT 0x0001
#define CYGARC_REG_IMM_ESTAT_BITERR_SHIFT 14
#define CYGARC_REG_IMM_ESTAT_FCS_SHIFT 4
//-----------------------------------------------------------------------------
// All registers in the internal memory map
#define CYGARC_REG_IMM_BASE 0x002fc000
 
// General register definitions
#define CYGARC_REG_IMM_SIUMCR (CYGARC_REG_IMM_BASE+0x0000)
#define CYGARC_REG_IMM_SYPCR (CYGARC_REG_IMM_BASE+0x0004)
#define CYGARC_REG_IMM_SWSR (CYGARC_REG_IMM_BASE+0x000e)
#define CYGARC_REG_IMM_SIPEND (CYGARC_REG_IMM_BASE+0x0010)
#define CYGARC_REG_IMM_SIMASK (CYGARC_REG_IMM_BASE+0x0014)
#define CYGARC_REG_IMM_SIEL (CYGARC_REG_IMM_BASE+0x0018)
#define CYGARC_REG_IMM_SIVEC (CYGARC_REG_IMM_BASE+0x001c)
#define CYGARC_REG_IMM_TESR (CYGARC_REG_IMM_BASE+0x0020)
#define CYGARC_REG_IMM_SGPIODT1 (CYGARC_REG_IMM_BASE+0x0024)
#define CYGARC_REG_IMM_SGPIODT2 (CYGARC_REG_IMM_BASE+0x0028)
#define CYGARC_REG_IMM_SGPIOCR (CYGARC_REG_IMM_BASE+0x002c)
#define CYGARC_REG_IMM_EMCR (CYGARC_REG_IMM_BASE+0x0030)
#define CYGARC_REG_IMM_PDMCR (CYGARC_REG_IMM_BASE+0x003c)
 
// Memory controller registers
#define CYGARC_REG_IMM_BR0 (CYGARC_REG_IMM_BASE+0x0100)
#define CYGARC_REG_IMM_OR0 (CYGARC_REG_IMM_BASE+0x0104)
#define CYGARC_REG_IMM_BR1 (CYGARC_REG_IMM_BASE+0x0108)
#define CYGARC_REG_IMM_OR1 (CYGARC_REG_IMM_BASE+0x010c)
#define CYGARC_REG_IMM_BR2 (CYGARC_REG_IMM_BASE+0x0110)
#define CYGARC_REG_IMM_OR2 (CYGARC_REG_IMM_BASE+0x0114)
#define CYGARC_REG_IMM_BR3 (CYGARC_REG_IMM_BASE+0x0118)
#define CYGARC_REG_IMM_OR3 (CYGARC_REG_IMM_BASE+0x011c)
#define CYGARC_REG_IMM_DMBR (CYGARC_REG_IMM_BASE+0x0140)
#define CYGARC_REG_IMM_DMOR (CYGARC_REG_IMM_BASE+0x0144)
#define CYGARC_REG_IMM_MSTAT (CYGARC_REG_IMM_BASE+0x0178)
 
// System integration timers
#define CYGARC_REG_IMM_TBSCR (CYGARC_REG_IMM_BASE+0x0200)
#define CYGARC_REG_IMM_TBREF0 (CYGARC_REG_IMM_BASE+0x0204)
#define CYGARC_REG_IMM_TBREF1 (CYGARC_REG_IMM_BASE+0x0208)
#define CYGARC_REG_IMM_RTCSC (CYGARC_REG_IMM_BASE+0x0220)
#define CYGARC_REG_IMM_RTC (CYGARC_REG_IMM_BASE+0x0224)
#define CYGARC_REG_IMM_RTSEC (CYGARC_REG_IMM_BASE+0x0228)
#define CYGARC_REG_IMM_RTCAL (CYGARC_REG_IMM_BASE+0x022c)
#define CYGARC_REG_IMM_PISCR (CYGARC_REG_IMM_BASE+0x0240)
#define CYGARC_REG_IMM_PITC (CYGARC_REG_IMM_BASE+0x0244)
#define CYGARC_REG_IMM_PITR (CYGARC_REG_IMM_BASE+0x0248)
 
// Clocks and resets
#define CYGARC_REG_IMM_SCCR (CYGARC_REG_IMM_BASE+0x0280)
#define CYGARC_REG_IMM_PLPRCR (CYGARC_REG_IMM_BASE+0x0284)
#define CYGARC_REG_IMM_RSR (CYGARC_REG_IMM_BASE+0x0288)
#define CYGARC_REG_IMM_COLIR (CYGARC_REG_IMM_BASE+0x028c)
#define CYGARC_REG_IMM_VSRMCR (CYGARC_REG_IMM_BASE+0x0290)
 
// System IntegrationTimer Keys
#define CYGARC_REG_IMM_TBSCRK (CYGARC_REG_IMM_BASE+0x0300)
#define CYGARC_REG_IMM_TBREF0K (CYGARC_REG_IMM_BASE+0x0304)
#define CYGARC_REG_IMM_TBREF1K (CYGARC_REG_IMM_BASE+0x0308)
#define CYGARC_REG_IMM_TBK (CYGARC_REG_IMM_BASE+0x030c)
#define CYGARC_REG_IMM_RTCSCK (CYGARC_REG_IMM_BASE+0x0320)
#define CYGARC_REG_IMM_RTCK (CYGARC_REG_IMM_BASE+0x0324)
#define CYGARC_REG_IMM_RTSECK (CYGARC_REG_IMM_BASE+0x0328)
#define CYGARC_REG_IMM_RTCALK (CYGARC_REG_IMM_BASE+0x032c)
#define CYGARC_REG_IMM_PISCRK (CYGARC_REG_IMM_BASE+0x0340)
#define CYGARC_REG_IMM_PITCK (CYGARC_REG_IMM_BASE+0x0344)
 
// Clocks and reset keys
#define CYGARC_REG_IMM_SCCRK (CYGARC_REG_IMM_BASE+0x0380)
#define CYGARC_REG_IMM_PLPRCRK (CYGARC_REG_IMM_BASE+0x0384)
#define CYGARC_REG_IMM_RSRK (CYGARC_REG_IMM_BASE+0x0388)
 
//-------------------------------------
// CMF (CDR Mone T FLASH EEPROM)
//-------------------------------------
// CMF_A
#define CYGARC_REG_IMM_CMFMCR_A (CYGARC_REG_IMM_BASE+0x0800)
#define CYGARC_REG_IMM_CMFTST_A (CYGARC_REG_IMM_BASE+0x0804)
#define CYGARC_REG_IMM_CMFCTL_A (CYGARC_REG_IMM_BASE+0x0808)
// CMF_B
#define CYGARC_REG_IMM_CMFMCR_B (CYGARC_REG_IMM_BASE+0x0840)
#define CYGARC_REG_IMM_CMFTST_B (CYGARC_REG_IMM_BASE+0x0844)
#define CYGARC_REG_IMM_CMFCTL_B (CYGARC_REG_IMM_BASE+0x0848)
 
//-------------------------------------
// DPTRAM (Dual-Port TPU RAM)
//-------------------------------------
#define CYGARC_REG_IMM_DPTMCR (CYGARC_REG_IMM_BASE+0x4000)
#define CYGARC_REG_IMM_RAMTST (CYGARC_REG_IMM_BASE+0x4002)
#define CYGARC_REG_IMM_RAMBAR (CYGARC_REG_IMM_BASE+0x4004)
#define CYGARC_REG_IMM_MISRH (CYGARC_REG_IMM_BASE+0x4006)
#define CYGARC_REG_IMM_MISRL (CYGARC_REG_IMM_BASE+0x4008)
#define CYGARC_REG_IMM_MISCNT (CYGARC_REG_IMM_BASE+0x400a)
 
//-------------------------------------
// TPU3 (Time processing unit)
//-------------------------------------
// TPU-A
#define CYGARC_REG_IMM_TPUMCR_A (CYGARC_REG_IMM_BASE+0x8000)
#define CYGARC_REG_IMM_TCR_A (CYGARC_REG_IMM_BASE+0x8002)
#define CYGARC_REG_IMM_DSCR_A (CYGARC_REG_IMM_BASE+0x8004)
#define CYGARC_REG_IMM_DSSR_A (CYGARC_REG_IMM_BASE+0x8006)
#define CYGARC_REG_IMM_TICR_A (CYGARC_REG_IMM_BASE+0x8008)
#define CYGARC_REG_IMM_CIER_A (CYGARC_REG_IMM_BASE+0x800a)
#define CYGARC_REG_IMM_CFSR0_A (CYGARC_REG_IMM_BASE+0x800c)
#define CYGARC_REG_IMM_CFSR1_A (CYGARC_REG_IMM_BASE+0x800e)
#define CYGARC_REG_IMM_CFSR2_A (CYGARC_REG_IMM_BASE+0x8010)
#define CYGARC_REG_IMM_CFSR3_A (CYGARC_REG_IMM_BASE+0x8012)
#define CYGARC_REG_IMM_HSQR0_A (CYGARC_REG_IMM_BASE+0x8014)
#define CYGARC_REG_IMM_HSQR1_A (CYGARC_REG_IMM_BASE+0x8016)
#define CYGARC_REG_IMM_HSRR0_A (CYGARC_REG_IMM_BASE+0x8018)
#define CYGARC_REG_IMM_HSRR1_A (CYGARC_REG_IMM_BASE+0x801a)
#define CYGARC_REG_IMM_CPR0_A (CYGARC_REG_IMM_BASE+0x801c)
#define CYGARC_REG_IMM_CPR1_A (CYGARC_REG_IMM_BASE+0x801e)
#define CYGARC_REG_IMM_CISR_A (CYGARC_REG_IMM_BASE+0x8020)
#define CYGARC_REG_IMM_LR_A (CYGARC_REG_IMM_BASE+0x8022)
#define CYGARC_REG_IMM_SGLR_A (CYGARC_REG_IMM_BASE+0x8024)
#define CYGARC_REG_IMM_DCNR_A (CYGARC_REG_IMM_BASE+0x8026)
#define CYGARC_REG_IMM_TPUMCR2_A (CYGARC_REG_IMM_BASE+0x8028)
#define CYGARC_REG_IMM_TPUMCR3_A (CYGARC_REG_IMM_BASE+0x802a)
#define CYGARC_REG_IMM_ISDR_A (CYGARC_REG_IMM_BASE+0x802c)
#define CYGARC_REG_IMM_ISCR_A (CYGARC_REG_IMM_BASE+0x802e)
 
// TPU-B
#define CYGARC_REG_IMM_TPUMCR_B (CYGARC_REG_IMM_BASE+0x8400)
#define CYGARC_REG_IMM_TCR_B (CYGARC_REG_IMM_BASE+0x8402)
#define CYGARC_REG_IMM_DSCR_B (CYGARC_REG_IMM_BASE+0x8404)
#define CYGARC_REG_IMM_DSSR_B (CYGARC_REG_IMM_BASE+0x8406)
#define CYGARC_REG_IMM_TICR_B (CYGARC_REG_IMM_BASE+0x8408)
#define CYGARC_REG_IMM_CIER_B (CYGARC_REG_IMM_BASE+0x840a)
#define CYGARC_REG_IMM_CFSR0_B (CYGARC_REG_IMM_BASE+0x840c)
#define CYGARC_REG_IMM_CFSR1_B (CYGARC_REG_IMM_BASE+0x840e)
#define CYGARC_REG_IMM_CFSR2_B (CYGARC_REG_IMM_BASE+0x8410)
#define CYGARC_REG_IMM_CFSR3_B (CYGARC_REG_IMM_BASE+0x8412)
#define CYGARC_REG_IMM_HSQR0_B (CYGARC_REG_IMM_BASE+0x8414)
#define CYGARC_REG_IMM_HSQR1_B (CYGARC_REG_IMM_BASE+0x8416)
#define CYGARC_REG_IMM_HSRR0_B (CYGARC_REG_IMM_BASE+0x8418)
#define CYGARC_REG_IMM_HSRR1_B (CYGARC_REG_IMM_BASE+0x841a)
#define CYGARC_REG_IMM_CPR0_B (CYGARC_REG_IMM_BASE+0x841c)
#define CYGARC_REG_IMM_CPR1_B (CYGARC_REG_IMM_BASE+0x841e)
#define CYGARC_REG_IMM_CISR_B (CYGARC_REG_IMM_BASE+0x8420)
#define CYGARC_REG_IMM_LR_B (CYGARC_REG_IMM_BASE+0x8422)
#define CYGARC_REG_IMM_SGLR_B (CYGARC_REG_IMM_BASE+0x8424)
#define CYGARC_REG_IMM_DCNR_B (CYGARC_REG_IMM_BASE+0x8426)
#define CYGARC_REG_IMM_TPUMCR2_B (CYGARC_REG_IMM_BASE+0x8428)
#define CYGARC_REG_IMM_TPUMCR3_B (CYGARC_REG_IMM_BASE+0x842a)
#define CYGARC_REG_IMM_ISDR_B (CYGARC_REG_IMM_BASE+0x842c)
#define CYGARC_REG_IMM_ISCR_B (CYGARC_REG_IMM_BASE+0x842e)
 
 
//-------------------------------------
// QADC64 (Queued Analog-to-digital Converter)
//-------------------------------------
// QUADC-A
#define CYGARC_REG_IMM_QUADC64MCR_A (CYGARC_REG_IMM_BASE+0x8800)
#define CYGARC_REG_IMM_QUADC64TEST_A (CYGARC_REG_IMM_BASE+0x8802)
#define CYGARC_REG_IMM_QUADC64INT_A (CYGARC_REG_IMM_BASE+0x8804)
#define CYGARC_REG_IMM_PORTQA_A_PORTQB_A (CYGARC_REG_IMM_BASE+0x8806)
#define CYGARC_REG_IMM_DDRQA_A_DDRQB_A (CYGARC_REG_IMM_BASE+0x8808)
#define CYGARC_REG_IMM_QUACR0_A (CYGARC_REG_IMM_BASE+0x880a)
#define CYGARC_REG_IMM_QUACR1_A (CYGARC_REG_IMM_BASE+0x880c)
#define CYGARC_REG_IMM_QUACR2_A (CYGARC_REG_IMM_BASE+0x880e)
#define CYGARC_REG_IMM_QUASR0_A (CYGARC_REG_IMM_BASE+0x8810)
#define CYGARC_REG_IMM_QUASR1_A (CYGARC_REG_IMM_BASE+0x8812)
#define CYGARC_REG_IMM_CCW_A (CYGARC_REG_IMM_BASE+0x8a00)
#define CYGARC_REG_IMM_RJURR_A (CYGARC_REG_IMM_BASE+0x8a80)
#define CYGARC_REG_IMM_LJSRR_A (CYGARC_REG_IMM_BASE+0x8b00)
#define CYGARC_REG_IMM_LJURR_A (CYGARC_REG_IMM_BASE+0x8b80)
 
// QUADC-B
#define CYGARC_REG_IMM_QUADC64MCR_B (CYGARC_REG_IMM_BASE+0x8c00)
#define CYGARC_REG_IMM_QUADC64TEST_B (CYGARC_REG_IMM_BASE+0x8c02)
#define CYGARC_REG_IMM_QUADC64INT_B (CYGARC_REG_IMM_BASE+0x8c04)
#define CYGARC_REG_IMM_PORTQA_B_PORTQB_B (CYGARC_REG_IMM_BASE+0x8c06)
#define CYGARC_REG_IMM_DDRQA_B_DDRQB_B (CYGARC_REG_IMM_BASE+0x8c08)
#define CYGARC_REG_IMM_QUACR0_B (CYGARC_REG_IMM_BASE+0x8c0a)
#define CYGARC_REG_IMM_QUACR1_B (CYGARC_REG_IMM_BASE+0x8c0c)
#define CYGARC_REG_IMM_QUACR2_B (CYGARC_REG_IMM_BASE+0x8c0e)
#define CYGARC_REG_IMM_QUASR0_B (CYGARC_REG_IMM_BASE+0x8c10)
#define CYGARC_REG_IMM_QUASR1_B (CYGARC_REG_IMM_BASE+0x8c12)
#define CYGARC_REG_IMM_CCW_B (CYGARC_REG_IMM_BASE+0x8e00)
#define CYGARC_REG_IMM_RJURR_B (CYGARC_REG_IMM_BASE+0x8e80)
#define CYGARC_REG_IMM_LJSRR_B (CYGARC_REG_IMM_BASE+0x8f00)
#define CYGARC_REG_IMM_LJURR_B (CYGARC_REG_IMM_BASE+0x8f80)
 
//-------------------------------------
// QSMCM (Queued Serial Multi-Channel Module)
//-------------------------------------
#define CYGARC_REG_IMM_QSMCMMCR (CYGARC_REG_IMM_BASE+0x9000)
#define CYGARC_REG_IMM_QTEST (CYGARC_REG_IMM_BASE+0x9002)
#define CYGARC_REG_IMM_QDSCI_IL (CYGARC_REG_IMM_BASE+0x9004)
#define CYGARC_REG_IMM_QSPI_IL (CYGARC_REG_IMM_BASE+0x9006)
#define CYGARC_REG_IMM_SCC1R0 (CYGARC_REG_IMM_BASE+0x9008)
#define CYGARC_REG_IMM_SCC1R1 (CYGARC_REG_IMM_BASE+0x900a)
#define CYGARC_REG_IMM_SC1SR (CYGARC_REG_IMM_BASE+0x900c)
#define CYGARC_REG_IMM_SC1DR (CYGARC_REG_IMM_BASE+0x900e)
#define CYGARC_REG_IMM_PORTQS (CYGARC_REG_IMM_BASE+0x9014)
#define CYGARC_REG_IMM_PQSPAR_DDRQST (CYGARC_REG_IMM_BASE+0x9016)
#define CYGARC_REG_IMM_SPCR0 (CYGARC_REG_IMM_BASE+0x9018)
#define CYGARC_REG_IMM_SPCR1 (CYGARC_REG_IMM_BASE+0x901a)
#define CYGARC_REG_IMM_SPCR2 (CYGARC_REG_IMM_BASE+0x901c)
#define CYGARC_REG_IMM_SPCR3 (CYGARC_REG_IMM_BASE+0x901e)
#define CYGARC_REG_IMM_SPSR (CYGARC_REG_IMM_BASE+0x901f)
#define CYGARC_REG_IMM_SCC2R0 (CYGARC_REG_IMM_BASE+0x9020)
#define CYGARC_REG_IMM_SCC2R1 (CYGARC_REG_IMM_BASE+0x9022)
#define CYGARC_REG_IMM_SC2SR (CYGARC_REG_IMM_BASE+0x9024)
#define CYGARC_REG_IMM_SC2DR (CYGARC_REG_IMM_BASE+0x9026)
#define CYGARC_REG_IMM_QSCI1CR (CYGARC_REG_IMM_BASE+0x9028)
#define CYGARC_REG_IMM_QSCI1SR (CYGARC_REG_IMM_BASE+0x902a)
#define CYGARC_REG_IMM_SCTQ (CYGARC_REG_IMM_BASE+0x902c)
#define CYGARC_REG_IMM_SCRQ (CYGARC_REG_IMM_BASE+0x904c)
#define CYGARC_REG_IMM_RECRAM (CYGARC_REG_IMM_BASE+0x9140)
#define CYGARC_REG_IMM_TRAN_RAM (CYGARC_REG_IMM_BASE+0x9180)
#define CYGARC_REG_IMM_COMD_RAM (CYGARC_REG_IMM_BASE+0x91c0)
 
//-------------------------------------
// MIOS1 (Modular Input/Output Subsystem)
//-------------------------------------
// MPIOS Pulse width modulation submodule 0
#define CYGARC_REG_IMM_MPWMSMPERR_0 (CYGARC_REG_IMM_BASE+0xa000)
#define CYGARC_REG_IMM_MPWMSMPULR_0 (CYGARC_REG_IMM_BASE+0xa002)
#define CYGARC_REG_IMM_MPWMSMCNTR_0 (CYGARC_REG_IMM_BASE+0xa004)
#define CYGARC_REG_IMM_MPWMSMSCR_0 (CYGARC_REG_IMM_BASE+0xa006)
// MPIOS Pulse width modulation submodule 1
#define CYGARC_REG_IMM_MPWMSMPERR_1 (CYGARC_REG_IMM_BASE+0xa008)
#define CYGARC_REG_IMM_MPWMSMPULR_1 (CYGARC_REG_IMM_BASE+0xa00a)
#define CYGARC_REG_IMM_MPWMSMCNTR_1 (CYGARC_REG_IMM_BASE+0xa00c)
#define CYGARC_REG_IMM_MPWMSMSCR_1 (CYGARC_REG_IMM_BASE+0xa00e)
 
// MPIOS Pulse width modulation submodule 2
#define CYGARC_REG_IMM_MPWMSMPERR_2 (CYGARC_REG_IMM_BASE+0xa010)
#define CYGARC_REG_IMM_MPWMSMPULR_2 (CYGARC_REG_IMM_BASE+0xa012)
#define CYGARC_REG_IMM_MPWMSMCNTR_2 (CYGARC_REG_IMM_BASE+0xa014)
#define CYGARC_REG_IMM_MPWMSMSCR_2 (CYGARC_REG_IMM_BASE+0xa016)
 
// MPIOS Pulse width modulation submodule 3
#define CYGARC_REG_IMM_MPWMSMPERR_3 (CYGARC_REG_IMM_BASE+0xa018)
#define CYGARC_REG_IMM_MPWMSMPULR_3 (CYGARC_REG_IMM_BASE+0xa01a)
#define CYGARC_REG_IMM_MPWMSMCNTR_3 (CYGARC_REG_IMM_BASE+0xa01c)
#define CYGARC_REG_IMM_MPWMSMSCR_3 (CYGARC_REG_IMM_BASE+0xa01e)
 
// MIOS Modulus counter submodule 6
#define CYGARC_REG_IMM_MMCSMCNT_6 (CYGARC_REG_IMM_BASE+0xa030)
#define CYGARC_REG_IMM_MMCSMML_6 (CYGARC_REG_IMM_BASE+0xa032)
#define CYGARC_REG_IMM_MMCSMSCRD_6 (CYGARC_REG_IMM_BASE+0xa034)
#define CYGARC_REG_IMM_MMCSMSCR_6 (CYGARC_REG_IMM_BASE+0xa036)
 
// MIOS Double Action submodule 11
#define CYGARC_REG_IMM_MDASMAR_11 (CYGARC_REG_IMM_BASE+0xa058)
#define CYGARC_REG_IMM_MDASMBR_11 (CYGARC_REG_IMM_BASE+0xa05a)
#define CYGARC_REG_IMM_MDASMSCRD_11 (CYGARC_REG_IMM_BASE+0xa05c)
#define CYGARC_REG_IMM_MDASMSCR_11 (CYGARC_REG_IMM_BASE+0xa05e)
 
// MIOS Double Action submodule 12
#define CYGARC_REG_IMM_MDASMAR_12 (CYGARC_REG_IMM_BASE+0xa060)
#define CYGARC_REG_IMM_MDASMBR_12 (CYGARC_REG_IMM_BASE+0xa062)
#define CYGARC_REG_IMM_MDASMSCRD_12 (CYGARC_REG_IMM_BASE+0xa064)
#define CYGARC_REG_IMM_MDASMSCR_12 (CYGARC_REG_IMM_BASE+0xa066)
 
// MIOS Double Action submodule 13
#define CYGARC_REG_IMM_MDASMAR_13 (CYGARC_REG_IMM_BASE+0xa068)
#define CYGARC_REG_IMM_MDASMBR_13 (CYGARC_REG_IMM_BASE+0xa06a)
#define CYGARC_REG_IMM_MDASMSCRD_13 (CYGARC_REG_IMM_BASE+0xa06c)
#define CYGARC_REG_IMM_MDASMSCR_13 (CYGARC_REG_IMM_BASE+0xa06e)
 
// MIOS Double Action submodule 14
#define CYGARC_REG_IMM_MDASMAR_14 (CYGARC_REG_IMM_BASE+0xa070)
#define CYGARC_REG_IMM_MDASMBR_14 (CYGARC_REG_IMM_BASE+0xa072)
#define CYGARC_REG_IMM_MDASMSCRD_14 (CYGARC_REG_IMM_BASE+0xa074)
#define CYGARC_REG_IMM_MDASMSCR_14 (CYGARC_REG_IMM_BASE+0xa076)
 
// MIOS Double Action submodule 15
#define CYGARC_REG_IMM_MDASMAR_15 (CYGARC_REG_IMM_BASE+0xa078)
#define CYGARC_REG_IMM_MDASMBR_15 (CYGARC_REG_IMM_BASE+0xa07a)
#define CYGARC_REG_IMM_MDASMSCRD_15 (CYGARC_REG_IMM_BASE+0xa07c)
#define CYGARC_REG_IMM_MDASMSCR_15 (CYGARC_REG_IMM_BASE+0xa07e)
 
// MPIOS Pulse width modulation submodule 16
#define CYGARC_REG_IMM_MPWMSMPERR_16 (CYGARC_REG_IMM_BASE+0xa080)
#define CYGARC_REG_IMM_MPWMSMPULR_16 (CYGARC_REG_IMM_BASE+0xa082)
#define CYGARC_REG_IMM_MPWMSMCNTR_16 (CYGARC_REG_IMM_BASE+0xa084)
#define CYGARC_REG_IMM_MPWMSMSCR_16 (CYGARC_REG_IMM_BASE+0xa086)
 
// MPIOS Pulse width modulation submodule 17
#define CYGARC_REG_IMM_MPWMSMPERR_17 (CYGARC_REG_IMM_BASE+0xa088)
#define CYGARC_REG_IMM_MPWMSMPULR_17 (CYGARC_REG_IMM_BASE+0xa08a)
#define CYGARC_REG_IMM_MPWMSMCNTR_17 (CYGARC_REG_IMM_BASE+0xa08c)
#define CYGARC_REG_IMM_MPWMSMSCR_17 (CYGARC_REG_IMM_BASE+0xa08e)
 
// MPIOS Pulse width modulation submodule 18
#define CYGARC_REG_IMM_MPWMSMPERR_18 (CYGARC_REG_IMM_BASE+0xa090)
#define CYGARC_REG_IMM_MPWMSMPULR_18 (CYGARC_REG_IMM_BASE+0xa092)
#define CYGARC_REG_IMM_MPWMSMCNTR_18 (CYGARC_REG_IMM_BASE+0xa094)
#define CYGARC_REG_IMM_MPWMSMSCR_18 (CYGARC_REG_IMM_BASE+0xa096)
 
// MPIOS Pulse width modulation submodule 19
#define CYGARC_REG_IMM_MPWMSMPERR_19 (CYGARC_REG_IMM_BASE+0xa098)
#define CYGARC_REG_IMM_MPWMSMPULR_19 (CYGARC_REG_IMM_BASE+0xa09a)
#define CYGARC_REG_IMM_MPWMSMCNTR_19 (CYGARC_REG_IMM_BASE+0xa09c)
#define CYGARC_REG_IMM_MPWMSMSCR_19 (CYGARC_REG_IMM_BASE+0xa09e)
 
// MIOS Modulus counter submodule 22
#define CYGARC_REG_IMM_MMCSMCNT_22 (CYGARC_REG_IMM_BASE+0xa0b0)
#define CYGARC_REG_IMM_MMCSMML_22 (CYGARC_REG_IMM_BASE+0xa0b2)
#define CYGARC_REG_IMM_MMCSMSCRD_22 (CYGARC_REG_IMM_BASE+0xa0b4)
#define CYGARC_REG_IMM_MMCSMSCR_22 (CYGARC_REG_IMM_BASE+0xa0b6)
 
// MIOS Double action submodule 27
#define CYGARC_REG_IMM_MDASMAR_27 (CYGARC_REG_IMM_BASE+0xa0d8)
#define CYGARC_REG_IMM_MDASMBR_27 (CYGARC_REG_IMM_BASE+0xa0da)
#define CYGARC_REG_IMM_MDASMSCRD_27 (CYGARC_REG_IMM_BASE+0xa0dc)
#define CYGARC_REG_IMM_MDASMSCR_27 (CYGARC_REG_IMM_BASE+0xa0de)
 
// MIOS Double action submodule 28
#define CYGARC_REG_IMM_MDASMAR_28 (CYGARC_REG_IMM_BASE+0xa0e0)
#define CYGARC_REG_IMM_MDASMBR_28 (CYGARC_REG_IMM_BASE+0xa0e2)
#define CYGARC_REG_IMM_MDASMSCRD_28 (CYGARC_REG_IMM_BASE+0xa0e4)
#define CYGARC_REG_IMM_MDASMSCR_28 (CYGARC_REG_IMM_BASE+0xa0e6)
 
// MIOS Double action submodule 29
#define CYGARC_REG_IMM_MDASMAR_29 (CYGARC_REG_IMM_BASE+0xa0e8)
#define CYGARC_REG_IMM_MDASMBR_29 (CYGARC_REG_IMM_BASE+0xa0ea)
#define CYGARC_REG_IMM_MDASMSCRD_29 (CYGARC_REG_IMM_BASE+0xa0ec)
#define CYGARC_REG_IMM_MDASMSCR_29 (CYGARC_REG_IMM_BASE+0xa0ee)
 
// MIOS Double action submodule 30
#define CYGARC_REG_IMM_MDASMAR_30 (CYGARC_REG_IMM_BASE+0xa0f0)
#define CYGARC_REG_IMM_MDASMBR_30 (CYGARC_REG_IMM_BASE+0xa0f2)
#define CYGARC_REG_IMM_MDASMSCRD_30 (CYGARC_REG_IMM_BASE+0xa0f4)
#define CYGARC_REG_IMM_MDASMSCR_30 (CYGARC_REG_IMM_BASE+0xa0f6)
 
// MIOS Double action submodule 31
#define CYGARC_REG_IMM_MDASMAR_31 (CYGARC_REG_IMM_BASE+0x0af8)
#define CYGARC_REG_IMM_MDASMBR_31 (CYGARC_REG_IMM_BASE+0xa0fa)
#define CYGARC_REG_IMM_MDASMSCRD_31 (CYGARC_REG_IMM_BASE+0xa0fc)
#define CYGARC_REG_IMM_MDASMSCR_31 (CYGARC_REG_IMM_BASE+0xa0fe)
 
// MIOS Paralell port I/O submodule
#define CYGARC_REG_IMM_MPIOSMDR (CYGARC_REG_IMM_BASE+0xa100)
#define CYGARC_REG_IMM_MPIOSMDDR (CYGARC_REG_IMM_BASE+0xa102)
 
// MIOS Bus interface Submodule
#define CYGARC_REG_IMM_MIOS1TPCR (CYGARC_REG_IMM_BASE+0xa800)
#define CYGARC_REG_IMM_MIOS1VNR (CYGARC_REG_IMM_BASE+0xa802)
#define CYGARC_REG_IMM_MIOS1MCR (CYGARC_REG_IMM_BASE+0xa806)
 
// MIOS Counter / Prescaler submodule
#define CYGARC_REG_IMM_MCPSMSCR (CYGARC_REG_IMM_BASE+0xa816)
 
// MIOS Interrupt request submodule 0
#define CYGARC_REG_IMM_MIOS1SR0 (CYGARC_REG_IMM_BASE+0xac00)
#define CYGARC_REG_IMM_MIOS1ER0 (CYGARC_REG_IMM_BASE+0xac04)
#define CYGARC_REG_IMM_MIOS1RPR0 (CYGARC_REG_IMM_BASE+0xac06)
#define CYGARC_REG_IMM_MIOS1LVL0 (CYGARC_REG_IMM_BASE+0xac30)
 
// Mios Interrupt request submodule 1
#define CYGARC_REG_IMM_MIOS1SR1 (CYGARC_REG_IMM_BASE+0xac40)
#define CYGARC_REG_IMM_MIOS1ER1 (CYGARC_REG_IMM_BASE+0xac44)
#define CYGARC_REG_IMM_MIOS1RPR1 (CYGARC_REG_IMM_BASE+0xac46)
#define CYGARC_REG_IMM_MIOS1LVL1 (CYGARC_REG_IMM_BASE+0xac70)
 
//-------------------------------------
// TouCAN (CAN 2.0B Controller)
//-------------------------------------
// TouCAN_A
#define CYGARC_REG_IMM_TCNMCR_A (CYGARC_REG_IMM_BASE+0xb080)
#define CYGARC_REG_IMM_TTR_A (CYGARC_REG_IMM_BASE+0xb082)
#define CYGARC_REG_IMM_CANICR_A (CYGARC_REG_IMM_BASE+0xb084)
#define CYGARC_REG_IMM_CANCTRL0_A_CANCTRL1_A (CYGARC_REG_IMM_BASE+0xb086)
#define CYGARC_REG_IMM_PRESDIV_A_CTRL2_A (CYGARC_REG_IMM_BASE+0xb088)
#define CYGARC_REG_IMM_TIMER_A (CYGARC_REG_IMM_BASE+0xb08a)
#define CYGARC_REG_IMM_RXGMASKHI_A (CYGARC_REG_IMM_BASE+0xb090)
#define CYGARC_REG_IMM_RXGMASKLO_A (CYGARC_REG_IMM_BASE+0xb092)
#define CYGARC_REG_IMM_RX14MASKHI_A (CYGARC_REG_IMM_BASE+0xb094)
#define CYGARC_REG_IMM_RX14MASKLO_A (CYGARC_REG_IMM_BASE+0xb096)
#define CYGARC_REG_IMM_RX15MASKHI_A (CYGARC_REG_IMM_BASE+0xb098)
#define CYGARC_REG_IMM_RX15MASKLO_A (CYGARC_REG_IMM_BASE+0xb09a)
#define CYGARC_REG_IMM_ESTAT_A (CYGARC_REG_IMM_BASE+0xb0a0)
#define CYGARC_REG_IMM_IMASK_A (CYGARC_REG_IMM_BASE+0xb0a2)
#define CYGARC_REG_IMM_IFLAG_A (CYGARC_REG_IMM_BASE+0xb0a4)
#define CYGARC_REG_IMM_RXECTR_A_TXECTR_A (CYGARC_REG_IMM_BASE+0xb0a6)
 
// TouCAN_B
#define CYGARC_REG_IMM_TCNMCR_B (CYGARC_REG_IMM_BASE+0xb480)
#define CYGARC_REG_IMM_TTR_B (CYGARC_REG_IMM_BASE+0xb482)
#define CYGARC_REG_IMM_CANICR_B (CYGARC_REG_IMM_BASE+0xb484)
#define CYGARC_REG_IMM_CANCTRL0_B_CANCTRL1_B (CYGARC_REG_IMM_BASE+0xb486)
#define CYGARC_REG_IMM_PRESDIV_B_CTRL2_B (CYGARC_REG_IMM_BASE+0xb488)
#define CYGARC_REG_IMM_TIMER_B (CYGARC_REG_IMM_BASE+0xb48a)
#define CYGARC_REG_IMM_RXGMASKHI_B (CYGARC_REG_IMM_BASE+0xb490)
#define CYGARC_REG_IMM_RXGMASKLO_B (CYGARC_REG_IMM_BASE+0xb492)
#define CYGARC_REG_IMM_RX14MASKHI_B (CYGARC_REG_IMM_BASE+0xb494)
#define CYGARC_REG_IMM_RX14MASKLO_B (CYGARC_REG_IMM_BASE+0xb496)
#define CYGARC_REG_IMM_RX15MASKHI_B (CYGARC_REG_IMM_BASE+0xb498)
#define CYGARC_REG_IMM_RX15MASKLO_B (CYGARC_REG_IMM_BASE+0xb49a)
#define CYGARC_REG_IMM_ESTAT_B (CYGARC_REG_IMM_BASE+0xb4a0)
#define CYGARC_REG_IMM_IMASK_B (CYGARC_REG_IMM_BASE+0xb4a2)
#define CYGARC_REG_IMM_IFLAG_B (CYGARC_REG_IMM_BASE+0xb4a4)
#define CYGARC_REG_IMM_RXECTR_A_TXECTR_B (CYGARC_REG_IMM_BASE+0xb4a6)
 
//-------------------------------------
// UIMB (U-Bus to IMB3 Bus Interface)
//-------------------------------------
#define CYGARC_REG_IMM_UMCR (CYGARC_REG_IMM_BASE+0xbf80)
#define CYGARC_REG_IMM_UTSTCREG (CYGARC_REG_IMM_BASE+0xbf90)
#define CYGARC_REG_IMM_UIPEND (CYGARC_REG_IMM_BASE+0xbfa0)
 
//-------------------------------------
// SRAM (Static RAM Access memory)
//-------------------------------------
#define CYGARC_REG_IMM_SRAMMCR_A (CYGARC_REG_IMM_BASE+0x84000)
#define CYGARC_REG_IMM_SRAMTST_A (CYGARC_REG_IMM_BASE+0x84004)
#define CYGARC_REG_IMM_SRAMMCR_B (CYGARC_REG_IMM_BASE+0x84008)
#define CYGARC_REG_IMM_SRAMTST_B (CYGARC_REG_IMM_BASE+0x8400c)
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
// definitions without CYGARC_REG_ can come here. If there is a need for it ....
#endif
 
//-----------------------------------------------------------------------------
#endif // ifdef CYGONCE_HAL_VAR_REGS_H
// End of var_regs.h
/ChangeLog
0,0 → 1,39
2002-04-25 Bob Koninckx <bob.koninckx@mech.kuleuven.ac.be>
2002-04-25 Jonathan Larmour <jlarmour@redhat.com>
 
* New package.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
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// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/src/mpc5xxrev.c
0,0 → 1,74
//==========================================================================
//
// mpc5xxrev.c
//
// MPC5xx Revision Identification
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors: Bob Koninckx
// Date: 2001-12-11
// Description: Print MPC5xx revision numbers
//####DESCRIPTIONEND####
 
#include <cyg/infra/testcase.h>
#include <stdio.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/hal_io.h>
#include <cyg/infra/diag.h>
 
int
main( void )
{
cyg_uint32 pvr, part_mask;
 
CYG_TEST_INIT();
 
asm volatile ("mfspr %0, 287;": "=r" (pvr));
diag_printf("Processor PVR: 0x%08x\n", pvr);
 
asm volatile ("mfspr %0, 638;": "=r" (part_mask));
part_mask = (part_mask >> 16);
diag_printf("Processor IMMR[00:15]: 0x%04x\n", (part_mask & 0xffff));
 
diag_printf("\nSee http://www.motorola.com/SPS/RISC/netcomm/ for erratas.\n");
diag_printf("Look for MPC5xx Versions and Masks in the Publications Library\n");
 
CYG_TEST_PASS_FINISH("mpc5xx revision dump");
}
// EOF mpc5xxrev.c
/src/var_misc.c
0,0 → 1,105
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors: Bob Koninckx
// Date: 2001-12-10
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/ppc_regs.h>
#include <cyg/infra/cyg_type.h> // types
#include <cyg/infra/diag.h> // diag_printf
 
#include <cyg/hal/hal_mem.h> // some of the functions defined here
 
//--------------------------------------------------------------------------
void
hal_variant_init(void)
{
// Disable serialization
{
cyg_uint32 ictrl;
CYGARC_MFSPR (ICTRL, ictrl);
ictrl |= ICTRL_NOSERSHOW;
CYGARC_MTSPR (ICTRL, ictrl);
}
}
 
//--------------------------------------------------------------------------
// Variant specific idle thread action.
bool
hal_variant_idle_thread_action( cyg_uint32 count )
{
// Let architecture idle thread action run
return true;
}
 
//---------------------------------------------------------------------------
// Use MMU resources to map memory regions.
// Takes and returns an int used to ID the MMU resource to use. This ID
// is increased as resources are used and should be used for subsequent
// invocations.
//
// The MPC5xx CPUs do not have cache. Leave these functions empty
int
cyg_hal_map_memory (int id,CYG_ADDRESS virt, CYG_ADDRESS phys,
cyg_int32 size, cyg_uint8 flags)
{
return 0;
}
 
void
cyg_hal_clear_MMU (void)
{
}
 
//--------------------------------------------------------------------------
// End of var_misc.c
/src/var_intr.c
0,0 → 1,285
//==========================================================================
//
// var_intr.c
//
// PowerPC variant interrupt handlers
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Bob Koninckx
// Contributors: Bob Koninckx
// Date: 2001-12-16
// Purpose: PowerPC variant interrupt handlers
// Description: This file contains code to handle interrupt related issues
// on the PowerPC variant.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/hal_arbiter.h>
 
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Since the interrupt sources do not have fixed vectors on the 5XX
// SIU, some arbitration is required.
 
// More than one interrupt source can be programmed to use the same
// vector, so all sources on the same vector have to be queried to
// find the one raising the interrupt. This functionality has not been
// implemented, but the arbiter functions for each of the SIU
// interrupt sources can be called in sequence without change.
 
 
 
// Timebase interrupt can be caused by match on either reference A
// or B.
// Note: If only one interrupt source is assigned per vector, and only
// reference interrupt A or B is used, this ISR is not
// necessary. Attach the timerbase reference A or B ISR directly to
// the LVLx vector instead.
externC cyg_uint32
hal_arbitration_isr_tb (CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 isr_ret;
cyg_uint16 tbscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_TBSCR, tbscr);
if (tbscr & CYGARC_REG_IMM_TBSCR_REFA) {
isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_A);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
if (isr_ret & CYG_ISR_HANDLED)
#endif
return isr_ret;
}
 
if (tbscr & CYGARC_REG_IMM_TBSCR_REFB) {
isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_TB_B);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
if (isr_ret & CYG_ISR_HANDLED)
#endif
return isr_ret;
}
 
return 0;
}
 
// Periodic interrupt.
// Note: If only one interrupt source is assigned per vector, this ISR
// is not necessary. Attach the periodic interrupt ISR directly to the
// LVLx vector instead.
externC cyg_uint32
hal_arbitration_isr_pit (CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 isr_ret;
cyg_uint16 piscr;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_PISCR, piscr);
if (piscr & CYGARC_REG_IMM_PISCR_PS) {
isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_PIT);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
if (isr_ret & CYG_ISR_HANDLED)
#endif
return isr_ret;
}
 
return 0;
}
 
// Real time clock interrupts can be caused by the alarm or
// once-per-second.
// Note: If only one interrupt source is assigned per vector, and only
// the alarm or once-per-second interrupt is used, this ISR is not
// necessary. Attach the alarm or once-per-second ISR directly to the
// LVLx vector instead.
externC cyg_uint32
hal_arbitration_isr_rtc (CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
cyg_uint32 isr_ret;
cyg_uint16 rtcsc;
 
HAL_READ_UINT16 (CYGARC_REG_IMM_RTCSC, rtcsc);
if (rtcsc & CYGARC_REG_IMM_RTCSC_SEC) {
isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_SEC);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
if (isr_ret & CYG_ISR_HANDLED)
#endif
return isr_ret;
}
 
if (rtcsc & CYGARC_REG_IMM_RTCSC_ALR) {
isr_ret = hal_call_isr (CYGNUM_HAL_INTERRUPT_SIU_RTC_ALR);
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
if (isr_ret & CYG_ISR_HANDLED)
#endif
return isr_ret;
}
 
return 0;
}
 
// -------------------------------------------------------------------------
// IMB3 interrupt decoding
//
// All interrupt priorities higher than 7 are mapped to SIU level 7. As much
// as 15 interrupting devices can be behind this. If more than one IMB3
// device is to be used with priorites in the range 7-31, a special kind of
// arbitration isr needs to be set up on SIU level 7. As this is not allways
// necessary, it is provided as a configuration option.
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
static hal_mpc5xx_arbitration_data * imb3_data_head = 0;
 
static cyg_uint32
hal_arbitration_imb3(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
hal_mpc5xx_arbitration_data * p =
*(hal_mpc5xx_arbitration_data **)data;
 
// Try them all, highest priorities come first. An ISR should return
// CYG_ISR_HANDLED or CYG_ISR_CALL_DSR. An arbitration ISR will
// strip the CYG_DSR_HANDLED from the ISR result, or returns 0 if
// no ISR could be called. This means that CYG_ISR_HANDLED implies
// that an ISR was called, 0 means that nothing was called.
// Notice that our approach tries to be efficient. We return as soon
// as the first interrupting source is found. This prevents from scanning
// the complete table for every interrupt. If more than one module
// requested at the same time, we will re-enter this procedure immediately
// anyway.
while(p)
{
if((p->arbiter(CYGNUM_HAL_INTERRUPT_SIU_LVL7, p->data))&CYG_ISR_HANDLED)
break;
else
p = (hal_mpc5xx_arbitration_data *)(p->reserved);
}
 
return 0;
}
 
static hal_mpc5xx_arbitration_data *
mpc5xx_insert(hal_mpc5xx_arbitration_data * list,
hal_mpc5xx_arbitration_data * data)
{
hal_mpc5xx_arbitration_data tmp;
hal_mpc5xx_arbitration_data * ptmp = &tmp;
tmp.reserved = list;
 
while(ptmp->reserved)
{
if(((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->priority > data->priority)
break;
ptmp = (hal_mpc5xx_arbitration_data *)(ptmp->reserved);
}
 
data->reserved = ptmp->reserved;
ptmp->reserved = data;
return (hal_mpc5xx_arbitration_data *)(tmp.reserved);
}
 
static hal_mpc5xx_arbitration_data *
mpc5xx_remove(hal_mpc5xx_arbitration_data * list,
hal_mpc5xx_arbitration_data * data)
{
hal_mpc5xx_arbitration_data tmp;
hal_mpc5xx_arbitration_data * ptmp = &tmp;
tmp.reserved = list;
 
while(ptmp->reserved)
{
if(ptmp->reserved == data)
break;
ptmp = (hal_mpc5xx_arbitration_data *)(ptmp->reserved);
}
 
if(ptmp->reserved)
ptmp->reserved = ((hal_mpc5xx_arbitration_data *)(ptmp->reserved))->reserved;
 
return (hal_mpc5xx_arbitration_data *)(tmp.reserved);
}
#endif
 
externC void
hal_mpc5xx_install_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
CYG_ADDRWORD vector = 2*(1 + adata->priority);
if(vector < CYGNUM_HAL_INTERRUPT_SIU_LVL7)
{
HAL_INTERRUPT_ATTACH(vector, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(vector);
}
else
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating
// the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_insert(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#else
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, adata->arbiter, adata->data, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
}
 
externC void
hal_mpc5xx_remove_arbitration_isr(hal_mpc5xx_arbitration_data * adata)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
// Prevent anything from coming through while manipulating the list
HAL_INTERRUPT_MASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
imb3_data_head = mpc5xx_remove(imb3_data_head, adata);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
 
// -------------------------------------------------------------------------
// Variant specific interrupt setup
externC void
hal_variant_IRQ_init(void)
{
#ifdef CYGSEM_HAL_POWERPC_MPC5XX_IMB3_ARBITER
HAL_INTERRUPT_ATTACH(CYGNUM_HAL_INTERRUPT_SIU_LVL7, hal_arbitration_imb3, &imb3_data_head, 0);
HAL_INTERRUPT_UNMASK(CYGNUM_HAL_INTERRUPT_SIU_LVL7);
#endif
}
 
// -------------------------------------------------------------------------
// EOF var_intr.c
/src/variant.S
0,0 → 1,85
##=============================================================================
##
## variant.S
##
## POWERPC MPC8xx variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): jskov
## Contributors:jskov
## Date: 2000-02-04
## Purpose: PowerPC MPC8xx variant code
## Description: Variant specific code for PowerPC MPC8xx CPUs.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/arch.inc>
#---------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
 
.data
 
.extern hal_default_decrementer_isr
.extern hal_default_isr
 
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_default_decrementer_isr
.rept CYGNUM_HAL_ISR_COUNT-1
.long hal_default_isr
.endr
 
.globl hal_interrupt_data
hal_interrupt_data:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
##-----------------------------------------------------------------------------
## end of variant.S

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