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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/powerpc/ppc40x
    from Rev 27 to Rev 174
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  •

Rev 27 → Rev 174

/v2_0/cdl/hal_powerpc_ppc40x.cdl
0,0 → 1,97
# ====================================================================
#
# hal_powerpc_ppc40x.cdl
#
# PowerPC/PPC40x variant architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Contributors: gthomas
# Date: 2000-08-27
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_POWERPC_PPC40x {
display "PowerPC 40x variant HAL"
parent CYGPKG_HAL_POWERPC
hardware
include_dir cyg/hal
define_header hal_powerpc_ppc40x.h
description "
The PowerPC 40x variant HAL package provides generic support
for this processor variant. It is also necessary to
select a specific target platform HAL package."
 
# Note: This should be sub-variant specific to reduce memory use.
define_proc {
puts $cdl_header "#define CYGHWR_HAL_VSR_TABLE (CYGHWR_HAL_POWERPC_VECTOR_BASE + 0x3000)"
puts $cdl_header "#define CYGHWR_HAL_VIRTUAL_VECTOR_TABLE (CYGHWR_HAL_VSR_TABLE + 0x200)"
}
 
cdl_component CYGPKG_HAL_POWERPC_PPC403 {
display "PowerPC 403 microprocessor"
default_value 1
implements CYGINT_HAL_POWERPC_VARIANT
description "
The PowerPC 403 microprocessor."
 
cdl_option CYGHWR_HAL_POWERPC_FPU {
display "Variant FPU support"
calculated 0
}
 
cdl_option CYGPKG_HAL_POWERPC_MSBFIRST {
display "CPU Variant big-endian"
calculated 1
}
}
 
define_proc {
puts $::cdl_header "#include <pkgconf/hal_powerpc.h>"
}
 
 
cdl_interface CYGINT_HAL_USE_ROM_MONITOR_UNSUPPORTED {
display "ROM monitor configuration is unsupported"
no_define
}
 
compile var_intr.c var_misc.c variant.S
}
/v2_0/include/var_cache.h
0,0 → 1,218
#ifndef CYGONCE_VAR_CACHE_H
#define CYGONCE_VAR_CACHE_H
//=============================================================================
//
// var_cache.h
//
// Variant HAL cache control API
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, jskov
// Date: 2000-04-02
// Purpose: Variant cache control API
// Description: The macros defined here provide the HAL APIs for handling
// cache control operations on the PPC60x variant CPUs.
// Usage: Is included via the architecture cache header:
// #include <cyg/hal/hal_cache.h>
// ...
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/ppc_regs.h>
 
#include <cyg/hal/plf_cache.h>
 
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE 8192 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 2 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 16384 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 2 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache - this is implicit whenever the MMU is turned on
#define HAL_DCACHE_ENABLE()
 
// Disable the data cache
#define HAL_DCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
int _i_, _ix_, _indx_; \
_indx_ = 0; \
_ix_ = HAL_DCACHE_SIZE/2; \
for (_i_ = 0; _i_ < HAL_DCACHE_SETS; _i_++) { \
/* asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); */ \
/* asm volatile ("dcbf %1,%0;" :: "r"(_indx_), "r"(_ix_)); */\
asm volatile ("dccci 0,%0;" :: "r"(_indx_)); \
_indx_ += HAL_DCACHE_LINE_SIZE; \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
int _indx_; \
for (_indx_ = 0; _indx_ < HAL_DCACHE_SIZE; _indx_ += HAL_DCACHE_LINE_SIZE) { \
asm volatile ("dcbf 0,%0;" :: "r"(_indx_)); \
} \
CYG_MACRO_END
 
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
(_state_) = 1; \
CYG_MACRO_END
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() \
CYG_MACRO_START \
int _i_, _indx_; \
_indx_ = 0; \
for (_i_ = 0; _i_ < HAL_ICACHE_SETS; _i_++) { \
asm volatile ("iccci 0,%0;" :: "r"(_indx_)); \
_indx_ += HAL_ICACHE_LINE_SIZE; \
} \
CYG_MACRO_END
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC() HAL_ICACHE_INVALIDATE_ALL()
 
// Query the state of the instruction cache
#define HAL_ICACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
(_state_) = 1; \
CYG_MACRO_END
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_CACHE_H
// End of var_cache.h
/v2_0/include/var_intr.h
0,0 → 1,145
#ifndef CYGONCE_VAR_INTR_H
#define CYGONCE_VAR_INTR_H
//=============================================================================
//
// var_intr.h
//
// Variant HAL interrupt and clock support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg
// Contributors:nickg, jskov, jlarmour, hmt, gthomas
// Date: 2000-04-02
// Purpose: Variant interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock on the PPC40x variant CPUs.
// Usage: Is included via the architecture interrupt header:
// #include <cyg/hal/hal_intr.h>
// ...
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/plf_intr.h>
 
// Special handling for additional exceptions
 
#define CYGNUM_HAL_VECTOR_TIMERS 16 // Note: must handle all 3!
#define CYGNUM_HAL_VECTOR_DATA_TLB_MISS 17
#define CYGNUM_HAL_VECTOR_INSTR_TLB_MISS 18
#define CYGNUM_HAL_VECTOR_DEBUG 32
 
// No 'trace'/'single step' trap on this processor
#define CYGNUM_HAL_NO_VECTOR_TRACE
 
#define CYGNUM_HAL_VSR_MAX CYGNUM_HAL_VECTOR_DEBUG
 
// Special handling for interrupts
 
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
 
// Additional interrupt sources which are supported by the 40x
#define CYGNUM_HAL_INTERRUPT_CRITICAL 2
#define CYGNUM_HAL_INTERRUPT_SERIAL_RCV 3
#define CYGNUM_HAL_INTERRUPT_SERIAL_XMT 4
#define CYGNUM_HAL_INTERRUPT_JTAG_RCV 5
#define CYGNUM_HAL_INTERRUPT_JTAG_XMT 6
#define CYGNUM_HAL_INTERRUPT_DMA0 7
#define CYGNUM_HAL_INTERRUPT_DMA1 8
#define CYGNUM_HAL_INTERRUPT_DMA2 9
#define CYGNUM_HAL_INTERRUPT_DMA3 10
#define CYGNUM_HAL_INTERRUPT_EXT0 11
#define CYGNUM_HAL_INTERRUPT_EXT1 12
#define CYGNUM_HAL_INTERRUPT_EXT2 13
#define CYGNUM_HAL_INTERRUPT_EXT3 14
#define CYGNUM_HAL_INTERRUPT_EXT4 15
#define CYGNUM_HAL_INTERRUPT_VAR_TIMER 16
#define CYGNUM_HAL_INTERRUPT_FIXED_TIMER 17
#define CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER 18
 
#define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER
 
//--------------------------------------------------------------------------
// Interrupt controller access
 
externC void hal_ppc40x_interrupt_mask(int);
externC void hal_ppc40x_interrupt_unmask(int);
externC void hal_ppc40x_interrupt_acknowledge(int);
externC void hal_ppc40x_interrupt_configure(int, int, int);
externC void hal_ppc40x_interrupt_set_level(int, int);
 
#define HAL_INTERRUPT_MASK( _vector_ ) \
hal_ppc40x_interrupt_mask( _vector_ )
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
hal_ppc40x_interrupt_unmask( _vector_ )
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
hal_ppc40x_interrupt_acknowledge( _vector_ )
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
hal_ppc40x_interrupt_configure( _vector_, _level_, _up_ )
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
hal_ppc40x_interrupt_set_level( _vector_, _level_ )
 
//--------------------------------------------------------------------------
// Clock control
 
externC void hal_ppc40x_clock_initialize(cyg_uint32);
externC void hal_ppc40x_clock_read(cyg_uint32 *);
externC void hal_ppc40x_clock_reset(cyg_uint32, cyg_uint32);
externC void hal_ppc40x_delay_us(int);
 
#define CYGHWR_HAL_CLOCK_DEFINED
#define HAL_CLOCK_INITIALIZE( _period_ ) hal_ppc40x_clock_initialize( _period_ )
#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_ppc40x_clock_reset( _vec_, _period_ )
#define HAL_CLOCK_READ( _pvalue_ ) hal_ppc40x_clock_read( _pvalue_ )
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
#endif
 
#define HAL_DELAY_US(n) hal_ppc40x_delay_us(n)
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_VAR_TIMER
 
//-----------------------------------------------------------------------------
// Symbols used by assembly code
#define CYGARC_VARIANT_DEFS \
DEFINE(CYGNUM_HAL_VECTOR_TIMERS, CYGNUM_HAL_VECTOR_TIMERS); \
DEFINE(CYGNUM_HAL_INTERRUPT_VAR_TIMER,CYGNUM_HAL_INTERRUPT_VAR_TIMER);
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_VAR_INTR_H
// End of var_intr.h
/v2_0/include/variant.inc
0,0 → 1,266
#ifndef CYGONCE_HAL_VARIANT_INC
#define CYGONCE_HAL_VARIANT_INC
##=============================================================================
##
## variant.inc
##
## PPC40x family assembler header file
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): jskov
## Contributors:jskov, gthomas
## Date: 2000-08-27
## Purpose: MPCxxx family definitions.
## Description: This file contains various definitions and macros that are
## useful for writing assembly code for the PPC40x CPU family.
## Usage:
## #include <cyg/hal/variant.inc>
## ...
##
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <pkgconf/hal.h>
#undef CYG_MSR_COMMON
#define CYG_MSR_COMMON (MSR_ME | MSR_RI)
 
#include <cyg/hal/arch.inc>
#include <cyg/hal/plf.inc>
 
##-----------------------------------------------------------------------------
## PPC40x defined vectors
## Special code to handle the various timers which generate non-standard
## interrupts. There are really three VSRs here, each 0x10 apart.
.macro timer_vector name
.p2align 8
.globl __exception_\name
__exception_\name:
# Variable timer interrupt
mtspr SPRG1,r3 # stash some work registers away
mtspr SPRG2,r4
li r4,0x1000 # vector offset
b 0f
# Fixed timer interrupt
mtspr SPRG1,r3 # stash some work registers away
mtspr SPRG2,r4
li r4,0x1010 # vector offset
b 0f
# Watchdog timer interrupt
mtspr SPRG1,r3 # stash some work registers away
mtspr SPRG2,r4
li r4,0x1020 # vector offset
0: mtspr SPRG3,r5
lwi r3,hal_vsr_table+(0x1000>>6) # table base
lwz r3,0(r3) # address of vsr
mflr r5 # save link register
mtlr r3 # put vsr address into it
mr r3,r4 # original vector
mfcr r4 # stash CR
blr # go to common code
.endm
 
.macro hal_extra_vectors
timer_vector ppc40x_timers
exception_vector data_TLB_miss
exception_vector instr_TLB_miss
exception_vector reserved_01300
exception_vector reserved_01400
exception_vector reserved_01500
exception_vector reserved_01600
exception_vector reserved_01700
exception_vector reserved_01800
exception_vector reserved_01900
exception_vector reserved_01A00
exception_vector reserved_01B00
exception_vector reserved_01C00
exception_vector reserved_01D00
exception_vector reserved_01E00
exception_vector reserved_01F00
exception_vector ppc40x_debug
.endm
 
##-----------------------------------------------------------------------------
## PPC40x CPU initialization
##
## Initialize CPU to a post-reset state, ensuring the ground doesn''t
## shift under us while we try to set things up.
.macro hal_cpu_init
# Set up MSR (disable MMU for now)
lwi r3,(CYG_MSR & ~(MSR_IR | MSR_DR))
sync
mfmsr r4
mtmsr r3
sync
.endm
 
##-----------------------------------------------------------------------------
## PPC40x monitor initialization
 
#ifndef CYGPKG_HAL_PPC_MON_DEFINED
 
#if defined(CYG_HAL_STARTUP_ROM) || \
( defined(CYG_HAL_STARTUP_RAM) && \
!defined(CYGSEM_HAL_USE_ROM_MONITOR))
 
.macro hal_mon_init
#ifdef CYGSEM_HAL_POWERPC_COPY_VECTORS
# If we are starting up from ROM and want vectors in RAM
# or we are starting in RAM and NOT using a ROM monitor,
# copy exception handler code to 0.
lwi r3,rom_vectors # r3 = rom start
lwi r4,0 # r4 = ram start
lwi r5,rom_vectors_end # r5 = rom end
cmplw r3,r5 # skip if no vectors
beq 2f
 
subi r3,r3,4
subi r4,r4,4
subi r5,r5,4
1:
lwzu r0,4(r3) # get word from ROM
stwu r0,4(r4) # store in RAM
cmplw r3,r5 # compare
blt 1b # loop if not yet done
2:
 
# Ensure that the vectors will come from 0x0000
lwi r4,0
mtspr SPR_EVPR,r4
#endif
 
# Next initialize the VSR table. This happens whether the
# vectors were copied to RAM or not.
 
# First fill with exception handlers
lwi r3,cyg_hal_default_exception_vsr
lwi r4,hal_vsr_table
subi r4,r4,4
li r5,CYGNUM_HAL_VSR_COUNT
1: stwu r3,4(r4)
subi r5,r5,1
cmpwi r5,0
bne 1b
 
# Then fill in the special vectors
lwi r3,cyg_hal_default_interrupt_vsr
lwi r4,hal_vsr_table
stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
.endm
 
#elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
 
# Initialize the VSR table entries
# We only take control of the interrupt vectors,
# the rest are left to the ROM for now...
 
.macro hal_mon_init
lwi r3,cyg_hal_default_interrupt_vsr
lwi r4,hal_vsr_table
stw r3,CYGNUM_HAL_VECTOR_INTERRUPT*4(r4)
stw r3,CYGNUM_HAL_VECTOR_DECREMENTER*4(r4)
stw r3,CYGNUM_HAL_VECTOR_TIMERS*4(r4)
.endm
 
 
#else
 
.macro hal_mon_init
 
.endm
 
#endif
 
 
#define CYGPKG_HAL_PPC_MON_DEFINED
 
#endif // CYGPKG_HAL_PPC_MON_DEFINED
 
##-----------------------------------------------------------------------------
## PPC40x exception state handling
.macro hal_variant_save regs
.endm
 
.macro hal_variant_load regs
.endm
 
##-----------------------------------------------------------------------------
## Indicate that the ISR tables are defined in variant.S
 
#define CYG_HAL_PPC_ISR_TABLES_DEFINED
 
##-----------------------------------------------------------------------------
## MPC4xx interrupt handling.
 
## Decode the EXISR appropriately
 
#define CYGPKG_HAL_POWERPC_INTC_DEFINED
# decode the interrupt
# the interrupt vector will be 0x500 or 0x10x0
# 0x0500 = external, must be decoded via EXISR
# 0x10X0 = timer, X is the timer type
# r3 used as scratch
.macro hal_intc_decode dreg,state
lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
extrwi. \dreg,\dreg,1,19 # isolate bit 19
beq 0f # timer interrupt = 1
lwz \dreg,CYGARC_PPCREG_VECTOR(\state) # retrieve vector number,
extrwi \dreg,\dreg,2,26 # isolate bits 26-27
addi \dreg,\dreg,CYGNUM_HAL_INTERRUPT_VAR_TIMER # FIXME
b 1f
0: mfdcr r3,DCR_EXISR # Interrupt status register
lwi \dreg,0x8FF0001F # significant bits
and \dreg,\dreg,r3
cntlzw r3,\dreg # find highest "1" bit
slwi r3,r3,2
lwi \dreg,EXISR_TAB # convert bit # to signal #
lwzx \dreg,\dreg,r3
1: stw \dreg,CYGARC_PPCREG_VECTOR(\state) # update vector in state frame.
slwi \dreg,\dreg,2 # convert to byte offset.
.endm
 
 
#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VARIANT_INC
# end of variant.inc
/v2_0/include/var_regs.h
0,0 → 1,159
#ifndef CYGONCE_HAL_VAR_REGS_H
#define CYGONCE_HAL_VAR_REGS_H
 
//==========================================================================
//
// var_regs.h
//
// PowerPC 40x variant CPU definitions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov,gthomas
// Date: 2000-08-27
// Purpose: Provide PPC40x register definitions
// Description: Provide PPC40x register definitions
// The short difinitions (sans CYGARC_REG_) are exported only
// if CYGARC_HAL_COMMON_EXPORT_CPU_MACROS is defined.
// Usage: Included via the acrhitecture register header:
// #include <cyg/hal/ppc_regs.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
//--------------------------------------------------------------------------
// Cache
#define CYGARC_REG_HID0 1008
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#define HID0 CYGARC_REG_HID0
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//--------------------------------------------------------------------------
// MMU control.
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
#define SPR_EVPR 982 // Exception vector prefix
#define SPR_PID 945 // Process ID
 
#define M_EPN_EPNMASK 0xfffff000 // effective page no mask
#define M_EPN_EV 0x00000040 // entry valid
#define M_EPN_SIZE(n) (n<<7) // entry size (0=1K, 1=4K, ... 7=16M)
 
#define M_RPN_RPNMASK 0xfffff000 // real page no mask
#define M_RPN_EX 0x00000200 // execute enable
#define M_RPN_WR 0x00000100 // write enable
#define M_RPN_W 0x00000008 // write-through (when cache enabled)
#define M_RPN_I 0x00000004 // cache inhibited
#define M_RPN_M 0x00000002 // memory coherent (not implemented)
#define M_RPN_G 0x00000001 // guarded
 
#define CYGARC_TLBWE(_id_, _hi_, _lo_) \
asm volatile ("tlbwe %1,%0,0; tlbwe %2,%0,1" :: "r"(_id_), "r"(_hi_), "r"(_lo_));
 
#define CYGARC_TLBRE(_id_, _hi_, _lo_) \
asm volatile ("tlbre %0,%2,0; tlbre %1,%2,1" : "=r"(_hi_), "=r"(_lo_) : "r"(_id_));
 
#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//--------------------------------------------------------------------------
// Device control register access macros.
#define CYGARC_MTDCR(_tbr_, _v_) \
asm volatile ("mtdcr %0, %1;" :: "I" (_tbr_), "r" (_v_));
#define CYGARC_MFDCR(_tbr_, _v_) \
asm volatile ("mfdcr %0, %1;" : "=r" (_v_) : "I" (_tbr_));
 
#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
// Interrupt control (device) registers
#define DCR_EXIER 66
#define DCR_EXISR 64
#define DCR_IOCR 160
 
// Timer control (special) registers
#define SPR_PIT 987
#define SPR_TCR 986
#define SPR_TSR 984
 
// Interval and watchdog timer control
#define TCR_WP 0xC0000000 // Watchdog timer period
#define TCR_WP_17 0x00000000 // 2^17 clocks
#define TCR_WP_21 0x40000000 // 2^21 clocks
#define TCR_WP_25 0x80000000 // 2^25 clocks
#define TCR_WP_29 0xC0000000 // 2^29 clocks
#define TCR_WRC 0x30000000 // Reset control
#define TCR_WRC_None 0x00000000 // No reset on timeout
#define TCR_WRC_Core 0x10000000 // Reset core on timeout
#define TCR_WRC_Chip 0x20000000 // Reset chip on timeout
#define TCR_WRC_System 0x30000000 // Reset system on timeout
#define TCR_WIE 0x08000000 // Watchdog interrupt enable
#define TCR_PIE 0x04000000 // Programmable timer interrupt
#define TCR_FP 0x03000000 // Fixed timer interval
#define TCR_FP_9 0x00000000 // 2^9 clocks
#define TCR_FP_13 0x01000000 // 2^13 clocks
#define TCR_FP_17 0x02000000 // 2^17 clocks
#define TCR_FP_21 0x03000000 // 2^21 clocks
#define TCR_FIE 0x00800000 // Fixed timer interrupt
#define TCR_ARE 0x00400000 // Auto-reload enable
 
// Interval and watchdog status
#define TSR_ENW 0x80000000 // Enable next watchdog
#define TSR_WIS 0x40000000 // Watchdog interrupt pending
#define TSR_WRS 0x30000000 // Watchdog reset state
#define TSR_WRS_None 0x00000000 // No watchdog reset
#define TSR_WRS_Core 0x10000000 // Core reset by watchdog
#define TSR_WRS_Chip 0x20000000 // Chip reset by watchdog
#define TSR_WRS_System 0x30000000 // System reset by watchdog
#define TSR_PIS 0x08000000 // Programmable timer interrupt
#define TSR_FIS 0x04000000 // Fixed timer interrupt
 
// Debug registers
#define SPR_DBSR 1008
#define SPR_DBCR 1010
 
#define DBCR_IDM 0x40000000 // Internal debug enable
#define DBCR_IC 0x08000000 // Instruction completion
 
#endif // CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
 
//-----------------------------------------------------------------------------
#endif // ifdef CYGONCE_HAL_VAR_REGS_H
// End of var_regs.h
/v2_0/ChangeLog
0,0 → 1,97
2002-05-22 Jesper Skov <jskov@redhat.com>
 
* src/var_intr.c: Fixed warning.
* src/var_misc.c: Same.
 
2002-05-13 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_powerpc_ppc40x.cdl: This processor family has no FPU.
 
2001-01-26 Jesper Skov <jskov@redhat.com>
 
* include/var_intr.h: Include plf_intr.h
 
2001-01-18 Gary Thomas <gthomas@redhat.com>
 
* cdl/hal_powerpc_ppc40x.cdl: Move CYGSEM_HAL_USE_ROM_MONITOR to
platform CDL.
 
2001-01-17 Gary Thomas <gthomas@redhat.com>
 
* include/variant.inc: Fix EXISR interrupt decode.
 
2001-01-16 Gary Thomas <gthomas@redhat.com>
 
* src/var_intr.c (hal_variant_IRQ_init): Add platform IRQ support.
(hal_ppc40x_interrupt_configure): Properly configure level interrupts.
 
2001-01-15 Gary Thomas <gthomas@redhat.com>
 
* include/var_regs.h (SPR_DBSR, SPR_DBCR): Special registers used
for debug support. Too bad the hardware is broken.
 
* include/var_intr.h (CYGNUM_HAL_NO_VECTOR_TRACE): Disable common
single step code [hardware does not work].
 
2000-11-21 Gary Thomas <gthomas@redhat.com>
 
* include/variant.inc: Include platform specifics <cyg/hal/plf.inc>
 
2000-11-12 Gary Thomas <gthomas@redhat.com>
 
* src/var_misc.c: Add hal_delay_us().
 
2000-11-04 Gary Thomas <gthomas@redhat.com>
 
* src/var_misc.c: Define clock handling for PPC40x (different
from default since there is no decrementer).
 
* include/variant.inc: Special interrupt fielder for timers.
Add interrupt decode.
 
* include/var_regs.h: Define architecture (variant) specific
registers and special instructions used to access them.
 
* src/var_intr.c:
* include/var_intr.h: Define proper interrupt support for
this platform.
 
* include/var_cache.h: Fix details of cache on PPC40x. Note:
the data cache has problems - currently left disabled.
 
* cdl/hal_powerpc_ppc40x.cdl: Add support for ROM_MONITOR.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
/v2_0/src/var_misc.c
0,0 → 1,215
//==========================================================================
//
// var_misc.c
//
// HAL implementation miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov, gthomas
// Date: 2000-02-04
// Purpose: HAL miscellaneous functions
// Description: This file contains miscellaneous functions provided by the
// HAL.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
 
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/ppc_regs.h>
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_mem.h>
 
void hal_ppc40x_clock_initialize(cyg_uint32 period);
 
//--------------------------------------------------------------------------
void hal_variant_init(void)
{
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
hal_ppc40x_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
}
 
 
//--------------------------------------------------------------------------
// Variant specific idle thread action.
bool
hal_variant_idle_thread_action( cyg_uint32 count )
{
// Let architecture idle thread action run
return true;
}
 
//---------------------------------------------------------------------------
// Use MMU resources to map memory regions.
// Takes and returns an int used to ID the MMU resource to use. This ID
// is increased as resources are used and should be used for subsequent
// invocations.
//
// The PPC4xx CPUs do not have BATs. Fortunately we don't currently
// use the MMU, so we can simulate BATs by using the TLBs.
int
cyg_hal_map_memory (int id, CYG_ADDRESS virt, CYG_ADDRESS phys,
cyg_int32 size, cyg_uint8 flags)
{
cyg_uint32 epn, rpn;
int sv, lv, max_tlbs;
 
// There are 64 TLBs.
max_tlbs = 64;
 
// Use the smallest "size" value which is big enough (round up)
for (sv = 0, lv = 0x400; sv < 8; sv++, lv <<= 2) {
if (lv >= size) break;
}
 
// Note: the process ID comes from the PID register (always 0)
epn = (virt & M_EPN_EPNMASK) | M_EPN_EV | M_EPN_SIZE(sv);
rpn = (phys & M_RPN_RPNMASK) | M_RPN_EX | M_RPN_WR;
 
if (flags & CYGARC_MEMDESC_CI) {
rpn |= M_RPN_I;
}
 
if (flags & CYGARC_MEMDESC_GUARDED)
rpn |= M_RPN_G;
 
CYGARC_TLBWE(id, epn, rpn);
id++;
 
// Make caches default disabled when MMU is disabled.
 
return id;
}
 
 
// Initialize MMU to a sane (NOP) state.
//
// Initialize TLBs with 0, Valid bits unset.
void
cyg_hal_clear_MMU (void)
{
cyg_uint32 tlbhi = 0;
cyg_uint32 tlblo = 0;
int id, max_tlbs;
 
// There are 64 TLBs.
max_tlbs = 64;
 
CYGARC_MTSPR (SPR_PID, 0);
 
for (id = 0; id < max_tlbs; id++) {
CYGARC_TLBWE(id, tlbhi, tlblo);
}
}
 
//--------------------------------------------------------------------------
// Clock control - use the programmable (variable period) timer
 
static cyg_uint32 _period;
extern cyg_uint32 _hold_tcr; // Shadow of TCR register which can't be read
 
void
hal_ppc40x_clock_initialize(cyg_uint32 period)
{
cyg_uint32 tcr;
 
// Enable auto-reload
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr |= TCR_ARE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
 
// Set up the counter register
_period = period;
CYGARC_MTSPR(SPR_PIT, period);
}
 
// Returns the number of clocks since the last interrupt
externC void
hal_ppc40x_clock_read(cyg_uint32 *val)
{
cyg_uint32 cur_val;
 
CYGARC_MFSPR(SPR_PIT, cur_val);
*val = _period - cur_val;
}
 
externC void
hal_ppc40x_clock_reset(cyg_uint32 vector, cyg_uint32 period)
{
hal_ppc40x_clock_initialize(period);
}
 
//
// Delay for the specified number of microseconds.
// Assumption: _period has been set already and corresponds to the
// system clock frequency, normally 10ms.
//
 
externC void
hal_ppc40x_delay_us(int us)
{
cyg_uint32 delay_period, delay, diff;
cyg_uint32 pit_val1, pit_val2;
 
delay_period = (_period * us) / 10000;
delay = 0;
CYGARC_MFSPR(SPR_PIT, pit_val1);
while (delay < delay_period) {
// Wait for clock to "tick"
while (true) {
CYGARC_MFSPR(SPR_PIT, pit_val2);
if (pit_val2 != pit_val1) break;
}
if (pit_val2 > pit_val1) {
diff = pit_val2 - pit_val1;
} else {
diff = (pit_val2 + _period) - pit_val1;
}
delay += diff;
pit_val1 = pit_val2;
}
}
 
//--------------------------------------------------------------------------
// End of var_misc.c
/v2_0/src/var_intr.c
0,0 → 1,300
//==========================================================================
//
// var_intr.c
//
// PowerPC variant interrupt handlers
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): jskov
// Contributors: jskov, gthomas
// Date: 2000-02-11
// Purpose: PowerPC variant interrupt handlers
// Description: This file contains code to handle interrupt related issues
// on the PowerPC variant.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
#include <cyg/hal/ppc_regs.h>
#include <cyg/hal/hal_intr.h>
#include <cyg/infra/cyg_type.h>
 
extern void hal_platform_IRQ_init(void);
 
 
static cyg_uint32 exier_mask[] = {
0x00000000, // Unused
0x00000000, // Unused
0x80000000, // CYGNUM_HAL_INTERRUPT_CRITICAL 2
0x08000000, // CYGNUM_HAL_INTERRUPT_SERIAL_RCV 3
0x04000000, // CYGNUM_HAL_INTERRUPT_SERIAL_XMT 4
0x02000000, // CYGNUM_HAL_INTERRUPT_JTAG_RCV 5
0x01000000, // CYGNUM_HAL_INTERRUPT_JTAG_XMT 6
0x00800000, // CYGNUM_HAL_INTERRUPT_DMA0 7
0x00400000, // CYGNUM_HAL_INTERRUPT_DMA1 8
0x00200000, // CYGNUM_HAL_INTERRUPT_DMA2 9
0x00100000, // CYGNUM_HAL_INTERRUPT_DMA3 10
0x00000010, // CYGNUM_HAL_INTERRUPT_EXT0 11
0x00000008, // CYGNUM_HAL_INTERRUPT_EXT1 12
0x00000004, // CYGNUM_HAL_INTERRUPT_EXT2 13
0x00000002, // CYGNUM_HAL_INTERRUPT_EXT3 14
0x00000001, // CYGNUM_HAL_INTERRUPT_EXT4 15
};
 
// This table inverts bit number to signal number
cyg_uint32 EXISR_TAB[] = {
CYGNUM_HAL_INTERRUPT_CRITICAL, // 0x80000000
0x00000000, // 0x40000000
0x00000000, // 0x20000000
0x00000000, // 0x10000000
CYGNUM_HAL_INTERRUPT_SERIAL_RCV, // 0x08000000
CYGNUM_HAL_INTERRUPT_SERIAL_XMT, // 0x04000000
CYGNUM_HAL_INTERRUPT_JTAG_RCV, // 0x02000000
CYGNUM_HAL_INTERRUPT_JTAG_XMT, // 0x01000000
CYGNUM_HAL_INTERRUPT_DMA0, // 0x00800000
CYGNUM_HAL_INTERRUPT_DMA1, // 0x00400000
CYGNUM_HAL_INTERRUPT_DMA2, // 0x00200000
CYGNUM_HAL_INTERRUPT_DMA3, // 0x00100000
0x00000000, // 0x00080000
0x00000000, // 0x00040000
0x00000000, // 0x00020000
0x00000000, // 0x00010000
0x00000000, // 0x00008000
0x00000000, // 0x00004000
0x00000000, // 0x00002000
0x00000000, // 0x00001000
0x00000000, // 0x00000800
0x00000000, // 0x00000400
0x00000000, // 0x00000200
0x00000000, // 0x00000100
0x00000000, // 0x00000080
0x00000000, // 0x00000040
0x00000000, // 0x00000020
CYGNUM_HAL_INTERRUPT_EXT0, // 0x00000010
CYGNUM_HAL_INTERRUPT_EXT1, // 0x00000008
CYGNUM_HAL_INTERRUPT_EXT2, // 0x00000004
CYGNUM_HAL_INTERRUPT_EXT3, // 0x00000002
CYGNUM_HAL_INTERRUPT_EXT4 // 0x00000001
};
 
cyg_uint32 _hold_tcr = 0; // Shadow of hardware register
 
externC void
hal_variant_IRQ_init(void)
{
cyg_uint32 iocr;
 
// Ensure all interrupts masked (disabled) & cleared
CYGARC_MTDCR(DCR_EXIER, 0);
CYGARC_MTDCR(DCR_EXISR, 0xFFFFFFFF);
 
// Configure all external interrupts to be level/low
CYGARC_MFDCR(DCR_IOCR, iocr);
iocr &= ~0xFFC00000;
CYGARC_MTDCR(DCR_IOCR, iocr);
 
// Disable timers
CYGARC_MTSPR(SPR_TCR, 0);
 
// Let the platform do any overrides
hal_platform_IRQ_init();
}
 
externC void
hal_ppc40x_interrupt_mask(int vector)
{
cyg_uint32 exier, tcr;
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_CRITICAL:
case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
case CYGNUM_HAL_INTERRUPT_DMA0:
case CYGNUM_HAL_INTERRUPT_DMA1:
case CYGNUM_HAL_INTERRUPT_DMA2:
case CYGNUM_HAL_INTERRUPT_DMA3:
case CYGNUM_HAL_INTERRUPT_EXT0:
case CYGNUM_HAL_INTERRUPT_EXT1:
case CYGNUM_HAL_INTERRUPT_EXT2:
case CYGNUM_HAL_INTERRUPT_EXT3:
case CYGNUM_HAL_INTERRUPT_EXT4:
CYGARC_MFDCR(DCR_EXIER, exier);
exier &= ~exier_mask[vector];
CYGARC_MTDCR(DCR_EXIER, exier);
break;
case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr &= ~TCR_PIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr &= ~TCR_FIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr &= ~TCR_WIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
default:
}
}
 
externC void
hal_ppc40x_interrupt_unmask(int vector)
{
cyg_uint32 exier, tcr;
 
switch (vector) {
case CYGNUM_HAL_INTERRUPT_CRITICAL:
case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
case CYGNUM_HAL_INTERRUPT_DMA0:
case CYGNUM_HAL_INTERRUPT_DMA1:
case CYGNUM_HAL_INTERRUPT_DMA2:
case CYGNUM_HAL_INTERRUPT_DMA3:
case CYGNUM_HAL_INTERRUPT_EXT0:
case CYGNUM_HAL_INTERRUPT_EXT1:
case CYGNUM_HAL_INTERRUPT_EXT2:
case CYGNUM_HAL_INTERRUPT_EXT3:
case CYGNUM_HAL_INTERRUPT_EXT4:
CYGARC_MFDCR(DCR_EXIER, exier);
exier |= exier_mask[vector];
CYGARC_MTDCR(DCR_EXIER, exier);
break;
case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr |= TCR_PIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr |= TCR_FIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
CYGARC_MFSPR(SPR_TCR, tcr);
tcr = _hold_tcr;
tcr |= TCR_WIE;
CYGARC_MTSPR(SPR_TCR, tcr);
_hold_tcr = tcr;
break;
default:
}
}
 
externC void
hal_ppc40x_interrupt_acknowledge(int vector)
{
switch (vector) {
case CYGNUM_HAL_INTERRUPT_EXT0:
case CYGNUM_HAL_INTERRUPT_EXT1:
case CYGNUM_HAL_INTERRUPT_EXT2:
case CYGNUM_HAL_INTERRUPT_EXT3:
case CYGNUM_HAL_INTERRUPT_EXT4:
CYGARC_MTDCR(DCR_EXISR, exier_mask[vector]);
break;
case CYGNUM_HAL_INTERRUPT_VAR_TIMER:
CYGARC_MTSPR(SPR_TSR, TSR_PIS); // clear & acknowledge interrupt
break;
case CYGNUM_HAL_INTERRUPT_FIXED_TIMER:
CYGARC_MTSPR(SPR_TSR, TSR_FIS); // clear & acknowledge interrupt
break;
case CYGNUM_HAL_INTERRUPT_WATCHDOG_TIMER:
CYGARC_MTSPR(SPR_TSR, TSR_WIS); // clear & acknowledge interrupt
break;
case CYGNUM_HAL_INTERRUPT_CRITICAL:
case CYGNUM_HAL_INTERRUPT_SERIAL_RCV:
case CYGNUM_HAL_INTERRUPT_SERIAL_XMT:
case CYGNUM_HAL_INTERRUPT_JTAG_RCV:
case CYGNUM_HAL_INTERRUPT_JTAG_XMT:
case CYGNUM_HAL_INTERRUPT_DMA0:
case CYGNUM_HAL_INTERRUPT_DMA1:
case CYGNUM_HAL_INTERRUPT_DMA2:
case CYGNUM_HAL_INTERRUPT_DMA3:
default:
}
}
 
// Note: These functions are only [well] defined for "external" interrupts
// which can be controlled via the EXIER register.
externC void
hal_ppc40x_interrupt_configure(int vector, int level, int dir)
{
cyg_uint32 mask, new_state, iocr;
 
if ((vector >= CYGNUM_HAL_INTERRUPT_EXT0) &&
(vector <= CYGNUM_HAL_INTERRUPT_EXT4)) {
mask = 0x03 << (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
new_state = (dir & 0x01); // Up/Down
if (level == 0) {
// Edge triggered
new_state = 0x02;
}
new_state <<= (30 - ((vector - CYGNUM_HAL_INTERRUPT_EXT0)*2));
CYGARC_MFDCR(DCR_IOCR, iocr);
iocr = (iocr & ~mask) | new_state;
CYGARC_MTDCR(DCR_IOCR, iocr);
}
}
 
externC void
hal_ppc40x_interrupt_set_level(int vector, int level)
{
}
 
// -------------------------------------------------------------------------
// EOF var_intr.c
/v2_0/src/variant.S
0,0 → 1,86
##=============================================================================
##
## variant.S
##
## PowerPC PPC40x variant code
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s): jskov
## Contributors:jskov,gthomas
## Date: 2000-08-27
## Purpose: PowerPC PPC40x variant code
## Description: Variant specific code for PowerPC 40x CPUs.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include <cyg/hal/variant.inc>
 
#---------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
 
.data
 
.extern hal_default_decrementer_isr
.extern hal_default_isr
 
.globl hal_interrupt_handlers
hal_interrupt_handlers:
.long hal_default_decrementer_isr
.rept CYGNUM_HAL_ISR_COUNT-1
.long hal_default_isr
.endr
 
.globl hal_interrupt_data
hal_interrupt_data:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
.globl hal_interrupt_objects
hal_interrupt_objects:
.rept CYGNUM_HAL_ISR_COUNT
.long 0
.endr
 
##-----------------------------------------------------------------------------
## end of variant.S

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