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    /openrisc/trunk/rtos/ecos-2.0/packages/hal/sparc
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Rev 27 → Rev 174

/arch/v2_0/cdl/hal_sparc.cdl
0,0 → 1,131
# ====================================================================
#
# hal_sparc.cdl
#
# SPARC architectural HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: hmt
# Contributors:
# Date: 1999-11-01, 2002-03-08
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_SPARC {
display "SPARC architecture"
parent CYGPKG_HAL
hardware
include_dir cyg/hal
define_header hal_sparc.h
description "
The SPARC architecture HAL package provides generic support
for this processor architecture. It is also necessary to select
a specific target platform HAL package."
 
compile vectors.S vec_ivsr.S vec_xvsr.S context.S icontext.c
compile hal_intr.c hal_boot.c
 
make {
<PREFIX>/lib/vectors.o : <PACKAGE>/src/vectors.S
$(CC) -Wp,-MD,vectors.tmp $(INCLUDE_PATH) $(CFLAGS) -c -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 vectors.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm vectors.tmp
}
 
make {
<PREFIX>/lib/target.ld: <PACKAGE>/src/sparc.ld
$(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<
@echo $@ ": \\" > $(notdir $@).deps
@tail +2 target.tmp >> $(notdir $@).deps
@echo >> $(notdir $@).deps
@rm target.tmp
}
 
cdl_component CYGPKG_HAL_SPARC_OPTIONS {
display "SPARC build options"
flavor none
description "
Package specific build options including control over
compiler flags used only in building this package,
and details of which tests are built."
 
 
cdl_option CYGPKG_HAL_SPARC_CFLAGS_ADD {
display "Additional compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the SPARC HAL. These flags are used in addition
to the set of global flags."
}
 
cdl_option CYGPKG_HAL_SPARC_CFLAGS_REMOVE {
display "Suppressed compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the SPARC HAL. These flags are removed from
the set of global flags if present."
}
 
cdl_option CYGPKG_HAL_SPARC_TESTS {
display "SPARC tests"
flavor data
no_define
calculated { "tests/sparc_ex" }
description "
This option specifies the set of tests for the SPARC HAL."
}
}
 
cdl_option CYGBLD_LINKER_SCRIPT {
display "Linker script"
flavor data
no_define
calculated { "src/sparc.ld" }
}
}
/arch/v2_0/tests/sparc_ex.c
0,0 → 1,437
/*=================================================================
//
// sparc_ex.c
//
// SPARC HAL exception and register manipulation test
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): dsm
// Contributors: dsm, nickg
// Date: 1998-06-18
//####DESCRIPTIONEND####
*/
 
#include <pkgconf/system.h>
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/infra/testcase.h>
 
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/hal_intr.h>
 
#include <pkgconf/infra.h>
 
#ifdef CYGDBG_USE_TRACING
#define OUTER_REPEATS 1
#define SIM_REPEATS 10
#define HW_REPEATS 1000
#else
#define OUTER_REPEATS 10
#define SIM_REPEATS 100
#define HW_REPEATS 10000
#endif // using tracing to slow everything down
 
// -------------------------------------------------------------------------
// These routines are used to cause an alignment trap; the compiler is too
// darned clever by half, if you try to inline this stuff as macros it uses
// different instruction sequences and register pairs. This makes for a
// less thorough test, but there's no option other than writing a LOT of
// assembler code.
 
// Further, with -O3, the compiler inlines these anyway and so makes
// non-trapping code. So they are now at the end, to prevent this.
 
extern cyg_uint64 get_ll( cyg_uint64 *p );
 
extern cyg_uint64 get_llplus( cyg_uint64 *p );
 
extern cyg_uint32 get_i( cyg_uint32 *p );
 
extern cyg_uint32 get_iplus( cyg_uint32 *p );
 
extern cyg_uint16 get_s( cyg_uint16 *p );
 
extern cyg_uint16 get_splus( cyg_uint16 *p );
 
// -------------------------------------------------------------------------
// Some memory to read in more-or-less aligned manners.
 
#define L1 (0x123456789abcdef0l)
#define L2 (0xfedcba9876543210l)
static cyg_uint64 a[ 2 ] = {
L1,
L2
};
 
#define M32 (0x00000000ffffffffl)
#define M16 (0x000000000000ffffl)
#define M8 (0x00000000000000ffl)
 
volatile cyg_uint32 trap = 0;
volatile cyg_uint32 same = 0;
volatile cyg_uint32 tcount = 0;
 
// -------------------------------------------------------------------------
// This macro invokes a routine then checks that a suitable trap occurred.
// It expects the instruction simply to be skipped, rather than the trap
// _handled_ or the unaligned access to be _emulated_ in any way. This
// test is just a proof that we could write such a handler.
 
#define TRAPPROC( _var_, _type_, _align_, _proc_ ) \
CYG_MACRO_START \
otrap = trap; \
otcount = tcount; \
_var_ = _proc_( (_type_ *)(cp + (_align_)) ); \
CYG_TEST_CHECK( trap != otrap || same > 0, \
"No trap [" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_TEST_CHECK( same < 20, \
"Undetected trap loop[" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_TEST_CHECK( tcount > otcount, \
"No trap counted [" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_TEST_CHECK( (tcount - 1) <= otcount, \
"Tcount overinc [" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_MACRO_END
 
// and this one expects no trap to occur:
#define SAFEPROC( _var_, _type_, _align_, _proc_ ) \
CYG_MACRO_START \
trap = 0; \
otcount = tcount; \
_var_ = _proc_( (_type_ *)(cp + (_align_)) ); \
CYG_TEST_CHECK( 0 == trap, \
"Trap [" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_TEST_CHECK( tcount == otcount, \
"Trap counted [" #_type_ ":" #_align_ "," #_proc_ "]" ); \
CYG_MACRO_END
 
static void do_test( void )
{
cyg_uint32 *ip = (cyg_uint32 *)a;
cyg_uint16 *sp = (cyg_uint16 *)a;
cyg_uint8 *cp = (cyg_uint8 *)a;
cyg_uint64 l;
cyg_uint32 i;
cyg_uint16 s;
cyg_uint8 c;
 
cyg_int32 z, repeats;
 
cyg_uint32 otrap;
cyg_uint32 otcount;
 
otrap = trap = 0;
otcount = tcount;
 
// First test interestingly aligned accesses that are legal.
 
l = a[0]; CYG_TEST_CHECK( L1 == l, "a[0] read bad" );
l = a[1]; CYG_TEST_CHECK( L2 == l, "a[1] read bad" );
 
i = ip[0]; CYG_TEST_CHECK( ((L1 >> 32) & M32) == i, "ip[0]" );
i = ip[1]; CYG_TEST_CHECK( ((L1 ) & M32) == i, "ip[1]" );
i = ip[2]; CYG_TEST_CHECK( ((L2 >> 32) & M32) == i, "ip[2]" );
i = ip[3]; CYG_TEST_CHECK( ((L2 ) & M32) == i, "ip[3]" );
s = sp[0]; CYG_TEST_CHECK( ((L1 >> 48) & M16) == s, "sp[0]" );
s = sp[1]; CYG_TEST_CHECK( ((L1 >> 32) & M16) == s, "sp[1]" );
s = sp[2]; CYG_TEST_CHECK( ((L1 >> 16) & M16) == s, "sp[2]" );
s = sp[3]; CYG_TEST_CHECK( ((L1 ) & M16) == s, "sp[3]" );
s = sp[4]; CYG_TEST_CHECK( ((L2 >> 48) & M16) == s, "sp[4]" );
s = sp[5]; CYG_TEST_CHECK( ((L2 >> 32) & M16) == s, "sp[5]" );
s = sp[6]; CYG_TEST_CHECK( ((L2 >> 16) & M16) == s, "sp[6]" );
s = sp[7]; CYG_TEST_CHECK( ((L2 ) & M16) == s, "sp[7]" );
c = cp[0]; CYG_TEST_CHECK( ((L1 >> 56) & M8) == c, "cp[0]" );
c = cp[1]; CYG_TEST_CHECK( ((L1 >> 48) & M8) == c, "cp[1]" );
c = cp[2]; CYG_TEST_CHECK( ((L1 >> 40) & M8) == c, "cp[2]" );
c = cp[3]; CYG_TEST_CHECK( ((L1 >> 32) & M8) == c, "cp[3]" );
c = cp[4]; CYG_TEST_CHECK( ((L1 >> 24) & M8) == c, "cp[4]" );
c = cp[5]; CYG_TEST_CHECK( ((L1 >> 16) & M8) == c, "cp[5]" );
c = cp[6]; CYG_TEST_CHECK( ((L1 >> 8) & M8) == c, "cp[6]" );
c = cp[7]; CYG_TEST_CHECK( ((L1 ) & M8) == c, "cp[7]" );
c = cp[8]; CYG_TEST_CHECK( ((L2 >> 56) & M8) == c, "cp[8]" );
c = cp[9]; CYG_TEST_CHECK( ((L2 >> 48) & M8) == c, "cp[9]" );
c = cp[10]; CYG_TEST_CHECK( ((L2 >> 40) & M8) == c, "cp[10]" );
c = cp[11]; CYG_TEST_CHECK( ((L2 >> 32) & M8) == c, "cp[11]" );
c = cp[12]; CYG_TEST_CHECK( ((L2 >> 24) & M8) == c, "cp[12]" );
c = cp[13]; CYG_TEST_CHECK( ((L2 >> 16) & M8) == c, "cp[13]" );
c = cp[14]; CYG_TEST_CHECK( ((L2 >> 8) & M8) == c, "cp[14]" );
c = cp[15]; CYG_TEST_CHECK( ((L2 ) & M8) == c, "cp[15]" );
 
CYG_TEST_CHECK( 0 == trap, "Traps occurred (legal accesses)" );
CYG_TEST_CHECK( tcount == otcount, "Traps counted (legal accesses)" );
 
CYG_TEST_PASS( "Aligned accesses OK" );
 
for ( z = OUTER_REPEATS; z > 0; z-- ) {
 
for ( repeats = (cyg_test_is_simulator ? SIM_REPEATS : HW_REPEATS) ;
repeats > 0 ; repeats-- ) {
 
TRAPPROC( l, cyg_uint64, 4, get_llplus );
TRAPPROC( l, cyg_uint64, 5, get_llplus );
TRAPPROC( l, cyg_uint64, 6, get_llplus );
TRAPPROC( l, cyg_uint64, 7, get_llplus );
 
TRAPPROC( l, cyg_uint64, 4, get_ll );
TRAPPROC( l, cyg_uint64, 1, get_ll );
TRAPPROC( l, cyg_uint64, 2, get_ll );
TRAPPROC( l, cyg_uint64, 3, get_ll );
 
TRAPPROC( i, cyg_uint32, 1, get_iplus );
TRAPPROC( i, cyg_uint32, 2, get_iplus );
TRAPPROC( i, cyg_uint32, 3, get_iplus );
 
TRAPPROC( i, cyg_uint32, 5, get_i );
TRAPPROC( i, cyg_uint32, 6, get_i );
TRAPPROC( i, cyg_uint32, 7, get_i );
 
TRAPPROC( s, cyg_uint16, 1, get_splus );
TRAPPROC( s, cyg_uint16, 3, get_splus );
 
TRAPPROC( s, cyg_uint16, 5, get_s );
TRAPPROC( s, cyg_uint16, 7, get_s );
}
 
CYG_TEST_PASS( "Unaligned accesses OK" );
 
// Now test some legal and illegal accesses intermingled.
 
for ( repeats = (cyg_test_is_simulator ? SIM_REPEATS : HW_REPEATS) ;
repeats > 0 ; repeats-- ) {
 
SAFEPROC( l, cyg_uint64, 0, get_llplus );
TRAPPROC( l, cyg_uint64, 5, get_llplus );
TRAPPROC( l, cyg_uint64, 6, get_llplus );
SAFEPROC( l, cyg_uint64, 8, get_llplus );
 
TRAPPROC( i, cyg_uint32, 1, get_iplus );
SAFEPROC( i, cyg_uint32, 4, get_iplus );
TRAPPROC( i, cyg_uint32, 2, get_iplus );
SAFEPROC( i, cyg_uint32, 8, get_iplus );
SAFEPROC( i, cyg_uint32, 12, get_iplus );
SAFEPROC( i, cyg_uint32, 16, get_iplus );
TRAPPROC( i, cyg_uint32, 3, get_iplus );
 
TRAPPROC( s, cyg_uint16, 5, get_s );
SAFEPROC( s, cyg_uint16, 6, get_s );
TRAPPROC( s, cyg_uint16, 7, get_s );
SAFEPROC( s, cyg_uint16, 8, get_s );
TRAPPROC( i, cyg_uint32, 5, get_i );
SAFEPROC( i, cyg_uint32, 4, get_i );
TRAPPROC( i, cyg_uint32, 6, get_i );
TRAPPROC( i, cyg_uint32, 7, get_i );
SAFEPROC( i, cyg_uint32, 0, get_i );
 
TRAPPROC( l, cyg_uint64, 4, get_ll );
SAFEPROC( l, cyg_uint64, 0, get_ll );
TRAPPROC( l, cyg_uint64, 1, get_ll );
SAFEPROC( l, cyg_uint64, 8, get_ll );
 
TRAPPROC( s, cyg_uint16, 1, get_splus );
SAFEPROC( s, cyg_uint16, 2, get_splus );
TRAPPROC( s, cyg_uint16, 3, get_splus );
SAFEPROC( s, cyg_uint16, 4, get_splus );
}
 
CYG_TEST_PASS( "Mixture of accesses OK" );
}
}
 
// -------------------------------------------------------------------------
 
externC void
skip_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer);
 
externC void
fail_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer);
 
// -------------------------------------------------------------------------
 
void sparc_ex_main( void )
{
int i;
 
CYG_TEST_INIT();
 
for ( i = CYGNUM_HAL_EXCEPTION_MIN; i <= CYGNUM_HAL_EXCEPTION_MAX; i++ ){
int j;
HAL_TRANSLATE_VECTOR( i, j );
HAL_INTERRUPT_ATTACH( j, &fail_exception_handler, j, 0 );
// we must also ensure that eCos handles the exception;
// do not drop into CygMon or equivalent.
// Leave USER_TRAP undisturbed so that breakpoints work.
if ( CYGNUM_HAL_VECTOR_USER_TRAP != i ) {
extern void hal_default_exception_vsr( void );
HAL_VSR_SET( i, (CYG_ADDRESS)hal_default_exception_vsr, NULL );
}
}
 
HAL_TRANSLATE_VECTOR( CYGNUM_HAL_VECTOR_UNALIGNED, i );
HAL_INTERRUPT_DETACH( i, &fail_exception_handler );
HAL_INTERRUPT_ATTACH( i, &skip_exception_handler, i, 0 );
 
CYG_TEST_INFO( "Vectors attached OK; calling do_test" );
 
do_test();
 
CYG_TEST_EXIT( "Done" );
}
 
// -------------------------------------------------------------------------
externC void
skip_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer)
{
HAL_SavedRegisters *save;
HAL_FrameStructure *frame;
 
HAL_FLUSH_REGISTERS_TO_STACK();
 
save = (HAL_SavedRegisters *) stackpointer;
frame = (HAL_FrameStructure *) (save + 1); // immediately after
 
// now, this is the invokation environment when this saved regset
// was created (copied from hal_xvsr.S):
// ! here,locals have been set up as follows:
// ! %l0 = psr (with this CWP/window-level in it)
// ! %l1 = pc
// ! %l2 = npc
// ! %l3 = vector number (16-25 for traps)
// ! and we are in our own register window, though it is likely that
// ! the next one will need to be saved before we can use it:
// ! ie. this one is the invalid register window.
// and the intention is that we can mess therewith:
 
// Check we're not in a trap loop
if ( trap == save->li.l[1] ) {
same++;
if ( 10 < same )
CYG_TEST_FAIL_EXIT( "Repeated trap" );
}
else // restart the count
same = 0;
 
// and record it
trap = save->li.l[1];
tcount++;
 
// now step on so that we return to the instruction after:
save->li.l[1] = save->li.l[2]; // PC := NPC
save->li.l[2] += 4; // NPC += 4
 
// that's all.
}
 
externC void
fail_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer)
{
HAL_FLUSH_REGISTERS_TO_STACK();
CYG_TEST_FAIL_EXIT( "Other exception handler called" );
}
 
// -------------------------------------------------------------------------
 
externC void
#ifdef CYGPKG_KERNEL
cyg_user_start( void )
#else
cyg_start( void )
#endif
{
sparc_ex_main();
}
 
// -------------------------------------------------------------------------
 
cyg_uint64 get_ll( cyg_uint64 *p )
{
return *p;
}
 
cyg_uint64 get_llplus( cyg_uint64 *p )
{
cyg_uint64 ll = 0l, v;
ll = (cyg_uint32)p;
ll++;
v = *p;
v^= ll;
return v;
}
 
cyg_uint32 get_i( cyg_uint32 *p )
{
return *p;
}
 
cyg_uint32 get_iplus( cyg_uint32 *p )
{
cyg_uint32 i = 0, v;
i = (cyg_uint32)p;
i++;
v = *p;
v^= i;
return v;
}
 
cyg_uint16 get_s( cyg_uint16 *p )
{
return *p;
}
 
cyg_uint16 get_splus( cyg_uint16 *p )
{
cyg_uint16 s = 0, v;
s = (cyg_uint16)(0xffff & (cyg_uint32)p);
s++;
v = *p;
v^= s;
return v;
}
 
// -------------------------------------------------------------------------
 
/* EOF sparc_ex.c */
/arch/v2_0/include/hal_io.h
0,0 → 1,183
#ifndef CYGONCE_HAL_IO_H
#define CYGONCE_HAL_IO_H
 
//=============================================================================
//
// hal_io.h
//
// HAL device IO register support.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, hmt
// Contributors: nickg, hmt
// Date: 1998-02-17
// Purpose: Define IO register support
// Description: The macros defined here provide the HAL APIs for handling
// device IO control registers.
//
// Usage:
// #include <cyg/hal/hal_io.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/system.h>
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// Enforce in-order IO for all HAL reads/writes using this macro.
#define HAL_IO_BARRIER() \
asm volatile ( "" : : : "memory" )
 
//-----------------------------------------------------------------------------
// IO Register address.
// This type is for recording the address of an IO register.
 
typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
 
//-----------------------------------------------------------------------------
// BYTE Register access.
// Individual and vectorized access to 8 bit registers.
 
#define HAL_READ_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_BYTE *)(_register_))); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
 
 
//-----------------------------------------------------------------------------
// 16 bit access.
// Individual and vectorized access to 16 bit registers.
#define HAL_READ_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD16 *)(_register_))); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD16 *)(_register_)) = (_value_)); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
 
//-----------------------------------------------------------------------------
// 32 bit access.
// Individual and vectorized access to 32 bit registers.
#define HAL_READ_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
((_value_) = *((volatile CYG_WORD32 *)(_register_))); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32( _register_, _value_ ) \
CYG_MACRO_START \
(*((volatile CYG_WORD32 *)(_register_)) = (_value_)); \
HAL_IO_BARRIER (); \
CYG_MACRO_END
 
#define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
(_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
 
#define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
CYG_MACRO_START \
cyg_count32 _i_,_j_; \
for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) { \
((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
HAL_IO_BARRIER (); \
} \
CYG_MACRO_END
//-----------------------------------------------------------------------------
 
#endif // ifndef CYGONCE_HAL_IO_H
// End of hal_io.h
/arch/v2_0/include/basetype.h
0,0 → 1,74
#ifndef CYGONCE_HAL_BASETYPE_H
#define CYGONCE_HAL_BASETYPE_H
 
//=============================================================================
//
// basetype.h
//
// Standard types for this architecture.
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1998-12-10
// Purpose: Define architecture base types.
// Usage: Included by "cyg_type.h", do not use directly
 
//
//####DESCRIPTIONEND####
//
 
//-----------------------------------------------------------------------------
// Characterize the architecture
 
#define CYG_BYTEORDER CYG_MSBFIRST // Big endian
 
//-----------------------------------------------------------------------------
// SPARC does not usually use labels with underscores.
 
//#define CYG_LABEL_NAME(_name_) _name_
 
//-----------------------------------------------------------------------------
// Define the standard variable sizes
 
// The SPARC architecture uses the default definitions of the base
// types, so we do not need to define any here.
 
//-----------------------------------------------------------------------------
#endif // CYGONCE_HAL_BASETYPE_H
// End of basetype.h
/arch/v2_0/include/hal_intr.h
0,0 → 1,407
#ifndef CYGONCE_HAL_INTR_H
#define CYGONCE_HAL_INTR_H
 
//===========================================================================
//
// hal_intr.h
//
// HAL Interrupt and clock support
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt,
// jlarmour
// Date: 1999-02-20, 2002-03-08
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// interrupts and the clock.
//
// Usage:
// #include <cyg/hal/hal_intr.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//===========================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_sparc.h>
 
#include <cyg/infra/cyg_type.h>
 
//---------------------------------------------------------------------------
// SPARC exception vectors.
//
// A note on nomenclature:
//
// SPARC has traps: interrupts are traps, and so are exceptions.
// There are 255 of them in the hardware: this HAL's trampoline code decodes
// them into the 27 listed below as CYGNUM_HAL_VECTOR_xxx.
// They are handled uniformly in the trampoline code in the sense that
// each vector has a VSR which is called in the same way.
// Interrupts (vectors 1-15) have one VSR by default, exceptions (vectors
// 16-26) another.
// The interrupt VSR sets up a C stack and calls the corresponding ISR with
// the required arguments; this ABI is mandated by the kernel.
// The exception VSR sets up a C stack and calls the corresponding XSR
// (just an entry in the ISR[sic] table) with similar arguments, such that
// it (by default) can call the kernel's cyg_hal_deliver_exception().
//
// So:
// CYGNUM_HAL_VSR_MAX/MIN/COUNT describe the number of VSR entries *and*
// the number of ISR (and associated data) entries (including those which
// are XSRs, just a special case of ISRs).
// CYGNUM_HAL_ISR_MAX/MIN/COUNT describe the number of interrupt sources
// and is used for bounds checking in kernel interrupt objects.
// CYGNUM_HAL_EXCEPTION_MAX/MIN/COUNT describe vector numbers which have
// by default the exception VSR and default XSR installed.
 
 
// These correspond to VSRs and the values are the ones to use for
// HAL_VSR_GET/SET
 
#define CYGNUM_HAL_VECTOR_RESERVED_0 0
#define CYGNUM_HAL_VECTOR_INTERRUPT_1 1 // NB: least important
#define CYGNUM_HAL_VECTOR_INTERRUPT_2 2 // (lowest priority)
#define CYGNUM_HAL_VECTOR_INTERRUPT_3 3
#define CYGNUM_HAL_VECTOR_INTERRUPT_4 4
#define CYGNUM_HAL_VECTOR_INTERRUPT_5 5
#define CYGNUM_HAL_VECTOR_INTERRUPT_6 6
#define CYGNUM_HAL_VECTOR_INTERRUPT_7 7
#define CYGNUM_HAL_VECTOR_INTERRUPT_8 8
#define CYGNUM_HAL_VECTOR_INTERRUPT_9 9
#define CYGNUM_HAL_VECTOR_INTERRUPT_10 10
#define CYGNUM_HAL_VECTOR_INTERRUPT_11 11
#define CYGNUM_HAL_VECTOR_INTERRUPT_12 12
#define CYGNUM_HAL_VECTOR_INTERRUPT_13 13
#define CYGNUM_HAL_VECTOR_INTERRUPT_14 14 // (highest priority)
#define CYGNUM_HAL_VECTOR_INTERRUPT_15 15 // NB: most important (NMI)
 
#define CYG_VECTOR_IS_INTERRUPT(v) (15 >= (v))
 
#define CYGNUM_HAL_VECTOR_USER_TRAP 16 // Ticc instructions
#define CYGNUM_HAL_VECTOR_FETCH_ABORT 17 // trap type 1
#define CYGNUM_HAL_VECTOR_ILLEGAL_OP 18 // trap type 2
#define CYGNUM_HAL_VECTOR_PRIV_OP 19 // tt 3: privileged op
#define CYGNUM_HAL_VECTOR_NOFPCP 20 // tt 4,36: FP or coproc
#define CYGNUM_HAL_VECTOR_RESERVED_1 21 // (not used)
#define CYGNUM_HAL_VECTOR_RESERVED_2 22 // (not used)
#define CYGNUM_HAL_VECTOR_UNALIGNED 23 // tt 7: unaligned memory access
#define CYGNUM_HAL_VECTOR_TT_EIGHT 24 // tt 8: not defined
#define CYGNUM_HAL_VECTOR_DATA_ABORT 25 // tt 9: read/write failed
#define CYGNUM_HAL_VECTOR_OTHERS 26 // any others
 
#define CYGNUM_HAL_VSR_MIN 0
#define CYGNUM_HAL_VSR_MAX 26
#define CYGNUM_HAL_VSR_COUNT 27
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
// Interrupt vectors. These are the values used with HAL_INTERRUPT_ATTACH()
// et al
 
#define CYGNUM_HAL_INTERRUPT_RESERVED_0 CYGNUM_HAL_VECTOR_RESERVED_0
#define CYGNUM_HAL_INTERRUPT_1 CYGNUM_HAL_VECTOR_INTERRUPT_1
#define CYGNUM_HAL_INTERRUPT_2 CYGNUM_HAL_VECTOR_INTERRUPT_2
#define CYGNUM_HAL_INTERRUPT_3 CYGNUM_HAL_VECTOR_INTERRUPT_3
#define CYGNUM_HAL_INTERRUPT_4 CYGNUM_HAL_VECTOR_INTERRUPT_4
#define CYGNUM_HAL_INTERRUPT_5 CYGNUM_HAL_VECTOR_INTERRUPT_5
#define CYGNUM_HAL_INTERRUPT_6 CYGNUM_HAL_VECTOR_INTERRUPT_6
#define CYGNUM_HAL_INTERRUPT_7 CYGNUM_HAL_VECTOR_INTERRUPT_7
#define CYGNUM_HAL_INTERRUPT_8 CYGNUM_HAL_VECTOR_INTERRUPT_8
#define CYGNUM_HAL_INTERRUPT_9 CYGNUM_HAL_VECTOR_INTERRUPT_9
#define CYGNUM_HAL_INTERRUPT_10 CYGNUM_HAL_VECTOR_INTERRUPT_10
#define CYGNUM_HAL_INTERRUPT_11 CYGNUM_HAL_VECTOR_INTERRUPT_11
#define CYGNUM_HAL_INTERRUPT_12 CYGNUM_HAL_VECTOR_INTERRUPT_12
#define CYGNUM_HAL_INTERRUPT_13 CYGNUM_HAL_VECTOR_INTERRUPT_13
#define CYGNUM_HAL_INTERRUPT_14 CYGNUM_HAL_VECTOR_INTERRUPT_14
#define CYGNUM_HAL_INTERRUPT_15 CYGNUM_HAL_VECTOR_INTERRUPT_15
 
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 15
#define CYGNUM_HAL_ISR_COUNT 16
 
// - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 
// Exception vectors. These are the values used when passed out to an
// external exception handler using cyg_hal_deliver_exception()
// They can also be used with HAL_INTERRUPT_ATTACH() et al to install
// different XSRs.
 
#define CYGNUM_HAL_EXCEPTION_TRAP CYGNUM_HAL_VECTOR_USER_TRAP
#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_FETCH_ABORT
#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
CYGNUM_HAL_VECTOR_ILLEGAL_OP
#define CYGNUM_HAL_EXCEPTION_PRIVILEGED_INSTRUCTION \
CYGNUM_HAL_VECTOR_PRIV_OP
#define CYGNUM_HAL_EXCEPTION_FPU_NOT_AVAIL CYGNUM_HAL_VECTOR_NOFPCP
#define CYGNUM_HAL_EXCEPTION_RESERVED1 CYGNUM_HAL_VECTOR_RESERVED1
#define CYGNUM_HAL_EXCEPTION_RESERVED2 CYGNUM_HAL_VECTOR_RESERVED2
#define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
CYGNUM_HAL_VECTOR_UNALIGNED
#define CYGNUM_HAL_EXCEPTION_TT_EIGHT CYGNUM_HAL_VECTOR_TT_EIGHT
#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_DATA_ABORT
#define CYGNUM_HAL_EXCEPTION_OTHERS CYGNUM_HAL_VECTOR_OTHERS
 
 
#define CYGNUM_HAL_EXCEPTION_MIN 16
#define CYGNUM_HAL_EXCEPTION_MAX (16 + 10)
#define CYGNUM_HAL_EXCEPTION_COUNT (1 + CYGNUM_HAL_EXCEPTION_MAX - \
CYGNUM_HAL_EXCEPTION_MIN)
 
//---------------------------------------------------------------------------
// (Null) Translation from a wider space of interrupt sources:
 
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) _index_ = (_vector_)
 
//---------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
hal_interrupt_stack_call_pending_DSRs()
 
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif
 
//---------------------------------------------------------------------------
// Static data used by HAL
 
// VSR table
externC volatile CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
 
// ISR + XSR tables - so VSR count.
externC volatile CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_VSR_COUNT];
externC volatile CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_VSR_COUNT];
externC volatile CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_VSR_COUNT];
// (interrupt_objects only used in the interrupt case _but_ the interrupt
// attach &co macros write it, so keep it full-sized)
 
//---------------------------------------------------------------------------
// Default ISRs for exception/interrupt handing.
 
// note that these have the same ABI apart from the extra SP parameter
// for exceptions.
 
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
// return code from ISR is passed to interrupt_end() in the kernel.
 
externC void cyg_hal_exception_handler(CYG_ADDRWORD vector,
CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer);
 
//---------------------------------------------------------------------------
// Default VSRs for exception/interrupt handing.
 
// note that these do not have a C ABI as such; they are *vector* service
// routines and are written in assembler.
 
externC void hal_default_exception_vsr( void );
externC void hal_default_interrupt_vsr( void );
 
//---------------------------------------------------------------------------
// Interrupt state storage
 
typedef cyg_uint32 CYG_INTERRUPT_STATE;
 
//---------------------------------------------------------------------------
// Interrupt control macros
 
// THIS ONE IS NOT A STANDARD HAL ENTRY (HAL_DISABLE_TRAPS)
// (so should be unused externally)
#define HAL_DISABLE_TRAPS(_old_) \
asm volatile ( \
"rd %%psr, %0;" \
"andn %0, 0x20, %%l7;" \
"wr %%l7, %%psr;" \
"nop; nop; nop" \
: "=r"(_old_) \
: \
: "l7" \
);
 
// THIS ONE IS NOT A STANDARD HAL ENTRY (HAL_QUERY_TRAPS)
// (so should be unused externally)
#define HAL_QUERY_TRAPS(_old_) \
asm volatile ( \
"rd %%psr, %%l7;" \
"and %%l7, 0x020, %0" \
: "=r"(_old_) \
: \
: "l7" \
);
 
#define HAL_DISABLE_INTERRUPTS(_old_) \
asm volatile ( \
"rd %%psr, %0;" \
"or %0, 0xf00, %%l7;" \
"wr %%l7, %%psr;" \
"nop; nop; nop" \
: "=r"(_old_) \
: \
: "l7" \
);
 
#define HAL_ENABLE_INTERRUPTS() \
asm volatile ( \
"rd %%psr, %%l7;" \
"andn %%l7, 0xf00, %%l7;" \
"or %%l7, 0x020, %%l7;" \
"wr %%l7, %%psr;" \
"nop; nop; nop" \
: \
: \
: "l7" \
);
 
#define HAL_RESTORE_INTERRUPTS(_old_) \
asm volatile ( \
"rd %%psr, %%l7;" \
"andn %%l7, 0xf20, %%l7;" \
"and %0 , 0xf20, %%l6;" \
"wr %%l6, %%l7, %%psr;" \
"nop; nop; nop" \
: \
: "r"(_old_) \
: "l6","l7" \
);
 
#define HAL_QUERY_INTERRUPTS(_old_) \
asm volatile ( \
"rd %%psr, %%l7;" \
"and %%l7, 0xf00, %%l7;" \
"xor %%l7, 0xf00, %0" \
: "=r"(_old_) \
: \
: "l7" \
);
 
 
//---------------------------------------------------------------------------
// Interrupt and VSR attachment macros
 
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if( (CYG_ADDRESS)hal_default_isr == hal_interrupt_handlers[_vector_] || \
(CYG_ADDRESS)cyg_hal_exception_handler == \
hal_interrupt_handlers[_vector_] ) { \
(_state_) = 0; \
} else { \
(_state_) = 1; \
} \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
CYG_MACRO_START \
if( (CYG_ADDRESS)hal_default_isr == hal_interrupt_handlers[_vector_] ||\
(CYG_ADDRESS)cyg_hal_exception_handler == \
hal_interrupt_handlers[_vector_] ) \
{ \
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
} \
CYG_MACRO_END
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) CYG_MACRO_START \
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
{ \
hal_interrupt_handlers[_vector_] = \
(CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
? (CYG_ADDRESS)hal_default_isr \
: (CYG_ADDRESS)cyg_hal_exception_handler); \
hal_interrupt_data[_vector_] = 0; \
hal_interrupt_objects[_vector_] = 0; \
} \
CYG_MACRO_END
 
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
 
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
if( _poldvsr_ != NULL ) \
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
CYG_MACRO_END
 
// This is an ugly name, but what it means is: grab the VSR back to eCos
// internal handling, or if you like, the default handler. But if
// cooperating with GDB and CygMon, the default behaviour is to pass most
// exceptions to CygMon. This macro undoes that so that eCos handles the
// exception. So use it with care.
 
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
if( _poldvsr_ != NULL ) \
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = ( CYG_VECTOR_IS_INTERRUPT( _vector_ ) \
? (CYG_ADDRESS)hal_default_interrupt_vsr \
: (CYG_ADDRESS)hal_default_exception_vsr ); \
CYG_MACRO_END
 
 
 
//---------------------------------------------------------------------------
 
// Which PIC (if any) is available is dependent on the board.
// This sets up that stuff:
 
#include <cyg/hal/hal_xpic.h>
 
// Ditto the clock(s)
// This defines all the clock macros the kernel requires:
 
#include <cyg/hal/hal_clock.h>
 
//---------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_INTR_H
// End of hal_intr.h
/arch/v2_0/include/hal_arch.h
0,0 → 1,371
#ifndef CYGONCE_HAL_ARCH_H
#define CYGONCE_HAL_ARCH_H
 
//==========================================================================
//
// hal_arch.h
//
// Architecture specific abstractions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-02-20
// Purpose: Define architecture abstractions
// Usage: #include <cyg/hal/hal_arch.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_sparc.h>
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/hal_intr.h> // HAL_DISABLE_INTERRUPTS
 
//--------------------------------------------------------------------------
// Processor saved states:
//
// All these structures must be doubleword (64 bit) aligned.
// The code that creates them on the stack will ensure this is so.
 
#define HAL_THREAD_CONTEXT_GLOBAL_BASE 0
#define HAL_THREAD_CONTEXT_OUT_BASE 8
#define HAL_THREAD_CONTEXT_LOCAL_BASE 16
#define HAL_THREAD_CONTEXT_IN_BASE 24
 
typedef struct
{
// this is the save structure found at *(stack_ptr) always, note that
// i[6] is the frame pointer is the previous stack pointer, and
// o[6] is the stack pointer is the next frame pointer,
// so they form a linked list back up the call stack.
cyg_uint32 l[8]; /* Locals r16-r23 */
cyg_uint32 i[8]; /* Ins r24-r31 */
} HAL_SavedWindow;
 
typedef struct
{
// Window save at stack pointer
HAL_SavedWindow li;
//16
// This is the rest of the save state:
// NOTE: g[0] is used for the CWP, for %g0 == 0. Also note that the
// assembler routines must load/store it in the right order.
cyg_uint32 g[8] ; /* Globals r0- r7 */
cyg_uint32 o[8] ; /* Outs r8-r15 */
//32 words in size
 
// There is no need to save any other state; for example, condition codes,
// the PC and NextPC, and Y, are preserved in local registers in the trap
// handling window and so preserved in the caller stack frame as viewed
// from an ISR. Note that the VSR is jumped to with those locals being set
// up (and Y in situ), and it must preserve them itself before calling any
// subsequent handlers (ISRs).
 
} HAL_SavedRegisters;
 
 
typedef struct
{
// Window save at stack pointer
HAL_SavedWindow li;
cyg_uint32 composite_return_ptr; /* structure returns */
cyg_uint32 spill_args[6]; /* for callee to store */
cyg_uint32 spare; /* keep this 64-bits */
} HAL_FrameStructure;
 
 
//--------------------------------------------------------------------------
// Exception handling function.
// This function is defined by the kernel according to this prototype. It is
// invoked from the HAL to deal with any CPU exceptions that the HAL does
// not want to deal with itself. It usually invokes the kernel's exception
// delivery mechanism.
 
externC void cyg_hal_deliver_exception( CYG_WORD code, CYG_ADDRWORD data );
 
//--------------------------------------------------------------------------
// Bit manipulation macros
#ifndef CYGPKG_HAL_SPARC_SCAN
/* Most sparc's does not have 'scan' instruction */
externC cyg_uint32 hal_lsbit_index(cyg_uint32 mask);
externC cyg_uint32 hal_msbit_index(cyg_uint32 mask);
#define HAL_LSBIT_INDEX(index, mask) index = hal_lsbit_index(mask);
#define HAL_MSBIT_INDEX(index, mask) index = hal_msbit_index(mask);
#else
#define HAL_LSBIT_INDEX(index, mask) \
CYG_MACRO_START \
asm volatile ( \
"scan %1, 0, %%l7;" \
"mov 31, %0;" \
"sub %0, %%l7, %0" \
: "=r"(index) \
: "r"(mask & ~(mask-1)) \
: "l7" \
); \
CYG_MACRO_END
 
#define HAL_MSBIT_INDEX(index, mask) \
CYG_MACRO_START \
asm volatile ( \
"scan %1, 0, %%l7;" \
"mov 31, %0;" \
"sub %0, %%l7, %0" \
: "=r"(index) \
: "r"(mask) \
: "l7" \
); \
CYG_MACRO_END
#endif
 
//--------------------------------------------------------------------------
// Context Initialization
// Initialize the context of a thread.
// Arguments:
// _sparg_ name of variable containing current sp, will be written with new sp
// _thread_ thread object address, passed as argument to entry point
// _entry_ entry point address.
// _id_ bit pattern used in initializing registers, for debugging.
 
externC CYG_ADDRESS
hal_thread_init_context( CYG_WORD sparg,
CYG_WORD thread,
CYG_WORD entry,
CYG_WORD id );
 
#define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
CYG_MACRO_START \
_sparg_ = hal_thread_init_context( (CYG_WORD)(_sparg_), \
(CYG_WORD)(_thread_), \
(CYG_WORD)(_entry_), \
(CYG_WORD)(_id_) ); \
CYG_MACRO_END
 
//---------------------------------------------------------------------------
// Context switch macros.
// The arguments are pointers to locations where the stack pointer
// of the current thread is to be stored, and from where the sp of the
// next thread is to be fetched.
 
externC void hal_thread_switch_context( CYG_ADDRESS to, CYG_ADDRESS from );
externC void hal_thread_load_context( CYG_ADDRESS to )
__attribute__ ((noreturn));
 
#define HAL_THREAD_SWITCH_CONTEXT(_fspptr_,_tspptr_) \
hal_thread_switch_context((CYG_ADDRESS)_tspptr_, \
(CYG_ADDRESS)_fspptr_);
 
#define HAL_THREAD_LOAD_CONTEXT(_tspptr_) \
hal_thread_load_context( (CYG_ADDRESS)_tspptr_ );
 
 
//---------------------------------------------------------------------------
// Execution reorder barrier.
// When optimizing the compiler can reorder code. In multithreaded systems
// where the order of actions is vital, this can sometimes cause problems.
// This macro may be inserted into places where reordering should not happen.
 
#define HAL_REORDER_BARRIER() asm volatile ( "" : : : "memory" )
 
//---------------------------------------------------------------------------
// Breakpoint support
// HAL_BREAKPOINT() is a code sequence that will cause a breakpoint to happen
// if executed.
// HAL_BREAKINST is the value of the breakpoint instruction and
// HAL_BREAKINST_SIZE is its size in bytes.
 
#define HAL_BREAKPOINT(_label_) \
asm volatile (" .globl " #_label_ ";" \
#_label_":" \
"ta 1" \
);
 
#define HAL_BREAKINST {0x91,0xd0,0x20,0x01}
#define HAL_BREAKINST_SIZE 4
 
//---------------------------------------------------------------------------
// Thread register state manipulation for GDB support.
 
// Translate a stack pointer as saved by the thread context macros above into
// a pointer to a HAL_SavedRegisters structure.
#define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
(_regs_) = (HAL_SavedRegisters *)(_sp_)
 
// Routines in icontext.c used here because they're quite large for
// the SPARC (note param order):
externC void
cyg_hal_sparc_get_gdb_regs( void *gdb_regset,
HAL_SavedRegisters *eCos_regset );
 
externC void
cyg_hal_sparc_set_gdb_regs( HAL_SavedRegisters *eCos_regset,
void *gdb_regset );
 
 
// Copy a set of registers from a HAL_SavedRegisters structure into a GDB
// ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
CYG_MACRO_START \
cyg_hal_sparc_get_gdb_regs( (_aregval_), (_regs_) ); \
CYG_MACRO_END
 
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
CYG_MACRO_START \
cyg_hal_sparc_set_gdb_regs( (_regs_), (_aregval_) ); \
CYG_MACRO_END
 
//---------------------------------------------------------------------------
// HAL setjmp
 
#define CYGARC_JMP_BUF_SIZE 32 // (words)
 
// this too must be doubleword aligned (64 bit)
 
typedef cyg_uint64 hal_jmp_buf[ CYGARC_JMP_BUF_SIZE / 2 ];
 
externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);
 
//---------------------------------------------------------------------------
// Flush Register Windows
//
// This is implemented as trap 3 in some SPARC systems.
// This macro is only for use from normal, foreground code.
// (including exception handlers and the like)
 
#define HAL_FLUSH_REGISTERS_TO_STACK() \
CYG_MACRO_START \
cyg_uint32 _saveintr_; \
HAL_DISABLE_INTERRUPTS( _saveintr_ ); /* leave traps on */ \
asm volatile ( \
/* force out all our callers register sets onto the stack */ \
/* if necessary: the system will handily take care of this for */ \
/* us as follows: */ \
"save %%sp, -16 * 4, %%sp;" /* need all these to preserve */ \
"save %%sp, -16 * 4, %%sp;" /* the linked list property... */ \
"save %%sp, -16 * 4, %%sp;" \
"save %%sp, -16 * 4, %%sp;" \
"save %%sp, -16 * 4, %%sp;" \
"save %%sp, -16 * 4, %%sp;" \
"restore;" \
"restore;" \
"restore;" \
"restore;" \
"restore;" \
"restore" \
/* six of these is correct; a seventh would force out the */ \
/* current set that we are using right now. Note that minimal */ \
/* space is allowed on stack for locals and ins in case this */ \
/* sequence itself gets interrupted and recurses too deep. */ \
: \
: \
: "memory" \
); \
HAL_RESTORE_INTERRUPTS( _saveintr_ ); \
CYG_MACRO_END
 
//---------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
 
externC void hal_idle_thread_action(cyg_uint32 loop_count);
 
#ifndef HAL_IDLE_THREAD_ACTION
#define HAL_IDLE_THREAD_ACTION(_count_) \
/* Cyg_Clock::real_time_clock->tick() */
#endif
 
//---------------------------------------------------------------------------
 
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
 
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
 
// We define quite large stack needs for SPARC, for it requires 576
// bytes (144 words) to process an interrupt and thread-switch, and
// momentarily, but needed in case of recursive interrupts, it needs 208
// words - if a sequence of saves to push out other regsets is interrupted.
 
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
 
// A minimal, optimized stack frame is 24 words, but even -O2 code seems to
// place a few locals in the locals area: round this up to provide a
// sensible overestimate:
#define CYGNUM_HAL_STACK_FRAME_SIZE (4 * 32)
 
// Stack needed for a context switch: this is implicit in the estimate for
// interrupts so not explicitly used below:
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (4 * 32)
 
// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE \
((208 * 4) + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
// And we have lots of registers so no particular amount is added in for
// typical local variable usage.
 
// Typically we have 4 nestable interrupt sources, clock, serialin,
// serialout, (and NMI button, but you want it to not destroy context):
 
#define CYGNUM_HAL_STACK_SIZE_MINIMUM \
(4 * CYGNUM_HAL_STACK_INTERRUPT_SIZE + 2 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
#define CYGNUM_HAL_STACK_SIZE_TYPICAL \
(CYGNUM_HAL_STACK_SIZE_MINIMUM + 8 * CYGNUM_HAL_STACK_FRAME_SIZE)
 
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()
 
//-----------------------------------------------------------------------------
 
#endif // CYGONCE_HAL_ARCH_H
// End of hal_arch.h
/arch/v2_0/include/vectors.h
0,0 → 1,118
#ifndef CYGONCE_HAL_VECTORS_H
#define CYGONCE_HAL_VECTORS_H
 
//=============================================================================
//
// vectors.h
//
// SPARC Architecture specific vector numbers &c
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors:hmt
// Date: 1998-12-10
// Purpose: Define architecture abstractions and some shared info;
// this file is included by assembler files as well as C/C++.
// Usage: #include <cyg/hal/vectors.h>
 
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#define __WINSIZE 8
 
#if __WINSIZE <= 8
# define __WINBITS 7
#else
# error __WINSIZE window size probably not supported
#endif
 
// These should be generic to all SPARCs:
 
#define __WINBITS_MAXIMAL 0x1f
 
#define __WIN_INIT (__WINSIZE - 1)
#define __WIM_INIT (1 << __WIN_INIT)
 
// ------------------------------------------------------------------------
 
#define TRAP_WUNDER 6 // Window Underflow trap number
#define TRAP_WOVER 5 // Window Overflow trap number
 
#define TRAP_INTR_MIN 17 // smallest interrupt trap number
#define TRAP_INTR_MAX 31 // largest interrupt trap number
 
#define TT_MASK 0xff0 // trap type mask from tbr
#define TT_SHL 4 // shift to get a tbr value
 
// Alternatively, detect an interrupt by testing tbr for being in the range
// 16-31 by masking &c:
#define TT_IS_INTR_MASK 0xf00
#define TT_IS_INTR_VALUE 0x100
 
#if TT_IS_INTR_VALUE != ((TRAP_INTR_MIN << TT_SHL) & TT_IS_INTR_MASK)
#error "Bad *_INTR_* symbol definition (1)"
#endif
 
#if TT_IS_INTR_VALUE != ((TRAP_INTR_MAX << TT_SHL) & TT_IS_INTR_MASK)
#error "Bad *_INTR_* symbol definition (2)"
#endif
 
#if TT_IS_INTR_VALUE != (((TRAP_INTR_MIN+1) << TT_SHL) & TT_IS_INTR_MASK)
#error "Bad *_INTR_* symbol definition (3)"
#endif
 
#if TT_IS_INTR_VALUE != (((TRAP_INTR_MAX-1) << TT_SHL) & TT_IS_INTR_MASK)
#error "Bad *_INTR_* symbol definition (4)"
#endif
 
 
//#define SCHED_LOCK_MANGLED_NAME _18Cyg_Scheduler_Base.sched_lock
#define SCHED_LOCK_MANGLED_NAME cyg_scheduler_sched_lock
 
 
 
#define SAVE_REGS_SIZE (4 * 32) // 32 words of 4 bytes each
 
 
 
 
#endif // CYGONCE_HAL_VECTORS_H
// EOF vectors.h
/arch/v2_0/ChangeLog
0,0 → 1,69
2003-04-10 Nick Garnett <nickg@balti.calivar.com>
 
* src/sparc.ld:
Added libsupc++.a to GROUP() directive for GCC versions later than
3.0.
 
2002-10-19 Jonathan Larmour <jifl@eCosCentric.com>
 
Patch from Jiri Gaisler:
* src/context.S (hal_thread_load_context): Wait a little after writing
psr.
(hal_setjmp): Ditto.
* src/vectors.S (genuine_reset): Reorder window setup writes to
streamline.
 
2002-04-29 Jonathan Larmour <jlarmour@redhat.com>
 
* src/vectors.S:
* src/vec_xvsr.S:
* src/vec_ivsr.S:
Don't use .file as it can confuse debugging since the .file
doesn't contain the path and therefore the debugger will never
know where it lives! This conflicts with using -Wa,--gstabs.
 
2002-03-18 Hugo Tyson <hmt@redhat.com>
 
* src/vectors.S: Add CYGPKG_HAL_SPARC_ERC32 to list of ifdefs.
 
2002-03-14 Jiri Gaisler <jiri@gaisler.com>
 
* Initial version based on the SPARClite HAL.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
//EOF ChangeLog
/arch/v2_0/src/vec_xvsr.S
0,0 → 1,297
/*===========================================================================
//
// vec_xvsr.S
//
// SPARC vectors: exception vector service routine
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-20
// Purpose: SPARC vector code
// Description: see vectors.S; this is the default vector service routine
// for exceptions.
//
//####DESCRIPTIONEND####
//
//=========================================================================*/
 
!-----------------------------------------------------------------------------
 
// .file "vec_xvsr.S"
 
!----------------------------------------------------------------------------
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#endif
 
!------------------------------------------------------------------------
 
#include <cyg/hal/vectors.h>
 
#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM
 
!------------------------------------------------------------------------
 
.text
 
!---------------------------------------------------------------------------
! default exception handler VSR, which calls the appropriate ISR after
! interrupt masking - much the same as the interrupt VSR but does not lock
! scheduler or call interrupt_end().
 
.global hal_default_exception_vsr
hal_default_exception_vsr:
! here,locals have been set up as follows:
! %l0 = psr (with this CWP/window-level in it)
! %l1 = pc
! %l2 = npc
! %l3 = vector number (16-25 for traps)
! and we are in our own register window, though it is likely that
! the next one will need to be saved before we can use it:
! ie. this one is the invalid register window.
 
! must establish a safe stack before re-enabling interrupts + traps
and %l0, __WINBITS, %l7 ! CWP extracted
! no inc/dec here, so no need for special measures for not-8-windows
mov 1, %l6
sll %l6, %l7, %l6 ! 1 << CWP
rd %wim, %l5
cmp %l5, %l6 ! are they the same?
bne 1f ! No, so the stack is OK as is.
 
! now do by hand an overflow trap, effectively
mov %g1, %l7 ! (DELAY SLOT)
srl %l5, 1, %l5
sll %l6, __WINSIZE-1, %l6
or %l6, %l5, %g1 ! new WIM in %g1 so we can get it
! within the save:
save ! Slip into next window
mov %g1, %wim ! Install the new wim
! (invalidates current window!)
#ifdef DELAYS_AFTER_WRWIM
nop
nop
nop
#endif
 
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
 
restore ! Go back to trap window.
mov %l7, %g1 ! Restore %g1
 
1: ! now save away the regs we must preserve
sub %fp, 32 * 4, %sp
! save a maximal context regardless: see also
! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
 
st %g1, [%sp + 17 * 4] ! save G registers
std %g2, [%sp + 18 * 4]
std %g4, [%sp + 20 * 4]
std %g6, [%sp + 22 * 4]
 
! no point whatsoever in saving O registers
 
! and save the CWP in %g0 save place
st %l0, [%sp + 16 * 4]
 
sub %sp, 24 * 4, %sp ! fresh frame including
! arg spill area for callees
 
! do not lock the scheduler
 
! HELP_GDB_WITH_BACKTRACE
mov %i7, %l5 ! preserve it JIC
mov %l1, %i7 ! bogus return link here
 
! and we must preserve the Y register (multiply/divide auxiliary)
! over these calls; we will keep it in %l4 which is otherwise unused.
rd %y, %l4
 
! Now we can reenable traps (preserving interrupt level)
or %l0, 0x0e0, %l7 ! set ET (+S,PS), preserve PIL
wr %l7, %psr ! and enable!
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
! now call the XSR and so on with the appropriate args:
! ie.
! isr_retcode = (*(hal_interrupt_handlers[ vector ]))
! ( vector, hal_interrupt_data[ vector ], stackp );
 
! from hal_arch.h
!// ISR tables
!CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
!CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
!CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
mov %l3, %o0
sll %l3, 2, %l3 ! %l3 to a word offset
sethi %hi(hal_interrupt_data), %l7
or %l7, %lo(hal_interrupt_data), %l7
ld [ %l7 + %l3 ], %o1 ! data
add %sp, 24 * 4, %o2 ! stackpointer of saved regset
 
sethi %hi(hal_interrupt_handlers), %l7
or %l7, %lo(hal_interrupt_handlers), %l7
ld [ %l7 + %l3 ], %l6
call %l6
nop
 
! do not call _interrupt_end()
 
! restore the Y register having done our callouts to C
wr %l4, %y
 
! We can reinstall the original CWP here; even if interrupt_end()
! performed a reschedule (ie. yield/resume pair) we will be in the
! same window. The window is preserved by reschedule precisely
! because it is impossible atomically to disable traps here without
! involving a CWP living in a register for a time when other
! interrupts may occur.
 
! disable traps (using the saved psr is fastest way)
wr %l0, %psr ! restores flags, disables traps, same PIL.
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
! HELP_GDB_WITH_BACKTRACE
mov %l5, %i7 ! restore (unused) return link
 
! and restore other saved regs
add %sp, 24 * 4, %sp ! undo fresh frame
! restore a maximal context regardless: see also
! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2 ! to support the handler
ldd [%sp + 4 * 4], %l4 ! having messed with them.
ldd [%sp + 6 * 4], %l6
 
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
 
ld [%sp + 17 * 4], %g1 ! and G registers
ldd [%sp + 18 * 4], %g2
ldd [%sp + 20 * 4], %g4
ldd [%sp + 22 * 4], %g6
! no point whatsoever in loading back O registers.
 
! Now test for window underflow here and fix up if needs be.
!
! Why? interrupt_end() might have yielded us, when only
! its own frame was restored; its own return to us caused a
! window underflow trap, as would our return to interruptee
! unless we deal with it now.
 
add %l0, 1, %l7 ! interruptee~s CWP plus noise
and %l7, __WINBITS, %l7 ! CWP only
#if 8 == __WINSIZE
! it is in range already
#else // expect 5 or 6 or 7 windows
cmp %l7, __WINSIZE
bge,a 567f ! taken: do delay slot, handle overflow
mov 0, %l7 ! only if .ge. above
567:
#endif
mov 1, %l6
sll %l6, %l7, %l6 ! 1 << CWP
rd %wim, %l5
cmp %l5, %l6 ! are they the same?
bne 2f ! No, so the stack is OK as is.
 
! now do by hand an underflow trap, effectively
sll %l5, 1, %l5 ! Rotate wim left
srl %l6, __WINSIZE-1, %l6
wr %l5, %l6, %wim
#ifdef DELAYS_AFTER_WRWIM
nop ! are these delays needed?
nop ! (following restore uses wim)
nop
#endif
restore ! Interruptee~s window
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2
ldd [%sp + 4 * 4], %l4
ldd [%sp + 6 * 4], %l6
 
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
save ! Back to trap window
 
2: ! restore the condition codes, PSR and PIL and return from trap.
wr %l0, %psr ! restores flags, disables traps, and old PIL
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
jmpl %l1, %g0
rett %l2
 
 
! end of vec_xvsr.S
/arch/v2_0/src/hal_intr.c
0,0 → 1,162
//==========================================================================
//
// hal_intr.c
//
// SPARC Architecture specific interrupt dispatch tables
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-20
// Purpose: Interrupt handler tables for SPARC.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_arch.h>
 
#include <cyg/infra/cyg_ass.h> // for CYG_FAIL() below
 
// ------------------------------------------------------------------------
// First level C default interrupt handler.
 
//static int count = 0;
 
cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
{
return 0; // 0x1def0000 + vector + (count += 0x0100);
}
 
// ------------------------------------------------------------------------
// First level C exception handler.
 
externC void __handle_exception (void);
 
externC HAL_SavedRegisters *_hal_registers;
 
void cyg_hal_exception_handler(CYG_ADDRWORD vector, CYG_ADDRWORD data,
CYG_ADDRWORD stackpointer )
{
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
// Set the pointer to the registers of the current exception
// context. At entry the GDB stub will expand the
// HAL_SavedRegisters structure into a (bigger) register array.
_hal_registers = (HAL_SavedRegisters *)stackpointer;
 
__handle_exception();
 
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
defined(CYGPKG_HAL_EXCEPTIONS)
// We should decode the vector and pass a more appropriate
// value as the second argument. For now we simply pass a
// pointer to the saved registers. We should also divert
// breakpoint and other debug vectors into the debug stubs.
 
cyg_hal_deliver_exception( vector, stackpointer );
 
#else
CYG_FAIL("Exception!!!");
#endif
return;
}
 
// ISR tables
volatile
CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_VSR_COUNT] = {
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
 
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
 
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
 
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr,
(CYG_ADDRESS)hal_default_isr, /* 16 of these */
 
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
 
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
(CYG_ADDRESS)cyg_hal_exception_handler,
 
(CYG_ADDRESS)cyg_hal_exception_handler, /* 11 of these */
};
 
volatile
CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_VSR_COUNT] = {
0x11da1a00, 0x11da1a01, 0x11da1a02, 0x11da1a03,
0x11da1a04, 0x11da1a05, 0x11da1a06, 0x11da1a07,
0x11da1a08, 0x11da1a09, 0x11da1a0a, 0x11da1a0b,
0x11da1a0c, 0x11da1a0d, 0x11da1a0e, 0x11da1a0f,
0xeeda1a00, 0xeeda1a01, 0xeeda1a02, 0xeeda1a03, 0xeeda1a04,
0xeeda1a05, 0xeeda1a06, 0xeeda1a07, 0xeeda1a08, 0xeeda1a09,
0xeeda1a0A
};
 
volatile
CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_VSR_COUNT] = {
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
 
0, 0, 0, 0, 0,
0, 0, 0, 0, 0,
0,
};
 
// EOF hal_intr.c
/arch/v2_0/src/vec_ivsr.S
0,0 → 1,443
/*===========================================================================
//
// vec_ivsr.S
//
// SPARC vectors: interrupt vector service routine
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-20
// Purpose: SPARC vector code
// Description: see vectors.S; this is the default vector service routine
// for interrupts.
//
//####DESCRIPTIONEND####
//
//=========================================================================*/
 
!----------------------------------------------------------------------------
 
// .file "vec_ivsr.S"
 
!----------------------------------------------------------------------------
 
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#else
# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
#endif
 
!------------------------------------------------------------------------
 
#include <cyg/hal/vectors.h>
 
#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM
 
! Macro to mark the stack as we descend, for debugging, because it is likely
! that actually running the ISR won~t touch the stack, but the memory needs
! to be there. Normally blank.
//#define MARKSTACKUSED st %sp, [ %sp ]
#define MARKSTACKUSED
 
!------------------------------------------------------------------------
 
.text
 
!---------------------------------------------------------------------------
! default interrupt VSR, which calls the appropriate ISR after scheduler
! lock and interrupt masking, then interrupt_end(). interrupt_end() must be
! called with interrupts enabled, on the original thread stack (no separate
! interrupt stack) or with interrupts masked, on the original stack (when
! separate interrupt stack is supported).
 
.global hal_default_interrupt_vsr
hal_default_interrupt_vsr:
! here,locals have been set up as follows:
! %l0 = psr (with this CWP/window-level in it)
! %l1 = pc
! %l2 = npc
! %l3 = vector number (1-15 for interrupts)
! and we are in our own register window, though it is likely that
! the next one will need to be saved before we can use it:
! ie. this one is the invalid register window.
 
! must establish a safe stack before re-enabling interrupts + traps
and %l0, __WINBITS, %l7 ! CWP extracted
! no inc/dec here, so no need for special measures for not-8-windows
mov 1, %l6
sll %l6, %l7, %l6 ! 1 << CWP
rd %wim, %l5
cmp %l5, %l6 ! are they the same?
bne 1f ! No, so the stack is OK as is.
 
! now do by hand an overflow trap, effectively
mov %g1, %l7 ! (DELAY SLOT)
srl %l5, 1, %l5
sll %l6, __WINSIZE-1, %l6
or %l6, %l5, %g1 ! new WIM in %g1 so we can get it
! within the save:
save ! Slip into next window
mov %g1, %wim ! Install the new wim
! (invalidates current window!)
#ifdef DELAYS_AFTER_WRWIM
nop
nop
nop
#endif
 
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
 
restore ! Go back to trap window.
mov %l7, %g1 ! Restore %g1
 
1: ! now save away the regs we must preserve
sub %fp, 32 * 4, %sp
#ifdef CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
std %g0, [%sp + 16 * 4] ! save G registers
std %g2, [%sp + 18 * 4] ! (set %g0 place to 0 to flag special context)
std %g4, [%sp + 20 * 4]
std %g6, [%sp + 22 * 4]
#else // not CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
 
st %g1, [%sp + 17 * 4] ! save G registers
std %g2, [%sp + 18 * 4]
std %g4, [%sp + 20 * 4]
std %g6, [%sp + 22 * 4]
 
! no point whatsoever in saving O registers
 
! and save the CWP in %g0 save place
st %l0, [%sp + 16 * 4]
#endif // ! CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT
 
sub %sp, 24 * 4, %sp ! fresh frame including
! arg spill area for callees
MARKSTACKUSED ! kilroy was here
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
! we will switch to the interrupt stack unless already running on it
 
.extern cyg_interrupt_stack
.extern cyg_interrupt_stack_base
set cyg_interrupt_stack, %g1
set cyg_interrupt_stack_base, %g2
 
cmp %sp, %g2 ! below base?
blu 1f ! if so, switch.
cmp %sp, %g1 ! below top? (DELAY SLOT)
blu 2f ! if so, DON~T switch.
nop ! (DELAY SLOT)
1: ! switch to the interrupt stack
st %sp, [ %g1 ] ! there is spare above stack
sub %g1, 24 * 4, %sp ! fresh frame including
! arg spill area for callees
MARKSTACKUSED ! kilroy was here
2:
! continue as before, already in the interrupt stack.
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
! Lock the scheduler
.extern SCHED_LOCK_MANGLED_NAME
sethi %hi(SCHED_LOCK_MANGLED_NAME), %l7
ld [ %l7 + %lo(SCHED_LOCK_MANGLED_NAME) ], %l6
add %l6, 1, %l6
st %l6, [ %l7 + %lo(SCHED_LOCK_MANGLED_NAME) ]
#endif
 
! HELP_GDB_WITH_BACKTRACE
mov %i7, %l5 ! preserve it in l5
mov %l1, %i7 ! bogus return link here
 
! and we must preserve the Y register (multiply/divide auxiliary)
! over these calls; we will keep it in %l4 which is otherwise unused.
rd %y, %l4
 
! Now we can reenable traps and mask off only lower prio interrupts:
andn %l0, 0xf00, %l7 ! clear PIL field
or %l7, 0x0e0, %l7 ! and ET (+S,PS)
sll %l3, 8, %l6 ! trap number (1-15) into PIL bitfield
wr %l7, %l6, %psr ! and enable!
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
! now call the ISR and so on with the appropriate args:
! ie.
! isr_retcode = (*(hal_interrupt_handlers[ vector ]))
! ( vector, hal_interrupt_data[ vector ] );
 
! from hal_arch.h
!// ISR tables
!CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
!CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
!CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
 
mov %l3, %o0
sll %l3, 2, %l3 ! %l3 to a word offset
sethi %hi(hal_interrupt_data), %l7
or %l7, %lo(hal_interrupt_data), %l7
ld [ %l7 + %l3 ], %o1
 
sethi %hi(hal_interrupt_handlers), %l7
or %l7, %lo(hal_interrupt_handlers), %l7
ld [ %l7 + %l3 ], %l6
call %l6
nop
 
#ifdef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
! We only need to call _interrupt_end() when there is a kernel
! present to do any tidying up.
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
! now we switch back to the user stack (if we~re at the top
! of the interrupt stack).
 
or %l0, 0xfe0, %l7
wr %l7, %psr ! Interrupts all masked, ET
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
.extern cyg_interrupt_stack
set cyg_interrupt_stack - (24 * 4), %g1
 
cmp %sp, %g1 ! is SP less?
blu 1f ! if so, do not change back
nop
! switch to the thread stack
ld [ %g1 + (24 * 4) ], %sp ! there is spare above stack
1:
 
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
! First restore the processor interrupt level to that interrupted
! (otherwise a task-switch runs at the current PIL) on the assumption
! that the ISR dealt with the interrupt source per se, so it is safe
! to unmask it, effectively:
or %l0, 0x0e0, %l7 ! original PSR and ET (+S,PS)
wr %l7, %psr ! and enable!
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
! then call interrupt_end( isr_retcode, &intr_object, &regsave )
! to unlock the scheduler and do any rescheduling that~s needed.
! argument 0 (isr_retcode) is already in place in %o0
sethi %hi(hal_interrupt_objects), %l7
or %l7, %lo(hal_interrupt_objects), %l7
ld [ %l7 + %l3 ], %o1
add %sp, 24 * 4, %o2 ! saved regset (maybe tiny)
 
.extern interrupt_end
call interrupt_end
nop
#endif
 
! restore the Y register having done our callouts to C
wr %l4, %y
 
! We can reinstall the original CWP here; even if interrupt_end()
! performed a reschedule (ie. yield/resume pair) we will be in the
! same window. The window is preserved by reschedule precisely
! because it is impossible atomically to disable traps here without
! involving a CWP living in a register for a time when other
! interrupts may occur.
 
! disable traps (using the saved psr is fastest way)
wr %l0, %psr ! restores flags, disables traps, and old PIL
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
 
! HELP_GDB_WITH_BACKTRACE
mov %l5, %i7 ! restore (unused) return link
 
! and restore other saved regs
! (see CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT)
add %sp, 24 * 4, %sp ! undo fresh frame
 
ld [%sp + 17 * 4], %g1 ! restore G registers
ldd [%sp + 18 * 4], %g2
ldd [%sp + 20 * 4], %g4
ldd [%sp + 22 * 4], %g6
 
! and do NOT restore any other registers L, I or O
 
! Now test for window underflow here and fix up if needs be.
!
! Why? interrupt_end() might have yielded us, when only
! its own frame was restored; its own return to us caused a
! window underflow trap, as would our return to interruptee
! unless we deal with it now.
 
add %l0, 1, %l7 ! interruptee~s CWP plus noise
and %l7, __WINBITS, %l7 ! CWP only
#if 8 == __WINSIZE
! it is in range already
#else // expect 5 or 6 or 7 windows
cmp %l7, __WINSIZE
bge,a 567f ! taken: do delay slot, handle overflow
mov 0, %l7 ! only if .ge. above
567:
#endif
mov 1, %l6
sll %l6, %l7, %l6 ! 1 << CWP
rd %wim, %l5
cmp %l5, %l6 ! are they the same?
bne 2f ! No, so the stack is OK as is.
 
! now do by hand an underflow trap, effectively
sll %l5, 1, %l5 ! Rotate wim left
srl %l6, __WINSIZE-1, %l6
wr %l5, %l6, %wim
#ifdef DELAYS_AFTER_WRWIM
nop ! are these delays needed?
nop ! (following restore uses wim)
nop
#endif
restore ! Interruptee~s window
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2
ldd [%sp + 4 * 4], %l4
ldd [%sp + 6 * 4], %l6
 
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
save ! Back to trap window
 
2: ! restore the condition codes, PSR and PIL and return from trap.
wr %l0, %psr ! restores flags, disables traps, and old PIL
#ifdef DELAYS_AFTER_WRPSR_SAME_WINDOW
nop
nop
nop
#endif
jmpl %l1, %g0
rett %l2
 
!----------------------------------------------------------------------------
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
! This routine can only be called from a thread stack, maybe
! with interrupts (but not traps) disabled.
! It switches to the interrupt stack then calls back to the
! kernel to execute DSRs.
 
.global hal_interrupt_stack_call_pending_DSRs
hal_interrupt_stack_call_pending_DSRs:
save %sp, -24 * 4, %sp
 
MARKSTACKUSED ! kilroy was here
 
! be atomic
rd %psr, %l0
andn %l0, 0x20, %l1 ! clear ET to disable traps
wr %l1, %psr ! into the PSR
nop
nop
nop
 
mov %sp, %l7 ! save calling stack location
 
! now switch stack to the interrupt stack, plus some headroom
! for saving a register set if we are interrupted
.extern cyg_interrupt_stack
set cyg_interrupt_stack - 4 * 24, %sp
 
MARKSTACKUSED ! kilroy was here
 
! and enable interrupts unconditionally to call the DSRs
or %l0, 0x0e0, %l2 ! set ET, S, PS
andn %l2, 0xf00, %l2 ! PIL to zero
wr %l2, %psr ! into the PSR
nop
nop
nop
.extern cyg_interrupt_call_pending_DSRs
call cyg_interrupt_call_pending_DSRs
nop
 
mov %l7, %sp ! restore calling stack
 
wr %l0, %psr ! restore interrupt status
nop
nop
nop
 
ret
restore
#endif // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
 
!----------------------------------------------------------------------------
 
! end of vec_ivsr.S
/arch/v2_0/src/context.S
0,0 → 1,403
/*=============================================================================
//
// context.S
//
// SPARC context switch code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1998-12-15
// Purpose: SPARC context switch code
// Description: This file contains implementations of the thread context
// switch routines. It also contains the longjmp() and setjmp()
// routines.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/vectors.h>
#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM
 
.text
 
! ------------------------------------------------------------------------------
! hal_thread_switch_context
! Switch thread contexts
! %o0 = address of sp of next thread to execute
! %o1 = address of sp save location of current thread
 
.global hal_thread_switch_context
hal_thread_switch_context:
 
! First take the stack down to make room for the saved register
! state, including a window save area at the base. Leave the
! current window save area undisturbed. It is unused within the
! save but will become current again when we continue in this
! context. This lets us do this whole piece of work without
! diabling interrupts for too long, since, for example, we can
! lower the stack atomically with one instruction:
sub %sp, SAVE_REGS_SIZE, %sp
st %sp, [ %o1 ] ! return SP for this thread
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
st %o7, [%sp + 31 * 4] ! save only the return address
! and no need to preserve %o0 even though it is restored
#else // save a maximal context
st %g1, [%sp + 17 * 4] ! save G & O registers
std %g2, [%sp + 18 * 4]
std %g4, [%sp + 20 * 4]
std %g6, [%sp + 22 * 4]
 
std %o0, [%sp + 24 * 4]
std %o2, [%sp + 26 * 4]
std %o4, [%sp + 28 * 4]
std %o6, [%sp + 30 * 4]
#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
! and save the CWP in %g0 save place
rd %psr, %g7
st %g7, [%sp + 16 * 4]
! Now load the destination thread by dropping through
! to hal_thread_load_context
! ------------------------------------------------------------------------------
! hal_thread_load_context
! Load thread context
! %o0 = address of sp of next thread to execute
! Note that this function is also the second half of hal_thread_switch_context
! and is simply dropped into from it.
 
.global hal_thread_load_context
hal_thread_load_context:
 
! Here, we are a leaf routine but with slightly odd properties.
! The stack is still the callers at this point but the register
! set is up for grabs. So we can use globals:
ld [ %o0 ], %g7 ! Get the next saved SP
! DISABLE INTERRUPTS *ONLY* NOT TRAPS
rd %psr, %g6
or %g6, 0xfe0, %g5 ! PIL up to 15 leave traps enabled
wr %g5, %psr
nop; nop; nop
! force out all our callers register sets onto the stack
! if necessary: the system will handily take care of this for
! us as follows:
save %sp, -16 * 4, %sp ! need all these to preserve
save %sp, -16 * 4, %sp ! the linked list property...
save %sp, -16 * 4, %sp
save %sp, -16 * 4, %sp
#if 6 < __WINSIZE
save %sp, -16 * 4, %sp
#if 7 < __WINSIZE
save %sp, -16 * 4, %sp
#endif
#endif
! Fewer saves if fewer register windows. For 8 register windows,
! six of these is correct; a seventh would force out the current
! set that was already saved manually above. Note that minimal
! space is allowed on stack for locals and ins in case this
! sequence itself gets interrupted and recurses too deep.
! now select the new window with traps disabled...
 
! get the new PSR and CWP that we will ultimately restore
! from the %g0 save place...
ld [%g7 + 16 * 4], %g6 ! %g7 holds the new stack pointer
andn %g6, 0x20, %g5 ! clear ET into %g5
and %g6, __WINBITS, %g4 ! CWP bits only in %g4
! calculate a new WIM...
add %g4, 1, %g3 ! required invalid window number
#if 8 == __WINSIZE
and %g3, __WINBITS, %g3 ! modulo 8
#else // expect 5 or 6 or 7 windows
cmp %g3, __WINSIZE
bge,a 567f ! taken: do delay slot, handle overflow
mov 0, %g3 ! only if .ge. above
567:
#endif
mov 1, %g2
sll %g2, %g3, %g2 ! converted to a mask for the WIM
 
! DISABLE INTERRUPTS (TRAPS)
wr %g5, %psr ! set CWP to new window, disable traps
wr %g2, %wim ! and WIM to new value
nop
nop
nop
! Must do this atomically so that the registers match the stack.
! After locals and ins are loaded, we are conformant to the PCS
! so can re-enable interrupts.
mov %g7, %sp ! target sp in situ (%sp = %o6)
 
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2
ldd [%sp + 4 * 4], %l4
ldd [%sp + 6 * 4], %l6
 
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
 
! RESTORE INTERRUPTS to saved state
wr %g6, %psr ! set new CWP and old ET and PIL
nop
nop
nop
! now load the rest of the context; we can be interrupted here
! (if the saved context was a voluntary yield or threadstart)
! but that is OK, other state will be preserved in that case...
 
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
ld [%sp + 24 * 4], %o0 ! must load the initial argument
#else // restore a maximal context
ld [%sp + 17 * 4], %g1
ldd [%sp + 18 * 4], %g2
ldd [%sp + 20 * 4], %g4
ldd [%sp + 22 * 4], %g6
 
ldd [%sp + 24 * 4], %o0
ldd [%sp + 26 * 4], %o2
ldd [%sp + 28 * 4], %o4
#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
! %o6 = %sp, already set up
ld [%sp + 31 * 4], %o7 ! "return" address
 
retl
add %sp, SAVE_REGS_SIZE, %sp ! and set the stack back
! to its entrant value
 
! ------------------------------------------------------------------------------
! HAL longjmp, setjmp implementations
 
!FUNC_START(hal_setjmp)
.global hal_setjmp
hal_setjmp:
! Treat this as a leaf routine, may as well.
! %o0 is the address of the buffer.
 
std %l0, [%o0 + 0 * 4] ! save L & I registers
std %l2, [%o0 + 2 * 4]
std %l4, [%o0 + 4 * 4]
std %l6, [%o0 + 6 * 4]
 
std %i0, [%o0 + 8 * 4]
std %i2, [%o0 + 10 * 4]
std %i4, [%o0 + 12 * 4]
std %i6, [%o0 + 14 * 4]
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
std %o6, [%o0 + 30 * 4] ! just save %sp and return address
#else // save a maximal context
st %g1, [%o0 + 17 * 4] ! save G & O registers
std %g2, [%o0 + 18 * 4]
std %g4, [%o0 + 20 * 4]
std %g6, [%o0 + 22 * 4]
 
std %o0, [%o0 + 24 * 4]
std %o2, [%o0 + 26 * 4]
std %o4, [%o0 + 28 * 4]
std %o6, [%o0 + 30 * 4]
#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
! and save the CWP in %g0 save place
rd %psr, %g7
st %g7, [%o0 + 16 * 4]
 
! DISABLE INTERRUPTS *ONLY* NOT TRAPS
or %g7, 0xfe0, %g6 ! PIL up to 15 leave traps enabled
wr %g6, %psr
nop; nop; nop
! force out all our callers register sets onto the stack
! if necessary: the system will handily take care of this for
! us as follows:
save %sp, -16 * 4, %sp ! need all these to preserve
save %sp, -16 * 4, %sp ! the linked list property...
save %sp, -16 * 4, %sp
save %sp, -16 * 4, %sp
#if 6 < __WINSIZE
save %sp, -16 * 4, %sp
#if 7 < __WINSIZE
save %sp, -16 * 4, %sp
#endif
#endif
! Fewer saves if fewer register windows. For 8 register windows,
! six of these is correct; a seventh would force out the current
! set that was already saved manually above. Note that minimal
! space is allowed on stack for locals and ins in case this
! sequence itself gets interrupted and recurses too deep.
 
! (after all, we are about to call deeper not shallower, otherwise
! using setjmp is inappropriate)
 
! ENABLE INTERRUPTS
wr %g7, %psr ! set CWP back to as-was
nop
nop
nop
#ifndef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
ldd [%o0 + 22 * 4], %g6 ! preserve %g7 and %g6
#endif
retl ! ret and return zero to indicate
mov 0, %o0 ! not longjumped-to
! hal_longjmp loads state from arg0 and returns arg1
!FUNC_START(hal_longjmp)
.global hal_longjmp
hal_longjmp:
! This is kind of a leaf routine, it returns elsewhere
! %o0 is the address of the buffer.
! %o1 is the value to return in %o0 (since we are a leaf)
 
mov %o0, %g7 ! keep the pointer handy
mov %o1, %g1 ! and the return value
! now select the new window with traps disabled...
rd %psr, %g6
! preserve ET, clear CWP
andn %g6, __WINBITS_MAXIMAL, %g6
andn %g6, 0x20, %g5 ! clear ET also into %g5
 
! get new CWP from %g0 save place...
ld [%g7 + 16 * 4], %g4 ! %g7 holds the new stack pointer
and %g4, __WINBITS, %g4 ! preserve CWP bits
! calculate a new WIM...
add %g4, 1, %g3 ! required invalid window number
#if 8 == __WINSIZE
and %g3, __WINBITS, %g3 ! modulo 8
#else // expect 5 or 6 or 7 windows
cmp %g3, __WINSIZE
bge,a 567f ! taken: do delay slot, handle overflow
mov 0, %g3 ! only if .ge. above
567:
#endif
mov 1, %g2
sll %g2, %g3, %g2 ! converted to a mask for the WIM
 
! DISABLE INTERRUPTS
wr %g5, %g4, %psr ! set CWP to new window, disable traps
wr %g2, %wim ! and WIM to new value
nop
nop
nop
! Must do this atomically so that the registers match the stack.
! After locals and ins are loaded, we are conformant to the PCS
! so can re-enable interrupts.
 
ldd [%g7 + 0 * 4], %l0 ! restore L & I registers
ldd [%g7 + 2 * 4], %l2
ldd [%g7 + 4 * 4], %l4
ldd [%g7 + 6 * 4], %l6
 
ldd [%g7 + 8 * 4], %i0
ldd [%g7 + 10 * 4], %i2
ldd [%g7 + 12 * 4], %i4
ldd [%g7 + 14 * 4], %i6
 
ld [%g7 + 30 * 4], %sp ! %o6 = %sp, set up now so as to conform
! to PCS and so be interruptible
! ENABLE INTERRUPTS
wr %g6, %g4, %psr ! set new CWP and old ET
nop
nop
nop
! now load the rest of the context; we can be interrupted here, but
! that is OK, other state will be preserved in that case...
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
! we are not preserving globals...
! %o6 = %sp, already set up
ld [%g7 + 31 * 4], %o7 ! "return" address
retl ! %g1 still holds the return value
mov %g1, %o0
 
#else // load a maximal context
mov %g7, %o0 ! original pointer was in %o0 anyway
 
ldd [%o0 + 18 * 4], %g2
ldd [%o0 + 20 * 4], %g4
ldd [%o0 + 22 * 4], %g6
 
ld [%o0 + 25 * 4], %o1 ! %o0 = original pointer
ldd [%o0 + 26 * 4], %o2
ldd [%o0 + 28 * 4], %o4
! %o6 = %sp, already set up
ld [%o0 + 31 * 4], %o7 ! "return" address
 
! %g1 still holds the return value; want to get this into %o0
! and restore %g1 from the saved state; %o0 is the state pointer:
! g1 = R, o0 = P
xor %o0, %g1, %g1 ! g1 = R^P, o0 = P
xor %o0, %g1, %o0 ! g1 = R^P, o0 = R
xor %o0, %g1, %g1 ! g1 = P, o0 = R all done
retl
ld [%g1 + 17 * 4], %g1 ! and finally restore %g1
#endif // !CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
! ------------------------------------------------------------------------------
! end of context.S
 
 
 
/arch/v2_0/src/sparc.ld
0,0 → 1,152
//===========================================================================
//
// MLT linker script for SPARC
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
STARTUP(vectors.o)
ENTRY(reset_vector)
#ifdef EXTRAS
INPUT(extras.o)
#endif
#if (__GNUC__ >= 3)
GROUP(libtarget.a libgcc.a libsupc++.a)
#else
GROUP(libtarget.a libgcc.a)
#endif
 
#define ALIGN_LMA 8
#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
#define LMA_EQ_VMA
#define FORCE_OUTPUT . = .
 
#define SECTIONS_BEGIN
 
#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
.rom_vectors _vma_ : _lma_ \
{ FORCE_OUTPUT; KEEP (*(.vectors)) } \
> _region_
 
#define SECTION_text(_region_, _vma_, _lma_) \
.text _vma_ : _lma_ \
{ _stext = ABSOLUTE(.); \
*(.text*) *(.gnu.warning) *(.gnu.linkonce*) *(.init) } \
> _region_ \
_etext = .; PROVIDE (etext = .);
 
#define SECTION_fini(_region_, _vma_, _lma_) \
.fini _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fini) } \
> _region_
 
#define SECTION_rodata(_region_, _vma_, _lma_) \
.rodata _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata*) } \
> _region_
 
#define SECTION_rodata1(_region_, _vma_, _lma_) \
.rodata1 _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.rodata1) } \
> _region_
 
#define SECTION_fixup(_region_, _vma_, _lma_) \
.fixup _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.fixup) } \
> _region_
 
#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
.gcc_except_table _vma_ : _lma_ \
{ FORCE_OUTPUT; *(.gcc_except_table) } \
> _region_
 
#define SECTION_ram_vectors(_region_, _vma_, _lma_) \
.ram_vectors _vma_ : _lma_ \
{ __ram_vectors_start = ABSOLUTE(.); \
KEEP (*(.ram_vectors)) \
__ram_vectors_end = ABSOLUTE(.); } \
> _region_
 
#define SECTION_data(_region_, _vma_, _lma_) \
.data _vma_ : _lma_ \
{ __ram_data_start = ABSOLUTE (.); \
*(.data*) *(.data1) \
_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
. = ALIGN (4); \
KEEP(*( SORT (.ecos.table.*))) ; \
__CTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(SORT(.ctors*))) \
__CTOR_END__ = ABSOLUTE (.); \
__DTOR_LIST__ = ABSOLUTE (.); \
KEEP(*(SORT(.dtors*))) \
__DTOR_END__ = ABSOLUTE (.); \
_GOT_START = ABSOLUTE (.); _GLOBAL_OFFSET_TABLE_ = ABSOLUTE (.) + 32768; \
_SDA_BASE_ = ABSOLUTE (.); \
*(.got.plt) *(.got) _GOT_END_ = ABSOLUTE (.); \
*(.dynamic) *(.sdata*) *(.sbss*) *(.eh_frame) } \
> _region_ \
__rom_data_start = LOADADDR (.data); \
. = ALIGN (8); \
__ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .);
#define SECTION_bss(_region_, _vma_, _lma_) \
.bss _vma_ : _lma_ \
{ __bss_start = ABSOLUTE (.); \
*(.scommon) *(.dynbss) *(.bss) *(COMMON) \
__bss_end = ABSOLUTE (.); } \
> _region_
 
#define SECTIONS_END . = ALIGN(8); _end = .; PROVIDE (end = .); \
.debug 0 : { *(.debug) } \
.line 0 : { *(.line) } \
.debug_srcinfo 0 : { *(.debug_srcinfo) } \
.debug_sfnames 0 : { *(.debug_sfnames) } \
.debug_aranges 0 : { *(.debug_aranges) } \
.debug_pubnames 0 : { *(.debug_pubnames) } \
.debug_info 0 : { *(.debug_info) } \
.debug_abbrev 0 : { *(.debug_abbrev) } \
.debug_line 0 : { *(.debug_line) } \
.debug_frame 0 : { *(.debug_frame) } \
.debug_str 0 : { *(.debug_str) } \
.debug_loc 0 : { *(.debug_loc) } \
.debug_macinfo 0 : { *(.debug_macinfo) } \
.debug_weaknames 0 : { *(.debug_weaknames) } \
.debug_funcnames 0 : { *(.debug_funcnames) } \
.debug_typenames 0 : { *(.debug_typenames) } \
.debug_varnames 0 : { *(.debug_varnames) }
 
#include <pkgconf/system.h>
#include CYGHWR_MEMORY_LAYOUT_LDI
/arch/v2_0/src/vectors.S
0,0 → 1,543
/*=============================================================================
//
// vectors.S
//
// SPARC vectors and bootup code
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors:hmt
// Date: 1998-12-15
// Purpose: SPARC vector code
// Description: This file contains the code which hangs off SPARC vectors
// including reset; it handles register under/overflow as well
// as bootup, anything else is deferred to the default interrupt
// or exception vsrs respectively. See vec_[ix]vsr.S ...
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
!-----------------------------------------------------------------------------
// .file "vectors.S"
 
!-----------------------------------------------------------------------------
#include <pkgconf/system.h>
#include <pkgconf/hal.h>
 
#include <pkgconf/hal_sparc.h>
#include CYGBLD_HAL_PLATFORM_H // Platform config file
 
#ifdef CYGPKG_KERNEL
# include <pkgconf/kernel.h>
#else
# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
#endif
#if defined( CYGPKG_HAL_SPARCLITE_SIM ) || \
defined( CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK ) || \
defined( CYGPKG_HAL_SPARC_LEON ) || \
defined( CYGPKG_HAL_SPARC_ERC32 )
#define BOOTUPSTACK_IS_INTERRUPTSTACK
#endif
//#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
 
#ifndef CYGHWR_HAL_SPARC_HAS_ASR17
#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
#error Single Vector Trapping (SVT) demands ASR17
#endif
#endif
#ifdef CYG_HAL_STARTUP_ROM
# ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
 
! ROM startup and Single Vector Trapping demands a copy to RAM.
! Otherwise it may be configured in, but it is not required.
# ifndef CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
# define CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
# endif
 
# endif
#endif
 
!------------------------------------------------------------------------
 
#include <cyg/hal/vectors.h>
 
#define DELAYS_AFTER_WRPSR_SAME_WINDOW
#define DELAYS_AFTER_WRWIM
 
!------------------------------------------------------------------------
 
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
 
.macro VECTOR_EXCEPTION
.p2align 4
rd %tbr, %l3
rd %psr, %l0
ba __entry_exception
and %l3, TT_MASK, %l4
.endm
.macro VECTOR_INTERRUPT level
.p2align 4
rd %psr, %l0
mov \level << 2, %l5
ba __entry_interrupt
mov \level << 4, %l4
.endm
.macro VECTOR_CODE_WIM name
.p2align 4
ba __entry_\name
rd %wim, %l0
.endm
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
 
!------------------------------------------------------------------------
! The start of the code; this is the entry point:
.section ".vectors","ax"
 
.global rom_vectors
rom_vectors:
.global reset_vector
reset_vector:
! this code goes to the real reset handler, it will be
! overwritten by the start of vectoring handler...
b genuine_reset
nop
! usually drop through to:
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
ba __entry_exception ! reset becomes an exception
and %l3, TT_MASK, %l4 ! once we are running
VECTOR_EXCEPTION ! 1
VECTOR_EXCEPTION ! 2
VECTOR_EXCEPTION ! 3
VECTOR_EXCEPTION ! 4
VECTOR_CODE_WIM wover ! 5 window overflow
VECTOR_CODE_WIM wunder ! 6 window underflow
VECTOR_EXCEPTION ! 7
VECTOR_EXCEPTION ! 8
VECTOR_EXCEPTION ! 9
 
VECTOR_EXCEPTION ! 10
VECTOR_EXCEPTION ! 11
VECTOR_EXCEPTION ! 12
VECTOR_EXCEPTION ! 13
VECTOR_EXCEPTION ! 14
VECTOR_EXCEPTION ! 15
VECTOR_EXCEPTION ! 16
VECTOR_INTERRUPT 1 ! 17 interrupt_level_1
VECTOR_INTERRUPT 2 ! 18 interrupt_level_2
VECTOR_INTERRUPT 3 ! 19 interrupt_level_3
VECTOR_INTERRUPT 4 ! 20 interrupt_level_4
VECTOR_INTERRUPT 5 ! 21 interrupt_level_5
VECTOR_INTERRUPT 6 ! 22 interrupt_level_6
VECTOR_INTERRUPT 7 ! 23 interrupt_level_7
VECTOR_INTERRUPT 8 ! 24 interrupt_level_8
VECTOR_INTERRUPT 9 ! 25 interrupt_level_9
VECTOR_INTERRUPT 10 ! 26 interrupt_level_10
VECTOR_INTERRUPT 11 ! 27 interrupt_level_11
VECTOR_INTERRUPT 12 ! 28 interrupt_level_12
VECTOR_INTERRUPT 13 ! 29 interrupt_level_13
VECTOR_INTERRUPT 14 ! 30 interrupt_level_14
VECTOR_INTERRUPT 15 ! 31 interrupt_level_15
VECTOR_EXCEPTION ! 32
VECTOR_EXCEPTION ! 33
VECTOR_EXCEPTION ! 34
 
VECTOR_EXCEPTION ! 35
VECTOR_EXCEPTION ! 36
VECTOR_EXCEPTION ! 37
VECTOR_EXCEPTION ! 38
VECTOR_EXCEPTION ! 39
.rept 216 ! 40-255 is 216 of them
VECTOR_EXCEPTION ! whichever
.endr
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
 
#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
real_vector:
! here,locals have been set up as follows:
! %l0 = psr
! %l1 = pc
! %l2 = npc
! %l3 = tbr
and %l3, TT_IS_INTR_MASK, %l4
cmp %l4, TT_IS_INTR_VALUE
bne not_an_interrupt ! delay slot does not matter
! here be the pre-vector interrupt handler
interrupt:
and %l3, 0x0f0, %l4 ! get an interrupt number out
srl %l4, 2, %l5 ! to a word address offset
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
__entry_interrupt:
sethi %hi(hal_vsr_table), %l6
or %l6, %lo(hal_vsr_table), %l6
ld [ %l6 + %l5 ], %l6 ! get vector in %l6
jmp %l6 ! and go there
srl %l4, 4, %l3 ! vector number into %l3: so that
! interrupts and exceptions/traps
! have the same API to VSRs
 
#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
not_an_interrupt:
and %l3, TT_MASK, %l4
cmp %l4, (TRAP_WUNDER << TT_SHL)
 
bne,a not_window_underflow
cmp %l4, (TRAP_WOVER << TT_SHL) ! (if taken)
 
! here be the window underflow handler:
window_underflow:
! CWP is trap handler
! CWP + 1 is trapped RESTORE instruction
! CWP + 2 is invalid context which must be restored
! CWP + 3 is next invalid context
 
wr %l0, %psr ! restore the condition flags
! (CWP is unchanged)
! the following instructions delay enough; no need for NOPs
rd %wim, %l0 ! get the wim
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
__entry_wunder:
sll %l0, 1, %l3 ! Rotate wim left
srl %l0, __WINSIZE-1, %l0
wr %l0, %l3, %wim ! Install the new wim
 
#ifdef DELAYS_AFTER_WRWIM
nop ! are these delays needed?
nop ! (following restore uses wim)
nop
#endif
restore ! Users window
restore ! Her callers window (now valid)
ldd [%sp + 0 * 4], %l0 ! restore L & I registers
ldd [%sp + 2 * 4], %l2
ldd [%sp + 4 * 4], %l4
ldd [%sp + 6 * 4], %l6
 
ldd [%sp + 8 * 4], %i0
ldd [%sp + 10 * 4], %i2
ldd [%sp + 12 * 4], %i4
ldd [%sp + 14 * 4], %i6
 
save ! Back to trap window
save
 
jmp %l1
rett %l2
 
#ifndef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
not_window_underflow:
bne,a not_window_overflow
srl %l4, 4, %l4 ! (if taken)
 
! here be the window overflow handler:
window_overflow:
! CWP + 1 is caller whose SAVE bounced
! CWP is trap handler = invalid window
! CWP - 1 is next invalid window which needs to be saved
 
wr %l0, %psr ! restore the condition flags
! (CWP is unchanged)
! the following instructions delay enough; no need for NOPs
rd %wim, %l0
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
__entry_wover:
mov %g1, %l3 ! Save g1, we use it to hold the wim
srl %l0, 1, %g1 ! Rotate wim right
sll %l0, __WINSIZE-1, %l0
or %l0, %g1, %g1
 
save ! Slip into next window
mov %g1, %wim ! Install the new wim
! (invalidates current window!)
 
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4]
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
 
restore ! Go back to trap window.
mov %l3, %g1 ! Restore %g1
 
jmpl %l1, %g0
rett %l2
 
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
// ADDITIONAL code to provide an entry point:
__entry_exception:
srl %l4, 4, %l4
#endif // CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
not_window_overflow:
! from here on in, %l4 is the trap number in clear
cmp %l4, 128
bge 1f
mov 0, %l5 ! offset 0 for user traps
 
cmp %l4, 36 ! coprocessor special case
beq 1f
mov 4, %l5 ! ...treated as FP, code 4
 
cmp %l4, 10
bge 1f
mov 10, %l5 ! offset 10 for "others"
 
! if we are here, the trap number is 1-9 inclusive
! so put it in %l5 and drop through...
mov %l4, %l5
1:
or %l5, 16, %l5 ! offset into table is 16... for traps.
sll %l5, 2, %l5 ! to a word address offset
sethi %hi(hal_vsr_table), %l6
or %l6, %lo(hal_vsr_table), %l6
ld [ %l6 + %l5 ], %l6 ! get vector in %l6
jmp %l6 ! and go there
srl %l5, 2, %l3 ! vector number into %l3: so that
! interrupts and exceptions/traps
! have the same API to VSRs
! NB that~s eCos vector number not TRAP number above.
! and that is the end of the pre-vector trap handler
 
.global rom_vectors_end
rom_vectors_end:
! these instructions are copied into the reset vector
! after startup to _not_ branch to the genuine_reset code below
real_vector_instructions:
rd %tbr, %l3
rd %psr, %l0
 
 
 
! genuine reset code called from time zero:
genuine_reset: ! set psr, mask interrupts & traps
sethi %hi(reset_vector), %g1
andn %g1, 0xfff, %g1 ! should not be needed
wr %g1, %tbr ! Traps are at reset_vector
wr %g0, 0xfc0 + __WIN_INIT, %psr ! mode = prevMode = S, CWP=7
wr %g0, 0, %wim ! No invalid windows (yet)
#ifdef CYGHWR_HAL_SPARC_HAS_ASR17
#ifdef CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
wr %g0, 0, %asr17 ! Multiple vector trapping
#else
wr %g0, 1, %asr17 ! Single vector trapping
#endif // !CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
#endif // CYGHWR_HAL_SPARC_HAS_ASR17
nop
nop
nop
 
// INCLUDE PLATFORM BOOT
 
// This should set up RAM and caches, and calm down any external interrupt
// sources. Also copy two instructions from real_vector_instructions
// into reset_vector, then invalidate the instruction cache.
#include <cyg/hal/halboot.si>
// halboot.si returns with %sp all set, in sleb versions.
// (though we override if there is an interrupt stack)
 
led 0x80
! now set up a stack and initial frame linkage
! so as to be able to make C function calls:
! current window is 7, the highest, so we store a
! saved frame thingy that refers to itself in the stack,
! then another which is valid and drop into main from there.
 
#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK
sethi %hi(cyg_interrupt_stack), %i6
or %i6, %lo(cyg_interrupt_stack), %i6
#endif
andn %i6, 7, %i6 ! round fp down to double alignment
mov 0, %i7 ! null return address
sethi %hi(0xb51ac000), %i0 ! "BStac" pattern
or %i0, 24, %i0
or %i0, 1, %i1
or %i0, 2, %i2
or %i0, 3, %i3
or %i0, 4, %i4
or %i0, 5, %i5
 
sethi %hi(0xb51ac000), %l0 ! "BStac" pattern
or %l0, 16, %l0
or %l0, 1, %l1
or %l0, 2, %l2
or %l0, 3, %l3
or %l0, 4, %l4
or %l0, 5, %l5
or %l0, 6, %l6
or %l0, 7, %l7
sub %fp, 16 * 4, %sp ! Stack pointer
 
led 0x90
std %l0, [%sp + 0 * 4] ! save L & I registers
std %l2, [%sp + 2 * 4] ! into new stack frame
std %l4, [%sp + 4 * 4]
std %l6, [%sp + 6 * 4]
 
led 0x91
std %i0, [%sp + 8 * 4]
std %i2, [%sp + 10 * 4]
std %i4, [%sp + 12 * 4]
std %i6, [%sp + 14 * 4]
led 0x92
sethi %hi(0xb0010000), %o0 ! "Boot" pattern
or %o0, 8, %o0
or %o0, 1, %o1
or %o0, 2, %o2
or %o0, 3, %o3
or %o0, 4, %o4
or %o0, 5, %o5
 
led 0x98
wr %g0, __WIM_INIT, %wim ! Window 7 (current) is invalid
nop
nop
nop
led 0x99
sethi %hi(0xb0010000), %g1 ! "Boot" pattern
or %g1, 2, %g2
or %g1, 3, %g3
or %g1, 4, %g4
or %g1, 5, %g5
or %g1, 6, %g6
or %g1, 7, %g7
or %g1, 1, %g1
 
led 0xa0
wr %g0, 0xfe0 + __WIN_INIT, %psr
nop ! Enable traps:
nop ! set psr, _do_ mask interrupts
nop ! mode = prevMode = S, CWP=7
 
led 0xb0
 
! now we can start calling out and running C code!
.extern cyg_hal_start
call cyg_hal_start ! puts return address in %o7
or %g1, 1, %g1
loop_forever:
ta 1
b loop_forever ! if it returns
nop
 
!---------------------------------------------------------------------------
! hal_vsr_table...
 
.section ".data"
.balign 4
.global hal_vsr_table
hal_vsr_table:
.rept 16
.word hal_default_interrupt_vsr
.endr
.rept 11
.word hal_default_exception_vsr
.endr
 
!---------------------------------------------------------------------------
! Bootup stack (only needed explicitly in sim)
#ifdef BOOTUPSTACK_IS_INTERRUPTSTACK
.section ".bss"
 
#ifndef CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 4096
#endif
.balign 16
.global cyg_interrupt_stack_base
cyg_interrupt_stack_base:
.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
.byte 0
.endr
.balign 16
.global cyg_interrupt_stack
cyg_interrupt_stack:
.long 0,0,0,0,0,0,0,0 ! here be secret state stored
#endif
 
!------------------------------------------------------------------------
! Define a section that reserves space at the start of RAM for the
! vectors to be copied into, for ROM start only.
.section ".ram_vectors","awx",@nobits
#ifdef CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
! need a space at base of RAM for copied vector/trampoline code
.align 0x1000
.space 8 ! for fencepost errors
.space (rom_vectors_end - rom_vectors)
#endif // CYGIMP_HAL_SPARC_COPY_VECTORS_TO_RAM
 
!------------------------------------------------------------------------
! end of vectors.S
/arch/v2_0/src/hal_boot.c
0,0 → 1,174
//==========================================================================
//
// hal_boot.c
//
// SPARC Architecture specific interrupt dispatch tables
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1998-12-10
// Purpose: Interrupt handler tables for SPARC.
//
//####DESCRIPTIONEND####
//
//==========================================================================
 
#include <pkgconf/hal.h>
#include <cyg/infra/cyg_type.h>
 
/*------------------------------------------------------------------------*/
/* calling this is our raison d'etre: */
extern void cyg_start( void );
 
/*------------------------------------------------------------------------*/
/* data copy and bss zero functions */
 
typedef void (CYG_ROM_ADDRESS)(void);
 
#ifdef CYG_HAL_STARTUP_ROM
void hal_copy_data(void)
{
extern char __ram_data_start;
extern char __ram_data_end;
extern CYG_ROM_ADDRESS __rom_data_start;
long *p = (long *)&__ram_data_start;
long *q = (long *)&__rom_data_start;
while( p <= (long *)&__ram_data_end )
*p++ = *q++;
}
#endif
 
void hal_zero_bss(void)
{
extern CYG_ROM_ADDRESS __bss_start;
extern CYG_ROM_ADDRESS __bss_end;
 
register long long zero = 0;
register long long *end = (long long *)&__bss_end;
register long long *p = (long long *)&__bss_start;
 
while( p <= end )
*p++ = zero;
}
 
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
cyg_bool cyg_hal_stop_constructors;
#endif
 
void
cyg_hal_invoke_constructors (void)
{
typedef void (*pfunc) (void);
extern pfunc __CTOR_LIST__[];
extern pfunc __CTOR_END__[];
 
#ifdef CYGSEM_HAL_STOP_CONSTRUCTORS_ON_FLAG
static pfunc *p = &__CTOR_END__[-1];
cyg_hal_stop_constructors = 0;
for (; p >= __CTOR_LIST__; p--) {
(*p) ();
if (cyg_hal_stop_constructors) {
p--;
break;
}
}
#else
pfunc *p;
 
for (p = &__CTOR_END__[-1]; p >= __CTOR_LIST__; p--)
(*p) ();
#endif
}
 
// Override any __gccmain the compiler might generate. We don't want
// constructors to be called twice.
void __gccmain(void) {}
 
/*------------------------------------------------------------------------*/
/* CYG_HAL_START - pre-main-entrypoint */
 
#ifdef CYGPKG_HAL_SPARCLITE_SLEB
#define SLEB_LED (*(volatile char *)(0x02000003))
#define LED( _x_ ) SLEB_LED = (char)(0xff & ~(_x_))
#else
#define LED( _x_ ) CYG_EMPTY_STATEMENT
#endif
 
extern void hal_board_prestart( void );
extern void hal_board_poststart( void );
 
// This is called with traps enabled, but interrupts masked out:
// Be sure to enable them in hal_board_poststart() at the latest.
 
void cyg_hal_start( void )
{
/* Board specific prestart that's best done in C */
hal_board_prestart();
 
LED( 0xd0 );
 
#ifdef CYG_HAL_STARTUP_ROM
/* Copy data from ROM to RAM */
hal_copy_data();
#endif
LED( 0xd4 );
 
/* Zero BSS */
hal_zero_bss();
 
LED( 0xd8 );
 
/* Call constructors */
cyg_hal_invoke_constructors();
 
LED( 0xdc );
 
/* Board specific late startup that's best done in C */
hal_board_poststart();
 
LED( 0xf8 );
 
/* Call cyg_start */
cyg_start(); /* does not return */
}
 
// EOF hal_boot.c
/arch/v2_0/src/icontext.c
0,0 → 1,498
/*=============================================================================
//
// icontext.c
//
// SPARC HAL context init function
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1998-12-14
// Purpose: HAL context initialization function
// Description: Initialize a HAL context for SPARC; this is in C and out
// of line because there is too much of it for a simple macro.
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/hal/hal_arch.h> // HAL header
 
#include <cyg/infra/cyg_type.h>
 
#include <cyg/hal/vectors.h> // SAVE_REGS_SIZE, __WINSIZE, ...
 
/*---------------------------------------------------------------------------*/
 
/* We lay out the stack in the manner that the PCS demands:
* frame pointer -----> [top of stack]
* Argument spill area (6 words)
* Return Arg pointer
* Initial saved register window (i[8], l[8])
* for use by program when it starts
* [rest of] saved register object (various)
* stack pointer -----> saved register window (i[8], l[8])
* to allow us to be interrupted.
*
* ie. frame pointer ->
* struct HAL_FrameStructure
* stack pointer -> struct HAL_SavedRegisters
*
* and when the context "resumes" sp is incremented by 40 * 4, the size of
* a _struct HAL_SavedRegisters_ which points it at the extant but unused
* _struct HAL_FrameStructure_ as the PCS requires. The frame pointer is
* left pointing off the top of stack.
*
*
* Thus the stack is the same if created from an already executing context:
*
* frame pointer ----->
* [temporaries and locals]
* [more arguments]
* Argument spill area (6 words)
* Return Arg pointer
* [sp at entry]------> Previous saved register window (i[8], l[8])
* for use by program when it starts
* [rest of] saved register object (various)
* stack pointer -----> saved register window (i[8], l[8])
* to allow us to be interrupted.
*/
 
CYG_ADDRESS
hal_thread_init_context( CYG_WORD sparg,
CYG_WORD thread,
CYG_WORD entry,
CYG_WORD id )
{
register CYG_WORD fp = sparg;
register CYG_WORD sp = 0;
register HAL_SavedRegisters *regs;
register HAL_FrameStructure *frame;
int i;
 
if ( 0 == (id & 0xffff0000) )
id <<= 16;
 
fp &= ~15; // round down to double alignment
 
frame = (HAL_FrameStructure *)(
fp - sizeof( HAL_FrameStructure ) );
regs = (HAL_SavedRegisters *)(
((CYG_WORD)frame) - sizeof(HAL_SavedRegisters) );
 
sp = (CYG_WORD)regs;
for ( i = 0; i < 6; i++ ) {
frame->spill_args[i] = id | 0xa0 | i;
}
frame->composite_return_ptr = 0;
 
for ( i = 0; i < 8; i++ ) {
frame->li.i[i] = id | ( 56 + i );
frame->li.l[i] = id | ( 48 + i );
regs ->li.i[i] = id | ( 24 + i );
regs ->li.l[i] = id | ( 16 + i );
regs ->o[i] = id | ( 8 + i );
regs ->g[i] = id | ( i );
}
 
// first terminate the linked list on the stack in the initial
// (already saved) register window:
frame->li.i[6] = regs->li.i[6] = (cyg_uint32)fp; // frame pointer
frame->li.i[7] = regs->li.i[7] = (cyg_uint32)0; // no ret addr here
 
// and set up other saved regs as if called from just before
// the entry point:
regs->o[7] = (entry - 8);
regs->o[6] = sp;
 
// this is the argument that the entry point is called with
regs->o[0] = thread;
 
// this is the initial CWP and interrupt state; CWP is quite arbitrary
// really, the WIM is set up accordingly in hal_thread_load_context().
 
regs->g[0] = 0x0e0 + __WIN_INIT; // PIL zero, ET, S, PS and CWP set.
 
return (CYG_ADDRESS)sp;
}
 
// ---------------------------------------------------------------------------
 
//#define THREAD_DEBUG_SERIAL_VERBOSE
 
#ifdef THREAD_DEBUG_SERIAL_VERBOSE // NOT INCLUDED
 
// This is unpleasant to try to debug, because these routines are called
// WHEN THE PROGRAM IS NOT RUNNING from the CygMon's GDB stubs - so you
// can't use any normal output: these little routines use the serial
// line directly, so are best used when debugging via Ethernet, so you
// just have a separate output stream to read. Nasty...
 
#include <cyg/hal/hal_diag.h>
 
#undef HAL_DIAG_WRITE_CHAR
#define HAL_DIAG_WRITE_CHAR(_c_) CYG_MACRO_START \
SLEB_LED = (_c_); \
HAL_DIAG_WRITE_CHAR_DIRECT( _c_ ); \
CYG_MACRO_END
 
static void swritec( char c )
{
HAL_DIAG_WRITE_CHAR( c );
}
 
static void swrites( char *s )
{
char c;
while ( 0 != (c = *s++) )
HAL_DIAG_WRITE_CHAR( c );
}
 
static void swritex( cyg_uint32 x )
{
int i;
swrites( "0x" );
for ( i = 28; i >= 0; i-= 4 ) {
char c = "0123456789abcdef"[ 0xf & (x >> i) ];
HAL_DIAG_WRITE_CHAR( c );
}
}
 
#define newline() swrites( "\n\r" )
 
static void x8( char *s, unsigned long *xp )
{
int i;
for ( i = 0; i < 8; i++ ) {
swrites( s );
swritec( '0' + i );
swrites( " = " );
swritex( xp[i] );
if ( 3 == (i & 3) )
newline();
else
swrites( " " );
}
}
 
#endif // THREAD_DEBUG_SERIAL_VERBOSE ... NOT INCLUDED
 
// ---------------------------------------------------------------------------
// Routines in icontext.c used here because they're quite large for
// the SPARC (note param order); these are used in talking to GDB.
 
enum regnames {G0 = 0, G1, G2, G3, G4, G5, G6, G7,
O0, O1, O2, O3, O4, O5, SP, O7,
L0, L1, L2, L3, L4, L5, L6, L7,
I0, I1, I2, I3, I4, I5, FP, I7,
 
F0, F1, F2, F3, F4, F5, F6, F7,
F8, F9, F10, F11, F12, F13, F14, F15,
F16, F17, F18, F19, F20, F21, F22, F23,
F24, F25, F26, F27, F28, F29, F30, F31,
Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR};
 
typedef unsigned long target_register_t;
 
void
cyg_hal_sparc_get_gdb_regs( void *gdb_regset,
HAL_SavedRegisters *eCos_regset )
{
target_register_t *gdb = (target_register_t *)gdb_regset;
int reg;
cyg_uint32 scratch = 0;
cyg_uint32 *sptrap;
HAL_SavedWindow *trapli, *ctxli;
 
if ( 0 == eCos_regset->g[0] ||
0xc0 == (0xe0 & eCos_regset->g[0]) ) {
// Then it's an interrupt stack saved state:
// (either minimal, or a saved PSR with traps disabled)
// The saved register set is pretty minimal, so we have to grub
// around in the stack to find out some truth...
sptrap = (cyg_uint32 *)eCos_regset; // point to the IL save area for
sptrap -= 24; // the trap handler, for PC, NPC
trapli = (HAL_SavedWindow *)sptrap; // Get at those regs
 
ctxli = (HAL_SavedWindow *)(trapli->i[6]); // (the frame pointer)
// and get at the interruptee's regs
 
// Pick up interruptee's registers from all over the stack:
for ( reg = 0; reg < 8 ; reg++ ) {
gdb[ G0 + reg ] = eCos_regset->g[reg];
gdb[ O0 + reg ] = trapli->i[reg];
gdb[ L0 + reg ] = ctxli->l[reg];
gdb[ I0 + reg ] = ctxli->i[reg];
}
// Clear out G0 which is always 0 (but abused in eCos_regset)
// and the FP regs which we do not have:
gdb[ G0 ] = 0;
for ( reg = F0; reg <= F31; reg++ )
gdb[ reg ] = 0;
// In the save context _of the trap handler_ registers are as follows:
// %l0 = psr (with this CWP/window-level in it)
// %l1 = pc
// %l2 = npc
// %l3 = vector number (1-15 for interrupts)
// %l4 = Y register preserved
gdb[ Y ] = trapli->l[4];
scratch = trapli->l[0]; // the PSR in the trap handler
#if 8 == __WINSIZE
scratch++; // back to interupted thread's window
scratch &=~ 0x38; // clear ET and any __WINSIZE overflow
gdb[ PSR ] = scratch;
gdb[ WIM ] = 1 << ((__WINBITS & (1 + scratch)));
#else // 6 or 7 windows only
reg = (int)(scratch & __WINBITS);
scratch &=~ (__WINBITS_MAXIMAL | 0x20); // clear ET and CWP
if ( __WINSIZE <= ++reg ) reg = 0; // back to intr'd window
gdb[ PSR ] = scratch | reg;
if ( __WINSIZE <= ++reg ) reg = 0; // good index for WIM
gdb[ WIM ] = 1 << reg;
#endif // __WINSIZE
// Read _a_ TBR value and ignore the current trap details:
asm volatile ( "rd %%tbr, %0" : "=r"(scratch) : );
gdb[ TBR ] = (scratch &~ 0xfff);
gdb[ PC ] = trapli->l[1];
gdb[ NPC ] = trapli->l[2];
gdb[ FPSR ] = 0;
gdb[ CPSR ] = 0;
 
#ifdef THREAD_DEBUG_SERIAL_VERBOSE
newline();
swrites( "-----------------------------------------------------" ); newline();
swrites( "-------------- INTERRUPT STACK GET ------------------" ); newline();
swrites( "eCos regset at " ); swritex( eCos_regset ); newline();
swrites( " trapli " ); swritex( trapli ); newline();
swrites( " ctxli " ); swritex( ctxli ); newline();
x8( "global ", &(gdb[G0]) );
x8( " in ", &(gdb[I0]) );
x8( " local ", &(gdb[L0]) );
x8( " out ", &(gdb[O0]) );
swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline();
swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline();
swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline();
#endif
 
}
else {
// It's a synchronous context switch that led to this object.
// Pick up interruptee's registers from the saved context:
for ( reg = 0; reg < 8 ; reg++ ) {
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
gdb[ G0 + reg ] = 0;
gdb[ O0 + reg ] = 0;
#else
gdb[ G0 + reg ] = eCos_regset->g[reg];
gdb[ O0 + reg ] = eCos_regset->o[reg];
#endif
gdb[ L0 + reg ] = eCos_regset->li.l[reg];
gdb[ I0 + reg ] = eCos_regset->li.i[reg];
}
 
#ifdef CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM
// Set up the stack pointer by arithmetic and the return address
gdb[ SP ] = ((cyg_uint32)(eCos_regset));
gdb[ O7 ] = eCos_regset->o[ 7 ];
#else
// Clear out G0 which is always 0 (but abused in eCos_regset)
gdb[ G0 ] = 0;
#endif
// and clear the FP regs which we do not have:
for ( reg = F0; reg <= F31; reg++ )
gdb[ reg ] = 0;
gdb[ Y ] = 0; // it's not preserved.
scratch = eCos_regset->g[ 0 ]; // the PSR in the saved context
gdb[ PSR ] = scratch; // return it verbatim.
#if 8 == __WINSIZE
gdb[ WIM ] = 1 << ((__WINBITS & (1 + scratch)));
#else // 6 or 7 windows only
reg = (int)(scratch & __WINBITS);
if ( __WINSIZE <= ++reg ) reg = 0; // good index for WIM
gdb[ WIM ] = 1 << reg;
#endif // __WINSIZE
// Read _a_ TBR value and ignore the current trap details:
asm volatile ( "rd %%tbr, %0" : "=r"(scratch) : );
gdb[ TBR ] = (scratch &~ 0xfff);
gdb[ PC ] = eCos_regset->o[ 7 ]; // the return address
gdb[ NPC ] = 4 + gdb[ PC ];
gdb[ FPSR ] = 0;
gdb[ CPSR ] = 0;
 
#ifdef THREAD_DEBUG_SERIAL_VERBOSE
newline();
swrites( "-----------------------------------------------------" ); newline();
swrites( "-------------- SYNCHRONOUS SWITCH GET----------------" ); newline();
swrites( "eCos regset at " ); swritex( eCos_regset ); newline();
x8( "global ", &(gdb[G0]) );
x8( " in ", &(gdb[I0]) );
x8( " local ", &(gdb[L0]) );
x8( " out ", &(gdb[O0]) );
swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline();
swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline();
swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline();
#endif
}
 
}
 
// ---------------------------------------------------------------------------
 
void
cyg_hal_sparc_set_gdb_regs( HAL_SavedRegisters *eCos_regset,
void *gdb_regset )
{
target_register_t *gdb = (target_register_t *)gdb_regset;
int reg;
cyg_uint32 scratch = 0;
cyg_uint32 *sptrap;
HAL_SavedWindow *trapli, *ctxli;
 
// Guess where the eCos register set really is:
if ( 0 == eCos_regset->g[0] ||
0xc0 == (0xe0 & eCos_regset->g[0]) ) {
// Then it's an interrupt stack saved state:
// (either minimal, or a saved PSR with traps disabled)
// The saved register set is pretty minimal, so we have to grub
// around in the stack to find out some truth...
sptrap = (cyg_uint32 *)eCos_regset; // point to the IL save area for
sptrap -= 24; // the trap handler, for PC, NPC
trapli = (HAL_SavedWindow *)sptrap; // Get at those regs
 
ctxli = (HAL_SavedWindow *)(trapli->i[6]); // (the frame pointer)
// and get at the interruptee's regs
 
scratch = eCos_regset->g[0];
 
// Put back interruptee's registers all over the stack:
for ( reg = 0; reg < 8 ; reg++ ) {
eCos_regset->g[reg] = gdb[ G0 + reg ] ;
trapli->i[reg] = gdb[ O0 + reg ] ;
ctxli->l[reg] = gdb[ L0 + reg ] ;
ctxli->i[reg] = gdb[ I0 + reg ] ;
}
// Put back the eCos G0 which is always 0 (but abused in eCos_regset)
eCos_regset->g[0] = scratch;
 
// In the save context _of the trap handler_ registers are as follows:
// %l0 = psr (with this CWP/window-level in it)
// %l1 = pc
// %l2 = npc
// %l3 = vector number (1-15 for interrupts)
// %l4 = Y register preserved
trapli->l[4] = gdb[ Y ];
// I am *not* interfering with the saved PSR, nor the TBR nor WIM.
// put back return PC and NPC
trapli->l[1] = gdb[ PC ] ;
trapli->l[2] = gdb[ NPC ];
#ifdef THREAD_DEBUG_SERIAL_VERBOSE
newline();
swrites( "-----------------------------------------------------" ); newline();
swrites( "-------------- INTERRUPT STACK SET ------------------" ); newline();
swrites( "eCos regset at " ); swritex( eCos_regset ); newline();
swrites( " trapli " ); swritex( trapli ); newline();
swrites( " ctxli " ); swritex( ctxli ); newline();
x8( "global ", &(gdb[G0]) );
x8( " in ", &(gdb[I0]) );
x8( " local ", &(gdb[L0]) );
x8( " out ", &(gdb[O0]) );
swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline();
swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline();
swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline();
#endif
 
}
else {
// It's a synchronous context switch that led to this object.
// Pick up interruptee's registers from the saved context:
 
scratch = eCos_regset->g[0];
 
for ( reg = 0; reg < 8 ; reg++ ) {
eCos_regset->g[reg] = gdb[ G0 + reg ];
eCos_regset->o[reg] = gdb[ O0 + reg ];
eCos_regset->li.l[reg] = gdb[ L0 + reg ];
eCos_regset->li.i[reg] = gdb[ I0 + reg ];
}
 
// Put back the eCos G0 which is always 0 (but abused in eCos_regset)
eCos_regset->g[0] = scratch;
// I am *not* interfering with the saved PSR, nor the TBR nor WIM.
 
// The PC is in o7, altering it via GDB's PC is not on.
// Setting the NPC in a voluntary context is meaningless.
 
#ifdef THREAD_DEBUG_SERIAL_VERBOSE
newline();
swrites( "-----------------------------------------------------" ); newline();
swrites( "-------------- SYNCHRONOUS SWITCH SET ---------------" ); newline();
swrites( "eCos regset at " ); swritex( eCos_regset ); newline();
x8( "global ", &(gdb[G0]) );
x8( " in ", &(gdb[I0]) );
x8( " local ", &(gdb[L0]) );
x8( " out ", &(gdb[O0]) );
swrites( "gdb PC = " ); swritex( gdb[ PC ] ); newline();
swrites( "gdb NPC = " ); swritex( gdb[ NPC ] ); newline();
swrites( "gdb PSR = " ); swritex( gdb[ PSR ] ); newline();
#endif
}
 
}
 
/*---------------------------------------------------------------------------*/
// EOF icontext.c
/leon/v2_0/cdl/hal_sparc_leon.cdl
0,0 → 1,201
# ====================================================================
#
# hal_sparc_leon.cdl
#
# SPARC LEON target HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: hmt
# Contributors:
# Date: 2000-02-10
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_SPARC_LEON {
display "LEON processor"
parent CYGPKG_HAL_SPARC
define_header hal_sparc_leon.h
include_dir cyg/hal
description "
The LEON HAL package is provided for both simulator (TSIM)
and real hardware use"
 
compile hal_priv.c
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sparc.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sparc_leon.h>"
puts $::cdl_header "#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING /* true for LEON */"
puts $::cdl_header "#define HAL_IDLE_THREAD_ACTION hal_idle_thread_action /* true for LEON */"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the LEON processor only the RAM startup type
is usable."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated 9999
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
parent CYGPKG_NONE
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "sparc-rtems" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-msoft-float -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-msoft-float -g -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
}
 
cdl_component CYGPKG_HAL_SPARC_LEON_OPTIONS {
display "LEON processor build options"
flavor none
description "
Package specific build options including control over
compiler flags used only in building this package,
and details of which tests are built."
 
 
cdl_option CYGPKG_HAL_SPARC_LEON_CFLAGS_ADD {
display "Additional compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the LEON processor HAL. These flags are
used in addition to the set of global flags."
}
 
cdl_option CYGPKG_HAL_SPARC_LEON_CFLAGS_REMOVE {
display "Suppressed compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the LEON processor HAL. These flags are
removed from the set of global flags if present."
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { "sparc_leon_ram" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { "<pkgconf/mlt_sparc_leon_ram.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { "<pkgconf/mlt_sparc_leon_ram.h>" }
}
}
}
/leon/v2_0/include/halboot.si
0,0 → 1,151
#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */
#define CYGONCE_HAL_HALBOOT_SI
// ====================================================================
//
// <platform>/halboot.si
//
// HAL bootup platform-oriented code (assembler)
//
// ====================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-01
// Purpose: Bootup code, platform oriented.
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
 
// External Platform Initial Setup
//
// This should set up RAM and caches, and calm down any external
// interrupt sources.
//
// It is just plain included in vectors.S
//
// RAM has not yet been touched at all; in fact all you have is a
// register window selected.
 
 
! Empty macro for debugging vectors.S
.macro led val
.endm
 
! Set memory according to simulator config
 
set 0x80000000, %l0 ! LEON register base address
 
ld [%l0 + 0x14], %l1 ! chech if we have been initialized
andcc %l1, 0x1, %g0
bne 4f
nop
 
flush ! if we are here, we are running on
set 0x1000f, %l1 ! the simulator....
 
st %l1, [%l0 + 0x14] ! enable caches
 
st %g0, [%l0 + 0x1c] ! clear LEON registers
st %g0, [%l0 + 0x20] !
st %g0, [%l0 + 0x90] !
st %g0, [%l0 + 0x94] !
st %g0, [%l0 + 0x98] !
st %g0, [%l0 + 0x9C] !
st %g0, [%l0 + 0xA0] !
st %g0, [%l0 + 0xA4] !
st %g0, [%l0 + 0xA4] !
st %g0, [%l0 + 0x78] !
st %g0, [%l0 + 0x88] !
 
ld [%l0 + 0xF8], %g1 ! load simulator rom size
clr %l2
subcc %g1, 0, %g0
be 3f
srl %g1, 13, %g1 ! calculate appropriate rom size
1:
srl %g1, 1, %g1
tst %g1
bne,a 1b
inc %l2
sll %l2, 14, %l2
st %l2, [%l0 + 0x00] ! set prom size in memcfg1
 
set 0, %l2
ld [%l0 + 0xF4], %g2 ! load simulator ram size
srl %g2, 13, %g1 ! calculate appropriate ram size
1:
srl %g1, 1, %g1
tst %g1
bne,a 1b
inc %l2
sll %l2, 9, %l2
or %l2, 0x20, %l2
st %l2, [%l0 + 0x04] ! set ram size in memcfg2
set 0x40000000, %l2
add %g2, %l2, %fp
sub %fp, 96*4, %sp
3:
st %g0, [%sp] !probe for FPU
! ld [%sp], %fsr
set 49, %l1
st %l1, [%l0 + 0x64] ! scaler = 49
st %l1, [%l0 + 0x60] ! scaler = 49
 
2:
 
set -1, %l1
st %l1, [%l0 + 0x44] ! timer 1 = 0xffffff
set 7, %l1
st %l1, [%l0 + 0x48] ! start timer 1
st %l1, [%l0 + 0x78] ! enable UARTS
st %l1, [%l0 + 0x88]
 
4:
! then copy the branch instructions into the vector
rd %tbr, %g1
andn %g1, 0xfff, %g1 ! clear non-address bits
sethi %hi(real_vector_instructions), %l0
or %l0, %lo(real_vector_instructions), %l0
ld [ %l0 ], %l1
st %l1, [ %g1 ] ! into the vector
ld [ %l0 + 4 ], %l1
st %l1, [ %g1 + 4 ] ! into the vector
 
#endif /* CYGONCE_HAL_HALBOOT_SI */
/* EOF halboot.si */
/leon/v2_0/include/hal_clock.h
0,0 → 1,128
#ifndef CYGONCE_HAL_CLOCK_H
#define CYGONCE_HAL_CLOCK_H
 
//=============================================================================
//
// hal_clock.h
//
// HAL clock support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define clock support
// Description: The macros defined here provide the HAL APIs for handling
// the clock.
//
// Usage:
// #include <cyg/hal/hal_intr.h> // which includes this file
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/hal_io.h>
 
//-----------------------------------------------------------------------------
// Clock control
 
// in erc32 simulator:
// 4 = UART A
// 5 = UART B
// 7 = UART error
// 12 = GPT (general purpose timer)
// 13 = TI1 (realtime clock)
// 15 = watchdog
 
// in erc32 simulator:
 
// The vector used by the Real time clock is defined in hal_xpic.h
 
// We could place conditional code here to choose one clock or the other
// depending on the selected interrupt vector... but pro tem: (pun intended)
 
#define SPARC_LEON_TIMER_SCALE (24)
 
/* These must be accessed word-wide to work! */
 
#define SPARC_LEON_REG (0x80000000)
 
#define SPARC_LEON_TI1_COUNTER (SPARC_LEON_REG + 0x40)
#define SPARC_LEON_TI1_CRELOAD (SPARC_LEON_REG + 0x44)
#define SPARC_LEON_SCALER (SPARC_LEON_REG + 0x60)
#define SPARC_LEON_SRELOAD (SPARC_LEON_REG + 0x64)
/* LEON timer control register bits */
#define SPARC_LEON_TI1_EN 1 /* System Enable */
#define SPARC_LEON_TI1_RL 2 /* Continuous Running */
#define SPARC_LEON_TI1_LD 4 /* Counter Load */
 
#define SPARC_LEON_TI1_CONTROL (SPARC_LEON_REG + 0x48)
 
externC cyg_int32 cyg_hal_sparc_clock_period;
 
#define HAL_CLOCK_INITIALIZE( _period_ ) CYG_MACRO_START \
cyg_hal_sparc_clock_period = (_period_); \
HAL_WRITE_UINT32( SPARC_LEON_TI1_CRELOAD, (_period_) ); \
HAL_WRITE_UINT32( SPARC_LEON_TI1_COUNTER, (_period_) ); \
HAL_WRITE_UINT32( SPARC_LEON_TI1_CONTROL, \
(SPARC_LEON_TI1_EN | \
SPARC_LEON_TI1_RL | \
SPARC_LEON_TI1_LD) ); \
CYG_MACRO_END
 
#define HAL_CLOCK_RESET( _vector_, _period_ ) /* nowt, it is freerunning */
 
#define HAL_CLOCK_READ( _pvalue_ ) CYG_MACRO_START \
cyg_uint32 _read_; \
HAL_READ_UINT32( SPARC_LEON_TI1_COUNTER, _read_ ); \
*((cyg_uint32 *)(_pvalue_)) = \
(cyg_hal_sparc_clock_period - _read_ ); \
CYG_MACRO_END
 
 
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( _pvalue_ )
#endif
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CLOCK_H
// End of hal_clock.h
/leon/v2_0/include/pkgconf/mlt_sparc_leon_ram.h
0,0 → 1,19
// eCos memory layout - Fri Oct 20 08:18:20 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x40000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x40080000 - (size_t) CYG_LABEL_NAME (__heap1))
 
#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING
/leon/v2_0/include/pkgconf/mlt_sparc_leon_ram.ldi
0,0 → 1,26
// eCos memory layout - Fri Oct 20 08:18:20 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x40000000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (ram, 0x40000000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/leon/v2_0/include/pkgconf/mlt_sparc_leon_ram.mlt
0,0 → 1,12
version 0
region ram 40000000 80000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 40000000 40000000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 1 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/leon/v2_0/include/hal_cache.h
0,0 → 1,182
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL Cache control support (such as it is in the simulator)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// the caches.
//
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_sparc.h>
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// LEON cache macros
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE 0x4000 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 16 // Size of a data cache line
#define HAL_DCACHE_WAYS 1 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 0x4000 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 16 // Size of a cache line
#define HAL_ICACHE_WAYS 1 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE() //*((int *)0x80000014) |= (int)0x0000000c
// Disable the data cache
#define HAL_DCACHE_DISABLE() //*((int *)0x80000014) &= ~(int)0x0000000c
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL() //*((int *)0x80000014) |= (int)0x00400000
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache - use Data cache controls since they
// are not separatable.
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/leon/v2_0/include/hal_xpic.h
0,0 → 1,122
#ifndef CYGONCE_HAL_XPIC_H
#define CYGONCE_HAL_XPIC_H
 
//=============================================================================
//
// hal_xpic.h
//
// HAL eXternal Programmable Interrupt Controller support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// an external interrupt controller, and which interrupt is
// used for what.
//
// Usage:
// #include <cyg/hal/hal_intr.h> // which includes this file
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/hal_io.h>
 
//-----------------------------------------------------------------------------
// Interrupt controller access
 
// in leon simulator:
// 2 = UART B
// 3 = UART A
// 1 = AHB error
// 9 = TI2 (general purpose timer)
// 8 = TI1 (realtime clock)
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_8
 
 
/* These must be accessed word-wide to work! */
#define SPARC_LEON_REG (0x80000000)
 
#define SPARC_LEON_INTCON_PENDING (SPARC_LEON_REG + 0x94)
#define SPARC_LEON_INTCON_MASK (SPARC_LEON_REG + 0x90)
#define SPARC_LEON_INTCON_CLEAR (SPARC_LEON_REG + 0x9C)
#define SPARC_LEON_INTCON_FORCE (SPARC_LEON_REG + 0x98)
 
 
#define HAL_INTERRUPT_MASK( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_, _mask_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_READ_UINT32( SPARC_LEON_INTCON_MASK, _mask_ ); \
_mask_ &= ~( 1 << (_vector_) ); \
HAL_WRITE_UINT32(SPARC_LEON_INTCON_MASK, _mask_ ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_, _mask_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_READ_UINT32( SPARC_LEON_INTCON_MASK, _mask_ ); \
_mask_ |= ( 1 << (_vector_) ); \
HAL_WRITE_UINT32( SPARC_LEON_INTCON_MASK, _mask_ ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ )
/* Interrupts are automatically acknowledged by hardware, not needed ...
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_WRITE_UINT32( SPARC_LEON_INTCON_CLEAR, ( 1 << (_vector_) ) ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
*/
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) /* nothing */
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) /* nothing */
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_XPIC_H
// End of hal_xpic.h
/leon/v2_0/include/hal_diag.h
0,0 → 1,132
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-01-11
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
/*---------------------------------------------------------------------------*/
 
#define CYG_DIAG_USE_LEON
 
/*---------------------------------------------------------------------------*/
 
#ifdef CYG_DIAG_USE_LEON
 
/*---------------------------------------------------------------------------*/
/* Register addresses */
 
#define SPARC_LEON_REG (0x80000000)
 
/* These must be accessed word-wide to work! */
#define SPARC_LEON_UART_IO( x ) ((cyg_uint32)(x))
 
#define SPARC_LEON_UART_A_RX ((volatile cyg_uint32 *)(SPARC_LEON_REG + 0x70))
#define SPARC_LEON_UART_A_TX ((volatile cyg_uint32 *)(SPARC_LEON_REG + 0x70))
#define SPARC_LEON_UART_STATUS ((volatile cyg_uint32 *)(SPARC_LEON_REG + 0x74))
#define SPARC_LEON_UART_RXAMASK (0x00001)
#define SPARC_LEON_UART_TXAMASK (0x00004)
 
/*---------------------------------------------------------------------------*/
 
#define HAL_DIAG_INIT()
 
#define HAL_DIAG_WRITE_CHAR(_c_) \
{ \
if( 1 || _c_ != '\r' ) \
{ \
while( (SPARC_LEON_UART_TXAMASK & *SPARC_LEON_UART_STATUS) == 0 ) \
continue; \
*SPARC_LEON_UART_A_TX = SPARC_LEON_UART_IO(_c_); \
} \
}
 
#define HAL_DIAG_READ_CHAR(_c_) \
{ \
while( (SPARC_LEON_UART_RXAMASK & *SPARC_LEON_UART_STATUS) == 0 ) \
continue; \
_c_ = (char)*SPARC_LEON_UART_A_TX; \
}
 
#define XHAL_DIAG_WRITE_CHAR(_c_) \
{ \
if( _c_ != '\r' ) \
{ \
*SPARC_LEON_UART_A_TX = SPARC_LEON_UART_IO(_c_); \
} \
}
 
#define XHAL_DIAG_READ_CHAR(_c_) \
{ \
_c_ = (char)*SPARC_LEON_UART_A_TX; \
}
 
#else
/*---------------------------------------------------------------------------*/
/* There is no diagnostic output on LEON processor */
 
#define HAL_DIAG_INIT()
 
#define HAL_DIAG_WRITE_CHAR(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) (_c_) = 0
 
#endif
 
/*---------------------------------------------------------------------------*/
/* end of hal_diag.h */
#endif /* CYGONCE_HAL_HAL_DIAG_H */
/leon/v2_0/ChangeLog
0,0 → 1,54
2002-10-19 Jonathan Larmour <jifl@eCosCentric.com>
 
Patch from Jiri Gaisler:
* cdl/hal_sparc_leon.cdl: -msoft-float needn't be used in local package
since it's defined globally.
* include/hal_diag.h: Fix UART TX mask.
 
2002-03-15 Hugo Tyson <hmt@redhat.com>
 
* cdl/hal_sparc_leon.cdl: Add -msoft-cloat to CYGBLD_GLOBAL_CFLAGS
(as well as LDFLAGS) - this gives perfect test coverage in minimal
build with the sim. NB pro tem the tools are called
sparc-rtems-gcc et al, but sparc-elf-gcc et al should be OK.
 
2002-03-14 Jiri Gaisler <jiri@gaisler.com>
 
* Initial version based on the SPARClite SIM HAL.
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
//EOF ChangeLog
/leon/v2_0/src/hal_priv.c
0,0 → 1,102
//===========================================================================
//
// hal_priv.c
//
// SPARC Architecture LEON-specific private variables
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-20
// Purpose: private vars for LEON processor.
//
//####DESCRIPTIONEND####
//
//===========================================================================
 
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_arch.h>
 
// ------------------------------------------------------------------------
// Clock static to keep period recorded.
cyg_int32 cyg_hal_sparc_clock_period = 0;
 
// ------------------------------------------------------------------------
// Board specific startups.
 
extern void hal_board_prestart( void );
extern void hal_board_poststart( void );
 
void hal_board_prestart( void )
{
}
 
void hal_board_poststart( void )
{
HAL_ENABLE_INTERRUPTS();
// OK to do this post constructors, and good for testing.
}
 
cyg_uint32
hal_lsbit_index(cyg_uint32 mask)
{
int i;
for (i = 0; i < 32; i++) {
if (mask & (1<<i)) return ((cyg_uint32)i);
}
return ((cyg_uint32)-1);
}
 
cyg_uint32
hal_msbit_index(cyg_uint32 mask)
{
int i;
for (i = 31; i >= 0; i--) {
if (mask & (1<<i)) return ((cyg_uint32)i);
}
return ((cyg_uint32)-1);
}
 
void
hal_idle_thread_action(cyg_uint32 loop_count)
{
*((volatile cyg_uint32 *) 0x80000018) = 0;
}
 
// EOF hal_priv.c
/leon/v2_0/support/do-gdb-sim
0,0 → 1,3
#! /bin/csh
tsim-leon -nfp -gdb >& /dev/stdout &
sparc-rtems-gdb -nw -nx $*:q
/leon/v2_0/support/README
0,0 → 1,32
 
LEON/TSIM Support
=================
 
See <http://www.gaisler.com> for information about the TSIM
simulator and Leon project per se.
 
The simulator TSIM can be run "as one" with GDB by using the
script do-gdb-sim in this directory. The script can be used in
automated testing systems to run as if it were embedded within
GDB. It contains:
 
----------------------------------------------------------------
#! /bin/csh
tsim-leon -nfp -gdb >& /dev/stdout &
sparc-rtems-gdb -nw -nx $*:q
----------------------------------------------------------------
 
which simply runs tsim in background, directing its output to the
common stdout.
 
The command to connect to the simulator target will be
 
(gdb) target remote localhost:1234
 
This fully described in the TSIM documentation from
(home) <http://www.gaisler.com/tsim.html>
(flyer) <http://www.gaisler.com/doc/tsim-erc32.pdf>
(doc) <http://www.gaisler.com/doc/tsim-1.0.18.pdf>
 
 
 
/erc32/v2_0/cdl/hal_sparc_erc32.cdl
0,0 → 1,201
# ====================================================================
#
# hal_sparc_erc32.cdl
#
# SPARC ERC32 target HAL package configuration data
#
# ====================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
# ====================================================================
######DESCRIPTIONBEGIN####
#
# Author(s): jskov
# Original data: hmt
# Contributors:
# Date: 2000-02-10
#
#####DESCRIPTIONEND####
#
# ====================================================================
 
cdl_package CYGPKG_HAL_SPARC_ERC32 {
display "ERC32 processor"
parent CYGPKG_HAL_SPARC
define_header hal_sparc_erc32.h
include_dir cyg/hal
description "
The ERC32 HAL package is provided for both simulator (TSIM)
and real hardware use"
 
compile hal_priv.c
 
define_proc {
puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_sparc.h>"
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_sparc_erc32.h>"
puts $::cdl_header "#define CYGHWR_HAL_SPARC_MULTIPLE_VECTOR_TRAPPING /* true for ERC32 */"
puts $::cdl_header "#define HAL_IDLE_THREAD_ACTION hal_idle_thread_action /* true for ERC32 */"
}
 
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
legal_values {"RAM"}
default_value {"RAM"}
no_define
define -file system.h CYG_HAL_STARTUP
description "
When targetting the ERC32 processor only the RAM startup type
is usable."
}
 
# Real-time clock/counter specifics
cdl_component CYGNUM_HAL_RTC_CONSTANTS {
display "Real-time clock constants."
flavor none
cdl_option CYGNUM_HAL_RTC_NUMERATOR {
display "Real-time clock numerator"
flavor data
calculated 1000000000
}
cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
display "Real-time clock denominator"
flavor data
calculated 100
}
cdl_option CYGNUM_HAL_RTC_PERIOD {
display "Real-time clock period"
flavor data
calculated 9999
}
}
 
cdl_component CYGBLD_GLOBAL_OPTIONS {
display "Global build options"
flavor none
description "
Global build options including control over
compiler flags, linker flags and choice of toolchain."
 
 
parent CYGPKG_NONE
 
cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
display "Global command prefix"
flavor data
no_define
default_value { "sparc-rtems" }
description "
This option specifies the command prefix used when
invoking the build tools."
}
 
cdl_option CYGBLD_GLOBAL_CFLAGS {
display "Global compiler flags"
flavor data
no_define
default_value { "-msoft-float -Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -ffunction-sections -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
description "
This option controls the global compiler flags which
are used to compile all packages by
default. Individual packages may define
options which override these global flags."
}
 
cdl_option CYGBLD_GLOBAL_LDFLAGS {
display "Global linker flags"
flavor data
no_define
default_value { "-msoft-float -g -nostdlib -Wl,--gc-sections -Wl,-static" }
description "
This option controls the global linker flags. Individual
packages may define options which override these global flags."
}
}
 
cdl_component CYGPKG_HAL_SPARC_ERC32_OPTIONS {
display "ERC32 processor build options"
flavor none
description "
Package specific build options including control over
compiler flags used only in building this package,
and details of which tests are built."
 
 
cdl_option CYGPKG_HAL_SPARC_ERC32_CFLAGS_ADD {
display "Additional compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the ERC32 processor HAL. These flags are
used in addition to the set of global flags."
}
 
cdl_option CYGPKG_HAL_SPARC_ERC32_CFLAGS_REMOVE {
display "Suppressed compiler flags"
flavor data
no_define
default_value { "" }
description "
This option modifies the set of compiler flags for
building the ERC32 processor HAL. These flags are
removed from the set of global flags if present."
}
}
 
cdl_component CYGHWR_MEMORY_LAYOUT {
display "Memory layout"
flavor data
no_define
calculated { "sparc_erc32_ram" }
 
cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
display "Memory layout linker script fragment"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
calculated { "<pkgconf/mlt_sparc_erc32_ram.ldi>" }
}
 
cdl_option CYGHWR_MEMORY_LAYOUT_H {
display "Memory layout header file"
flavor data
no_define
define -file system.h CYGHWR_MEMORY_LAYOUT_H
calculated { "<pkgconf/mlt_sparc_erc32_ram.h>" }
}
}
}
/erc32/v2_0/include/halboot.si
0,0 → 1,133
#ifndef CYGONCE_HAL_HALBOOT_SI /* -*-asm-*- */
#define CYGONCE_HAL_HALBOOT_SI
// ====================================================================
//
// <platform>/halboot.si
//
// HAL bootup platform-oriented code (assembler)
//
// ====================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
// ====================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-01
// Purpose: Bootup code, platform oriented.
// Description:
//
//####DESCRIPTIONEND####
//
// ====================================================================
 
// External Platform Initial Setup
//
// This should set up RAM and caches, and calm down any external
// interrupt sources.
//
// It is just plain included in vectors.S
//
// RAM has not yet been touched at all; in fact all you have is a
// register window selected.
 
 
! Empty macro for debugging vectors.S
.macro led val
.endm
 
 
set 0x01f80000, %l0 ! MEC register base address
ld [%l0], %l1 ! Check if MEC has been initialised
set 0xfe080000, %l2 ! by checking baud rate register
andcc %l2, %l1, %g0
bne 2f ! skip
nop
 
! Set memory according to simulator config
 
st %g0, [%l0 + 0x64] ! Disable watchdog for now
ld [%l0], %g1
or %g1, 1, %g1
st %g1, [%l0] ! Enable power down
st %g0, [%l0 + 0x18] ! No waitstates
ld [%l0 + 0xF8], %g1 ! load simulator rom size
clr %l2
srl %g1, 17, %g1 ! calculate appropriate MEC rom size
1:
srl %g1, 1, %g1
tst %g1
bne,a 1b
inc %l2
sll %l2, 8, %l2
ld [%l0 + 0xF4], %g2 ! load simulator ram size
srl %g2, 18, %g1 ! calculate appropriate MEC ram size
1:
srl %g1, 1, %g1
tst %g1
bne,a 1b
inc %l2
sll %l2, 10, %l2
st %l2, [%l0 + 0x10] ! program MEC memory config register
set 0x2000000, %l2
add %g2, %l2, %fp
sub %fp, 96*4, %sp
! st %g0, [%sp] ! probe for FPU
! ld [%sp], %fsr
 
set 13, %l1
st %l1, [%l0 + 0x84] ! RTC scaler = 13
 
2:
set reset_vector, %g1
set 0x0d00, %l1
st %l1, [%g1 + 0x7c0] ! Store TCR mirror
st %l1, [%l0 + 0x98] ! Start RTC
mov %g3, %o7
 
 
4:
! then copy the branch instructions into the vector
rd %tbr, %g1
andn %g1, 0xfff, %g1 ! clear non-address bits
sethi %hi(real_vector_instructions), %l0
or %l0, %lo(real_vector_instructions), %l0
ld [ %l0 ], %l1
st %l1, [ %g1 ] ! into the vector
ld [ %l0 + 4 ], %l1
st %l1, [ %g1 + 4 ] ! into the vector
 
#endif /* CYGONCE_HAL_HALBOOT_SI */
/* EOF halboot.si */
/erc32/v2_0/include/hal_clock.h
0,0 → 1,131
#ifndef CYGONCE_HAL_CLOCK_H
#define CYGONCE_HAL_CLOCK_H
 
//=============================================================================
//
// hal_clock.h
//
// HAL clock support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define clock support
// Description: The macros defined here provide the HAL APIs for handling
// the clock.
//
// Usage:
// #include <cyg/hal/hal_intr.h> // which includes this file
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/hal_io.h>
 
//-----------------------------------------------------------------------------
// Clock control
 
// in erc32 simulator:
// 4 = UART A
// 5 = UART B
// 7 = UART error
// 12 = GPT (general purpose timer)
// 13 = RTC (realtime clock)
// 15 = watchdog
 
// in erc32 simulator:
 
// The vector used by the Real time clock is defined in hal_xpic.h
 
// We could place conditional code here to choose one clock or the other
// depending on the selected interrupt vector... but pro tem: (pun intended)
 
/* These must be accessed word-wide to work! */
 
#define SPARC_MEC_RTC (0x01f80080)
 
#define SPARC_MEC_RTC_COUNTER (SPARC_MEC_RTC + 0)
#define SPARC_MEC_RTC_SCALER (SPARC_MEC_RTC + 4)
#define SPARC_MEC_GPT_COUNTER (SPARC_MEC_RTC + 8)
#define SPARC_MEC_GPT_SCALER (SPARC_MEC_RTC + 0x0c)
 
/* MEC timer control register bits */
#define SPARC_MEC_TCR_GACR 1 /* Continuous Running */
#define SPARC_MEC_TCR_GACL 2 /* Counter Load */
#define SPARC_MEC_TCR_GASE 4 /* System Enable */
#define SPARC_MEC_TCR_GASL 8 /* not used */
#define SPARC_MEC_TCR_TCRCR 0x100 /* Continuous Running */
#define SPARC_MEC_TCR_TCRCL 0x200 /* Counter Load */
#define SPARC_MEC_TCR_TCRSE 0x400 /* System Enable */
#define SPARC_MEC_TCR_TCRSL 0x800 /* not used */
 
#define SPARC_MEC_RTC_CONTROL (SPARC_MEC_RTC + 0x18)
 
externC cyg_int32 cyg_hal_sparc_clock_period;
 
#define HAL_CLOCK_INITIALIZE( _period_ ) CYG_MACRO_START \
cyg_hal_sparc_clock_period = (_period_); \
HAL_WRITE_UINT32( SPARC_MEC_RTC_COUNTER, (_period_) ); \
HAL_WRITE_UINT32( SPARC_MEC_RTC_CONTROL, \
(SPARC_MEC_TCR_TCRCR | \
SPARC_MEC_TCR_TCRCL | \
SPARC_MEC_TCR_TCRSE) ); \
CYG_MACRO_END
 
#define HAL_CLOCK_RESET( _vector_, _period_ ) /* nowt, it is freerunning */
 
#define HAL_CLOCK_READ( _pvalue_ ) CYG_MACRO_START \
cyg_uint32 _read_; \
HAL_READ_UINT32( SPARC_MEC_RTC_COUNTER, _read_ ); \
*((cyg_uint32 *)(_pvalue_)) = \
(cyg_hal_sparc_clock_period - _read_ ); \
CYG_MACRO_END
 
 
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
#define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( _pvalue_ )
#endif
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CLOCK_H
// End of hal_clock.h
/erc32/v2_0/include/pkgconf/mlt_sparc_erc32_ram.h
0,0 → 1,17
// eCos memory layout - Fri Oct 20 08:18:20 2000
 
// This is a generated file - do not edit
 
#ifndef __ASSEMBLER__
#include <cyg/infra/cyg_type.h>
#include <stddef.h>
 
#endif
#define CYGMEM_REGION_ram (0x2000000)
#define CYGMEM_REGION_ram_SIZE (0x80000)
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
#ifndef __ASSEMBLER__
extern char CYG_LABEL_NAME (__heap1) [];
#endif
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
#define CYGMEM_SECTION_heap1_SIZE (0x2080000 - (size_t) CYG_LABEL_NAME (__heap1))
/erc32/v2_0/include/pkgconf/mlt_sparc_erc32_ram.ldi
0,0 → 1,26
// eCos memory layout - Fri Oct 20 08:18:20 2000
 
// This is a generated file - do not edit
 
#include <cyg/infra/cyg_type.inc>
 
MEMORY
{
ram : ORIGIN = 0x2000000, LENGTH = 0x80000
}
 
SECTIONS
{
SECTIONS_BEGIN
SECTION_rom_vectors (ram, 0x2000000, LMA_EQ_VMA)
SECTION_text (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fini (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_rodata1 (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_fixup (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_gcc_except_table (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_data (ram, ALIGN (0x1), LMA_EQ_VMA)
SECTION_bss (ram, ALIGN (0x8), LMA_EQ_VMA)
CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
SECTIONS_END
}
/erc32/v2_0/include/pkgconf/mlt_sparc_erc32_ram.mlt
0,0 → 1,12
version 0
region ram 2000000 80000 0 !
section rom_vectors 0 1 0 1 1 1 1 1 2000000 2000000 text text !
section text 0 1 0 1 0 1 0 1 fini fini !
section fini 0 1 0 1 0 1 0 1 rodata rodata !
section rodata 0 1 0 1 0 1 0 1 rodata1 rodata1 !
section rodata1 0 1 0 1 0 1 0 1 fixup fixup !
section fixup 0 1 0 1 0 1 0 1 gcc_except_table gcc_except_table !
section gcc_except_table 0 1 0 1 0 1 0 1 data data !
section data 0 1 0 1 0 1 0 1 bss bss !
section bss 0 8 0 1 0 1 0 1 heap1 heap1 !
section heap1 0 8 0 0 0 0 0 0 !
/erc32/v2_0/include/hal_cache.h
0,0 → 1,182
#ifndef CYGONCE_HAL_CACHE_H
#define CYGONCE_HAL_CACHE_H
 
//=============================================================================
//
// hal_cache.h
//
// HAL Cache control support (such as it is in the simulator)
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// the caches.
//
// Usage:
// #include <cyg/hal/hal_cache.h>
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <pkgconf/hal.h>
#include <pkgconf/hal_sparc.h>
 
#include <cyg/infra/cyg_type.h>
 
//-----------------------------------------------------------------------------
// SPARC cache macros
 
//-----------------------------------------------------------------------------
// Cache dimensions
 
// Data cache
#define HAL_DCACHE_SIZE 0x800 // Size of data cache in bytes
#define HAL_DCACHE_LINE_SIZE 4 // Size of a data cache line
#define HAL_DCACHE_WAYS 4 // Associativity of the cache
 
// Instruction cache
#define HAL_ICACHE_SIZE 0x800 // Size of cache in bytes
#define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
 
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 
//-----------------------------------------------------------------------------
// Global control of data cache
 
// Enable the data cache
#define HAL_DCACHE_ENABLE()
// Disable the data cache
#define HAL_DCACHE_DISABLE()
// Invalidate the entire cache
#define HAL_DCACHE_INVALIDATE_ALL()
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC()
 
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
 
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
 
//#define HAL_DCACHE_WRITETHRU_MODE 0
//#define HAL_DCACHE_WRITEBACK_MODE 1
 
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Data cache line control
 
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
 
// Write dirty cache lines to memory for the given address range.
//#define HAL_DCACHE_STORE( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
// Global control of Instruction cache - use Data cache controls since they
// are not separatable.
 
// Enable the instruction cache
#define HAL_ICACHE_ENABLE() HAL_DCACHE_ENABLE()
 
// Disable the instruction cache
#define HAL_ICACHE_DISABLE() HAL_DCACHE_DISABLE()
 
// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL() HAL_DCACHE_SYNC(); HAL_DCACHE_INVALIDATE_ALL()
 
// Synchronize the contents of the cache with memory.
#define HAL_ICACHE_SYNC()
 
// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_size_)
 
// Load the contents of the given address range into the instruction cache
// and then lock the cache so that it stays there.
//#define HAL_ICACHE_LOCK(_base_, _size_)
 
// Undo a previous lock operation
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
 
// Unlock entire cache
//#define HAL_ICACHE_UNLOCK_ALL()
 
//-----------------------------------------------------------------------------
// Instruction cache line control
 
// Invalidate cache lines in the given range without writing to memory.
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
/erc32/v2_0/include/hal_xpic.h
0,0 → 1,120
#ifndef CYGONCE_HAL_XPIC_H
#define CYGONCE_HAL_XPIC_H
 
//=============================================================================
//
// hal_xpic.h
//
// HAL eXternal Programmable Interrupt Controller support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): nickg, gthomas, hmt
// Contributors: nickg, gthomas, hmt
// Date: 1999-01-28
// Purpose: Define Interrupt support
// Description: The macros defined here provide the HAL APIs for handling
// an external interrupt controller, and which interrupt is
// used for what.
//
// Usage:
// #include <cyg/hal/hal_intr.h> // which includes this file
// ...
//
//
//####DESCRIPTIONEND####
//
//=============================================================================
 
#include <cyg/hal/hal_io.h>
 
//-----------------------------------------------------------------------------
// Interrupt controller access
 
// in erc32 simulator:
// 4 = UART A
// 5 = UART B
// 7 = UART error
// 12 = GPT (general purpose timer)
// 13 = RTC (realtime clock)
// 15 = watchdog
 
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_13
 
 
/* These must be accessed word-wide to work! */
#define SPARC_MEC_INTCON (0x01f80000)
 
#define SPARC_MEC_INTCON_PENDING (SPARC_MEC_INTCON + 0x48)
#define SPARC_MEC_INTCON_MASK (SPARC_MEC_INTCON + 0x4c)
#define SPARC_MEC_INTCON_CLEAR (SPARC_MEC_INTCON + 0x50)
#define SPARC_MEC_INTCON_FORCE (SPARC_MEC_INTCON + 0x54)
 
 
#define HAL_INTERRUPT_MASK( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_, _mask_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_READ_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \
_mask_ |= ( 1 << (_vector_) ); \
HAL_WRITE_UINT32(SPARC_MEC_INTCON_MASK, _mask_ ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_UNMASK( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_, _mask_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_READ_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \
_mask_ &=~ ( 1 << (_vector_) ); \
HAL_WRITE_UINT32( SPARC_MEC_INTCON_MASK, _mask_ ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) CYG_MACRO_START \
cyg_uint32 _traps_; \
HAL_DISABLE_TRAPS( _traps_ ); \
HAL_WRITE_UINT32( SPARC_MEC_INTCON_CLEAR, ( 1 << (_vector_) ) ); \
HAL_RESTORE_INTERRUPTS( _traps_ ); \
CYG_MACRO_END
 
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) /* nothing */
 
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) /* nothing */
 
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_XPIC_H
// End of hal_xpic.h
/erc32/v2_0/include/hal_diag.h
0,0 → 1,136
#ifndef CYGONCE_HAL_HAL_DIAG_H
#define CYGONCE_HAL_HAL_DIAG_H
 
/*=============================================================================
//
// hal_diag.h
//
// HAL Support for Kernel Diagnostic Routines
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-01-11
// Purpose: HAL Support for Kernel Diagnostic Routines
// Description: Diagnostic routines for use during kernel development.
// Usage: #include <cyg/hal/hal_diag.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
 
#include <pkgconf/hal.h>
 
#include <cyg/infra/cyg_type.h>
 
/*---------------------------------------------------------------------------*/
 
#define CYG_DIAG_USE_ERC32
 
/*---------------------------------------------------------------------------*/
 
#ifdef CYG_DIAG_USE_ERC32
 
/*---------------------------------------------------------------------------*/
/* Register addresses */
 
#define SPARC_MEC_UART (0x01f800e0)
 
/* These must be accessed word-wide to work! */
#define SPARC_MEC_UART_IO( x ) ((cyg_uint32)(x))
 
#define SPARC_MEC_UART_A_RX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 0))
#define SPARC_MEC_UART_A_TX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 0))
#define SPARC_MEC_UART_B_RX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 4))
#define SPARC_MEC_UART_B_TX ((volatile cyg_uint32 *)(SPARC_MEC_UART + 4))
#define SPARC_MEC_UART_STATUS ((volatile cyg_uint32 *)(SPARC_MEC_UART + 8))
#define SPARC_MEC_UART_TXAMASK (0x00004)
#define SPARC_MEC_UART_TXBMASK (0x40000)
#define SPARC_MEC_UART_RXAMASK (0x00001)
#define SPARC_MEC_UART_RXBMASK (0x10000)
 
/*---------------------------------------------------------------------------*/
 
#define HAL_DIAG_INIT()
 
#define HAL_DIAG_WRITE_CHAR(_c_) \
{ \
if( 1 || _c_ != '\r' ) \
{ \
while( (SPARC_MEC_UART_TXAMASK & *SPARC_MEC_UART_STATUS) == 0 ) \
continue; \
*SPARC_MEC_UART_A_TX = SPARC_MEC_UART_IO(_c_); \
} \
}
 
#define HAL_DIAG_READ_CHAR(_c_) \
{ \
while( (SPARC_MEC_UART_RXAMASK & *SPARC_MEC_UART_STATUS) == 0 ) \
continue; \
_c_ = (char)*SPARC_MEC_UART_A_TX; \
}
 
#define XHAL_DIAG_WRITE_CHAR(_c_) \
{ \
if( _c_ != '\r' ) \
{ \
*SPARC_MEC_UART_A_TX = SPARC_MEC_UART_IO(_c_); \
} \
}
 
#define XHAL_DIAG_READ_CHAR(_c_) \
{ \
_c_ = (char)*SPARC_MEC_UART_A_TX; \
}
 
#else
/*---------------------------------------------------------------------------*/
/* There is no diagnostic output on SPARC simulator */
 
#define HAL_DIAG_INIT()
 
#define HAL_DIAG_WRITE_CHAR(_c_)
 
#define HAL_DIAG_READ_CHAR(_c_) (_c_) = 0
 
#endif
 
/*---------------------------------------------------------------------------*/
/* end of hal_diag.h */
#endif /* CYGONCE_HAL_HAL_DIAG_H */
/erc32/v2_0/ChangeLog
0,0 → 1,48
2002-10-19 Jonathan Larmour <jifl@eCosCentric.com>
 
Patch from Jiri Gaisler:
* cdl/hal_sparc_erc32.cdl: -msoft-float should be used in global
CFLAGS, not just locally.
* include/hal_diag.h: Fix UART TX masks.
 
2002-03-14 Jiri Gaisler <jiri@gaisler.com>
 
* Initial version based on the SPARClite SIM HAL.
 
 
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
 
//EOF ChangeLog
/erc32/v2_0/src/hal_priv.c
0,0 → 1,103
//===========================================================================
//
// hal_priv.c
//
// SPARC ERC32 Architecture sim-specific private variables
//
//===========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt
// Contributors: hmt
// Date: 1999-02-20
// Purpose: private vars for SPARC ERC32.
//
//####DESCRIPTIONEND####
//
//===========================================================================
 
 
#include <cyg/hal/hal_intr.h>
#include <cyg/hal/hal_arch.h>
 
// ------------------------------------------------------------------------
// Clock static to keep period recorded.
cyg_int32 cyg_hal_sparc_clock_period = 0;
 
// ------------------------------------------------------------------------
// Board specific startups.
 
extern void hal_board_prestart( void );
extern void hal_board_poststart( void );
 
void hal_board_prestart( void )
{
}
 
void hal_board_poststart( void )
{
HAL_ENABLE_INTERRUPTS();
// OK to do this post constructors, and good for testing.
}
 
cyg_uint32
hal_lsbit_index(cyg_uint32 mask)
{
int i;
for (i = 0; i < 32; i++) {
if (mask & (1<<i)) return ((cyg_uint32)i);
}
return ((cyg_uint32)-1);
}
 
cyg_uint32
hal_msbit_index(cyg_uint32 mask)
{
int i;
for (i = 31; i >= 0; i--) {
if (mask & (1<<i)) return ((cyg_uint32)i);
}
return ((cyg_uint32)-1);
}
 
void
hal_idle_thread_action(cyg_uint32 loop_count)
{
*((volatile cyg_uint32 *) 0x01f80008) = 0;
}
 
 
// EOF hal_priv.c

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