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/openrisc/trunk/rtos/freertos-6.1.1/Demo/CORTEX_EFMG890F128_IAR
- from Rev 596 to Rev 597
- ↔ Reverse comparison
Rev 596 → Rev 597
CMSIS Debug Support
+ ++ +
Cortex-M3 ITM Debug Access
++ The Cortex-M3 incorporates the Instrumented Trace Macrocell (ITM) that provides together with + the Serial Viewer Output trace capabilities for the microcontroller system. The ITM has + 32 communication channels which are able to transmit 32 / 16 / 8 bit values; two ITM + communication channels are used by CMSIS to output the following information: +
+-
+
- ITM Channel 0: used for printf-style output via the debug interface. +
- ITM Channel 31: is reserved for RTOS kernel awareness debugging. +
Debug IN / OUT functions
+CMSIS provides following debug functions:
+-
+
- ITM_SendChar (uses ITM channel 0) +
- ITM_ReceiveChar (uses global variable) +
- ITM_CheckChar (uses global variable) +
ITM_SendChar
+
+ ITM_SendChar is used to transmit a character over ITM channel 0 from
+ the microcontroller system to the debug system.
+ Only a 8 bit value is transmitted.
+
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ /* check if debugger connected and ITM channel enabled for tracing */
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+ITM_ReceiveChar
++ ITM communication channel is only capable for OUT direction. For IN direction + a globel variable is used. A simple mechansim detects if a character is received. + The project to test need to be build with debug information. +
+ ++ The globale variable ITM_RxBuffer is used to transmit a 8 bit value from debug system + to microcontroller system. ITM_RxBuffer is 32 bit wide to enshure a proper handshake. +
+
+extern volatile int ITM_RxBuffer; /* variable to receive characters */
+
++ A dedicated bit pattern is used to determin if ITM_RxBuffer is empty + or contains a valid value. +
+
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /* value identifying ITM_RxBuffer is ready for next character */
+
++ ITM_ReceiveChar is used to receive a 8 bit value from the debug system. The function is nonblocking. + It returns the received character or '-1' if no character was available. +
+
+static __INLINE int ITM_ReceiveChar (void) {
+ int ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+ITM_CheckChar
++ ITM_CheckChar is used to check if a character is received. +
+
+static __INLINE int ITM_CheckChar (void) {
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+ return (0); /* no character available */
+ } else {
+ return (1); /* character available */
+ }
+}
+
+
+ITM Debug Support in uVision
++ uVision uses in a debug session the Debug (printf) Viewer window to + display the debug data. +
+Direction microcontroller system -> uVision:
+-
+
- + Characters received via ITM communication channel 0 are written in a printf style + to Debug (printf) Viewer window. + +
Direction uVision -> microcontroller system:
+-
+
- Check if ITM_RxBuffer variable is available (only performed once). +
- Read character from Debug (printf) Viewer window. +
- If ITM_RxBuffer empty write character to ITM_RxBuffer. +
Note
+-
+
Current solution does not use a buffer machanism for trasmitting the characters.
+
+
RTX Kernel awareness in uVision
+
+ uVision / RTX are using a simple and efficient solution for RTX Kernel awareness.
+ No format overhead is necessary.
+ uVsion debugger decodes the RTX events via the 32 / 16 / 8 bit ITM write access
+ to ITM communication channel 31.
+
Following RTX events are traced:
+-
+
- Task Create / Delete event
+
-
+
- 32 bit access. Task start address is transmitted +
- 16 bit access. Task ID and Create/Delete flag are transmitted
+ High byte holds Create/Delete flag, Low byte holds TASK ID. +
+
+ - Task switch event
+
-
+
- 8 bit access. Task ID of current task is transmitted +
+
Note
+-
+
Other RTOS information could be retrieved via memory read access in a polling mode manner.
+
+
+ +
+ +
Copyright © KEIL - An ARM Company.
+All rights reserved.
+Visit our web site at www.keil.com.
+
Changes to CMSIS version V1.20
+ ++ +
1. Removed CMSIS Middelware packages
++ CMSIS Middleware is on hold from ARM side until a agreement between all CMSIS partners is found. +
+ +2. SystemFrequency renamed to SystemCoreClock
++ The variable name SystemCoreClock is more precise than SystemFrequency + because the variable holds the clock value at which the core is running. +
+ +3. Changed startup concept
++ The old startup concept (calling SystemInit_ExtMemCtl from startup file and calling SystemInit + from main) has the weakness that it does not work for controllers which need a already + configuerd clock system to configure the external memory controller. +
+ +Changed startup concept
+-
+
- + SystemInit() is called from startup file before premain. + +
- + SystemInit() configures the clock system and also configures + an existing external memory controller. + +
- + SystemInit() must not use global variables. + +
- + SystemCoreClock is initialized with a correct predefined value. + +
-
+ Additional function void SystemCoreClockUpdate (void) is provided.
+ SystemCoreClockUpdate() updates the variable SystemCoreClock + and must be called whenever the core clock is changed.
+ SystemCoreClockUpdate() evaluates the clock register settings and calculates + the current core clock. +
+
4. Advanced Debug Functions
++ ITM communication channel is only capable for OUT direction. To allow also communication for + IN direction a simple concept is provided. +
+-
+
- + Global variable volatile int ITM_RxBuffer used for IN data. + +
- + Function int ITM_CheckChar (void) checks if a new character is available. + +
- + Function int ITM_ReceiveChar (void) retrieves the new character. + +
+ For detailed explanation see file CMSIS debug support.htm. +
+ + +5. Core Register Bit Definitions
++ Files core_cm3.h and core_cm0.h contain now bit definitions for Core Registers. The name for the + defines correspond with the Cortex-M Technical Reference Manual. +
++ e.g. SysTick structure with bit definitions +
+
+/** @addtogroup CMSIS_CM3_SysTick CMSIS CM3 SysTick
+ memory mapped structure for SysTick
+ @{
+ */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< Offset: 0x00 SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< Offset: 0x04 SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< Offset: 0x08 SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< Offset: 0x0C SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1ul << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1ul << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1ul << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1ul << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFul << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1ul << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1ul << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFul << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
+/*@}*/ /* end of group CMSIS_CM3_SysTick */
+
+7. DoxyGen Tags
++ DoxyGen tags in files core_cm3.[c,h] and core_cm0.[c,h] are reworked to create proper documentation + using DoxyGen. +
+ +8. Folder Structure
++ The folder structure is changed to differentiate the single support packages. +
+ +-
+
- CM0 +
- CM3
+
-
+
- CoreSupport +
- DeviceSupport +
- Vendor
+
-
+
- Device
+
-
+
- Startup
+
-
+
- Toolchain +
- Toolchain +
- ... +
+
+ - Startup
+
- Device +
- ... +
+ - Device
+
- Vendor +
- ... +
-
+
+ - Example
+
-
+
- Toolchain
+
-
+
- Device +
- Device +
- ... +
+ - Toolchain +
- ... +
+ - Toolchain
+
9. Open Points
++ Following points need to be clarified and solved: +
+-
+
-
+
+ Equivalent C and Assembler startup files. +
++ Is there a need for having C startup files although assembler startup files are + very efficient and do not need to be changed? +
+
+ -
+
+ Placing of HEAP in external RAM. +
++ It must be possible to place HEAP in external RAM if the device supports an + external memory controller. +
+
+ -
+
+ Placing of STACK /HEAP. +
++ STACK should always be placed at the end of internal RAM. +
++ If HEAP is placed in internal RAM than it should be placed after RW ZI section. +
+
+ -
+
+ Removing core_cm3.c and core_cm0.c. +
++ On a long term the functions in core_cm3.c and core_cm0.c must be replaced with + appropriate compiler intrinsics. +
+
+
10. Limitations
++ The following limitations are not covered with the current CMSIS version: +
+-
+
- + No C startup files for ARM toolchain are provided. + +
- + No C startup files for GNU toolchain are provided. + +
- + No C startup files for IAR toolchain are provided. + +
- + No Tasking projects are provided yet. + +