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/drivers/LuminaryMicro/hw_nvic.h
0,0 → 1,1024
//***************************************************************************** |
// |
// hw_nvic.h - Macros used when accessing the NVIC hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_NVIC_H__ |
#define __HW_NVIC_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the NVIC register addresses. |
// |
//***************************************************************************** |
#define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg. |
#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status Reg. |
#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register |
#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register |
#define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg. |
#define NVIC_EN0 0xE000E100 // IRQ 0 to 31 Set Enable Register |
#define NVIC_EN1 0xE000E104 // IRQ 32 to 63 Set Enable Register |
#define NVIC_DIS0 0xE000E180 // IRQ 0 to 31 Clear Enable Reg. |
#define NVIC_DIS1 0xE000E184 // IRQ 32 to 63 Clear Enable Reg. |
#define NVIC_PEND0 0xE000E200 // IRQ 0 to 31 Set Pending Register |
#define NVIC_PEND1 0xE000E204 // IRQ 32 to 63 Set Pending Reg. |
#define NVIC_UNPEND0 0xE000E280 // IRQ 0 to 31 Clear Pending Reg. |
#define NVIC_UNPEND1 0xE000E284 // IRQ 32 to 63 Clear Pending Reg. |
#define NVIC_ACTIVE0 0xE000E300 // IRQ 0 to 31 Active Register |
#define NVIC_ACTIVE1 0xE000E304 // IRQ 32 to 63 Active Register |
#define NVIC_PRI0 0xE000E400 // IRQ 0 to 3 Priority Register |
#define NVIC_PRI1 0xE000E404 // IRQ 4 to 7 Priority Register |
#define NVIC_PRI2 0xE000E408 // IRQ 8 to 11 Priority Register |
#define NVIC_PRI3 0xE000E40C // IRQ 12 to 15 Priority Register |
#define NVIC_PRI4 0xE000E410 // IRQ 16 to 19 Priority Register |
#define NVIC_PRI5 0xE000E414 // IRQ 20 to 23 Priority Register |
#define NVIC_PRI6 0xE000E418 // IRQ 24 to 27 Priority Register |
#define NVIC_PRI7 0xE000E41C // IRQ 28 to 31 Priority Register |
#define NVIC_PRI8 0xE000E420 // IRQ 32 to 35 Priority Register |
#define NVIC_PRI9 0xE000E424 // IRQ 36 to 39 Priority Register |
#define NVIC_PRI10 0xE000E428 // IRQ 40 to 43 Priority Register |
#define NVIC_PRI11 0xE000E42C // IRQ 44 to 47 Priority Register |
#define NVIC_CPUID 0xE000ED00 // CPUID Base Register |
#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control State Register |
#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset Register |
#define NVIC_APINT 0xE000ED0C // App. Int & Reset Control Reg. |
#define NVIC_SYS_CTRL 0xE000ED10 // System Control Register |
#define NVIC_CFG_CTRL 0xE000ED14 // Configuration Control Register |
#define NVIC_SYS_PRI1 0xE000ED18 // Sys. Handlers 4 to 7 Priority |
#define NVIC_SYS_PRI2 0xE000ED1C // Sys. Handlers 8 to 11 Priority |
#define NVIC_SYS_PRI3 0xE000ED20 // Sys. Handlers 12 to 15 Priority |
#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State |
#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status Reg. |
#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status Register |
#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register |
#define NVIC_MM_ADDR 0xE000ED34 // Mem Manage Address Register |
#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address Register |
#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type Register |
#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control Register |
#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number Register |
#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address Register |
#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute & Size Reg. |
#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg. |
#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select |
#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data |
#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control |
#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt Reg. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_INT_TYPE register. |
// |
//***************************************************************************** |
#define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) |
#define NVIC_INT_TYPE_LINES_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ST_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_ST_CTRL_COUNT 0x00010000 // Count flag |
#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source |
#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt enable |
#define NVIC_ST_CTRL_ENABLE 0x00000001 // Counter mode |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ST_RELOAD register. |
// |
//***************************************************************************** |
#define NVIC_ST_RELOAD_M 0x00FFFFFF // Counter load value |
#define NVIC_ST_RELOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ST_CURRENT |
// register. |
// |
//***************************************************************************** |
#define NVIC_ST_CURRENT_M 0x00FFFFFF // Counter current value |
#define NVIC_ST_CURRENT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ST_CAL register. |
// |
//***************************************************************************** |
#define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock |
#define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew |
#define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value |
#define NVIC_ST_CAL_ONEMS_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_EN0 register. |
// |
//***************************************************************************** |
#define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable |
#define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable |
#define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable |
#define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable |
#define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable |
#define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable |
#define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable |
#define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable |
#define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable |
#define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable |
#define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable |
#define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable |
#define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable |
#define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable |
#define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable |
#define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable |
#define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable |
#define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable |
#define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable |
#define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable |
#define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable |
#define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable |
#define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable |
#define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable |
#define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable |
#define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable |
#define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable |
#define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable |
#define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable |
#define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable |
#define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable |
#define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_EN1 register. |
// |
//***************************************************************************** |
#define NVIC_EN1_INT59 0x08000000 // Interrupt 59 enable |
#define NVIC_EN1_INT58 0x04000000 // Interrupt 58 enable |
#define NVIC_EN1_INT57 0x02000000 // Interrupt 57 enable |
#define NVIC_EN1_INT56 0x01000000 // Interrupt 56 enable |
#define NVIC_EN1_INT55 0x00800000 // Interrupt 55 enable |
#define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable |
#define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable |
#define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable |
#define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable |
#define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable |
#define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable |
#define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable |
#define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable |
#define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable |
#define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable |
#define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable |
#define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable |
#define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable |
#define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable |
#define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable |
#define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable |
#define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable |
#define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable |
#define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable |
#define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable |
#define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable |
#define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable |
#define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DIS0 register. |
// |
//***************************************************************************** |
#define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable |
#define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable |
#define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable |
#define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable |
#define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable |
#define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable |
#define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable |
#define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable |
#define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable |
#define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable |
#define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable |
#define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable |
#define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable |
#define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable |
#define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable |
#define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable |
#define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable |
#define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable |
#define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable |
#define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable |
#define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable |
#define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable |
#define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable |
#define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable |
#define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable |
#define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable |
#define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable |
#define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable |
#define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable |
#define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable |
#define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable |
#define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DIS1 register. |
// |
//***************************************************************************** |
#define NVIC_DIS1_INT59 0x08000000 // Interrupt 59 disable |
#define NVIC_DIS1_INT58 0x04000000 // Interrupt 58 disable |
#define NVIC_DIS1_INT57 0x02000000 // Interrupt 57 disable |
#define NVIC_DIS1_INT56 0x01000000 // Interrupt 56 disable |
#define NVIC_DIS1_INT55 0x00800000 // Interrupt 55 disable |
#define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable |
#define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable |
#define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable |
#define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable |
#define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable |
#define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable |
#define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable |
#define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable |
#define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable |
#define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable |
#define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable |
#define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable |
#define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable |
#define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable |
#define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable |
#define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable |
#define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable |
#define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable |
#define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable |
#define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable |
#define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable |
#define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable |
#define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PEND0 register. |
// |
//***************************************************************************** |
#define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend |
#define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend |
#define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend |
#define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend |
#define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend |
#define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend |
#define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend |
#define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend |
#define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend |
#define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend |
#define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend |
#define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend |
#define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend |
#define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend |
#define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend |
#define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend |
#define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend |
#define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend |
#define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend |
#define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend |
#define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend |
#define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend |
#define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend |
#define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend |
#define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend |
#define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend |
#define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend |
#define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend |
#define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend |
#define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend |
#define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend |
#define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PEND1 register. |
// |
//***************************************************************************** |
#define NVIC_PEND1_INT59 0x08000000 // Interrupt 59 pend |
#define NVIC_PEND1_INT58 0x04000000 // Interrupt 58 pend |
#define NVIC_PEND1_INT57 0x02000000 // Interrupt 57 pend |
#define NVIC_PEND1_INT56 0x01000000 // Interrupt 56 pend |
#define NVIC_PEND1_INT55 0x00800000 // Interrupt 55 pend |
#define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend |
#define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend |
#define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend |
#define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend |
#define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend |
#define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend |
#define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend |
#define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend |
#define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend |
#define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend |
#define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend |
#define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend |
#define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend |
#define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend |
#define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend |
#define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend |
#define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend |
#define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend |
#define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend |
#define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend |
#define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend |
#define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend |
#define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_UNPEND0 register. |
// |
//***************************************************************************** |
#define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend |
#define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend |
#define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend |
#define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend |
#define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend |
#define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend |
#define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend |
#define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend |
#define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend |
#define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend |
#define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend |
#define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend |
#define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend |
#define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend |
#define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend |
#define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend |
#define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend |
#define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend |
#define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend |
#define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend |
#define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend |
#define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend |
#define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend |
#define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend |
#define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend |
#define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend |
#define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend |
#define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend |
#define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend |
#define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend |
#define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend |
#define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_UNPEND1 register. |
// |
//***************************************************************************** |
#define NVIC_UNPEND1_INT59 0x08000000 // Interrupt 59 unpend |
#define NVIC_UNPEND1_INT58 0x04000000 // Interrupt 58 unpend |
#define NVIC_UNPEND1_INT57 0x02000000 // Interrupt 57 unpend |
#define NVIC_UNPEND1_INT56 0x01000000 // Interrupt 56 unpend |
#define NVIC_UNPEND1_INT55 0x00800000 // Interrupt 55 unpend |
#define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend |
#define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend |
#define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend |
#define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend |
#define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend |
#define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend |
#define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend |
#define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend |
#define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend |
#define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend |
#define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend |
#define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend |
#define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend |
#define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend |
#define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend |
#define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend |
#define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend |
#define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend |
#define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend |
#define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend |
#define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend |
#define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend |
#define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ACTIVE0 register. |
// |
//***************************************************************************** |
#define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active |
#define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active |
#define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active |
#define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active |
#define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active |
#define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active |
#define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active |
#define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active |
#define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active |
#define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active |
#define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active |
#define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active |
#define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active |
#define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active |
#define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active |
#define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active |
#define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active |
#define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active |
#define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active |
#define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active |
#define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active |
#define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active |
#define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active |
#define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active |
#define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active |
#define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active |
#define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active |
#define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active |
#define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active |
#define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active |
#define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active |
#define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_ACTIVE1 register. |
// |
//***************************************************************************** |
#define NVIC_ACTIVE1_INT59 0x08000000 // Interrupt 59 active |
#define NVIC_ACTIVE1_INT58 0x04000000 // Interrupt 58 active |
#define NVIC_ACTIVE1_INT57 0x02000000 // Interrupt 57 active |
#define NVIC_ACTIVE1_INT56 0x01000000 // Interrupt 56 active |
#define NVIC_ACTIVE1_INT55 0x00800000 // Interrupt 55 active |
#define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active |
#define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active |
#define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active |
#define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active |
#define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active |
#define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active |
#define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active |
#define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active |
#define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active |
#define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active |
#define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active |
#define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active |
#define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active |
#define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active |
#define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active |
#define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active |
#define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active |
#define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active |
#define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active |
#define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active |
#define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active |
#define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active |
#define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI0 register. |
// |
//***************************************************************************** |
#define NVIC_PRI0_INT3_M 0xFF000000 // Interrupt 3 priority mask |
#define NVIC_PRI0_INT2_M 0x00FF0000 // Interrupt 2 priority mask |
#define NVIC_PRI0_INT1_M 0x0000FF00 // Interrupt 1 priority mask |
#define NVIC_PRI0_INT0_M 0x000000FF // Interrupt 0 priority mask |
#define NVIC_PRI0_INT3_S 24 |
#define NVIC_PRI0_INT2_S 16 |
#define NVIC_PRI0_INT1_S 8 |
#define NVIC_PRI0_INT0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI1 register. |
// |
//***************************************************************************** |
#define NVIC_PRI1_INT7_M 0xFF000000 // Interrupt 7 priority mask |
#define NVIC_PRI1_INT6_M 0x00FF0000 // Interrupt 6 priority mask |
#define NVIC_PRI1_INT5_M 0x0000FF00 // Interrupt 5 priority mask |
#define NVIC_PRI1_INT4_M 0x000000FF // Interrupt 4 priority mask |
#define NVIC_PRI1_INT7_S 24 |
#define NVIC_PRI1_INT6_S 16 |
#define NVIC_PRI1_INT5_S 8 |
#define NVIC_PRI1_INT4_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI2 register. |
// |
//***************************************************************************** |
#define NVIC_PRI2_INT11_M 0xFF000000 // Interrupt 11 priority mask |
#define NVIC_PRI2_INT10_M 0x00FF0000 // Interrupt 10 priority mask |
#define NVIC_PRI2_INT9_M 0x0000FF00 // Interrupt 9 priority mask |
#define NVIC_PRI2_INT8_M 0x000000FF // Interrupt 8 priority mask |
#define NVIC_PRI2_INT11_S 24 |
#define NVIC_PRI2_INT10_S 16 |
#define NVIC_PRI2_INT9_S 8 |
#define NVIC_PRI2_INT8_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI3 register. |
// |
//***************************************************************************** |
#define NVIC_PRI3_INT15_M 0xFF000000 // Interrupt 15 priority mask |
#define NVIC_PRI3_INT14_M 0x00FF0000 // Interrupt 14 priority mask |
#define NVIC_PRI3_INT13_M 0x0000FF00 // Interrupt 13 priority mask |
#define NVIC_PRI3_INT12_M 0x000000FF // Interrupt 12 priority mask |
#define NVIC_PRI3_INT15_S 24 |
#define NVIC_PRI3_INT14_S 16 |
#define NVIC_PRI3_INT13_S 8 |
#define NVIC_PRI3_INT12_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI4 register. |
// |
//***************************************************************************** |
#define NVIC_PRI4_INT19_M 0xFF000000 // Interrupt 19 priority mask |
#define NVIC_PRI4_INT18_M 0x00FF0000 // Interrupt 18 priority mask |
#define NVIC_PRI4_INT17_M 0x0000FF00 // Interrupt 17 priority mask |
#define NVIC_PRI4_INT16_M 0x000000FF // Interrupt 16 priority mask |
#define NVIC_PRI4_INT19_S 24 |
#define NVIC_PRI4_INT18_S 16 |
#define NVIC_PRI4_INT17_S 8 |
#define NVIC_PRI4_INT16_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI5 register. |
// |
//***************************************************************************** |
#define NVIC_PRI5_INT23_M 0xFF000000 // Interrupt 23 priority mask |
#define NVIC_PRI5_INT22_M 0x00FF0000 // Interrupt 22 priority mask |
#define NVIC_PRI5_INT21_M 0x0000FF00 // Interrupt 21 priority mask |
#define NVIC_PRI5_INT20_M 0x000000FF // Interrupt 20 priority mask |
#define NVIC_PRI5_INT23_S 24 |
#define NVIC_PRI5_INT22_S 16 |
#define NVIC_PRI5_INT21_S 8 |
#define NVIC_PRI5_INT20_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI6 register. |
// |
//***************************************************************************** |
#define NVIC_PRI6_INT27_M 0xFF000000 // Interrupt 27 priority mask |
#define NVIC_PRI6_INT26_M 0x00FF0000 // Interrupt 26 priority mask |
#define NVIC_PRI6_INT25_M 0x0000FF00 // Interrupt 25 priority mask |
#define NVIC_PRI6_INT24_M 0x000000FF // Interrupt 24 priority mask |
#define NVIC_PRI6_INT27_S 24 |
#define NVIC_PRI6_INT26_S 16 |
#define NVIC_PRI6_INT25_S 8 |
#define NVIC_PRI6_INT24_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI7 register. |
// |
//***************************************************************************** |
#define NVIC_PRI7_INT31_M 0xFF000000 // Interrupt 31 priority mask |
#define NVIC_PRI7_INT30_M 0x00FF0000 // Interrupt 30 priority mask |
#define NVIC_PRI7_INT29_M 0x0000FF00 // Interrupt 29 priority mask |
#define NVIC_PRI7_INT28_M 0x000000FF // Interrupt 28 priority mask |
#define NVIC_PRI7_INT31_S 24 |
#define NVIC_PRI7_INT30_S 16 |
#define NVIC_PRI7_INT29_S 8 |
#define NVIC_PRI7_INT28_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI8 register. |
// |
//***************************************************************************** |
#define NVIC_PRI8_INT35_M 0xFF000000 // Interrupt 35 priority mask |
#define NVIC_PRI8_INT34_M 0x00FF0000 // Interrupt 34 priority mask |
#define NVIC_PRI8_INT33_M 0x0000FF00 // Interrupt 33 priority mask |
#define NVIC_PRI8_INT32_M 0x000000FF // Interrupt 32 priority mask |
#define NVIC_PRI8_INT35_S 24 |
#define NVIC_PRI8_INT34_S 16 |
#define NVIC_PRI8_INT33_S 8 |
#define NVIC_PRI8_INT32_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI9 register. |
// |
//***************************************************************************** |
#define NVIC_PRI9_INT39_M 0xFF000000 // Interrupt 39 priority mask |
#define NVIC_PRI9_INT38_M 0x00FF0000 // Interrupt 38 priority mask |
#define NVIC_PRI9_INT37_M 0x0000FF00 // Interrupt 37 priority mask |
#define NVIC_PRI9_INT36_M 0x000000FF // Interrupt 36 priority mask |
#define NVIC_PRI9_INT39_S 24 |
#define NVIC_PRI9_INT38_S 16 |
#define NVIC_PRI9_INT37_S 8 |
#define NVIC_PRI9_INT36_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_PRI10 register. |
// |
//***************************************************************************** |
#define NVIC_PRI10_INT43_M 0xFF000000 // Interrupt 43 priority mask |
#define NVIC_PRI10_INT42_M 0x00FF0000 // Interrupt 42 priority mask |
#define NVIC_PRI10_INT41_M 0x0000FF00 // Interrupt 41 priority mask |
#define NVIC_PRI10_INT40_M 0x000000FF // Interrupt 40 priority mask |
#define NVIC_PRI10_INT43_S 24 |
#define NVIC_PRI10_INT42_S 16 |
#define NVIC_PRI10_INT41_S 8 |
#define NVIC_PRI10_INT40_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_CPUID register. |
// |
//***************************************************************************** |
#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer |
#define NVIC_CPUID_VAR_M 0x00F00000 // Variant |
#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Processor part number |
#define NVIC_CPUID_REV_M 0x0000000F // Revision |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_INT_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_INT_CTRL_NMI_SET 0x80000000 // Pend a NMI |
#define NVIC_INT_CTRL_PEND_SV 0x10000000 // Pend a PendSV |
#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // Unpend a PendSV |
#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug interrupt handling |
#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Debug interrupt pending |
#define NVIC_INT_CTRL_VEC_PEN_M 0x003FF000 // Highest pending exception |
#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to base |
#define NVIC_INT_CTRL_VEC_ACT_M 0x000003FF // Current active exception |
#define NVIC_INT_CTRL_VEC_PEN_S 12 |
#define NVIC_INT_CTRL_VEC_ACT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_VTABLE register. |
// |
//***************************************************************************** |
#define NVIC_VTABLE_BASE 0x20000000 // Vector table base |
#define NVIC_VTABLE_OFFSET_M 0x1FFFFF00 // Vector table offset |
#define NVIC_VTABLE_OFFSET_S 8 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_APINT register. |
// |
//***************************************************************************** |
#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Vector key mask |
#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key |
#define NVIC_APINT_ENDIANESS 0x00008000 // Data endianess |
#define NVIC_APINT_PRIGROUP_M 0x00000700 // Priority group |
#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split |
#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split |
#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split |
#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split |
#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split |
#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split |
#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split |
#define NVIC_APINT_SYSRESETREQ 0x00000004 // System reset request |
#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear active NMI/fault info |
#define NVIC_APINT_VECT_RESET 0x00000001 // System reset |
#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SYS_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wakeup on pend |
#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep sleep enable |
#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR exit |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_CFG_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore bus fault in NMI/fault |
#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on divide by 0 |
#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on unaligned access |
#define NVIC_CFG_CTRL_DEEP_PEND 0x00000004 // Allow deep interrupt trigger |
#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow main interrupt trigger |
#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread state control |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SYS_PRI1 register. |
// |
//***************************************************************************** |
#define NVIC_SYS_PRI1_RES_M 0xFF000000 // Priority of reserved handler |
#define NVIC_SYS_PRI1_USAGE_M 0x00FF0000 // Priority of usage fault handler |
#define NVIC_SYS_PRI1_BUS_M 0x0000FF00 // Priority of bus fault handler |
#define NVIC_SYS_PRI1_MEM_M 0x000000FF // Priority of mem manage handler |
#define NVIC_SYS_PRI1_USAGE_S 16 |
#define NVIC_SYS_PRI1_BUS_S 8 |
#define NVIC_SYS_PRI1_MEM_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SYS_PRI2 register. |
// |
//***************************************************************************** |
#define NVIC_SYS_PRI2_SVC_M 0xFF000000 // Priority of SVCall handler |
#define NVIC_SYS_PRI2_RES_M 0x00FFFFFF // Priority of reserved handlers |
#define NVIC_SYS_PRI2_SVC_S 24 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SYS_PRI3 register. |
// |
//***************************************************************************** |
#define NVIC_SYS_PRI3_TICK_M 0xFF000000 // Priority of Sys Tick handler |
#define NVIC_SYS_PRI3_PENDSV_M 0x00FF0000 // Priority of PendSV handler |
#define NVIC_SYS_PRI3_RES_M 0x0000FF00 // Priority of reserved handler |
#define NVIC_SYS_PRI3_DEBUG_M 0x000000FF // Priority of debug handler |
#define NVIC_SYS_PRI3_TICK_S 24 |
#define NVIC_SYS_PRI3_PENDSV_S 16 |
#define NVIC_SYS_PRI3_DEBUG_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL |
// register. |
// |
//***************************************************************************** |
#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage fault enable |
#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus fault enable |
#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Mem manage fault enable |
#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVCall is pended |
#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus fault is pended |
#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // Sys tick is active |
#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV is active |
#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Monitor is active |
#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVCall is active |
#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage fault is active |
#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus fault is active |
#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Mem manage is active |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_FAULT_STAT |
// register. |
// |
//***************************************************************************** |
#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide by zero fault |
#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned access fault |
#define NVIC_FAULT_STAT_NOCP 0x00080000 // No coprocessor fault |
#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC fault |
#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid state fault |
#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined instruction fault |
#define NVIC_FAULT_STAT_BFARV 0x00008000 // BFAR is valid |
#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack bus fault |
#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack bus fault |
#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise data bus error |
#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise data bus error |
#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction bus fault |
#define NVIC_FAULT_STAT_MMARV 0x00000080 // MMAR is valid |
#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack access violation |
#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack access violation |
#define NVIC_FAULT_STAT_DERR 0x00000002 // Data access violation |
#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction access violation |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_HFAULT_STAT |
// register. |
// |
//***************************************************************************** |
#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug event |
#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Cannot execute fault handler |
#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector table read fault |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DEBUG_STAT |
// register. |
// |
//***************************************************************************** |
#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted |
#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch |
#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match |
#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction |
#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MM_ADDR register. |
// |
//***************************************************************************** |
#define NVIC_MM_ADDR_M 0xFFFFFFFF // Data fault address |
#define NVIC_MM_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_FAULT_ADDR |
// register. |
// |
//***************************************************************************** |
#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Data bus fault address |
#define NVIC_FAULT_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MPU_TYPE register. |
// |
//***************************************************************************** |
#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I regions |
#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D regions |
#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or unified MPU |
#define NVIC_MPU_TYPE_IREGION_S 16 |
#define NVIC_MPU_TYPE_DREGION_S 8 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MPU_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU default region in priv mode |
#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU enabled during faults |
#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MPU_NUMBER |
// register. |
// |
//***************************************************************************** |
#define NVIC_MPU_NUMBER_M 0x000000FF // MPU region to access |
#define NVIC_MPU_NUMBER_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MPU_BASE register. |
// |
//***************************************************************************** |
#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base address mask |
#define NVIC_MPU_BASE_VALID 0x00000010 // Region number valid |
#define NVIC_MPU_BASE_REGION_M 0x0000000F // Region number |
#define NVIC_MPU_BASE_ADDR_S 8 |
#define NVIC_MPU_BASE_REGION_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_MPU_ATTR register. |
// |
//***************************************************************************** |
#define NVIC_MPU_ATTR_M 0xFFFF0000 // Attributes |
#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access |
#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable |
#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable |
#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable |
#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type extension mask |
#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none |
#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only |
#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw |
#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none |
#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro |
#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access permissions mask |
#define NVIC_MPU_ATTR_XN 0x10000000 // Execute disable |
#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Sub-region disable mask |
#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable |
#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable |
#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable |
#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable |
#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable |
#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable |
#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable |
#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable |
#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region size mask |
#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes |
#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes |
#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes |
#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes |
#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes |
#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes |
#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes |
#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes |
#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes |
#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes |
#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes |
#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes |
#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes |
#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes |
#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes |
#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes |
#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes |
#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes |
#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes |
#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes |
#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes |
#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes |
#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes |
#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes |
#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes |
#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes |
#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes |
#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes |
#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DBG_CTRL register. |
// |
//***************************************************************************** |
#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask |
#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key |
#define NVIC_DBG_CTRL_MON_PEND 0x00008000 // Pend the monitor |
#define NVIC_DBG_CTRL_MON_REQ 0x00004000 // Monitor request |
#define NVIC_DBG_CTRL_MON_EN 0x00002000 // Debug monitor enable |
#define NVIC_DBG_CTRL_MONSTEP 0x00001000 // Monitor step the core |
#define NVIC_DBG_CTRL_S_SLEEP 0x00000400 // Core is sleeping |
#define NVIC_DBG_CTRL_S_HALT 0x00000200 // Core status on halt |
#define NVIC_DBG_CTRL_S_REGRDY 0x00000100 // Register read/write available |
#define NVIC_DBG_CTRL_S_LOCKUP 0x00000080 // Core is locked up |
#define NVIC_DBG_CTRL_C_RESET 0x00000010 // Reset the core |
#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping |
#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core |
#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core |
#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DBG_XFER register. |
// |
//***************************************************************************** |
#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read |
#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register |
#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask |
#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP |
#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP |
#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP |
#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register |
#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 |
#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 |
#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 |
#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 |
#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 |
#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 |
#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 |
#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 |
#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 |
#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 |
#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 |
#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 |
#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 |
#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 |
#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 |
#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DBG_DATA register. |
// |
//***************************************************************************** |
#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache |
#define NVIC_DBG_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_DBG_INT register. |
// |
//***************************************************************************** |
#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault |
#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors |
#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error |
#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state |
#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check |
#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error |
#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault |
#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status |
#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset |
#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending |
#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the NVIC_SW_TRIG register. |
// |
//***************************************************************************** |
#define NVIC_SW_TRIG_INTID_M 0x000003FF // Interrupt to trigger |
#define NVIC_SW_TRIG_INTID_S 0 |
|
#endif // __HW_NVIC_H__ |
/drivers/LuminaryMicro/rom.h
0,0 → 1,1251
//***************************************************************************** |
// |
// rom.h - Macros to facilitate calling functions in the ROM. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __ROM_H__ |
#define __ROM_H__ |
|
//***************************************************************************** |
// |
// Pointers to the main API tables. |
// |
//***************************************************************************** |
#define ROM_APITABLE ((unsigned long *)0x01000010) |
#define ROM_VERSION (ROM_APITABLE[0]) |
#define ROM_UARTTABLE ((unsigned long *)(ROM_APITABLE[1])) |
#define ROM_SSITABLE ((unsigned long *)(ROM_APITABLE[2])) |
#define ROM_I2CTABLE ((unsigned long *)(ROM_APITABLE[3])) |
#define ROM_GPIOTABLE ((unsigned long *)(ROM_APITABLE[4])) |
#define ROM_ADCTABLE ((unsigned long *)(ROM_APITABLE[5])) |
#define ROM_COMPARATORTABLE ((unsigned long *)(ROM_APITABLE[6])) |
#define ROM_FLASHTABLE ((unsigned long *)(ROM_APITABLE[7])) |
#define ROM_PWMTABLE ((unsigned long *)(ROM_APITABLE[8])) |
#define ROM_QEITABLE ((unsigned long *)(ROM_APITABLE[9])) |
#define ROM_SYSTICKTABLE ((unsigned long *)(ROM_APITABLE[10])) |
#define ROM_TIMERTABLE ((unsigned long *)(ROM_APITABLE[11])) |
#define ROM_WATCHDOGTABLE ((unsigned long *)(ROM_APITABLE[12])) |
#define ROM_SYSCTLTABLE ((unsigned long *)(ROM_APITABLE[13])) |
#define ROM_INTERRUPTTABLE ((unsigned long *)(ROM_APITABLE[14])) |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the ADC API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceDataGet \ |
((long (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum, \ |
unsigned long *pulBuffer))ROM_ADCTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum, \ |
tBoolean bMasked))ROM_ADCTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum, \ |
unsigned long ulTrigger, \ |
unsigned long ulPriority))ROM_ADCTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceStepConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum, \ |
unsigned long ulStep, \ |
unsigned long ulConfig))ROM_ADCTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceOverflow \ |
((long (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceOverflowClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceUnderflow \ |
((long (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCSequenceUnderflowClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCProcessorTrigger \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSequenceNum))ROM_ADCTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ADCHardwareOversampleConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulFactor))ROM_ADCTABLE[14]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the Comparator API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulComp))ROM_COMPARATORTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulComp, \ |
unsigned long ulConfig))ROM_COMPARATORTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorRefSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulRef))ROM_COMPARATORTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorValueGet \ |
((tBoolean (*)(unsigned long ulBase, \ |
unsigned long ulComp))ROM_COMPARATORTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulComp))ROM_COMPARATORTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulComp))ROM_COMPARATORTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_ComparatorIntStatus \ |
((tBoolean (*)(unsigned long ulBase, \ |
unsigned long ulComp, \ |
tBoolean bMasked))ROM_COMPARATORTABLE[6]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the Flash API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashProgram \ |
((long (*)(unsigned long *pulData, \ |
unsigned long ulAddress, \ |
unsigned long ulCount))ROM_FLASHTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashUsecGet \ |
((unsigned long (*)(void))ROM_FLASHTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashUsecSet \ |
((void (*)(unsigned long ulClocks))ROM_FLASHTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashErase \ |
((long (*)(unsigned long ulAddress))ROM_FLASHTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashProtectGet \ |
((tFlashProtection (*)(unsigned long ulAddress))ROM_FLASHTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashProtectSet \ |
((long (*)(unsigned long ulAddress, \ |
tFlashProtection eProtect))ROM_FLASHTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashProtectSave \ |
((long (*)(void))ROM_FLASHTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashUserGet \ |
((long (*)(unsigned long *pulUser0, \ |
unsigned long *pulUser1))ROM_FLASHTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashUserSet \ |
((long (*)(unsigned long ulUser0, \ |
unsigned long ulUser1))ROM_FLASHTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashUserSave \ |
((long (*)(void))ROM_FLASHTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashIntEnable \ |
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashIntDisable \ |
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashIntGetStatus \ |
((unsigned long (*)(tBoolean bMasked))ROM_FLASHTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_FlashIntClear \ |
((void (*)(unsigned long ulIntFlags))ROM_FLASHTABLE[13]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the GPIO API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinWrite \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins, \ |
unsigned char ucVal))ROM_GPIOTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIODirModeSet \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins, \ |
unsigned long ulPinIO))ROM_GPIOTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIODirModeGet \ |
((unsigned long (*)(unsigned long ulPort, \ |
unsigned char ucPin))ROM_GPIOTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOIntTypeSet \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins, \ |
unsigned long ulIntType))ROM_GPIOTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOIntTypeGet \ |
((unsigned long (*)(unsigned long ulPort, \ |
unsigned char ucPin))ROM_GPIOTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPadConfigSet \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins, \ |
unsigned long ulStrength, \ |
unsigned long ulPadType))ROM_GPIOTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPadConfigGet \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPin, \ |
unsigned long *pulStrength, \ |
unsigned long *pulPadType))ROM_GPIOTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinIntEnable \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinIntDisable \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinIntStatus \ |
((long (*)(unsigned long ulPort, \ |
tBoolean bMasked))ROM_GPIOTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinIntClear \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinRead \ |
((long (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeCAN \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeComparator \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeGPIOInput \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeGPIOOutput \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeI2C \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypePWM \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeQEI \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeSSI \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeTimer \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeUART \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[21]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_GPIOPinTypeGPIOOutputOD \ |
((void (*)(unsigned long ulPort, \ |
unsigned char ucPins))ROM_GPIOTABLE[22]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the I2C API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterDataPut \ |
((void (*)(unsigned long ulBase, \ |
unsigned char ucData))ROM_I2CTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterInitExpClk \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulI2CClk, \ |
tBoolean bFast))ROM_I2CTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveInit \ |
((void (*)(unsigned long ulBase, \ |
unsigned char ucSlaveAddr))ROM_I2CTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterEnable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveEnable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterDisable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveDisable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterIntEnable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveIntEnable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterIntDisable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveIntDisable \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterIntStatus \ |
((tBoolean (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_I2CTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveIntStatus \ |
((tBoolean (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_I2CTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterIntClear \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveIntClear \ |
((void (*)(unsigned long ulBase))ROM_I2CTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterSlaveAddrSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned char ucSlaveAddr, \ |
tBoolean bReceive))ROM_I2CTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterBusy \ |
((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterBusBusy \ |
((tBoolean (*)(unsigned long ulBase))ROM_I2CTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterControl \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulCmd))ROM_I2CTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterErr \ |
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CMasterDataGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveStatus \ |
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[21]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveDataPut \ |
((void (*)(unsigned long ulBase, \ |
unsigned char ucData))ROM_I2CTABLE[22]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_I2CSlaveDataGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_I2CTABLE[23]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UpdateI2C \ |
((void (*)(void))ROM_I2CTABLE[24]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the Interrupt API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntEnable \ |
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntDisable \ |
((void (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntPriorityGroupingSet \ |
((void (*)(unsigned long ulBits))ROM_INTERRUPTTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntPriorityGroupingGet \ |
((unsigned long (*)(void))ROM_INTERRUPTTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntPrioritySet \ |
((void (*)(unsigned long ulInterrupt, \ |
unsigned char ucPriority))ROM_INTERRUPTTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_IntPriorityGet \ |
((long (*)(unsigned long ulInterrupt))ROM_INTERRUPTTABLE[7]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the PWM API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMPulseWidthSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPWMOut, \ |
unsigned long ulWidth))ROM_PWMTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned long ulConfig))ROM_PWMTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenPeriodSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned long ulPeriod))ROM_PWMTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenPeriodGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulGen))ROM_PWMTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen))ROM_PWMTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen))ROM_PWMTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMPulseWidthGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulPWMOut))ROM_PWMTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMDeadBandEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned short usRise, \ |
unsigned short usFall))ROM_PWMTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMDeadBandDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen))ROM_PWMTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMSyncUpdate \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGenBits))ROM_PWMTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMSyncTimeBase \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGenBits))ROM_PWMTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMOutputState \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPWMOutBits, \ |
tBoolean bEnable))ROM_PWMTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMOutputInvert \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPWMOutBits, \ |
tBoolean bInvert))ROM_PWMTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMOutputFault \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPWMOutBits, \ |
tBoolean bFaultSuppress))ROM_PWMTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenIntTrigEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned long ulIntTrig))ROM_PWMTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenIntTrigDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned long ulIntTrig))ROM_PWMTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
tBoolean bMasked))ROM_PWMTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMGenIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGen, \ |
unsigned long ulInts))ROM_PWMTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGenFault))ROM_PWMTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulGenFault))ROM_PWMTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMFaultIntClear \ |
((void (*)(unsigned long ulBase))ROM_PWMTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_PWMIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_PWMTABLE[21]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the QEI API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIPositionGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIEnable \ |
((void (*)(unsigned long ulBase))ROM_QEITABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIDisable \ |
((void (*)(unsigned long ulBase))ROM_QEITABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulConfig, \ |
unsigned long ulMaxPosition))ROM_QEITABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIPositionSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPosition))ROM_QEITABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIDirectionGet \ |
((long (*)(unsigned long ulBase))ROM_QEITABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIErrorGet \ |
((tBoolean (*)(unsigned long ulBase))ROM_QEITABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIVelocityEnable \ |
((void (*)(unsigned long ulBase))ROM_QEITABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIVelocityDisable \ |
((void (*)(unsigned long ulBase))ROM_QEITABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIVelocityConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulPreDiv, \ |
unsigned long ulPeriod))ROM_QEITABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIVelocityGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_QEITABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_QEITABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_QEITABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_QEITABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_QEIIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_QEITABLE[14]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the SSI API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIDataPut \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulData))ROM_SSITABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIConfigSetExpClk \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulSSIClk, \ |
unsigned long ulProtocol, \ |
unsigned long ulMode, \ |
unsigned long ulBitRate, \ |
unsigned long ulDataWidth))ROM_SSITABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIEnable \ |
((void (*)(unsigned long ulBase))ROM_SSITABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIDisable \ |
((void (*)(unsigned long ulBase))ROM_SSITABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_SSITABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_SSITABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_SSITABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_SSITABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIDataPutNonBlocking \ |
((long (*)(unsigned long ulBase, \ |
unsigned long ulData))ROM_SSITABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIDataGet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long *pulData))ROM_SSITABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SSIDataGetNonBlocking \ |
((long (*)(unsigned long ulBase, \ |
unsigned long *pulData))ROM_SSITABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UpdateSSI \ |
((void (*)(void))ROM_SSITABLE[11]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the SysCtl API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlSleep \ |
((void (*)(void))ROM_SYSCTLTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlSRAMSizeGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlFlashSizeGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPinPresent \ |
((tBoolean (*)(unsigned long ulPin))ROM_SYSCTLTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralPresent \ |
((tBoolean (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralReset \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralEnable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralDisable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralSleepEnable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralSleepDisable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralDeepSleepEnable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralDeepSleepDisable \ |
((void (*)(unsigned long ulPeripheral))ROM_SYSCTLTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPeripheralClockGating \ |
((void (*)(tBoolean bEnable))ROM_SYSCTLTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlIntEnable \ |
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlIntDisable \ |
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlIntClear \ |
((void (*)(unsigned long ulInts))ROM_SYSCTLTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlIntStatus \ |
((unsigned long (*)(tBoolean bMasked))ROM_SYSCTLTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlLDOSet \ |
((void (*)(unsigned long ulVoltage))ROM_SYSCTLTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlLDOGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlReset \ |
((void (*)(void))ROM_SYSCTLTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlDeepSleep \ |
((void (*)(void))ROM_SYSCTLTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlResetCauseGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[21]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlResetCauseClear \ |
((void (*)(unsigned long ulCauses))ROM_SYSCTLTABLE[22]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlClockSet \ |
((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[23]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlClockGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[24]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPWMClockSet \ |
((void (*)(unsigned long ulConfig))ROM_SYSCTLTABLE[25]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlPWMClockGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[26]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlADCSpeedSet \ |
((void (*)(unsigned long ulSpeed))ROM_SYSCTLTABLE[27]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlADCSpeedGet \ |
((unsigned long (*)(void))ROM_SYSCTLTABLE[28]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlGPIOAHBEnable \ |
((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[29]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysCtlGPIOAHBDisable \ |
((void (*)(unsigned long ulGPIOPeripheral))ROM_SYSCTLTABLE[30]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the SysTick API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickValueGet \ |
((unsigned long (*)(void))ROM_SYSTICKTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickEnable \ |
((void (*)(void))ROM_SYSTICKTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickDisable \ |
((void (*)(void))ROM_SYSTICKTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickIntEnable \ |
((void (*)(void))ROM_SYSTICKTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickIntDisable \ |
((void (*)(void))ROM_SYSTICKTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickPeriodSet \ |
((void (*)(unsigned long ulPeriod))ROM_SYSTICKTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_SysTickPeriodGet \ |
((unsigned long (*)(void))ROM_SYSTICKTABLE[6]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the Timer API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_TIMERTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerConfigure \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulConfig))ROM_TIMERTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerControlLevel \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
tBoolean bInvert))ROM_TIMERTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerControlTrigger \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
tBoolean bEnable))ROM_TIMERTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerControlEvent \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
unsigned long ulEvent))ROM_TIMERTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerControlStall \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
tBoolean bStall))ROM_TIMERTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerRTCEnable \ |
((void (*)(unsigned long ulBase))ROM_TIMERTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerRTCDisable \ |
((void (*)(unsigned long ulBase))ROM_TIMERTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerPrescaleSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
unsigned long ulValue))ROM_TIMERTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerPrescaleGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerLoadSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
unsigned long ulValue))ROM_TIMERTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerLoadGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerValueGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerMatchSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTimer, \ |
unsigned long ulValue))ROM_TIMERTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerMatchGet \ |
((unsigned long (*)(unsigned long ulBase, \ |
unsigned long ulTimer))ROM_TIMERTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_TIMERTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_TIMERTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_TimerIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_TIMERTABLE[21]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the UART API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTCharPut \ |
((void (*)(unsigned long ulBase, \ |
unsigned char ucData))ROM_UARTTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTParityModeSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulParity))ROM_UARTTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTParityModeGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_UARTTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTFIFOLevelSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulTxLevel, \ |
unsigned long ulRxLevel))ROM_UARTTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTFIFOLevelGet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long *pulTxLevel, \ |
unsigned long *pulRxLevel))ROM_UARTTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTConfigSetExpClk \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulUARTClk, \ |
unsigned long ulBaud, \ |
unsigned long ulConfig))ROM_UARTTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTConfigGetExpClk \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulUARTClk, \ |
unsigned long *pulBaud, \ |
unsigned long *pulConfig))ROM_UARTTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTEnable \ |
((void (*)(unsigned long ulBase))ROM_UARTTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTDisable \ |
((void (*)(unsigned long ulBase))ROM_UARTTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTEnableSIR \ |
((void (*)(unsigned long ulBase, \ |
tBoolean bLowPower))ROM_UARTTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTDisableSIR \ |
((void (*)(unsigned long ulBase))ROM_UARTTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTCharsAvail \ |
((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTSpaceAvail \ |
((tBoolean (*)(unsigned long ulBase))ROM_UARTTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTCharGetNonBlocking \ |
((long (*)(unsigned long ulBase))ROM_UARTTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTCharGet \ |
((long (*)(unsigned long ulBase))ROM_UARTTABLE[14]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTCharPutNonBlocking \ |
((tBoolean (*)(unsigned long ulBase, \ |
unsigned char ucData))ROM_UARTTABLE[15]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTBreakCtl \ |
((void (*)(unsigned long ulBase, \ |
tBoolean bBreakState))ROM_UARTTABLE[16]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTIntEnable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_UARTTABLE[17]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTIntDisable \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_UARTTABLE[18]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_UARTTABLE[19]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UARTIntClear \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulIntFlags))ROM_UARTTABLE[20]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_UpdateUART \ |
((void (*)(void))ROM_UARTTABLE[21]) |
#endif |
|
//***************************************************************************** |
// |
// Macros for calling ROM functions in the Watchdog API. |
// |
//***************************************************************************** |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogIntClear \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[0]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogRunning \ |
((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[1]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogEnable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[2]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogResetEnable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[3]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogResetDisable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[4]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogLock \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[5]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogUnlock \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[6]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogLockState \ |
((tBoolean (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[7]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogReloadSet \ |
((void (*)(unsigned long ulBase, \ |
unsigned long ulLoadVal))ROM_WATCHDOGTABLE[8]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogReloadGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[9]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogValueGet \ |
((unsigned long (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[10]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogIntEnable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[11]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogIntStatus \ |
((unsigned long (*)(unsigned long ulBase, \ |
tBoolean bMasked))ROM_WATCHDOGTABLE[12]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogStallEnable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[13]) |
#endif |
#if defined(TARGET_IS_DUSTDEVIL_RA0) |
#define ROM_WatchdogStallDisable \ |
((void (*)(unsigned long ulBase))ROM_WATCHDOGTABLE[14]) |
#endif |
|
#endif // __ROM_H__ |
/drivers/LuminaryMicro/hw_watchdog.h
0,0 → 1,179
//***************************************************************************** |
// |
// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_WATCHDOG_H__ |
#define __HW_WATCHDOG_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the Watchdog Timer register offsets. |
// |
//***************************************************************************** |
#define WDT_O_LOAD 0x00000000 // Load register |
#define WDT_O_VALUE 0x00000004 // Current value register |
#define WDT_O_CTL 0x00000008 // Control register |
#define WDT_O_ICR 0x0000000C // Interrupt clear register |
#define WDT_O_RIS 0x00000010 // Raw interrupt status register |
#define WDT_O_MIS 0x00000014 // Masked interrupt status register |
#define WDT_O_TEST 0x00000418 // Test register |
#define WDT_O_LOCK 0x00000C00 // Lock register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_CTL register. |
// |
//***************************************************************************** |
#define WDT_CTL_RESEN 0x00000002 // Enable reset output |
#define WDT_CTL_INTEN 0x00000001 // Enable the WDT counter and int |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and |
// WDT_MIS registers. |
// |
//***************************************************************************** |
#define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_TEST register. |
// |
//***************************************************************************** |
#define WDT_TEST_STALL 0x00000100 // Watchdog stall enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_LOCK register. |
// |
//***************************************************************************** |
#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock. |
#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer |
#define WDT_LOCK_LOCKED 0x00000001 // Watchdog timer is locked |
#define WDT_LOCK_UNLOCKED 0x00000000 // Watchdog timer is unlocked |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_O_LOAD register. |
// |
//***************************************************************************** |
#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value. |
#define WDT_LOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_O_VALUE register. |
// |
//***************************************************************************** |
#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value. |
#define WDT_VALUE_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_O_ICR register. |
// |
//***************************************************************************** |
#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear. |
#define WDT_ICR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_O_RIS register. |
// |
//***************************************************************************** |
#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the WDT_O_MIS register. |
// |
//***************************************************************************** |
#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt |
// Status. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Watchdog Timer register |
// offsets. |
// |
//***************************************************************************** |
#define WDT_O_PeriphID4 0x00000FD0 |
#define WDT_O_PeriphID5 0x00000FD4 |
#define WDT_O_PeriphID6 0x00000FD8 |
#define WDT_O_PeriphID7 0x00000FDC |
#define WDT_O_PeriphID0 0x00000FE0 |
#define WDT_O_PeriphID1 0x00000FE4 |
#define WDT_O_PeriphID2 0x00000FE8 |
#define WDT_O_PeriphID3 0x00000FEC |
#define WDT_O_PCellID0 0x00000FF0 |
#define WDT_O_PCellID1 0x00000FF4 |
#define WDT_O_PCellID2 0x00000FF8 |
#define WDT_O_PCellID3 0x00000FFC |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the WDT_TEST |
// register. |
// |
//***************************************************************************** |
#define WDT_TEST_STALL_EN 0x00000100 // Watchdog stall enable |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values for the WDT |
// registers. |
// |
//***************************************************************************** |
#define WDT_RV_VALUE 0xFFFFFFFF // Current value register |
#define WDT_RV_LOAD 0xFFFFFFFF // Load register |
#define WDT_RV_PCellID1 0x000000F0 |
#define WDT_RV_PCellID3 0x000000B1 |
#define WDT_RV_PeriphID1 0x00000018 |
#define WDT_RV_PeriphID2 0x00000018 |
#define WDT_RV_PCellID0 0x0000000D |
#define WDT_RV_PCellID2 0x00000005 |
#define WDT_RV_PeriphID0 0x00000005 |
#define WDT_RV_PeriphID3 0x00000001 |
#define WDT_RV_PeriphID5 0x00000000 |
#define WDT_RV_RIS 0x00000000 // Raw interrupt status register |
#define WDT_RV_CTL 0x00000000 // Control register |
#define WDT_RV_PeriphID4 0x00000000 |
#define WDT_RV_PeriphID6 0x00000000 |
#define WDT_RV_PeriphID7 0x00000000 |
#define WDT_RV_LOCK 0x00000000 // Lock register |
#define WDT_RV_MIS 0x00000000 // Masked interrupt status register |
|
#endif |
|
#endif // __HW_WATCHDOG_H__ |
/drivers/LuminaryMicro/comp.h
0,0 → 1,134
//***************************************************************************** |
// |
// comp.h - Prototypes for the analog comparator driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __COMP_H__ |
#define __COMP_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to ComparatorConfigure() as the ulConfig |
// parameter. For each group (i.e. COMP_TRIG_xxx, COMP_INT_xxx, etc.), one of |
// the values may be selected and combined together with values from the other |
// groups via a logical OR. |
// |
//***************************************************************************** |
#define COMP_TRIG_NONE 0x00000000 // No ADC trigger |
#define COMP_TRIG_HIGH 0x00000880 // Trigger when high |
#define COMP_TRIG_LOW 0x00000800 // Trigger when low |
#define COMP_TRIG_FALL 0x00000820 // Trigger on falling edge |
#define COMP_TRIG_RISE 0x00000840 // Trigger on rising edge |
#define COMP_TRIG_BOTH 0x00000860 // Trigger on both edges |
#define COMP_INT_HIGH 0x00000010 // Interrupt when high |
#define COMP_INT_LOW 0x00000000 // Interrupt when low |
#define COMP_INT_FALL 0x00000004 // Interrupt on falling edge |
#define COMP_INT_RISE 0x00000008 // Interrupt on rising edge |
#define COMP_INT_BOTH 0x0000000C // Interrupt on both edges |
#define COMP_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin |
#define COMP_ASRCP_PIN0 0x00000200 // Comp0+ pin |
#define COMP_ASRCP_REF 0x00000400 // Internal voltage reference |
#ifndef DEPRECATED |
#define COMP_OUTPUT_NONE 0x00000000 // No comparator output |
#endif |
#define COMP_OUTPUT_NORMAL 0x00000000 // Comparator output normal |
#define COMP_OUTPUT_INVERT 0x00000002 // Comparator output inverted |
|
//***************************************************************************** |
// |
// Values that can be passed to ComparatorSetRef() as the ulRef parameter. |
// |
//***************************************************************************** |
#define COMP_REF_OFF 0x00000000 // Turn off the internal reference |
#define COMP_REF_0V 0x00000300 // Internal reference of 0V |
#define COMP_REF_0_1375V 0x00000301 // Internal reference of 0.1375V |
#define COMP_REF_0_275V 0x00000302 // Internal reference of 0.275V |
#define COMP_REF_0_4125V 0x00000303 // Internal reference of 0.4125V |
#define COMP_REF_0_55V 0x00000304 // Internal reference of 0.55V |
#define COMP_REF_0_6875V 0x00000305 // Internal reference of 0.6875V |
#define COMP_REF_0_825V 0x00000306 // Internal reference of 0.825V |
#define COMP_REF_0_928125V 0x00000201 // Internal reference of 0.928125V |
#define COMP_REF_0_9625V 0x00000307 // Internal reference of 0.9625V |
#define COMP_REF_1_03125V 0x00000202 // Internal reference of 1.03125V |
#define COMP_REF_1_134375V 0x00000203 // Internal reference of 1.134375V |
#define COMP_REF_1_1V 0x00000308 // Internal reference of 1.1V |
#define COMP_REF_1_2375V 0x00000309 // Internal reference of 1.2375V |
#define COMP_REF_1_340625V 0x00000205 // Internal reference of 1.340625V |
#define COMP_REF_1_375V 0x0000030A // Internal reference of 1.375V |
#define COMP_REF_1_44375V 0x00000206 // Internal reference of 1.44375V |
#define COMP_REF_1_5125V 0x0000030B // Internal reference of 1.5125V |
#define COMP_REF_1_546875V 0x00000207 // Internal reference of 1.546875V |
#define COMP_REF_1_65V 0x0000030C // Internal reference of 1.65V |
#define COMP_REF_1_753125V 0x00000209 // Internal reference of 1.753125V |
#define COMP_REF_1_7875V 0x0000030D // Internal reference of 1.7875V |
#define COMP_REF_1_85625V 0x0000020A // Internal reference of 1.85625V |
#define COMP_REF_1_925V 0x0000030E // Internal reference of 1.925V |
#define COMP_REF_1_959375V 0x0000020B // Internal reference of 1.959375V |
#define COMP_REF_2_0625V 0x0000030F // Internal reference of 2.0625V |
#define COMP_REF_2_165625V 0x0000020D // Internal reference of 2.165625V |
#define COMP_REF_2_26875V 0x0000020E // Internal reference of 2.26875V |
#define COMP_REF_2_371875V 0x0000020F // Internal reference of 2.371875V |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void ComparatorConfigure(unsigned long ulBase, unsigned long ulComp, |
unsigned long ulConfig); |
extern void ComparatorRefSet(unsigned long ulBase, unsigned long ulRef); |
extern tBoolean ComparatorValueGet(unsigned long ulBase, unsigned long ulComp); |
extern void ComparatorIntRegister(unsigned long ulBase, unsigned long ulComp, |
void (*pfnHandler)(void)); |
extern void ComparatorIntUnregister(unsigned long ulBase, |
unsigned long ulComp); |
extern void ComparatorIntEnable(unsigned long ulBase, unsigned long ulComp); |
extern void ComparatorIntDisable(unsigned long ulBase, unsigned long ulComp); |
extern tBoolean ComparatorIntStatus(unsigned long ulBase, unsigned long ulComp, |
tBoolean bMasked); |
extern void ComparatorIntClear(unsigned long ulBase, unsigned long ulComp); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __COMP_H__ |
/drivers/LuminaryMicro/gpio.h
0,0 → 1,156
//***************************************************************************** |
// |
// gpio.h - Defines and Macros for GPIO API. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __GPIO_H__ |
#define __GPIO_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// The following values define the bit field for the ucPins argument to several |
// of the APIs. |
// |
//***************************************************************************** |
#define GPIO_PIN_0 0x00000001 // GPIO pin 0 |
#define GPIO_PIN_1 0x00000002 // GPIO pin 1 |
#define GPIO_PIN_2 0x00000004 // GPIO pin 2 |
#define GPIO_PIN_3 0x00000008 // GPIO pin 3 |
#define GPIO_PIN_4 0x00000010 // GPIO pin 4 |
#define GPIO_PIN_5 0x00000020 // GPIO pin 5 |
#define GPIO_PIN_6 0x00000040 // GPIO pin 6 |
#define GPIO_PIN_7 0x00000080 // GPIO pin 7 |
|
//***************************************************************************** |
// |
// Values that can be passed to GPIODirModeSet as the ulPinIO parameter, and |
// returned from GPIODirModeGet. |
// |
//***************************************************************************** |
#define GPIO_DIR_MODE_IN 0x00000000 // Pin is a GPIO input |
#define GPIO_DIR_MODE_OUT 0x00000001 // Pin is a GPIO output |
#define GPIO_DIR_MODE_HW 0x00000002 // Pin is a peripheral function |
|
//***************************************************************************** |
// |
// Values that can be passed to GPIOIntTypeSet as the ulIntType parameter, and |
// returned from GPIOIntTypeGet. |
// |
//***************************************************************************** |
#define GPIO_FALLING_EDGE 0x00000000 // Interrupt on falling edge |
#define GPIO_RISING_EDGE 0x00000004 // Interrupt on rising edge |
#define GPIO_BOTH_EDGES 0x00000001 // Interrupt on both edges |
#define GPIO_LOW_LEVEL 0x00000002 // Interrupt on low level |
#define GPIO_HIGH_LEVEL 0x00000007 // Interrupt on high level |
|
//***************************************************************************** |
// |
// Values that can be passed to GPIOPadConfigSet as the ulStrength parameter, |
// and returned by GPIOPadConfigGet in the *pulStrength parameter. |
// |
//***************************************************************************** |
#define GPIO_STRENGTH_2MA 0x00000001 // 2mA drive strength |
#define GPIO_STRENGTH_4MA 0x00000002 // 4mA drive strength |
#define GPIO_STRENGTH_8MA 0x00000004 // 8mA drive strength |
#define GPIO_STRENGTH_8MA_SC 0x0000000C // 8mA drive with slew rate control |
|
//***************************************************************************** |
// |
// Values that can be passed to GPIOPadConfigSet as the ulPadType parameter, |
// and returned by GPIOPadConfigGet in the *pulPadType parameter. |
// |
//***************************************************************************** |
#define GPIO_PIN_TYPE_STD 0x00000008 // Push-pull |
#define GPIO_PIN_TYPE_STD_WPU 0x0000000A // Push-pull with weak pull-up |
#define GPIO_PIN_TYPE_STD_WPD 0x0000000C // Push-pull with weak pull-down |
#define GPIO_PIN_TYPE_OD 0x00000009 // Open-drain |
#define GPIO_PIN_TYPE_OD_WPU 0x0000000B // Open-drain with weak pull-up |
#define GPIO_PIN_TYPE_OD_WPD 0x0000000D // Open-drain with weak pull-down |
#define GPIO_PIN_TYPE_ANALOG 0x00000000 // Analog comparator |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void GPIODirModeSet(unsigned long ulPort, unsigned char ucPins, |
unsigned long ulPinIO); |
extern unsigned long GPIODirModeGet(unsigned long ulPort, unsigned char ucPin); |
extern void GPIOIntTypeSet(unsigned long ulPort, unsigned char ucPins, |
unsigned long ulIntType); |
extern unsigned long GPIOIntTypeGet(unsigned long ulPort, unsigned char ucPin); |
extern void GPIOPadConfigSet(unsigned long ulPort, unsigned char ucPins, |
unsigned long ulStrength, |
unsigned long ulPadType); |
extern void GPIOPadConfigGet(unsigned long ulPort, unsigned char ucPin, |
unsigned long *pulStrength, |
unsigned long *pulPadType); |
extern void GPIOPinIntEnable(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinIntDisable(unsigned long ulPort, unsigned char ucPins); |
extern long GPIOPinIntStatus(unsigned long ulPort, tBoolean bMasked); |
extern void GPIOPinIntClear(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPortIntRegister(unsigned long ulPort, |
void (*pfnIntHandler)(void)); |
extern void GPIOPortIntUnregister(unsigned long ulPort); |
extern long GPIOPinRead(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinWrite(unsigned long ulPort, unsigned char ucPins, |
unsigned char ucVal); |
extern void GPIOPinTypeADC(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeCAN(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeComparator(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeGPIOInput(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeGPIOOutput(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeGPIOOutputOD(unsigned long ulPort, |
unsigned char ucPins); |
extern void GPIOPinTypeI2C(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypePWM(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeQEI(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeSSI(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeTimer(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeUART(unsigned long ulPort, unsigned char ucPins); |
extern void GPIOPinTypeUSBDigital(unsigned long ulPort, unsigned char ucPins); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __GPIO_H__ |
/drivers/LuminaryMicro/ssi.h
0,0 → 1,128
//***************************************************************************** |
// |
// ssi.h - Prototypes for the Synchronous Serial Interface Driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __SSI_H__ |
#define __SSI_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to SSIIntEnable, SSIIntDisable, and SSIIntClear |
// as the ulIntFlags parameter, and returned by SSIIntStatus. |
// |
//***************************************************************************** |
#define SSI_TXFF 0x00000008 // TX FIFO half empty or less |
#define SSI_RXFF 0x00000004 // RX FIFO half full or less |
#define SSI_RXTO 0x00000002 // RX timeout |
#define SSI_RXOR 0x00000001 // RX overrun |
|
//***************************************************************************** |
// |
// Values that can be passed to SSIConfigSetExpClk. |
// |
//***************************************************************************** |
#define SSI_FRF_MOTO_MODE_0 0x00000000 // Moto fmt, polarity 0, phase 0 |
#define SSI_FRF_MOTO_MODE_1 0x00000002 // Moto fmt, polarity 0, phase 1 |
#define SSI_FRF_MOTO_MODE_2 0x00000001 // Moto fmt, polarity 1, phase 0 |
#define SSI_FRF_MOTO_MODE_3 0x00000003 // Moto fmt, polarity 1, phase 1 |
#define SSI_FRF_TI 0x00000010 // TI frame format |
#define SSI_FRF_NMW 0x00000020 // National MicroWire frame format |
|
#define SSI_MODE_MASTER 0x00000000 // SSI master |
#define SSI_MODE_SLAVE 0x00000001 // SSI slave |
#define SSI_MODE_SLAVE_OD 0x00000002 // SSI slave with output disabled |
|
//***************************************************************************** |
// |
// Values that can be passed to SSIDMAEnable() and SSIDMADisable(). |
// |
//***************************************************************************** |
#define SSI_DMA_TX 0x00000002 // Enable DMA for transmit |
#define SSI_DMA_RX 0x00000001 // Enable DMA for receive |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void SSIConfigSetExpClk(unsigned long ulBase, unsigned long ulSSIClk, |
unsigned long ulProtocol, unsigned long ulMode, |
unsigned long ulBitRate, |
unsigned long ulDataWidth); |
extern void SSIDataGet(unsigned long ulBase, unsigned long *pulData); |
extern long SSIDataGetNonBlocking(unsigned long ulBase, |
unsigned long *pulData); |
extern void SSIDataPut(unsigned long ulBase, unsigned long ulData); |
extern long SSIDataPutNonBlocking(unsigned long ulBase, unsigned long ulData); |
extern void SSIDisable(unsigned long ulBase); |
extern void SSIEnable(unsigned long ulBase); |
extern void SSIIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
extern void SSIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void SSIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void SSIIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); |
extern unsigned long SSIIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void SSIIntUnregister(unsigned long ulBase); |
extern void SSIDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); |
extern void SSIDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); |
|
//***************************************************************************** |
// |
// Several SSI APIs have been renamed, with the original function name being |
// deprecated. These defines provide backward compatibility. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#include "sysctl.h" |
#define SSIConfig(a, b, c, d, e) \ |
SSIConfigSetExpClk(a, SysCtlClockGet(), b, c, d, e) |
#define SSIDataNonBlockingGet(a, b) \ |
SSIDataGetNonBlocking(a, b) |
#define SSIDataNonBlockingPut(a, b) \ |
SSIDataPutNonBlocking(a, b) |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __SSI_H__ |
/drivers/LuminaryMicro/grlib.h
0,0 → 1,1285
//***************************************************************************** |
// |
// grlib.h - Prototypes for the low level primitives provided by the graphics |
// library. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Graphics Library. |
// |
//***************************************************************************** |
|
#ifndef __GRLIB_H__ |
#define __GRLIB_H__ |
|
//***************************************************************************** |
// |
//! \addtogroup primitives_api |
//! @{ |
// |
//***************************************************************************** |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
//! This structure defines the extents of a rectangle. All points greater than |
//! or equal to the minimum and less than or equal to the maximum are part of |
//! the rectangle. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! The minimum X coordinate of the rectangle. |
// |
short sXMin; |
|
// |
//! The minimum Y coordinate of the rectangle. |
// |
short sYMin; |
|
// |
//! The maximum X coordinate of the rectangle. |
// |
short sXMax; |
|
// |
//! The maximum Y coordinate of the rectangle. |
// |
short sYMax; |
} |
tRectangle; |
|
//***************************************************************************** |
// |
//! This structure defines the characteristics of a display driver. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! The size of this structure. |
// |
long lSize; |
|
// |
//! A pointer to display driver-specific data. |
// |
void *pvDisplayData; |
|
// |
//! The width of this display. |
// |
unsigned short usWidth; |
|
// |
//! The height of this display. |
// |
unsigned short usHeight; |
|
// |
//! A pointer to the function to draw a pixel on this display. |
// |
void (*pfnPixelDraw)(void *pvDisplayData, long lX, long lY, |
unsigned long ulValue); |
|
// |
//! A pointer to the function to draw multiple pixels on this display. |
// |
void (*pfnPixelDrawMultiple)(void *pvDisplayData, long lX, long lY, |
long lX0, long lCount, long lBPP, |
const unsigned char *pucData, |
const unsigned char *pucPalette); |
|
// |
//! A pointer to the function to draw a horizontal line on this display. |
// |
void (*pfnLineDrawH)(void *pvDisplayData, long lX1, long lX2, long lY, |
unsigned long ulValue); |
|
// |
//! A pointer to the function to draw a vertical line on this display. |
// |
void (*pfnLineDrawV)(void *pvDisplayData, long lX, long lY1, long lY2, |
unsigned long ulValue); |
|
// |
//! A pointer to the function to draw a filled rectangle on this display. |
// |
void (*pfnRectFill)(void *pvDisplayData, const tRectangle *pRect, |
unsigned long ulValue); |
|
// |
//! A pointer to the function to translate 24-bit RGB colors to |
//! display-specific colors. |
// |
unsigned long (*pfnColorTranslate)(void *pvDisplayData, |
unsigned long ulValue); |
|
// |
//! A pointer to the function to flush any cached drawing operations on |
//! this display. |
// |
void (*pfnFlush)(void *pvDisplayData); |
} |
tDisplay; |
|
//***************************************************************************** |
// |
//! This structure describes a font used for drawing text onto the screen. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! The format of the font. Can be one of FONT_FMT_UNCOMPRESSED or |
//! FONT_FMT_PIXEL_RLE. |
// |
unsigned char ucFormat; |
|
// |
//! The maximum width of a character; this is the width of the widest |
//! character in the font, though any individual character may be narrower |
//! than this width. |
// |
unsigned char ucMaxWidth; |
|
// |
//! The height of the character cell; this may be taller than the font data |
//! for the characters (to provide inter-line spacing). |
// |
unsigned char ucHeight; |
|
// |
//! The offset between the top of the character cell and the baseline of |
//! the glyph. The baseline is the bottom row of a capital letter, below |
//! which only the descenders of the lower case letters occur. |
// |
unsigned char ucBaseline; |
|
// |
//! The offset within pucData to the data for each character in the font. |
// |
unsigned short pusOffset[96]; |
|
// |
//! A pointer to the data for the font. |
// |
const unsigned char *pucData; |
} |
tFont; |
|
//***************************************************************************** |
// |
//! Indicates that the font data is stored in an uncompressed format. |
// |
//***************************************************************************** |
#define FONT_FMT_UNCOMPRESSED 0x00 |
|
//***************************************************************************** |
// |
//! Indicates that the font data is stored using a pixel-based RLE format. |
// |
//***************************************************************************** |
#define FONT_FMT_PIXEL_RLE 0x01 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is not compressed and represents each pixel |
//! with a single bit. |
// |
//***************************************************************************** |
#define IMAGE_FMT_1BPP_UNCOMP 0x01 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is not compressed and represents each pixel |
//! with four bits. |
// |
//***************************************************************************** |
#define IMAGE_FMT_4BPP_UNCOMP 0x04 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is not compressed and represents each pixel |
//! with eight bits. |
// |
//***************************************************************************** |
#define IMAGE_FMT_8BPP_UNCOMP 0x08 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is compressed and represents each pixel with |
//! a single bit. |
// |
//***************************************************************************** |
#define IMAGE_FMT_1BPP_COMP 0x81 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is compressed and represents each pixel with |
//! four bits. |
// |
//***************************************************************************** |
#define IMAGE_FMT_4BPP_COMP 0x84 |
|
//***************************************************************************** |
// |
//! Indicates that the image data is compressed and represents each pixel with |
//! eight bits. |
// |
//***************************************************************************** |
#define IMAGE_FMT_8BPP_COMP 0x88 |
|
//***************************************************************************** |
// |
//! This structure defines a drawing context to be used to draw onto the |
//! screen. Multiple drawing contexts may exist at any time. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! The size of this structure. |
// |
long lSize; |
|
// |
//! The screen onto which drawing operations are performed. |
// |
const tDisplay *pDisplay; |
|
// |
//! The clipping region to be used when drawing onto the screen. |
// |
tRectangle sClipRegion; |
|
// |
//! The color used to draw primitives onto the screen. |
// |
unsigned long ulForeground; |
|
// |
//! The background color used to draw primitives onto the screen. |
// |
unsigned long ulBackground; |
|
// |
//! The font used to render text onto the screen. |
// |
const tFont *pFont; |
} |
tContext; |
|
//***************************************************************************** |
// |
//! Sets the background color to be used. |
//! |
//! \param pContext is a pointer to the drawing context to modify. |
//! \param ulValue is the 24-bit RGB color to be used. |
//! |
//! This function sets the background color to be used for drawing operations |
//! in the specified drawing context. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrContextBackgroundSet(pContext, ulValue) \ |
do \ |
{ \ |
tContext *pC = pContext; \ |
pC->ulBackground = DpyColorTranslate(pC->pDisplay, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Sets the background color to be used. |
//! |
//! \param pContext is a pointer to the drawing context to modify. |
//! \param ulValue is the display driver-specific color to be used. |
//! |
//! This function sets the background color to be used for drawing operations |
//! in the specified drawing context, using a color that has been previously |
//! translated to a driver-specific color (for example, via |
//! DpyColorTranslate()). |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrContextBackgroundSetTranslated(pContext, ulValue) \ |
do \ |
{ \ |
tContext *pC = pContext; \ |
pC->ulBackground = ulValue; \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the width of the display being used by this drawing context. |
//! |
//! \param pContext is a pointer to the drawing context to query. |
//! |
//! This function returns the width of the display that is being used by this |
//! drawing context. |
//! |
//! \return Returns the width of the display in pixels. |
// |
//***************************************************************************** |
#define GrContextDpyWidthGet(pContext) \ |
(DpyWidthGet((pContext)->pDisplay)) |
|
//***************************************************************************** |
// |
//! Gets the height of the display being used by this drawing context. |
//! |
//! \param pContext is a pointer to the drawing context to query. |
//! |
//! This function returns the height of the display that is being used by this |
//! drawing context. |
//! |
//! \return Returns the height of the display in pixels. |
// |
//***************************************************************************** |
#define GrContextDpyHeightGet(pContext) \ |
(DpyHeightGet((pContext)->pDisplay)) |
|
//***************************************************************************** |
// |
//! Sets the font to be used. |
//! |
//! \param pContext is a pointer to the drawing context to modify. |
//! \param pFnt is a pointer to the font to be used. |
//! |
//! This function sets the font to be used for string drawing operations in the |
//! specified drawing context. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrContextFontSet(pContext, pFnt) \ |
do \ |
{ \ |
tContext *pC = pContext; \ |
const tFont *pF = pFnt; \ |
pC->pFont = pF; \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Sets the foreground color to be used. |
//! |
//! \param pContext is a pointer to the drawing context to modify. |
//! \param ulValue is the 24-bit RGB color to be used. |
//! |
//! This function sets the color to be used for drawing operations in the |
//! specified drawing context. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrContextForegroundSet(pContext, ulValue) \ |
do \ |
{ \ |
tContext *pC = pContext; \ |
pC->ulForeground = DpyColorTranslate(pC->pDisplay, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Sets the foreground color to be used. |
//! |
//! \param pContext is a pointer to the drawing context to modify. |
//! \param ulValue is the display driver-specific color to be used. |
//! |
//! This function sets the foreground color to be used for drawing operations |
//! in the specified drawing context, using a color that has been previously |
//! translated to a driver-specific color (for example, via |
//! DpyColorTranslate()). |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrContextForegroundSetTranslated(pContext, ulValue) \ |
do \ |
{ \ |
tContext *pC = pContext; \ |
pC->ulForeground = ulValue; \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Flushes any cached drawing operations. |
//! |
//! \param pContext is a pointer to the drawing context to use. |
//! |
//! This function flushes any cached drawing operations. For display drivers |
//! that draw into a local frame buffer before writing to the actual display, |
//! calling this function will cause the display to be updated to match the |
//! contents of the local frame buffer. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrFlush(pContext) \ |
do \ |
{ \ |
const tContext *pC = pContext; \ |
DpyFlush(pC->pDisplay); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the baseline of a font. |
//! |
//! \param pFont is a pointer to the font to query. |
//! |
//! This function determines the baseline position of a font. The baseline is |
//! the offset between the top of the font and the bottom of the capital |
//! letters. The only font data that exists below the baseline are the |
//! descenders on some lower-case letters (such as ``y''). |
//! |
//! \return Returns the baseline of the font, in pixels. |
// |
//***************************************************************************** |
#define GrFontBaselineGet(pFont) \ |
((pFont)->ucBaseline) |
|
//***************************************************************************** |
// |
//! Gets the height of a font. |
//! |
//! \param pFont is a pointer to the font to query. |
//! |
//! This function determines the height of a font. The height is the offset |
//! between the top of the font and the bottom of the font, including any |
//! ascenders and descenders. |
//! |
//! \return Returns the height of the font, in pixels. |
// |
//***************************************************************************** |
#define GrFontHeightGet(pFont) \ |
((pFont)->ucHeight) |
|
//***************************************************************************** |
// |
//! Gets the maximum width of a font. |
//! |
//! \param pFont is a pointer to the font to query. |
//! |
//! This function determines the maximum width of a font. The maximum width is |
//! the width of the widest individual character in the font. |
//! |
//! \return Returns the maximum width of the font, in pixels. |
// |
//***************************************************************************** |
#define GrFontMaxWidthGet(pFont) \ |
((pFont)->ucMaxWidth) |
|
//***************************************************************************** |
// |
//! Gets the number of colors in an image. |
//! |
//! \param pucImage is a pointer to the image to query. |
//! |
//! This function determines the number of colors in the palette of an image. |
//! This is only valid for 4bpp and 8bpp images; 1bpp images do not contain a |
//! palette. |
//! |
//! \return Returns the number of colors in the image. |
// |
//***************************************************************************** |
#define GrImageColorsGet(pucImage) \ |
(((unsigned char *)pucImage)[5] + 1) |
|
//***************************************************************************** |
// |
//! Gets the height of an image. |
//! |
//! \param pucImage is a pointer to the image to query. |
//! |
//! This function determines the height of an image in pixels. |
//! |
//! \return Returns the height of the image in pixels. |
// |
//***************************************************************************** |
#define GrImageHeightGet(pucImage) \ |
(*(unsigned short *)(pucImage + 3)) |
|
//***************************************************************************** |
// |
//! Gets the width of an image. |
//! |
//! \param pucImage is a pointer to the image to query. |
//! |
//! This function determines the width of an image in pixels. |
//! |
//! \return Returns the width of the image in pixels. |
// |
//***************************************************************************** |
#define GrImageWidthGet(pucImage) \ |
(*(unsigned short *)(pucImage + 1)) |
|
//***************************************************************************** |
// |
//! Determines the size of the buffer for a 1 BPP off-screen image. |
//! |
//! \param lWidth is the width of the image in pixels. |
//! \param lHeight is the height of the image in pixels. |
//! |
//! This function determines the size of the memory buffer required to hold a |
//! 1 BPP off-screen image of the specified geometry. |
//! |
//! \return Returns the number of bytes required by the image. |
// |
//***************************************************************************** |
#define GrOffScreen1BPPSize(lWidth, lHeight) \ |
(5 + (((lWidth + 7) / 8) * lHeight)) |
|
//***************************************************************************** |
// |
//! Determines the size of the buffer for a 4 BPP off-screen image. |
//! |
//! \param lWidth is the width of the image in pixels. |
//! \param lHeight is the height of the image in pixels. |
//! |
//! This function determines the size of the memory buffer required to hold a |
//! 4 BPP off-screen image of the specified geometry. |
//! |
//! \return Returns the number of bytes required by the image. |
// |
//***************************************************************************** |
#define GrOffScreen4BPPSize(lWidth, lHeight) \ |
(6 + (16 * 3) + (((lWidth + 1) / 2) * lHeight)) |
|
//***************************************************************************** |
// |
//! Determines the size of the buffer for an 8 BPP off-screen image. |
//! |
//! \param lWidth is the width of the image in pixels. |
//! \param lHeight is the height of the image in pixels. |
//! |
//! This function determines the size of the memory buffer required to hold an |
//! 8 BPP off-screen image of the specified geometry. |
//! |
//! \return Returns the number of bytes required by the image. |
// |
//***************************************************************************** |
#define GrOffScreen8BPPSize(lWidth, lHeight) \ |
(6 + (256 * 3) + (lWidth * lHeight)) |
|
//***************************************************************************** |
// |
//! Draws a pixel. |
//! |
//! \param pContext is a pointer to the drawing context to use. |
//! \param lX is the X coordinate of the pixel. |
//! \param lY is the Y coordinate of the pixel. |
//! |
//! This function draws a pixel if it resides within the clipping region. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrPixelDraw(pContext, lX, lY) \ |
do \ |
{ \ |
const tContext *pC = pContext; \ |
if((lX >= pC->sClipRegion.sXMin) && \ |
(lX <= pC->sClipRegion.sXMax) && \ |
(lY >= pC->sClipRegion.sYMin) && \ |
(lY <= pC->sClipRegion.sYMax)) \ |
{ \ |
DpyPixelDraw(pC->pDisplay, lX, lY, pC->ulForeground); \ |
} \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the baseline of a string. |
//! |
//! \param pContext is a pointer to the drawing context to query. |
//! |
//! This function determines the baseline position of a string. The baseline |
//! is the offset between the top of the string and the bottom of the capital |
//! letters. The only string data that exists below the baseline are the |
//! descenders on some lower-case letters (such as ``y''). |
//! |
//! \return Returns the baseline of the string, in pixels. |
// |
//***************************************************************************** |
#define GrStringBaselineGet(pContext) \ |
((pContext)->pFont->ucBaseline) |
|
//***************************************************************************** |
// |
//! Draws a centered string. |
//! |
//! \param pContext is a pointer to the drawing context to use. |
//! \param pcString is a pointer to the string to be drawn. |
//! \param lLength is the number of characters from the string that should be |
//! drawn on the screen. |
//! \param lX is the X coordinate of the center of the string position on the |
//! screen. |
//! \param lY is the Y coordinate of the center of the string position on the |
//! screen. |
//! \param bOpaque is \b true if the background of each character should be |
//! drawn and \b false if it should not (leaving the background as is). |
//! |
//! This function draws a string of test on the screen centered upon the |
//! provided position. The \e lLength parameter allows a portion of the |
//! string to be examined without having to insert a NULL character at the |
//! stopping point (which would not be possible if the string was located in |
//! flash); specifying a length of -1 will cause the entire string to be |
//! rendered (subject to clipping). |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define GrStringDrawCentered(pContext, pcString, lLength, lX, lY, bOpaque) \ |
do \ |
{ \ |
const tContext *pC = pContext; \ |
const char *pcStr = pcString; \ |
\ |
GrStringDraw(pC, pcStr, lLength, \ |
(lX) - (GrStringWidthGet(pC, pcStr, lLength) / 2), \ |
(lY) - (pC->pFont->ucBaseline / 2), bOpaque); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the height of a string. |
//! |
//! \param pContext is a pointer to the drawing context to query. |
//! |
//! This function determines the height of a string. The height is the offset |
//! between the top of the string and the bottom of the string, including any |
//! ascenders and descenders. Note that this will not account for the case |
//! where the string in question does not have any characters that use |
//! descenders but the font in the drawing context does contain characters with |
//! descenders. |
//! |
//! \return Returns the height of the string, in pixels. |
// |
//***************************************************************************** |
#define GrStringHeightGet(pContext) \ |
((pContext)->pFont->ucHeight) |
|
//***************************************************************************** |
// |
//! Gets the maximum width of a character in a string. |
//! |
//! \param pContext is a pointer to the drawing context to query. |
//! |
//! This function determines the maximum width of a character in a string. The |
//! maximum width is the width of the widest individual character in the font |
//! used to render the string, which may be wider than the widest character |
//! that is used to render a particular string. |
//! |
//! \return Returns the maximum width of a character in a string, in pixels. |
// |
//***************************************************************************** |
#define GrStringMaxWidthGet(pContext) \ |
((pContext)->pFont->ucMaxWidth) |
|
//***************************************************************************** |
// |
// A set of color definitions. This set is the subset of the X11 colors (from |
// rgb.txt) that are supported by typical web browsers. |
// |
//***************************************************************************** |
#define ClrAliceBlue 0x00F0F8FF |
#define ClrAntiqueWhite 0x00FAEBD7 |
#define ClrAqua 0x0000FFFF |
#define ClrAquamarine 0x007FFFD4 |
#define ClrAzure 0x00F0FFFF |
#define ClrBeige 0x00F5F5DC |
#define ClrBisque 0x00FFE4C4 |
#define ClrBlack 0x00000000 |
#define ClrBlanchedAlmond 0x00FFEBCD |
#define ClrBlue 0x000000FF |
#define ClrBlueViolet 0x008A2BE2 |
#define ClrBrown 0x00A52A2A |
#define ClrBurlyWood 0x00DEB887 |
#define ClrCadetBlue 0x005F9EA0 |
#define ClrChartreuse 0x007FFF00 |
#define ClrChocolate 0x00D2691E |
#define ClrCoral 0x00FF7F50 |
#define ClrCornflowerBlue 0x006495ED |
#define ClrCornsilk 0x00FFF8DC |
#define ClrCrimson 0x00DC143C |
#define ClrCyan 0x0000FFFF |
#define ClrDarkBlue 0x0000008B |
#define ClrDarkCyan 0x00008B8B |
#define ClrDarkGoldenrod 0x00B8860B |
#define ClrDarkGray 0x00A9A9A9 |
#define ClrDarkGreen 0x00006400 |
#define ClrDarkKhaki 0x00BDB76B |
#define ClrDarkMagenta 0x008B008B |
#define ClrDarkOliveGreen 0x00556B2F |
#define ClrDarkOrange 0x00FF8C00 |
#define ClrDarkOrchid 0x009932CC |
#define ClrDarkRed 0x008B0000 |
#define ClrDarkSalmon 0x00E9967A |
#define ClrDarkSeaGreen 0x008FBC8F |
#define ClrDarkSlateBlue 0x00483D8B |
#define ClrDarkSlateGray 0x002F4F4F |
#define ClrDarkTurquoise 0x0000CED1 |
#define ClrDarkViolet 0x009400D3 |
#define ClrDeepPink 0x00FF1493 |
#define ClrDeepSkyBlue 0x0000BFFF |
#define ClrDimGray 0x00696969 |
#define ClrDodgerBlue 0x001E90FF |
#define ClrFireBrick 0x00B22222 |
#define ClrFloralWhite 0x00FFFAF0 |
#define ClrForestGreen 0x00228B22 |
#define ClrFuchsia 0x00FF00FF |
#define ClrGainsboro 0x00DCDCDC |
#define ClrGhostWhite 0x00F8F8FF |
#define ClrGold 0x00FFD700 |
#define ClrGoldenrod 0x00DAA520 |
#define ClrGray 0x00808080 |
#define ClrGreen 0x00008000 |
#define ClrGreenYellow 0x00ADFF2F |
#define ClrHoneydew 0x00F0FFF0 |
#define ClrHotPink 0x00FF69B4 |
#define ClrIndianRed 0x00CD5C5C |
#define ClrIndigo 0x004B0082 |
#define ClrIvory 0x00FFFFF0 |
#define ClrKhaki 0x00F0E68C |
#define ClrLavender 0x00E6E6FA |
#define ClrLavenderBlush 0x00FFF0F5 |
#define ClrLawnGreen 0x007CFC00 |
#define ClrLemonChiffon 0x00FFFACD |
#define ClrLightBlue 0x00ADD8E6 |
#define ClrLightCoral 0x00F08080 |
#define ClrLightCyan 0x00E0FFFF |
#define ClrLightGoldenrodYellow 0x00FAFAD2 |
#define ClrLightGreen 0x0090EE90 |
#define ClrLightGrey 0x00D3D3D3 |
#define ClrLightPink 0x00FFB6C1 |
#define ClrLightSalmon 0x00FFA07A |
#define ClrLightSeaGreen 0x0020B2AA |
#define ClrLightSkyBlue 0x0087CEFA |
#define ClrLightSlateGray 0x00778899 |
#define ClrLightSteelBlue 0x00B0C4DE |
#define ClrLightYellow 0x00FFFFE0 |
#define ClrLime 0x0000FF00 |
#define ClrLimeGreen 0x0032CD32 |
#define ClrLinen 0x00FAF0E6 |
#define ClrMagenta 0x00FF00FF |
#define ClrMaroon 0x00800000 |
#define ClrMediumAquamarine 0x0066CDAA |
#define ClrMediumBlue 0x000000CD |
#define ClrMediumOrchid 0x00BA55D3 |
#define ClrMediumPurple 0x009370DB |
#define ClrMediumSeaGreen 0x003CB371 |
#define ClrMediumSlateBlue 0x007B68EE |
#define ClrMediumSpringGreen 0x0000FA9A |
#define ClrMediumTurquoise 0x0048D1CC |
#define ClrMediumVioletRed 0x00C71585 |
#define ClrMidnightBlue 0x00191970 |
#define ClrMintCream 0x00F5FFFA |
#define ClrMistyRose 0x00FFE4E1 |
#define ClrMoccasin 0x00FFE4B5 |
#define ClrNavajoWhite 0x00FFDEAD |
#define ClrNavy 0x00000080 |
#define ClrOldLace 0x00FDF5E6 |
#define ClrOlive 0x00808000 |
#define ClrOliveDrab 0x006B8E23 |
#define ClrOrange 0x00FFA500 |
#define ClrOrangeRed 0x00FF4500 |
#define ClrOrchid 0x00DA70D6 |
#define ClrPaleGoldenrod 0x00EEE8AA |
#define ClrPaleGreen 0x0098FB98 |
#define ClrPaleTurquoise 0x00AFEEEE |
#define ClrPaleVioletRed 0x00DB7093 |
#define ClrPapayaWhip 0x00FFEFD5 |
#define ClrPeachPuff 0x00FFDAB9 |
#define ClrPeru 0x00CD853F |
#define ClrPink 0x00FFC0CB |
#define ClrPlum 0x00DDA0DD |
#define ClrPowderBlue 0x00B0E0E6 |
#define ClrPurple 0x00800080 |
#define ClrRed 0x00FF0000 |
#define ClrRosyBrown 0x00BC8F8F |
#define ClrRoyalBlue 0x004169E1 |
#define ClrSaddleBrown 0x008B4513 |
#define ClrSalmon 0x00FA8072 |
#define ClrSandyBrown 0x00F4A460 |
#define ClrSeaGreen 0x002E8B57 |
#define ClrSeashell 0x00FFF5EE |
#define ClrSienna 0x00A0522D |
#define ClrSilver 0x00C0C0C0 |
#define ClrSkyBlue 0x0087CEEB |
#define ClrSlateBlue 0x006A5ACD |
#define ClrSlateGray 0x00708090 |
#define ClrSnow 0x00FFFAFA |
#define ClrSpringGreen 0x0000FF7F |
#define ClrSteelBlue 0x004682B4 |
#define ClrTan 0x00D2B48C |
#define ClrTeal 0x00008080 |
#define ClrThistle 0x00D8BFD8 |
#define ClrTomato 0x00FF6347 |
#define ClrTurquoise 0x0040E0D0 |
#define ClrViolet 0x00EE82EE |
#define ClrWheat 0x00F5DEB3 |
#define ClrWhite 0x00FFFFFF |
#define ClrWhiteSmoke 0x00F5F5F5 |
#define ClrYellow 0x00FFFF00 |
#define ClrYellowGreen 0x009ACD32 |
|
//***************************************************************************** |
// |
// Masks and shifts to aid in color format translation by drivers. |
// |
//***************************************************************************** |
#define ClrRedMask 0x00FF0000 |
#define ClrRedShift 16 |
#define ClrGreenMask 0x0000FF00 |
#define ClrGreenShift 8 |
#define ClrBlueMask 0x000000FF |
#define ClrBlueShift 0 |
|
//***************************************************************************** |
// |
// Prototypes for the predefined fonts in the graphics library. ..Cm.. is the |
// computer modern font, which is a serif font. ..Cmsc.. is the computer |
// modern small-caps font, which is also a serif font. ..Cmss.. is the |
// computer modern sans-serif font. |
// |
//***************************************************************************** |
extern const tFont g_sFontCm12; |
extern const tFont g_sFontCm12b; |
extern const tFont g_sFontCm12i; |
extern const tFont g_sFontCm14; |
extern const tFont g_sFontCm14b; |
extern const tFont g_sFontCm14i; |
extern const tFont g_sFontCm16; |
extern const tFont g_sFontCm16b; |
extern const tFont g_sFontCm16i; |
extern const tFont g_sFontCm18; |
extern const tFont g_sFontCm18b; |
extern const tFont g_sFontCm18i; |
extern const tFont g_sFontCm20; |
extern const tFont g_sFontCm20b; |
extern const tFont g_sFontCm20i; |
extern const tFont g_sFontCm22; |
extern const tFont g_sFontCm22b; |
extern const tFont g_sFontCm22i; |
extern const tFont g_sFontCm24; |
extern const tFont g_sFontCm24b; |
extern const tFont g_sFontCm24i; |
extern const tFont g_sFontCm26; |
extern const tFont g_sFontCm26b; |
extern const tFont g_sFontCm26i; |
extern const tFont g_sFontCm28; |
extern const tFont g_sFontCm28b; |
extern const tFont g_sFontCm28i; |
extern const tFont g_sFontCm30; |
extern const tFont g_sFontCm30b; |
extern const tFont g_sFontCm30i; |
extern const tFont g_sFontCm32; |
extern const tFont g_sFontCm32b; |
extern const tFont g_sFontCm32i; |
extern const tFont g_sFontCm34; |
extern const tFont g_sFontCm34b; |
extern const tFont g_sFontCm34i; |
extern const tFont g_sFontCm36; |
extern const tFont g_sFontCm36b; |
extern const tFont g_sFontCm36i; |
extern const tFont g_sFontCm38; |
extern const tFont g_sFontCm38b; |
extern const tFont g_sFontCm38i; |
extern const tFont g_sFontCm40; |
extern const tFont g_sFontCm40b; |
extern const tFont g_sFontCm40i; |
extern const tFont g_sFontCm42; |
extern const tFont g_sFontCm42b; |
extern const tFont g_sFontCm42i; |
extern const tFont g_sFontCm44; |
extern const tFont g_sFontCm44b; |
extern const tFont g_sFontCm44i; |
extern const tFont g_sFontCm46; |
extern const tFont g_sFontCm46b; |
extern const tFont g_sFontCm46i; |
extern const tFont g_sFontCm48; |
extern const tFont g_sFontCm48b; |
extern const tFont g_sFontCm48i; |
extern const tFont g_sFontCmsc12; |
extern const tFont g_sFontCmsc14; |
extern const tFont g_sFontCmsc16; |
extern const tFont g_sFontCmsc18; |
extern const tFont g_sFontCmsc20; |
extern const tFont g_sFontCmsc22; |
extern const tFont g_sFontCmsc24; |
extern const tFont g_sFontCmsc26; |
extern const tFont g_sFontCmsc28; |
extern const tFont g_sFontCmsc30; |
extern const tFont g_sFontCmsc32; |
extern const tFont g_sFontCmsc34; |
extern const tFont g_sFontCmsc36; |
extern const tFont g_sFontCmsc38; |
extern const tFont g_sFontCmsc40; |
extern const tFont g_sFontCmsc42; |
extern const tFont g_sFontCmsc44; |
extern const tFont g_sFontCmsc46; |
extern const tFont g_sFontCmsc48; |
extern const tFont g_sFontCmss12; |
extern const tFont g_sFontCmss12b; |
extern const tFont g_sFontCmss12i; |
extern const tFont g_sFontCmss14; |
extern const tFont g_sFontCmss14b; |
extern const tFont g_sFontCmss14i; |
extern const tFont g_sFontCmss16; |
extern const tFont g_sFontCmss16b; |
extern const tFont g_sFontCmss16i; |
extern const tFont g_sFontCmss18; |
extern const tFont g_sFontCmss18b; |
extern const tFont g_sFontCmss18i; |
extern const tFont g_sFontCmss20; |
extern const tFont g_sFontCmss20b; |
extern const tFont g_sFontCmss20i; |
extern const tFont g_sFontCmss22; |
extern const tFont g_sFontCmss22b; |
extern const tFont g_sFontCmss22i; |
extern const tFont g_sFontCmss24; |
extern const tFont g_sFontCmss24b; |
extern const tFont g_sFontCmss24i; |
extern const tFont g_sFontCmss26; |
extern const tFont g_sFontCmss26b; |
extern const tFont g_sFontCmss26i; |
extern const tFont g_sFontCmss28; |
extern const tFont g_sFontCmss28b; |
extern const tFont g_sFontCmss28i; |
extern const tFont g_sFontCmss30; |
extern const tFont g_sFontCmss30b; |
extern const tFont g_sFontCmss30i; |
extern const tFont g_sFontCmss32; |
extern const tFont g_sFontCmss32b; |
extern const tFont g_sFontCmss32i; |
extern const tFont g_sFontCmss34; |
extern const tFont g_sFontCmss34b; |
extern const tFont g_sFontCmss34i; |
extern const tFont g_sFontCmss36; |
extern const tFont g_sFontCmss36b; |
extern const tFont g_sFontCmss36i; |
extern const tFont g_sFontCmss38; |
extern const tFont g_sFontCmss38b; |
extern const tFont g_sFontCmss38i; |
extern const tFont g_sFontCmss40; |
extern const tFont g_sFontCmss40b; |
extern const tFont g_sFontCmss40i; |
extern const tFont g_sFontCmss42; |
extern const tFont g_sFontCmss42b; |
extern const tFont g_sFontCmss42i; |
extern const tFont g_sFontCmss44; |
extern const tFont g_sFontCmss44b; |
extern const tFont g_sFontCmss44i; |
extern const tFont g_sFontCmss46; |
extern const tFont g_sFontCmss46b; |
extern const tFont g_sFontCmss46i; |
extern const tFont g_sFontCmss48; |
extern const tFont g_sFontCmss48b; |
extern const tFont g_sFontCmss48i; |
extern const tFont g_sFontFixed6x8; |
|
//***************************************************************************** |
// |
//! Translates a 24-bit RGB color to a display driver-specific color. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param ulValue is the 24-bit RGB color. The least-significant byte is the |
//! blue channel, the next byte is the green channel, and the third byte is the |
//! red channel. |
//! |
//! This function translates a 24-bit RGB color into a value that can be |
//! written into the display's frame buffer in order to reproduce that color, |
//! or the closest possible approximation of that color. |
//! |
//! \return Returns the display-driver specific color. |
// |
//***************************************************************************** |
#define DpyColorTranslate(pDisplay, ulValue) \ |
((pDisplay)->pfnColorTranslate((pDisplay)->pvDisplayData, ulValue)) |
|
//***************************************************************************** |
// |
//! Flushes cached drawing operations. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! |
//! This function flushes any cached drawing operations on a display. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyFlush(pDisplay) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnFlush(pD->pvDisplayData); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the height of the display. |
//! |
//! \param pDisplay is a pointer to the display driver structure for the |
//! display to query. |
//! |
//! This function determines the height of the display. |
//! |
//! \return Returns the height of the display in pixels. |
// |
//***************************************************************************** |
#define DpyHeightGet(pDisplay) \ |
((pDisplay)->usHeight) |
|
//***************************************************************************** |
// |
//! Draws a horizontal line on a display. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param lX1 is the starting X coordinate of the line. |
//! \param lX2 is the ending X coordinate of the line. |
//! \param lY is the Y coordinate of the line. |
//! \param ulValue is the color to draw the line. |
//! |
//! This function draws a horizontal line on a display. This assumes that |
//! clipping has already been performed, and that both end points of the line |
//! are within the extents of the display. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyLineDrawH(pDisplay, lX1, lX2, lY, ulValue) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnLineDrawH(pD->pvDisplayData, lX1, lX2, lY, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Draws a vertical line on a display. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param lX is the X coordinate of the line. |
//! \param lY1 is the starting Y coordinate of the line. |
//! \param lY2 is the ending Y coordinate of the line. |
//! \param ulValue is the color to draw the line. |
//! |
//! This function draws a vertical line on a display. This assumes that |
//! clipping has already been performed, and that both end points of the line |
//! are within the extents of the display. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyLineDrawV(pDisplay, lX, lY1, lY2, ulValue) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnLineDrawV(pD->pvDisplayData, lX, lY1, lY2, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Draws a pixel on a display. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param lX is the X coordinate of the pixel. |
//! \param lY is the Y coordinate of the pixel. |
//! \param ulValue is the color to draw the pixel. |
//! |
//! This function draws a pixel on a display. This assumes that clipping has |
//! already been performed. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyPixelDraw(pDisplay, lX, lY, ulValue) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnPixelDraw(pD->pvDisplayData, lX, lY, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Draws a horizontal sequence of pixels on a display. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param lX is the X coordinate of the first pixel. |
//! \param lY is the Y coordinate of the first pixel. |
//! \param lX0 is sub-pixel offset within the pixel data, which is valid for 1 |
//! or 4 bit per pixel formats. |
//! \param lCount is the number of pixels to draw. |
//! \param lBPP is the number of bits per pixel; must be 1, 4, or 8. |
//! \param pucData is a pointer to the pixel data. For 1 and 4 bit per pixel |
//! formats, the most significant bit(s) represent the left-most pixel. |
//! \param pucPalette is a pointer to the palette used to draw the pixels. |
//! |
//! This function draws a horizontal sequence of pixels on a display, using the |
//! supplied palette. For 1 bit per pixel format, the palette contains |
//! pre-translated colors; for 4 and 8 bit per pixel formats, the palette |
//! contains 24-bit RGB values that must be translated before being written to |
//! the display. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyPixelDrawMultiple(pDisplay, lX, lY, lX0, lCount, lBPP, pucData, \ |
pucPalette) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnPixelDrawMultiple(pD->pvDisplayData, lX, lY, lX0, lCount, \ |
lBPP, pucData, pucPalette); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Fills a rectangle on a display. |
//! |
//! \param pDisplay is the pointer to the display driver structure for the |
//! display to operate upon. |
//! \param pRect is a pointer to the structure describing the rectangle to |
//! fill. |
//! \param ulValue is the color to fill the rectangle. |
//! |
//! This function fills a rectangle on the display. This assumes that clipping |
//! has already been performed, and that all sides of the rectangle are within |
//! the extents of the display. |
//! |
//! \return None. |
// |
//***************************************************************************** |
#define DpyRectFill(pDisplay, pRect, ulValue) \ |
do \ |
{ \ |
const tDisplay *pD = pDisplay; \ |
pD->pfnRectFill(pD->pvDisplayData, pRect, ulValue); \ |
} \ |
while(0) |
|
//***************************************************************************** |
// |
//! Gets the width of the display. |
//! |
//! \param pDisplay is a pointer to the display driver structure for the |
//! display to query. |
//! |
//! This function determines the width of the display. |
//! |
//! \return Returns the width of the display in pixels. |
// |
//***************************************************************************** |
#define DpyWidthGet(pDisplay) \ |
((pDisplay)->usWidth) |
|
//***************************************************************************** |
// |
// Prototypes for the graphics library functions. |
// |
//***************************************************************************** |
extern void GrCircleDraw(const tContext *pContext, long lX, long lY, |
long lRadius); |
extern void GrCircleFill(const tContext *pContext, long lX, long lY, |
long lRadius); |
extern void GrContextClipRegionSet(tContext *pContext, tRectangle *pRect); |
extern void GrContextInit(tContext *pContext, const tDisplay *pDisplay); |
extern void GrImageDraw(const tContext *pContext, |
const unsigned char *pucImage, long lX, long lY); |
extern void GrLineDraw(const tContext *pContext, long lX1, long lY1, long lX2, |
long lY2); |
extern void GrLineDrawH(const tContext *pContext, long lX1, long lX2, long lY); |
extern void GrLineDrawV(const tContext *pContext, long lX, long lY1, long lY2); |
extern void GrOffScreen1BPPInit(tDisplay *pDisplay, unsigned char *pucImage, |
long lWidth, long lHeight); |
extern void GrOffScreen4BPPInit(tDisplay *pDisplay, unsigned char *pucImage, |
long lWidth, long lHeight); |
extern void GrOffScreen4BPPPaletteSet(tDisplay *pDisplay, |
unsigned long *pulPalette, |
unsigned long ulOffset, |
unsigned long ulCount); |
extern void GrOffScreen8BPPInit(tDisplay *pDisplay, unsigned char *pucImage, |
long lWidth, long lHeight); |
extern void GrOffScreen8BPPPaletteSet(tDisplay *pDisplay, |
unsigned long *pulPalette, |
unsigned long ulOffset, |
unsigned long ulCount); |
extern void GrRectDraw(const tContext *pContext, const tRectangle *pRect); |
extern void GrRectFill(const tContext *pContext, const tRectangle *pRect); |
extern void GrStringDraw(const tContext *pContext, const char *pcString, |
long lLength, long lX, long lY, |
unsigned long bOpaque); |
extern long GrStringWidthGet(const tContext *pContext, const char *pcString, |
long lLength); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
//***************************************************************************** |
// |
// Close the Doxygen group. |
//! @} |
// |
//***************************************************************************** |
|
#endif // __GRLIB_H__ |
/drivers/LuminaryMicro/hw_can.h
0,0 → 1,757
//***************************************************************************** |
// |
// hw_can.h - Defines and macros used when accessing the can. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_CAN_H__ |
#define __HW_CAN_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the CAN register offsets. |
// |
//***************************************************************************** |
#define CAN_O_CTL 0x00000000 // Control register |
#define CAN_O_STS 0x00000004 // Status register |
#define CAN_O_ERR 0x00000008 // Error register |
#define CAN_O_BIT 0x0000000C // Bit Timing register |
#define CAN_O_INT 0x00000010 // Interrupt register |
#define CAN_O_TST 0x00000014 // Test register |
#define CAN_O_BRPE 0x00000018 // Baud Rate Prescaler register |
#define CAN_O_IF1CRQ 0x00000020 // Interface 1 Command Request reg. |
#define CAN_O_IF1CMSK 0x00000024 // Interface 1 Command Mask reg. |
#define CAN_O_IF1MSK1 0x00000028 // Interface 1 Mask 1 register |
#define CAN_O_IF1MSK2 0x0000002C // Interface 1 Mask 2 register |
#define CAN_O_IF1ARB1 0x00000030 // Interface 1 Arbitration 1 reg. |
#define CAN_O_IF1ARB2 0x00000034 // Interface 1 Arbitration 2 reg. |
#define CAN_O_IF1MCTL 0x00000038 // Interface 1 Message Control reg. |
#define CAN_O_IF1DA1 0x0000003C // Interface 1 DataA 1 register |
#define CAN_O_IF1DA2 0x00000040 // Interface 1 DataA 2 register |
#define CAN_O_IF1DB1 0x00000044 // Interface 1 DataB 1 register |
#define CAN_O_IF1DB2 0x00000048 // Interface 1 DataB 2 register |
#define CAN_O_IF2CRQ 0x00000080 // Interface 2 Command Request reg. |
#define CAN_O_IF2CMSK 0x00000084 // Interface 2 Command Mask reg. |
#define CAN_O_IF2MSK1 0x00000088 // Interface 2 Mask 1 register |
#define CAN_O_IF2MSK2 0x0000008C // Interface 2 Mask 2 register |
#define CAN_O_IF2ARB1 0x00000090 // Interface 2 Arbitration 1 reg. |
#define CAN_O_IF2ARB2 0x00000094 // Interface 2 Arbitration 2 reg. |
#define CAN_O_IF2MCTL 0x00000098 // Interface 2 Message Control reg. |
#define CAN_O_IF2DA1 0x0000009C // Interface 2 DataA 1 register |
#define CAN_O_IF2DA2 0x000000A0 // Interface 2 DataA 2 register |
#define CAN_O_IF2DB1 0x000000A4 // Interface 2 DataB 1 register |
#define CAN_O_IF2DB2 0x000000A8 // Interface 2 DataB 2 register |
#define CAN_O_TXRQ1 0x00000100 // Transmission Request 1 register |
#define CAN_O_TXRQ2 0x00000104 // Transmission Request 2 register |
#define CAN_O_NWDA1 0x00000120 // New Data 1 register |
#define CAN_O_NWDA2 0x00000124 // New Data 2 register |
#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending |
#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending |
#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid |
#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_CTL register. |
// |
//***************************************************************************** |
#define CAN_CTL_TEST 0x00000080 // Test mode enable |
#define CAN_CTL_CCE 0x00000040 // Configuration change enable |
#define CAN_CTL_DAR 0x00000020 // Disable automatic retransmission |
#define CAN_CTL_EIE 0x00000008 // Error interrupt enable |
#define CAN_CTL_SIE 0x00000004 // Status change interrupt enable |
#define CAN_CTL_IE 0x00000002 // Module interrupt enable |
#define CAN_CTL_INIT 0x00000001 // Initialization |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_STS register. |
// |
//***************************************************************************** |
#define CAN_STS_BOFF 0x00000080 // Bus Off status |
#define CAN_STS_EWARN 0x00000040 // Error Warning status |
#define CAN_STS_EPASS 0x00000020 // Error Passive status |
#define CAN_STS_RXOK 0x00000010 // Received Message Successful |
#define CAN_STS_TXOK 0x00000008 // Transmitted Message Successful |
#define CAN_STS_LEC_M 0x00000007 // Last Error Code |
#define CAN_STS_LEC_NONE 0x00000000 // No error |
#define CAN_STS_LEC_STUFF 0x00000001 // Stuff error |
#define CAN_STS_LEC_FORM 0x00000002 // Form(at) error |
#define CAN_STS_LEC_ACK 0x00000003 // Ack error |
#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 error |
#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 error |
#define CAN_STS_LEC_CRC 0x00000006 // CRC error |
#define CAN_STS_LEC_NOEVENT 0x00000007 // Unused |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_ERR register. |
// |
//***************************************************************************** |
#define CAN_ERR_RP 0x00008000 // Receive error passive status |
#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter. |
#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter. |
#define CAN_ERR_REC_S 8 // Receive error counter bit pos |
#define CAN_ERR_TEC_S 0 // Transmit error counter bit pos |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_BIT register. |
// |
//***************************************************************************** |
#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point. |
#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample |
// Point. |
#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width. |
#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescalar. |
#define CAN_BIT_TSEG2_S 12 |
#define CAN_BIT_TSEG1_S 8 |
#define CAN_BIT_SJW_S 6 |
#define CAN_BIT_BRP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_INT register. |
// |
//***************************************************************************** |
#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier. |
#define CAN_INT_INTID_NONE 0x00000000 // No Interrupt Pending |
#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_TST register. |
// |
//***************************************************************************** |
#define CAN_TST_RX 0x00000080 // CAN_RX pin status |
#define CAN_TST_TX_M 0x00000060 // Overide control of CAN_TX pin |
#define CAN_TST_TX_CANCTL 0x00000000 // CAN core controls CAN_TX |
#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point on CAN_TX |
#define CAN_TST_TX_DOMINANT 0x00000040 // Dominant value on CAN_TX |
#define CAN_TST_TX_RECESSIVE 0x00000060 // Recessive value on CAN_TX |
#define CAN_TST_LBACK 0x00000010 // Loop back mode |
#define CAN_TST_SILENT 0x00000008 // Silent mode |
#define CAN_TST_BASIC 0x00000004 // Basic mode |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_BRPE register. |
// |
//***************************************************************************** |
#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescalar Extension. |
#define CAN_BRPE_BRPE_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_TXRQ1 register. |
// |
//***************************************************************************** |
#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits. |
#define CAN_TXRQ1_TXRQST_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_TXRQ2 register. |
// |
//***************************************************************************** |
#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits. |
#define CAN_TXRQ2_TXRQST_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_NWDA1 register. |
// |
//***************************************************************************** |
#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits. |
#define CAN_NWDA1_NEWDAT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_NWDA2 register. |
// |
//***************************************************************************** |
#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits. |
#define CAN_NWDA2_NEWDAT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1CRQ register. |
// |
//***************************************************************************** |
#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag. |
#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number. |
#define CAN_IF1CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; |
// it is interpreted as 0x20, or |
// object 32. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1CMSK register. |
// |
//***************************************************************************** |
#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read. |
#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits. |
#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits. |
#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits. |
#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. |
#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data. |
#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request. |
#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. |
#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1MSK1 register. |
// |
//***************************************************************************** |
#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. |
#define CAN_IF1MSK1_IDMSK_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1MSK2 register. |
// |
//***************************************************************************** |
#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier. |
#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction. |
#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask. |
#define CAN_IF1MSK2_IDMSK_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1ARB1 register. |
// |
//***************************************************************************** |
#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier. |
#define CAN_IF1ARB1_ID_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1ARB2 register. |
// |
//***************************************************************************** |
#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid. |
#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier. |
#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction. |
#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier. |
#define CAN_IF1ARB2_ID_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1MCTL register. |
// |
//***************************************************************************** |
#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data. |
#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost. |
#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending. |
#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask. |
#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. |
#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable. |
#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable. |
#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request. |
#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer. |
#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code. |
#define CAN_IF1MCTL_DLC_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1DA1 register. |
// |
//***************************************************************************** |
#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data. |
#define CAN_IF1DA1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1DA2 register. |
// |
//***************************************************************************** |
#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data. |
#define CAN_IF1DA2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1DB1 register. |
// |
//***************************************************************************** |
#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data. |
#define CAN_IF1DB1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF1DB2 register. |
// |
//***************************************************************************** |
#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data. |
#define CAN_IF1DB2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2CRQ register. |
// |
//***************************************************************************** |
#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag. |
#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number. |
#define CAN_IF2CRQ_MNUM_RSVD 0x00000000 // 0 is not a valid message number; |
// it is interpreted as 0x20, or |
// object 32. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2CMSK register. |
// |
//***************************************************************************** |
#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read. |
#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits. |
#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits. |
#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits. |
#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit. |
#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data. |
#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request. |
#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3. |
#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2MSK1 register. |
// |
//***************************************************************************** |
#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask. |
#define CAN_IF2MSK1_IDMSK_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2MSK2 register. |
// |
//***************************************************************************** |
#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier. |
#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction. |
#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask. |
#define CAN_IF2MSK2_IDMSK_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2ARB1 register. |
// |
//***************************************************************************** |
#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier. |
#define CAN_IF2ARB1_ID_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2ARB2 register. |
// |
//***************************************************************************** |
#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid. |
#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier. |
#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction. |
#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier. |
#define CAN_IF2ARB2_ID_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2MCTL register. |
// |
//***************************************************************************** |
#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data. |
#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost. |
#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending. |
#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask. |
#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable. |
#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable. |
#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable. |
#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request. |
#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer. |
#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code. |
#define CAN_IF2MCTL_DLC_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2DA1 register. |
// |
//***************************************************************************** |
#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data. |
#define CAN_IF2DA1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2DA2 register. |
// |
//***************************************************************************** |
#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data. |
#define CAN_IF2DA2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2DB1 register. |
// |
//***************************************************************************** |
#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data. |
#define CAN_IF2DB1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_IF2DB2 register. |
// |
//***************************************************************************** |
#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data. |
#define CAN_IF2DB2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_MSG1INT register. |
// |
//***************************************************************************** |
#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. |
#define CAN_MSG1INT_INTPND_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_MSG2INT register. |
// |
//***************************************************************************** |
#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits. |
#define CAN_MSG2INT_INTPND_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_MSG1VAL register. |
// |
//***************************************************************************** |
#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. |
#define CAN_MSG1VAL_MSGVAL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the CAN_O_MSG2VAL register. |
// |
//***************************************************************************** |
#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits. |
#define CAN_MSG2VAL_MSGVAL_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the CAN register offsets. |
// |
//***************************************************************************** |
#define CAN_O_MSGINT1 0x00000140 // Intr. Pending in Msg Obj 1 reg. |
#define CAN_O_MSGINT2 0x00000144 // Intr. Pending in Msg Obj 2 reg. |
#define CAN_O_MSGVAL1 0x00000160 // Message Valid in Msg Obj 1 reg. |
#define CAN_O_MSGVAL2 0x00000164 // Message Valid in Msg Obj 2 reg. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values of the can |
// registers. |
// |
//***************************************************************************** |
#define CAN_RV_IF1MSK2 0x0000FFFF |
#define CAN_RV_IF1MSK1 0x0000FFFF |
#define CAN_RV_IF2MSK1 0x0000FFFF |
#define CAN_RV_IF2MSK2 0x0000FFFF |
#define CAN_RV_BIT 0x00002301 |
#define CAN_RV_CTL 0x00000001 |
#define CAN_RV_IF1CRQ 0x00000001 |
#define CAN_RV_IF2CRQ 0x00000001 |
#define CAN_RV_TXRQ2 0x00000000 |
#define CAN_RV_IF2DB1 0x00000000 |
#define CAN_RV_INT 0x00000000 |
#define CAN_RV_IF1DB2 0x00000000 |
#define CAN_RV_BRPE 0x00000000 |
#define CAN_RV_IF2DA2 0x00000000 |
#define CAN_RV_MSGVAL2 0x00000000 |
#define CAN_RV_TXRQ1 0x00000000 |
#define CAN_RV_IF1MCTL 0x00000000 |
#define CAN_RV_IF1DB1 0x00000000 |
#define CAN_RV_STS 0x00000000 |
#define CAN_RV_MSGINT1 0x00000000 |
#define CAN_RV_IF1DA2 0x00000000 |
#define CAN_RV_TST 0x00000000 |
#define CAN_RV_IF1ARB1 0x00000000 |
#define CAN_RV_IF1ARB2 0x00000000 |
#define CAN_RV_NWDA2 0x00000000 |
#define CAN_RV_IF2CMSK 0x00000000 |
#define CAN_RV_NWDA1 0x00000000 |
#define CAN_RV_IF1DA1 0x00000000 |
#define CAN_RV_IF2DA1 0x00000000 |
#define CAN_RV_IF2MCTL 0x00000000 |
#define CAN_RV_MSGVAL1 0x00000000 |
#define CAN_RV_IF1CMSK 0x00000000 |
#define CAN_RV_ERR 0x00000000 |
#define CAN_RV_IF2ARB2 0x00000000 |
#define CAN_RV_MSGINT2 0x00000000 |
#define CAN_RV_IF2ARB1 0x00000000 |
#define CAN_RV_IF2DB2 0x00000000 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_STS |
// register. |
// |
//***************************************************************************** |
#define CAN_STS_LEC_MSK 0x00000007 // Last Error Code |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_ERR |
// register. |
// |
//***************************************************************************** |
#define CAN_ERR_REC_MASK 0x00007F00 // Receive error counter status |
#define CAN_ERR_TEC_MASK 0x000000FF // Transmit error counter status |
#define CAN_ERR_REC_SHIFT 8 // Receive error counter bit pos |
#define CAN_ERR_TEC_SHIFT 0 // Transmit error counter bit pos |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_BIT |
// register. |
// |
//***************************************************************************** |
#define CAN_BIT_TSEG2 0x00007000 // Time segment after sample point |
#define CAN_BIT_TSEG1 0x00000F00 // Time segment before sample point |
#define CAN_BIT_SJW 0x000000C0 // (Re)Synchronization jump width |
#define CAN_BIT_BRP 0x0000003F // Baud rate prescaler |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_INT |
// register. |
// |
//***************************************************************************** |
#define CAN_INT_INTID_MSK 0x0000FFFF // Interrupt Identifier |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_TST |
// register. |
// |
//***************************************************************************** |
#define CAN_TST_TX_MSK 0x00000060 // Overide control of CAN_TX pin |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_BRPE |
// register. |
// |
//***************************************************************************** |
#define CAN_BRPE_BRPE 0x0000000F // Baud rate prescaler extension |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1CRQ |
// and CAN_IF1CRQ registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFCRQ_BUSY 0x00008000 // Busy flag status |
#define CAN_IFCRQ_MNUM_MSK 0x0000003F // Message Number |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1CMSK |
// and CAN_IF2CMSK registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFCMSK_WRNRD 0x00000080 // Write, not Read |
#define CAN_IFCMSK_MASK 0x00000040 // Access Mask Bits |
#define CAN_IFCMSK_ARB 0x00000020 // Access Arbitration Bits |
#define CAN_IFCMSK_CONTROL 0x00000010 // Access Control Bits |
#define CAN_IFCMSK_CLRINTPND 0x00000008 // Clear interrupt pending Bit |
#define CAN_IFCMSK_TXRQST 0x00000004 // Access Tx request bit (WRNRD=1) |
#define CAN_IFCMSK_NEWDAT 0x00000004 // Access New Data bit (WRNRD=0) |
#define CAN_IFCMSK_DATAA 0x00000002 // DataA access - bytes 0 to 3 |
#define CAN_IFCMSK_DATAB 0x00000001 // DataB access - bytes 4 to 7 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1MSK1 |
// and CAN_IF2MSK1 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFMSK1_MSK 0x0000FFFF // Identifier Mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1MSK2 |
// and CAN_IF2MSK2 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFMSK2_MXTD 0x00008000 // Mask extended identifier |
#define CAN_IFMSK2_MDIR 0x00004000 // Mask message direction |
#define CAN_IFMSK2_MSK 0x00001FFF // Mask identifier |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1ARB1 |
// and CAN_IF2ARB1 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFARB1_ID 0x0000FFFF // Identifier |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1ARB2 |
// and CAN_IF2ARB2 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFARB2_MSGVAL 0x00008000 // Message valid |
#define CAN_IFARB2_XTD 0x00004000 // Extended identifier |
#define CAN_IFARB2_DIR 0x00002000 // Message direction |
#define CAN_IFARB2_ID 0x00001FFF // Message identifier |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1MCTL |
// and CAN_IF2MCTL registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFMCTL_NEWDAT 0x00008000 // New Data |
#define CAN_IFMCTL_MSGLST 0x00004000 // Message lost |
#define CAN_IFMCTL_INTPND 0x00002000 // Interrupt pending |
#define CAN_IFMCTL_UMASK 0x00001000 // Use acceptance mask |
#define CAN_IFMCTL_TXIE 0x00000800 // Transmit interrupt enable |
#define CAN_IFMCTL_RXIE 0x00000400 // Receive interrupt enable |
#define CAN_IFMCTL_RMTEN 0x00000200 // Remote enable |
#define CAN_IFMCTL_TXRQST 0x00000100 // Transmit request |
#define CAN_IFMCTL_EOB 0x00000080 // End of buffer |
#define CAN_IFMCTL_DLC 0x0000000F // Data length code |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1DA1 |
// and CAN_IF2DA1 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFDA1_DATA 0x0000FFFF // Data - bytes 1 and 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1DA2 |
// and CAN_IF2DA2 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFDA2_DATA 0x0000FFFF // Data - bytes 3 and 2 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1DB1 |
// and CAN_IF2DB1 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFDB1_DATA 0x0000FFFF // Data - bytes 5 and 4 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_IF1DB2 |
// and CAN_IF2DB2 registers. |
// Note: All bits may not be available in all registers |
// |
//***************************************************************************** |
#define CAN_IFDB2_DATA 0x0000FFFF // Data - bytes 7 and 6 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_TXRQ1 |
// register. |
// |
//***************************************************************************** |
#define CAN_TXRQ1_TXRQST 0x0000FFFF // Transmission Request Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_TXRQ2 |
// register. |
// |
//***************************************************************************** |
#define CAN_TXRQ2_TXRQST 0x0000FFFF // Transmission Request Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_NWDA1 |
// register. |
// |
//***************************************************************************** |
#define CAN_NWDA1_NEWDATA 0x0000FFFF // New Data Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_NWDA2 |
// register. |
// |
//***************************************************************************** |
#define CAN_NWDA2_NEWDATA 0x0000FFFF // New Data Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_MSGINT1 |
// register. |
// |
//***************************************************************************** |
#define CAN_MSGINT1_INTPND 0x0000FFFF // Interrupt Pending Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_MSGINT2 |
// register. |
// |
//***************************************************************************** |
#define CAN_MSGINT2_INTPND 0x0000FFFF // Interrupt Pending Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_MSGVAL1 |
// register. |
// |
//***************************************************************************** |
#define CAN_MSGVAL1_MSGVAL 0x0000FFFF // Message Valid Bits |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the CAN_MSGVAL2 |
// register. |
// |
//***************************************************************************** |
#define CAN_MSGVAL2_MSGVAL 0x0000FFFF // Message Valid Bits |
|
#endif |
|
#endif // __HW_CAN_H__ |
/drivers/LuminaryMicro/hibernate.h
0,0 → 1,131
//***************************************************************************** |
// |
// hibernate.h - API definition for the Hibernation module. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HIBERNATE_H__ |
#define __HIBERNATE_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Macros needed for selecting the clock source for HibernateClockSelect() |
// |
//***************************************************************************** |
#define HIBERNATE_CLOCK_SEL_RAW 0x04 |
#define HIBERNATE_CLOCK_SEL_DIV128 0x00 |
|
//***************************************************************************** |
// |
// Macros need to configure wake events for HibernateWakeSet() |
// |
//***************************************************************************** |
#define HIBERNATE_WAKE_PIN 0x10 |
#define HIBERNATE_WAKE_RTC 0x08 |
|
//***************************************************************************** |
// |
// Macros needed to configure low battery detect for HibernateLowBatSet() |
// |
//***************************************************************************** |
#define HIBERNATE_LOW_BAT_DETECT 0x20 |
#define HIBERNATE_LOW_BAT_ABORT 0xA0 |
|
//***************************************************************************** |
// |
// Macros defining interrupt source bits for the interrupt functions. |
// |
//***************************************************************************** |
#define HIBERNATE_INT_PIN_WAKE 0x08 |
#define HIBERNATE_INT_LOW_BAT 0x04 |
#define HIBERNATE_INT_RTC_MATCH_0 0x01 |
#define HIBERNATE_INT_RTC_MATCH_1 0x02 |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void HibernateEnableExpClk(unsigned long ulHibClk); |
extern void HibernateDisable(void); |
extern void HibernateClockSelect(unsigned long ulClockInput); |
extern void HibernateRTCEnable(void); |
extern void HibernateRTCDisable(void); |
extern void HibernateWakeSet(unsigned long ulWakeFlags); |
extern unsigned long HibernateWakeGet(void); |
extern void HibernateLowBatSet(unsigned long ulLowBatFlags); |
extern unsigned long HibernateLowBatGet(void); |
extern void HibernateRTCSet(unsigned long ulRTCValue); |
extern unsigned long HibernateRTCGet(void); |
extern void HibernateRTCMatch0Set(unsigned long ulMatch); |
extern unsigned long HibernateRTCMatch0Get(void); |
extern void HibernateRTCMatch1Set(unsigned long ulMatch); |
extern unsigned long HibernateRTCMatch1Get(void); |
extern void HibernateRTCTrimSet(unsigned long ulTrim); |
extern unsigned long HibernateRTCTrimGet(void); |
extern void HibernateDataSet(unsigned long *pulData, unsigned long ulCount); |
extern void HibernateDataGet(unsigned long *pulData, unsigned long ulCount); |
extern void HibernateRequest(void); |
extern void HibernateIntEnable(unsigned long ulIntFlags); |
extern void HibernateIntDisable(unsigned long ulIntFlags); |
extern void HibernateIntRegister(void (*pfnHandler)(void)); |
extern void HibernateIntUnregister(void); |
extern unsigned long HibernateIntStatus(tBoolean bMasked); |
extern void HibernateIntClear(unsigned long ulIntFlags); |
extern unsigned int HibernateIsActive(void); |
|
//***************************************************************************** |
// |
// Several Hibernate module APIs have been renamed, with the original function |
// name being deprecated. These defines provide backward compatibility. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#include "sysctl.h" |
#define HibernateEnable(a) \ |
HibernateEnableExpClk(a, SysCtlClockGet()) |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __HIBERNATE_H__ |
/drivers/LuminaryMicro/ustdlib.c
0,0 → 1,670
//***************************************************************************** |
// |
// ustdlib.c - Simple standard library functions. |
// |
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. Any use in violation |
// of the foregoing restrictions may subject the user to criminal sanctions |
// under applicable laws, as well as to civil liability for the breach of the |
// terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
//***************************************************************************** |
|
#include <stdarg.h> |
#include <string.h> |
#include "debug.h" |
|
//***************************************************************************** |
// |
//! \addtogroup utilities_api |
//! @{ |
// |
//***************************************************************************** |
|
//***************************************************************************** |
// |
// A mapping from an integer between 0 and 15 to its ASCII character |
// equivalent. |
// |
//***************************************************************************** |
static const char * const g_pcHex = "0123456789abcdef"; |
|
//***************************************************************************** |
// |
//! A simple vsnprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. |
//! |
//! \param pcBuf points to the buffer where the converted string is stored. |
//! \param ulSize is the size of the buffer. |
//! \param pcString is the format string. |
//! \param vaArgP is the list of optional arguments, which depend on the |
//! contents of the format string. |
//! |
//! This function is very similar to the C library <tt>vsnprintf()</tt> |
//! function. Only the following formatting characters are supported: |
//! |
//! - \%c to print a character |
//! - \%d to print a decimal value |
//! - \%s to print a string |
//! - \%u to print an unsigned decimal value |
//! - \%x to print a hexadecimal value using lower case letters |
//! - \%X to print a hexadecimal value using lower case letters (not upper case |
//! letters as would typically be used) |
//! - \%\% to print out a \% character |
//! |
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% |
//! and the format character, which specifies the minimum number of characters |
//! to use for that value; if preceeded by a 0 then the extra characters will |
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use |
//! eight characters to print the decimal value with spaces added to reach |
//! eight; ``\%08d'' will use eight characters as well but will add zeros |
//! instead of spaces. |
//! |
//! The type of the arguments after \b pcString must match the requirements of |
//! the format string. For example, if an integer was passed where a string |
//! was expected, an error of some kind will most likely occur. |
//! |
//! The \b ulSize parameter limits the number of characters that will be |
//! stored in the buffer pointed to by \b pcBuf to prevent the possibility |
//! of a buffer overflow. The buffer size should be large enough to hold |
//! the expected converted output string, including the null termination |
//! character. |
//! |
//! The function will return the number of characters that would be |
//! converted as if there were no limit on the buffer size. Therefore |
//! it is possible for the function to return a count that is greater than |
//! the specified buffer size. If this happens, it means that the output |
//! was truncated. |
//! |
//! \return the number of characters that were to be stored, not including |
//! the NULL termination character, regardless of space in the buffer. |
// |
//***************************************************************************** |
int |
uvsnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, |
va_list vaArgP) |
{ |
unsigned long ulIdx, ulValue, ulCount, ulBase; |
char *pcStr, cFill; |
int iConvertCount = 0; |
|
// |
// Check the arguments. |
// |
ASSERT(pcString != 0); |
ASSERT(pcBuf != 0); |
ASSERT(ulSize != 0); |
|
// |
// Adjust buffer size limit to allow one space for null termination. |
// |
if(ulSize) |
{ |
ulSize--; |
} |
|
// |
// Initialize the count of characters converted. |
// |
iConvertCount = 0; |
|
// |
// Loop while there are more characters in the format string. |
// |
while(*pcString) |
{ |
// |
// Find the first non-% character, or the end of the string. |
// |
for(ulIdx = 0; (pcString[ulIdx] != '%') && (pcString[ulIdx] != '\0'); |
ulIdx++) |
{ |
} |
|
// |
// Write this portion of the string to the output buffer. If |
// there are more characters to write than there is space in the |
// buffer, then only write as much as will fit in the buffer. |
// |
if(ulIdx > ulSize) |
{ |
strncpy(pcBuf, pcString, ulSize); |
pcBuf += ulSize; |
ulSize = 0; |
} |
else |
{ |
strncpy(pcBuf, pcString, ulIdx); |
pcBuf += ulIdx; |
ulSize -= ulIdx; |
} |
|
// |
// Update the conversion count. This will be the number of |
// characters that should have been written, even if there was |
// not room in the buffer. |
// |
iConvertCount += ulIdx; |
|
// |
// Skip the portion of the format string that was written. |
// |
pcString += ulIdx; |
|
// |
// See if the next character is a %. |
// |
if(*pcString == '%') |
{ |
// |
// Skip the %. |
// |
pcString++; |
|
// |
// Set the digit count to zero, and the fill character to space |
// (i.e. to the defaults). |
// |
ulCount = 0; |
cFill = ' '; |
|
// |
// It may be necessary to get back here to process more characters. |
// Goto's aren't pretty, but effective. I feel extremely dirty for |
// using not one but two of the beasts. |
// |
again: |
|
// |
// Determine how to handle the next character. |
// |
switch(*pcString++) |
{ |
// |
// Handle the digit characters. |
// |
case '0': |
case '1': |
case '2': |
case '3': |
case '4': |
case '5': |
case '6': |
case '7': |
case '8': |
case '9': |
{ |
// |
// If this is a zero, and it is the first digit, then the |
// fill character is a zero instead of a space. |
// |
if((pcString[-1] == '0') && (ulCount == 0)) |
{ |
cFill = '0'; |
} |
|
// |
// Update the digit count. |
// |
ulCount *= 10; |
ulCount += pcString[-1] - '0'; |
|
// |
// Get the next character. |
// |
goto again; |
} |
|
// |
// Handle the %c command. |
// |
case 'c': |
{ |
// |
// Get the value from the varargs. |
// |
ulValue = va_arg(vaArgP, unsigned long); |
|
// |
// Copy the character to the output buffer, if |
// there is room. Update the buffer size remaining. |
// |
if(ulSize != 0) |
{ |
*pcBuf++ = (char)ulValue; |
ulSize--; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount++; |
|
// |
// This command has been handled. |
// |
break; |
} |
|
// |
// Handle the %d command. |
// |
case 'd': |
{ |
// |
// Get the value from the varargs. |
// |
ulValue = va_arg(vaArgP, unsigned long); |
|
// |
// If the value is negative, make it positive and stick a |
// minus sign in the beginning of the buffer. |
// |
if((long)ulValue < 0) |
{ |
ulValue = -(long)ulValue; |
|
if(ulSize != 0) |
{ |
*pcBuf++ = '-'; |
ulSize--; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount++; |
} |
|
// |
// Set the base to 10. |
// |
ulBase = 10; |
|
// |
// Convert the value to ASCII. |
// |
goto convert; |
} |
|
// |
// Handle the %s command. |
// |
case 's': |
{ |
// |
// Get the string pointer from the varargs. |
// |
pcStr = va_arg(vaArgP, char *); |
|
// |
// Determine the length of the string. |
// |
for(ulIdx = 0; pcStr[ulIdx] != '\0'; ulIdx++) |
{ |
} |
|
// |
// Copy the string to the output buffer. Only copy |
// as much as will fit in the buffer. Update the |
// output buffer pointer and the space remaining. |
// |
if(ulIdx > ulSize) |
{ |
strncpy(pcBuf, pcStr, ulSize); |
pcBuf += ulSize; |
ulSize = 0; |
} |
else |
{ |
strncpy(pcBuf, pcStr, ulIdx); |
pcBuf += ulIdx; |
ulSize -= ulIdx; |
} |
|
// |
// Update the conversion count. This will be the number of |
// characters that should have been written, even if there |
// was not room in the buffer. |
// |
iConvertCount += ulIdx; |
|
// |
// |
// This command has been handled. |
// |
break; |
} |
|
// |
// Handle the %u command. |
// |
case 'u': |
{ |
// |
// Get the value from the varargs. |
// |
ulValue = va_arg(vaArgP, unsigned long); |
|
// |
// Set the base to 10. |
// |
ulBase = 10; |
|
// |
// Convert the value to ASCII. |
// |
goto convert; |
} |
|
// |
// Handle the %x and %X commands. Note that they are treated |
// identically; i.e. %X will use lower case letters for a-f |
// instead of the upper case letters is should use. |
// |
case 'x': |
case 'X': |
{ |
// |
// Get the value from the varargs. |
// |
ulValue = va_arg(vaArgP, unsigned long); |
|
// |
// Set the base to 16. |
// |
ulBase = 16; |
|
// |
// Determine the number of digits in the string version of |
// the value. |
// |
convert: |
for(ulIdx = 1; |
(((ulIdx * ulBase) <= ulValue) && |
(((ulIdx * ulBase) / ulBase) == ulIdx)); |
ulIdx *= ulBase, ulCount--) |
{ |
} |
|
// |
// Provide additional padding at the beginning of the |
// string conversion if needed. |
// |
if((ulCount > 1) && (ulCount < 16)) |
{ |
for(ulCount--; ulCount; ulCount--) |
{ |
// |
// Copy the character to the output buffer if |
// there is room. |
// |
if(ulSize != 0) |
{ |
*pcBuf++ = cFill; |
ulSize--; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount++; |
} |
} |
|
// |
// Convert the value into a string. |
// |
for(; ulIdx; ulIdx /= ulBase) |
{ |
// |
// Copy the character to the output buffer if |
// there is room. |
// |
if(ulSize != 0) |
{ |
*pcBuf++ = g_pcHex[(ulValue / ulIdx) % ulBase]; |
ulSize--; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount++; |
} |
|
// |
// This command has been handled. |
// |
break; |
} |
|
// |
// Handle the %% command. |
// |
case '%': |
{ |
// |
// Simply write a single %. |
// |
if(ulSize != 0) |
{ |
*pcBuf++ = pcString[-1]; |
ulSize--; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount++; |
|
// |
// This command has been handled. |
// |
break; |
} |
|
// |
// Handle all other commands. |
// |
default: |
{ |
// |
// Indicate an error. |
// |
if(ulSize >= 5) |
{ |
strncpy(pcBuf, "ERROR", 5); |
pcBuf += 5; |
ulSize -= 5; |
} |
else |
{ |
strncpy(pcBuf, "ERROR", ulSize); |
pcBuf += ulSize; |
ulSize = 0; |
} |
|
// |
// Update the conversion count. |
// |
iConvertCount += 5; |
|
// |
// This command has been handled. |
// |
break; |
} |
} |
} |
} |
|
// |
// Null terminate the string in the buffer. |
// |
*pcBuf = 0; |
return(iConvertCount); |
} |
|
//***************************************************************************** |
// |
//! A simple sprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. |
//! |
//! \param pcBuf is the buffer where the converted string is stored. |
//! \param pcString is the format string. |
//! \param ... are the optional arguments, which depend on the contents of the |
//! format string. |
//! |
//! This function is very similar to the C library <tt>sprintf()</tt> function. |
//! Only the following formatting characters are supported: |
//! |
//! - \%c to print a character |
//! - \%d to print a decimal value |
//! - \%s to print a string |
//! - \%u to print an unsigned decimal value |
//! - \%x to print a hexadecimal value using lower case letters |
//! - \%X to print a hexadecimal value using lower case letters (not upper case |
//! letters as would typically be used) |
//! - \%\% to print out a \% character |
//! |
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% |
//! and the format character, which specifies the minimum number of characters |
//! to use for that value; if preceeded by a 0 then the extra characters will |
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use |
//! eight characters to print the decimal value with spaces added to reach |
//! eight; ``\%08d'' will use eight characters as well but will add zeros |
//! instead of spaces. |
//! |
//! The type of the arguments after \b pcString must match the requirements of |
//! the format string. For example, if an integer was passed where a string |
//! was expected, an error of some kind will most likely occur. |
//! |
//! The caller must ensure that the buffer pcBuf is large enough to hold the |
//! entire converted string, including the null termination character. |
//! |
//! \return The count of characters that were written to the output buffer, |
//! not including the NULL termination character. |
// |
//***************************************************************************** |
int |
usprintf(char *pcBuf, const char *pcString, ...) |
{ |
va_list vaArgP; |
int iRet; |
|
// |
// Start the varargs processing. |
// |
va_start(vaArgP, pcString); |
|
// |
// Call vsnprintf to perform the conversion. Use a |
// large number for the buffer size. |
// |
iRet = uvsnprintf(pcBuf, 0xffff, pcString, vaArgP); |
|
// |
// End the varargs processing. |
// |
va_end(vaArgP); |
|
// |
// Return the conversion count. |
// |
return(iRet); |
} |
|
//***************************************************************************** |
// |
//! A simple snprintf function supporting \%c, \%d, \%s, \%u, \%x, and \%X. |
//! |
//! \param pcBuf is the buffer where the converted string is stored. |
//! \param ulSize is the size of the buffer. |
//! \param pcString is the format string. |
//! \param ... are the optional arguments, which depend on the contents of the |
//! format string. |
//! |
//! This function is very similar to the C library <tt>sprintf()</tt> function. |
//! Only the following formatting characters are supported: |
//! |
//! - \%c to print a character |
//! - \%d to print a decimal value |
//! - \%s to print a string |
//! - \%u to print an unsigned decimal value |
//! - \%x to print a hexadecimal value using lower case letters |
//! - \%X to print a hexadecimal value using lower case letters (not upper case |
//! letters as would typically be used) |
//! - \%\% to print out a \% character |
//! |
//! For \%d, \%u, \%x, and \%X, an optional number may reside between the \% |
//! and the format character, which specifies the minimum number of characters |
//! to use for that value; if preceeded by a 0 then the extra characters will |
//! be filled with zeros instead of spaces. For example, ``\%8d'' will use |
//! eight characters to print the decimal value with spaces added to reach |
//! eight; ``\%08d'' will use eight characters as well but will add zeros |
//! instead of spaces. |
//! |
//! The type of the arguments after \b pcString must match the requirements of |
//! the format string. For example, if an integer was passed where a string |
//! was expected, an error of some kind will most likely occur. |
//! |
//! The function will copy at most \b ulSize - 1 characters into the |
//! buffer \b pcBuf. One space is reserved in the buffer for the null |
//! termination character. |
//! |
//! The function will return the number of characters that would be |
//! converted as if there were no limit on the buffer size. Therefore |
//! it is possible for the function to return a count that is greater than |
//! the specified buffer size. If this happens, it means that the output |
//! was truncated. |
//! |
//! \return the number of characters that were to be stored, not including |
//! the NULL termination character, regardless of space in the buffer. |
// |
//***************************************************************************** |
int |
usnprintf(char *pcBuf, unsigned long ulSize, const char *pcString, ...) |
{ |
int iRet; |
|
va_list vaArgP; |
|
// |
// Start the varargs processing. |
// |
va_start(vaArgP, pcString); |
|
// |
// Call vsnprintf to perform the conversion. |
// |
iRet = uvsnprintf(pcBuf, ulSize, pcString, vaArgP); |
|
// |
// End the varargs processing. |
// |
va_end(vaArgP); |
|
// |
// Return the conversion count. |
// |
return(iRet); |
} |
|
//***************************************************************************** |
// |
// Close the Doxygen group. |
//! @} |
// |
//***************************************************************************** |
/drivers/LuminaryMicro/pwm.h
0,0 → 1,270
//***************************************************************************** |
// |
// pwm.h - API function protoypes for Pulse Width Modulation (PWM) ports |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __PWM_H__ |
#define __PWM_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// The following defines are passed to PWMGenConfigure() as the ulConfig |
// parameter and specify the configuration of the PWM generator. |
// |
//***************************************************************************** |
#define PWM_GEN_MODE_DOWN 0x00000000 // Down count mode |
#define PWM_GEN_MODE_UP_DOWN 0x00000002 // Up/Down count mode |
#define PWM_GEN_MODE_SYNC 0x00000038 // Synchronous updates |
#define PWM_GEN_MODE_NO_SYNC 0x00000000 // Immediate updates |
#define PWM_GEN_MODE_DBG_RUN 0x00000004 // Continue running in debug mode |
#define PWM_GEN_MODE_DBG_STOP 0x00000000 // Stop running in debug mode |
#define PWM_GEN_MODE_FAULT_LATCHED \ |
0x00040000 // Fault is latched |
#define PWM_GEN_MODE_FAULT_UNLATCHED \ |
0x00000000 // Fault is not latched |
#define PWM_GEN_MODE_FAULT_MINPER \ |
0x00020000 // Enable min fault period |
#define PWM_GEN_MODE_FAULT_NO_MINPER \ |
0x00000000 // Disable min fault period |
#define PWM_GEN_MODE_FAULT_EXT 0x00010000 // Enable extended fault support |
#define PWM_GEN_MODE_FAULT_LEGACY \ |
0x00000000 // Disable extended fault support |
#define PWM_GEN_MODE_DB_NO_SYNC 0x00000000 // Deadband updates occur |
// immediately |
#define PWM_GEN_MODE_DB_SYNC_LOCAL \ |
0x0000A800 // Deadband updates locally |
// synchronized |
#define PWM_GEN_MODE_DB_SYNC_GLOBAL \ |
0x0000FC00 // Deadband updates globally |
// synchronized |
#define PWM_GEN_MODE_GEN_NO_SYNC \ |
0x00000000 // Generator mode updates occur |
// immediately |
#define PWM_GEN_MODE_GEN_SYNC_LOCAL \ |
0x00000280 // Generator mode updates locally |
// synchronized |
#define PWM_GEN_MODE_GEN_SYNC_GLOBAL \ |
0x000003C0 // Generator mode updates globally |
// synchronized |
|
//***************************************************************************** |
// |
// Defines for enabling, disabling, and clearing PWM generator interrupts and |
// triggers. |
// |
//***************************************************************************** |
#define PWM_INT_CNT_ZERO 0x00000001 // Int if COUNT = 0 |
#define PWM_INT_CNT_LOAD 0x00000002 // Int if COUNT = LOAD |
#define PWM_INT_CNT_AU 0x00000004 // Int if COUNT = CMPA U |
#define PWM_INT_CNT_AD 0x00000008 // Int if COUNT = CMPA D |
#define PWM_INT_CNT_BU 0x00000010 // Int if COUNT = CMPA U |
#define PWM_INT_CNT_BD 0x00000020 // Int if COUNT = CMPA D |
#define PWM_TR_CNT_ZERO 0x00000100 // Trig if COUNT = 0 |
#define PWM_TR_CNT_LOAD 0x00000200 // Trig if COUNT = LOAD |
#define PWM_TR_CNT_AU 0x00000400 // Trig if COUNT = CMPA U |
#define PWM_TR_CNT_AD 0x00000800 // Trig if COUNT = CMPA D |
#define PWM_TR_CNT_BU 0x00001000 // Trig if COUNT = CMPA U |
#define PWM_TR_CNT_BD 0x00002000 // Trig if COUNT = CMPA D |
|
//***************************************************************************** |
// |
// Defines for enabling, disabling, and clearing PWM interrupts. |
// |
//***************************************************************************** |
#define PWM_INT_GEN_0 0x00000001 // Generator 0 interrupt |
#define PWM_INT_GEN_1 0x00000002 // Generator 1 interrupt |
#define PWM_INT_GEN_2 0x00000004 // Generator 2 interrupt |
#define PWM_INT_GEN_3 0x00000008 // Generator 3 interrupt |
#ifndef DEPRECATED |
#define PWM_INT_FAULT 0x00010000 // Fault interrupt |
#endif |
#define PWM_INT_FAULT0 0x00010000 // Fault0 interrupt |
#define PWM_INT_FAULT1 0x00020000 // Fault1 interrupt |
#define PWM_INT_FAULT2 0x00040000 // Fault2 interrupt |
#define PWM_INT_FAULT3 0x00080000 // Fault3 interrupt |
#define PWM_INT_FAULT_M 0x000F0000 // Fault interrupt source mask |
|
//***************************************************************************** |
// |
// Defines to identify the generators within a module. |
// |
//***************************************************************************** |
#define PWM_GEN_0 0x00000040 // Offset address of Gen0 |
#define PWM_GEN_1 0x00000080 // Offset address of Gen1 |
#define PWM_GEN_2 0x000000C0 // Offset address of Gen2 |
#define PWM_GEN_3 0x00000100 // Offset address of Gen3 |
|
#define PWM_GEN_0_BIT 0x00000001 // Bit-wise ID for Gen0 |
#define PWM_GEN_1_BIT 0x00000002 // Bit-wise ID for Gen1 |
#define PWM_GEN_2_BIT 0x00000004 // Bit-wise ID for Gen2 |
#define PWM_GEN_3_BIT 0x00000008 // Bit-wise ID for Gen3 |
|
#define PWM_GEN_EXT_0 0x00000800 // Offset of Gen0 ext address range |
#define PWM_GEN_EXT_1 0x00000880 // Offset of Gen1 ext address range |
#define PWM_GEN_EXT_2 0x00000900 // Offset of Gen2 ext address range |
#define PWM_GEN_EXT_3 0x00000980 // Offset of Gen3 ext address range |
|
//***************************************************************************** |
// |
// Defines to identify the outputs within a module. |
// |
//***************************************************************************** |
#define PWM_OUT_0 0x00000040 // Encoded offset address of PWM0 |
#define PWM_OUT_1 0x00000041 // Encoded offset address of PWM1 |
#define PWM_OUT_2 0x00000082 // Encoded offset address of PWM2 |
#define PWM_OUT_3 0x00000083 // Encoded offset address of PWM3 |
#define PWM_OUT_4 0x000000C4 // Encoded offset address of PWM4 |
#define PWM_OUT_5 0x000000C5 // Encoded offset address of PWM5 |
#define PWM_OUT_6 0x00000106 // Encoded offset address of PWM6 |
#define PWM_OUT_7 0x00000107 // Encoded offset address of PWM7 |
|
#define PWM_OUT_0_BIT 0x00000001 // Bit-wise ID for PWM0 |
#define PWM_OUT_1_BIT 0x00000002 // Bit-wise ID for PWM1 |
#define PWM_OUT_2_BIT 0x00000004 // Bit-wise ID for PWM2 |
#define PWM_OUT_3_BIT 0x00000008 // Bit-wise ID for PWM3 |
#define PWM_OUT_4_BIT 0x00000010 // Bit-wise ID for PWM4 |
#define PWM_OUT_5_BIT 0x00000020 // Bit-wise ID for PWM5 |
#define PWM_OUT_6_BIT 0x00000040 // Bit-wise ID for PWM6 |
#define PWM_OUT_7_BIT 0x00000080 // Bit-wise ID for PWM7 |
|
//***************************************************************************** |
// |
// Defines to identify each of the possible fault trigger conditions in |
// PWM_FAULT_GROUP_0 |
// |
//***************************************************************************** |
#define PWM_FAULT_GROUP_0 0 |
|
#define PWM_FAULT_FAULT0 0x00000001 |
#define PWM_FAULT_FAULT1 0x00000002 |
#define PWM_FAULT_FAULT2 0x00000004 |
#define PWM_FAULT_FAULT3 0x00000008 |
#define PWM_FAULT_ACMP0 0x00010000 |
#define PWM_FAULT_ACMP1 0x00020000 |
#define PWM_FAULT_ACMP2 0x00040000 |
|
//***************************************************************************** |
// |
// Defines to identify the sense of each of the external FAULTn signals |
// |
//***************************************************************************** |
#define PWM_FAULT0_SENSE_HIGH 0x00000000 |
#define PWM_FAULT0_SENSE_LOW 0x00000001 |
#define PWM_FAULT1_SENSE_HIGH 0x00000000 |
#define PWM_FAULT1_SENSE_LOW 0x00000002 |
#define PWM_FAULT2_SENSE_HIGH 0x00000000 |
#define PWM_FAULT2_SENSE_LOW 0x00000004 |
#define PWM_FAULT3_SENSE_HIGH 0x00000000 |
#define PWM_FAULT3_SENSE_LOW 0x00000008 |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void PWMGenConfigure(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulConfig); |
extern void PWMGenPeriodSet(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulPeriod); |
extern unsigned long PWMGenPeriodGet(unsigned long ulBase, |
unsigned long ulGen); |
extern void PWMGenEnable(unsigned long ulBase, unsigned long ulGen); |
extern void PWMGenDisable(unsigned long ulBase, unsigned long ulGen); |
extern void PWMPulseWidthSet(unsigned long ulBase, unsigned long ulPWMOut, |
unsigned long ulWidth); |
extern unsigned long PWMPulseWidthGet(unsigned long ulBase, |
unsigned long ulPWMOut); |
extern void PWMDeadBandEnable(unsigned long ulBase, unsigned long ulGen, |
unsigned short usRise, unsigned short usFall); |
extern void PWMDeadBandDisable(unsigned long ulBase, unsigned long ulGen); |
extern void PWMSyncUpdate(unsigned long ulBase, unsigned long ulGenBits); |
extern void PWMSyncTimeBase(unsigned long ulBase, unsigned long ulGenBits); |
extern void PWMOutputState(unsigned long ulBase, unsigned long ulPWMOutBits, |
tBoolean bEnable); |
extern void PWMOutputInvert(unsigned long ulBase, unsigned long ulPWMOutBits, |
tBoolean bInvert); |
extern void PWMOutputFaultLevel(unsigned long ulBase, |
unsigned long ulPWMOutBits, |
tBoolean bDriveHigh); |
extern void PWMOutputFault(unsigned long ulBase, unsigned long ulPWMOutBits, |
tBoolean bFaultSuppress); |
extern void PWMGenIntRegister(unsigned long ulBase, unsigned long ulGen, |
void (*pfnIntHandler)(void)); |
extern void PWMGenIntUnregister(unsigned long ulBase, unsigned long ulGen); |
extern void PWMFaultIntRegister(unsigned long ulBase, |
void (*pfnIntHandler)(void)); |
extern void PWMFaultIntUnregister(unsigned long ulBase); |
extern void PWMGenIntTrigEnable(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulIntTrig); |
extern void PWMGenIntTrigDisable(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulIntTrig); |
extern unsigned long PWMGenIntStatus(unsigned long ulBase, unsigned long ulGen, |
tBoolean bMasked); |
extern void PWMGenIntClear(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulInts); |
extern void PWMIntEnable(unsigned long ulBase, unsigned long ulGenFault); |
extern void PWMIntDisable(unsigned long ulBase, unsigned long ulGenFault); |
extern void PWMFaultIntClear(unsigned long ulBase); |
extern unsigned long PWMIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void PWMFaultIntClearExt(unsigned long ulBase, |
unsigned long ulFaultInts); |
extern void PWMGenFaultConfigure(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulMinFaultPeriod, |
unsigned long ulFaultSenses); |
extern void PWMGenFaultTriggerSet(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulGroup, |
unsigned long ulFaultTriggers); |
extern unsigned long PWMGenFaultTriggerGet(unsigned long ulBase, |
unsigned long ulGen, |
unsigned long ulGroup); |
extern unsigned long PWMGenFaultStatus(unsigned long ulBase, |
unsigned long ulGen, |
unsigned long ulGroup); |
extern void PWMGenFaultClear(unsigned long ulBase, unsigned long ulGen, |
unsigned long ulGroup, |
unsigned long ulFaultTriggers); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __PWM_H__ |
/drivers/LuminaryMicro/hw_uart.h
0,0 → 1,341
//***************************************************************************** |
// |
// hw_uart.h - Macros and defines used when accessing the UART hardware |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_UART_H__ |
#define __HW_UART_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the UART Register offsets. |
// |
//***************************************************************************** |
#define UART_O_DR 0x00000000 // Data Register |
#define UART_O_RSR 0x00000004 // Receive Status Register (read) |
#define UART_O_ECR 0x00000004 // Error Clear Register (write) |
#define UART_O_FR 0x00000018 // Flag Register (read only) |
#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register |
#define UART_O_IBRD 0x00000024 // Integer Baud Rate Divisor Reg |
#define UART_O_FBRD 0x00000028 // Fractional Baud Rate Divisor Reg |
#define UART_O_LCRH 0x0000002C // UART Line Control |
#define UART_O_CTL 0x00000030 // Control Register |
#define UART_O_IFLS 0x00000034 // Interrupt FIFO Level Select Reg |
#define UART_O_IM 0x00000038 // Interrupt Mask Set/Clear Reg |
#define UART_O_RIS 0x0000003C // Raw Interrupt Status Register |
#define UART_O_MIS 0x00000040 // Masked Interrupt Status Register |
#define UART_O_ICR 0x00000044 // Interrupt Clear Register |
#define UART_O_DMACTL 0x00000048 // UART DMA Control |
|
//***************************************************************************** |
// |
// The following are defines for the Data Register bits |
// |
//***************************************************************************** |
#define UART_DR_OE 0x00000800 // Overrun Error |
#define UART_DR_BE 0x00000400 // Break Error |
#define UART_DR_PE 0x00000200 // Parity Error |
#define UART_DR_FE 0x00000100 // Framing Error |
#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received. |
#define UART_DR_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the Receive Status Register bits |
// |
//***************************************************************************** |
#define UART_RSR_OE 0x00000008 // Overrun Error |
#define UART_RSR_BE 0x00000004 // Break Error |
#define UART_RSR_PE 0x00000002 // Parity Error |
#define UART_RSR_FE 0x00000001 // Framing Error |
|
//***************************************************************************** |
// |
// The following are defines for the Flag Register bits |
// |
//***************************************************************************** |
#define UART_FR_TXFE 0x00000080 // TX FIFO Empty |
#define UART_FR_RXFF 0x00000040 // RX FIFO Full |
#define UART_FR_TXFF 0x00000020 // TX FIFO Full |
#define UART_FR_RXFE 0x00000010 // RX FIFO Empty |
#define UART_FR_BUSY 0x00000008 // UART Busy |
|
//***************************************************************************** |
// |
// The following are defines for the Integer baud-rate divisor |
// |
//***************************************************************************** |
#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor. |
#define UART_IBRD_DIVINT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the Fractional baud-rate divisor |
// |
//***************************************************************************** |
#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor. |
#define UART_FBRD_DIVFRAC_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the Control Register bits |
// |
//***************************************************************************** |
#define UART_CTL_RXE 0x00000200 // Receive Enable |
#define UART_CTL_TXE 0x00000100 // Transmit Enable |
#define UART_CTL_LBE 0x00000080 // Loopback Enable |
#define UART_CTL_SIRLP 0x00000004 // SIR (IrDA) Low Power Enable |
#define UART_CTL_SIREN 0x00000002 // SIR (IrDA) Enable |
#define UART_CTL_UARTEN 0x00000001 // UART Enable |
|
//***************************************************************************** |
// |
// The following are defines for the Interrupt FIFO Level Select Register bits |
// |
//***************************************************************************** |
#define UART_IFLS_RX_M 0x00000038 // RX FIFO Level Interrupt Mask |
#define UART_IFLS_RX1_8 0x00000000 // 1/8 Full |
#define UART_IFLS_RX2_8 0x00000008 // 1/4 Full |
#define UART_IFLS_RX4_8 0x00000010 // 1/2 Full |
#define UART_IFLS_RX6_8 0x00000018 // 3/4 Full |
#define UART_IFLS_RX7_8 0x00000020 // 7/8 Full |
#define UART_IFLS_TX_M 0x00000007 // TX FIFO Level Interrupt Mask |
#define UART_IFLS_TX1_8 0x00000000 // 1/8 Full |
#define UART_IFLS_TX2_8 0x00000001 // 1/4 Full |
#define UART_IFLS_TX4_8 0x00000002 // 1/2 Full |
#define UART_IFLS_TX6_8 0x00000003 // 3/4 Full |
#define UART_IFLS_TX7_8 0x00000004 // 7/8 Full |
|
//***************************************************************************** |
// |
// The following are defines for the Interrupt Mask Set/Clear Register bits |
// |
//***************************************************************************** |
#define UART_IM_OEIM 0x00000400 // Overrun Error Interrupt Mask |
#define UART_IM_BEIM 0x00000200 // Break Error Interrupt Mask |
#define UART_IM_PEIM 0x00000100 // Parity Error Interrupt Mask |
#define UART_IM_FEIM 0x00000080 // Framing Error Interrupt Mask |
#define UART_IM_RTIM 0x00000040 // Receive Timeout Interrupt Mask |
#define UART_IM_TXIM 0x00000020 // Transmit Interrupt Mask |
#define UART_IM_RXIM 0x00000010 // Receive Interrupt Mask |
|
//***************************************************************************** |
// |
// The following are defines for the Raw Interrupt Status Register |
// |
//***************************************************************************** |
#define UART_RIS_OERIS 0x00000400 // Overrun Error Interrupt Status |
#define UART_RIS_BERIS 0x00000200 // Break Error Interrupt Status |
#define UART_RIS_PERIS 0x00000100 // Parity Error Interrupt Status |
#define UART_RIS_FERIS 0x00000080 // Framing Error Interrupt Status |
#define UART_RIS_RTRIS 0x00000040 // Receive Timeout Interrupt Status |
#define UART_RIS_TXRIS 0x00000020 // Transmit Interrupt Status |
#define UART_RIS_RXRIS 0x00000010 // Receive Interrupt Status |
|
//***************************************************************************** |
// |
// The following are defines for the Masked Interrupt Status Register |
// |
//***************************************************************************** |
#define UART_MIS_OEMIS 0x00000400 // Overrun Error Interrupt Status |
#define UART_MIS_BEMIS 0x00000200 // Break Error Interrupt Status |
#define UART_MIS_PEMIS 0x00000100 // Parity Error Interrupt Status |
#define UART_MIS_FEMIS 0x00000080 // Framing Error Interrupt Status |
#define UART_MIS_RTMIS 0x00000040 // Receive Timeout Interrupt Status |
#define UART_MIS_TXMIS 0x00000020 // Transmit Interrupt Status |
#define UART_MIS_RXMIS 0x00000010 // Receive Interrupt Status |
|
//***************************************************************************** |
// |
// The following are defines for the Interrupt Clear Register bits |
// |
//***************************************************************************** |
#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear |
#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear |
#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear |
#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear |
#define UART_ICR_RTIC 0x00000040 // Receive Timeout Interrupt Clear |
#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear |
#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UART_O_ECR register. |
// |
//***************************************************************************** |
#define UART_ECR_DATA_M 0x000000FF // Error Clear. |
#define UART_ECR_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UART_O_LCRH register. |
// |
//***************************************************************************** |
#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select. |
#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length. |
#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default) |
#define UART_LCRH_WLEN_6 0x00000020 // 6 bits |
#define UART_LCRH_WLEN_7 0x00000040 // 7 bits |
#define UART_LCRH_WLEN_8 0x00000060 // 8 bits |
#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs. |
#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select. |
#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select. |
#define UART_LCRH_PEN 0x00000002 // UART Parity Enable. |
#define UART_LCRH_BRK 0x00000001 // UART Send Break. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UART_O_ILPR register. |
// |
//***************************************************************************** |
#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor. |
#define UART_ILPR_ILPDVSR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UART_O_DMACTL register. |
// |
//***************************************************************************** |
#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error. |
#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. |
#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the UART Register offsets. |
// |
//***************************************************************************** |
#define UART_O_LCR_H 0x0000002C // Line Control Register, HIGH byte |
#define UART_O_PeriphID4 0x00000FD0 |
#define UART_O_PeriphID5 0x00000FD4 |
#define UART_O_PeriphID6 0x00000FD8 |
#define UART_O_PeriphID7 0x00000FDC |
#define UART_O_PeriphID0 0x00000FE0 |
#define UART_O_PeriphID1 0x00000FE4 |
#define UART_O_PeriphID2 0x00000FE8 |
#define UART_O_PeriphID3 0x00000FEC |
#define UART_O_PCellID0 0x00000FF0 |
#define UART_O_PCellID1 0x00000FF4 |
#define UART_O_PCellID2 0x00000FF8 |
#define UART_O_PCellID3 0x00000FFC |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Data Register bits |
// |
//***************************************************************************** |
#define UART_DR_DATA_MASK 0x000000FF // UART data |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Integer baud-rate divisor |
// |
//***************************************************************************** |
#define UART_IBRD_DIVINT_MASK 0x0000FFFF // Integer baud-rate divisor |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Fractional baud-rate divisor |
// |
//***************************************************************************** |
#define UART_FBRD_DIVFRAC_MASK 0x0000003F // Fractional baud-rate divisor |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Line Control Register High bits |
// |
//***************************************************************************** |
#define UART_LCR_H_SPS 0x00000080 // Stick Parity Select |
#define UART_LCR_H_WLEN 0x00000060 // Word length |
#define UART_LCR_H_WLEN_5 0x00000000 // 5 bit data |
#define UART_LCR_H_WLEN_6 0x00000020 // 6 bit data |
#define UART_LCR_H_WLEN_7 0x00000040 // 7 bit data |
#define UART_LCR_H_WLEN_8 0x00000060 // 8 bit data |
#define UART_LCR_H_FEN 0x00000010 // Enable FIFO |
#define UART_LCR_H_STP2 0x00000008 // Two Stop Bits Select |
#define UART_LCR_H_EPS 0x00000004 // Even Parity Select |
#define UART_LCR_H_PEN 0x00000002 // Parity Enable |
#define UART_LCR_H_BRK 0x00000001 // Send Break |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Interrupt FIFO Level Select |
// Register bits |
// |
//***************************************************************************** |
#define UART_IFLS_RX_MASK 0x00000038 // RX FIFO level mask |
#define UART_IFLS_TX_MASK 0x00000007 // TX FIFO level mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Interrupt Clear Register bits |
// |
//***************************************************************************** |
#define UART_RSR_ANY (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \ |
UART_RSR_FE) |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Reset Values for UART |
// Registers. |
// |
//***************************************************************************** |
#define UART_RV_CTL 0x00000300 |
#define UART_RV_PCellID1 0x000000F0 |
#define UART_RV_PCellID3 0x000000B1 |
#define UART_RV_FR 0x00000090 |
#define UART_RV_PeriphID2 0x00000018 |
#define UART_RV_IFLS 0x00000012 |
#define UART_RV_PeriphID0 0x00000011 |
#define UART_RV_PCellID0 0x0000000D |
#define UART_RV_PCellID2 0x00000005 |
#define UART_RV_PeriphID3 0x00000001 |
#define UART_RV_PeriphID4 0x00000000 |
#define UART_RV_LCR_H 0x00000000 |
#define UART_RV_PeriphID6 0x00000000 |
#define UART_RV_DR 0x00000000 |
#define UART_RV_RSR 0x00000000 |
#define UART_RV_ECR 0x00000000 |
#define UART_RV_PeriphID5 0x00000000 |
#define UART_RV_RIS 0x00000000 |
#define UART_RV_FBRD 0x00000000 |
#define UART_RV_IM 0x00000000 |
#define UART_RV_MIS 0x00000000 |
#define UART_RV_ICR 0x00000000 |
#define UART_RV_PeriphID1 0x00000000 |
#define UART_RV_PeriphID7 0x00000000 |
#define UART_RV_IBRD 0x00000000 |
|
#endif |
|
#endif // __HW_UART_H__ |
/drivers/LuminaryMicro/hw_memmap.h
0,0 → 1,111
//***************************************************************************** |
// |
// hw_memmap.h - Macros defining the memory map of Stellaris. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_MEMMAP_H__ |
#define __HW_MEMMAP_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the base address of the memories and |
// peripherals. |
// |
//***************************************************************************** |
#define FLASH_BASE 0x00000000 // FLASH memory |
#define SRAM_BASE 0x20000000 // SRAM memory |
#define WATCHDOG_BASE 0x40000000 // Watchdog |
#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A |
#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B |
#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C |
#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D |
#define SSI0_BASE 0x40008000 // SSI0 |
#define SSI1_BASE 0x40009000 // SSI1 |
#define UART0_BASE 0x4000C000 // UART0 |
#define UART1_BASE 0x4000D000 // UART1 |
#define UART2_BASE 0x4000E000 // UART2 |
#define I2C0_MASTER_BASE 0x40020000 // I2C0 Master |
#define I2C0_SLAVE_BASE 0x40020800 // I2C0 Slave |
#define I2C1_MASTER_BASE 0x40021000 // I2C1 Master |
#define I2C1_SLAVE_BASE 0x40021800 // I2C1 Slave |
#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E |
#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F |
#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G |
#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H |
#define PWM_BASE 0x40028000 // PWM |
#define QEI0_BASE 0x4002C000 // QEI0 |
#define QEI1_BASE 0x4002D000 // QEI1 |
#define TIMER0_BASE 0x40030000 // Timer0 |
#define TIMER1_BASE 0x40031000 // Timer1 |
#define TIMER2_BASE 0x40032000 // Timer2 |
#define TIMER3_BASE 0x40033000 // Timer3 |
#define ADC_BASE 0x40038000 // ADC |
#define COMP_BASE 0x4003C000 // Analog comparators |
#define CAN0_BASE 0x40040000 // CAN0 |
#define CAN1_BASE 0x40041000 // CAN1 |
#define CAN2_BASE 0x40042000 // CAN2 |
#define ETH_BASE 0x40048000 // Ethernet |
#define MAC_BASE 0x40048000 // Ethernet |
#define USB0_BASE 0x40050000 // USB 0 Controller |
#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed) |
#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed) |
#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed) |
#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed) |
#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed) |
#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed) |
#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed) |
#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed) |
#define HIB_BASE 0x400FC000 // Hibernation Module |
#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller |
#define SYSCTL_BASE 0x400FE000 // System Control |
#define UDMA_BASE 0x400FF000 // uDMA Controller |
#define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell |
#define DWT_BASE 0xE0001000 // Data Watchpoint and Trace |
#define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint |
#define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl |
#define TPIU_BASE 0xE0040000 // Trace Port Interface Unit |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the base address of the memories |
// and peripherals. |
// |
//***************************************************************************** |
#define SSI_BASE 0x40008000 // SSI |
#define I2C_MASTER_BASE 0x40020000 // I2C Master |
#define I2C_SLAVE_BASE 0x40020800 // I2C Slave |
#define QEI_BASE 0x4002C000 // QEI |
|
#endif |
|
#endif // __HW_MEMMAP_H__ |
/drivers/LuminaryMicro/hw_ints.h
0,0 → 1,134
//***************************************************************************** |
// |
// hw_ints.h - Macros that define the interrupt assignment on Stellaris. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_INTS_H__ |
#define __HW_INTS_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the fault assignments. |
// |
//***************************************************************************** |
#define FAULT_NMI 2 // NMI fault |
#define FAULT_HARD 3 // Hard fault |
#define FAULT_MPU 4 // MPU fault |
#define FAULT_BUS 5 // Bus fault |
#define FAULT_USAGE 6 // Usage fault |
#define FAULT_SVCALL 11 // SVCall |
#define FAULT_DEBUG 12 // Debug monitor |
#define FAULT_PENDSV 14 // PendSV |
#define FAULT_SYSTICK 15 // System Tick |
|
//***************************************************************************** |
// |
// The following are defines for the interrupt assignments. |
// |
//***************************************************************************** |
#define INT_GPIOA 16 // GPIO Port A |
#define INT_GPIOB 17 // GPIO Port B |
#define INT_GPIOC 18 // GPIO Port C |
#define INT_GPIOD 19 // GPIO Port D |
#define INT_GPIOE 20 // GPIO Port E |
#define INT_UART0 21 // UART0 Rx and Tx |
#define INT_UART1 22 // UART1 Rx and Tx |
#define INT_SSI0 23 // SSI0 Rx and Tx |
#define INT_I2C0 24 // I2C0 Master and Slave |
#define INT_PWM_FAULT 25 // PWM Fault |
#define INT_PWM0 26 // PWM Generator 0 |
#define INT_PWM1 27 // PWM Generator 1 |
#define INT_PWM2 28 // PWM Generator 2 |
#define INT_QEI0 29 // Quadrature Encoder 0 |
#define INT_ADC0 30 // ADC Sequence 0 |
#define INT_ADC1 31 // ADC Sequence 1 |
#define INT_ADC2 32 // ADC Sequence 2 |
#define INT_ADC3 33 // ADC Sequence 3 |
#define INT_WATCHDOG 34 // Watchdog timer |
#define INT_TIMER0A 35 // Timer 0 subtimer A |
#define INT_TIMER0B 36 // Timer 0 subtimer B |
#define INT_TIMER1A 37 // Timer 1 subtimer A |
#define INT_TIMER1B 38 // Timer 1 subtimer B |
#define INT_TIMER2A 39 // Timer 2 subtimer A |
#define INT_TIMER2B 40 // Timer 2 subtimer B |
#define INT_COMP0 41 // Analog Comparator 0 |
#define INT_COMP1 42 // Analog Comparator 1 |
#define INT_COMP2 43 // Analog Comparator 2 |
#define INT_SYSCTL 44 // System Control (PLL, OSC, BO) |
#define INT_FLASH 45 // FLASH Control |
#define INT_GPIOF 46 // GPIO Port F |
#define INT_GPIOG 47 // GPIO Port G |
#define INT_GPIOH 48 // GPIO Port H |
#define INT_UART2 49 // UART2 Rx and Tx |
#define INT_SSI1 50 // SSI1 Rx and Tx |
#define INT_TIMER3A 51 // Timer 3 subtimer A |
#define INT_TIMER3B 52 // Timer 3 subtimer B |
#define INT_I2C1 53 // I2C1 Master and Slave |
#define INT_QEI1 54 // Quadrature Encoder 1 |
#define INT_CAN0 55 // CAN0 |
#define INT_CAN1 56 // CAN1 |
#define INT_CAN2 57 // CAN2 |
#define INT_ETH 58 // Ethernet |
#define INT_HIBERNATE 59 // Hibernation module |
#define INT_USB0 60 // USB 0 Controller |
#define INT_PWM3 61 // PWM Generator 3 |
#define INT_UDMA 62 // uDMA controller |
#define INT_UDMAERR 63 // uDMA Error |
|
//***************************************************************************** |
// |
// The following are defines for the total number of interrupts. |
// |
//***************************************************************************** |
#define NUM_INTERRUPTS 64 |
|
//***************************************************************************** |
// |
// The following are defines for the total number of priority levels. |
// |
//***************************************************************************** |
#define NUM_PRIORITY 8 |
#define NUM_PRIORITY_BITS 3 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the interrupt assignments. |
// |
//***************************************************************************** |
#define INT_SSI 23 // SSI Rx and Tx |
#define INT_I2C 24 // I2C Master and Slave |
#define INT_QEI 29 // Quadrature Encoder |
|
#endif |
|
#endif // __HW_INTS_H__ |
/drivers/LuminaryMicro/hw_qei.h
0,0 → 1,199
//***************************************************************************** |
// |
// hw_qei.h - Macros used when accessing the QEI hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_QEI_H__ |
#define __HW_QEI_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the QEI register offsets. |
// |
//***************************************************************************** |
#define QEI_O_CTL 0x00000000 // Configuration and control reg. |
#define QEI_O_STAT 0x00000004 // Status register |
#define QEI_O_POS 0x00000008 // Current position register |
#define QEI_O_MAXPOS 0x0000000C // Maximum position register |
#define QEI_O_LOAD 0x00000010 // Velocity timer load register |
#define QEI_O_TIME 0x00000014 // Velocity timer register |
#define QEI_O_COUNT 0x00000018 // Velocity pulse count register |
#define QEI_O_SPEED 0x0000001C // Velocity speed register |
#define QEI_O_INTEN 0x00000020 // Interrupt enable register |
#define QEI_O_RIS 0x00000024 // Raw interrupt status register |
#define QEI_O_ISC 0x00000028 // Interrupt status register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_CTL register. |
// |
//***************************************************************************** |
#define QEI_CTL_STALLEN 0x00001000 // Stall enable |
#define QEI_CTL_INVI 0x00000800 // Invert Index input |
#define QEI_CTL_INVB 0x00000400 // Invert PhB input |
#define QEI_CTL_INVA 0x00000200 // Invert PhA input |
#define QEI_CTL_VELDIV_M 0x000001C0 // Velocity predivider mask |
#define QEI_CTL_VELDIV_1 0x00000000 // Predivide by 1 |
#define QEI_CTL_VELDIV_2 0x00000040 // Predivide by 2 |
#define QEI_CTL_VELDIV_4 0x00000080 // Predivide by 4 |
#define QEI_CTL_VELDIV_8 0x000000C0 // Predivide by 8 |
#define QEI_CTL_VELDIV_16 0x00000100 // Predivide by 16 |
#define QEI_CTL_VELDIV_32 0x00000140 // Predivide by 32 |
#define QEI_CTL_VELDIV_64 0x00000180 // Predivide by 64 |
#define QEI_CTL_VELDIV_128 0x000001C0 // Predivide by 128 |
#define QEI_CTL_VELEN 0x00000020 // Velocity enable |
#define QEI_CTL_RESMODE 0x00000010 // Position counter reset mode |
#define QEI_CTL_CAPMODE 0x00000008 // Edge capture mode |
#define QEI_CTL_SIGMODE 0x00000004 // Encoder signaling mode |
#define QEI_CTL_SWAP 0x00000002 // Swap input signals |
#define QEI_CTL_ENABLE 0x00000001 // QEI enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_STAT register. |
// |
//***************************************************************************** |
#define QEI_STAT_DIRECTION 0x00000002 // Direction of rotation |
#define QEI_STAT_ERROR 0x00000001 // Signalling error detected |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_POS register. |
// |
//***************************************************************************** |
#define QEI_POS_M 0xFFFFFFFF // Current encoder position |
#define QEI_POS_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_MAXPOS register. |
// |
//***************************************************************************** |
#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum encoder position |
#define QEI_MAXPOS_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_LOAD register. |
// |
//***************************************************************************** |
#define QEI_LOAD_M 0xFFFFFFFF // Velocity timer load value |
#define QEI_LOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_TIME register. |
// |
//***************************************************************************** |
#define QEI_TIME_M 0xFFFFFFFF // Velocity timer current value |
#define QEI_TIME_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_COUNT register. |
// |
//***************************************************************************** |
#define QEI_COUNT_M 0xFFFFFFFF // Encoder running pulse count |
#define QEI_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_SPEED register. |
// |
//***************************************************************************** |
#define QEI_SPEED_M 0xFFFFFFFF // Encoder pulse count |
#define QEI_SPEED_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_INTEN register. |
// |
//***************************************************************************** |
#define QEI_INTEN_ERROR 0x00000008 // Phase error detected |
#define QEI_INTEN_DIR 0x00000004 // Direction change |
#define QEI_INTEN_TIMER 0x00000002 // Velocity timer expired |
#define QEI_INTEN_INDEX 0x00000001 // Index pulse detected |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_RIS register. |
// |
//***************************************************************************** |
#define QEI_RIS_ERROR 0x00000008 // Phase error detected |
#define QEI_RIS_DIR 0x00000004 // Direction change |
#define QEI_RIS_TIMER 0x00000002 // Velocity timer expired |
#define QEI_RIS_INDEX 0x00000001 // Index pulse detected |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the QEI_O_ISC register. |
// |
//***************************************************************************** |
#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt. |
#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt. |
#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired |
// Interrupt. |
#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the QEI_ISC |
// register. |
// |
//***************************************************************************** |
#define QEI_INT_ERROR 0x00000008 // Phase error detected |
#define QEI_INT_DIR 0x00000004 // Direction change |
#define QEI_INT_TIMER 0x00000002 // Velocity timer expired |
#define QEI_INT_INDEX 0x00000001 // Index pulse detected |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values for the QEI |
// registers. |
// |
//***************************************************************************** |
#define QEI_RV_POS 0x00000000 // Current position register |
#define QEI_RV_LOAD 0x00000000 // Velocity timer load register |
#define QEI_RV_CTL 0x00000000 // Configuration and control reg. |
#define QEI_RV_RIS 0x00000000 // Raw interrupt status register |
#define QEI_RV_ISC 0x00000000 // Interrupt status register |
#define QEI_RV_SPEED 0x00000000 // Velocity speed register |
#define QEI_RV_INTEN 0x00000000 // Interrupt enable register |
#define QEI_RV_STAT 0x00000000 // Status register |
#define QEI_RV_COUNT 0x00000000 // Velocity pulse count register |
#define QEI_RV_MAXPOS 0x00000000 // Maximum position register |
#define QEI_RV_TIME 0x00000000 // Velocity timer register |
|
#endif |
|
#endif // __HW_QEI_H__ |
/drivers/LuminaryMicro/hw_ethernet.h
0,0 → 1,576
//***************************************************************************** |
// |
// hw_ethernet.h - Macros used when accessing the Ethernet hardware. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_ETHERNET_H__ |
#define __HW_ETHERNET_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the MAC register offsets in the Ethernet |
// Controller. |
// |
//***************************************************************************** |
#define MAC_O_RIS 0x00000000 // Ethernet MAC Raw Interrupt |
// Status |
#define MAC_O_IACK 0x00000000 // Interrupt Acknowledge Register |
#define MAC_O_IM 0x00000004 // Interrupt Mask Register |
#define MAC_O_RCTL 0x00000008 // Receive Control Register |
#define MAC_O_TCTL 0x0000000C // Transmit Control Register |
#define MAC_O_DATA 0x00000010 // Data Register |
#define MAC_O_IA0 0x00000014 // Individual Address Register 0 |
#define MAC_O_IA1 0x00000018 // Individual Address Register 1 |
#define MAC_O_THR 0x0000001C // Threshold Register |
#define MAC_O_MCTL 0x00000020 // Management Control Register |
#define MAC_O_MDV 0x00000024 // Management Divider Register |
#define MAC_O_MTXD 0x0000002C // Management Transmit Data Reg |
#define MAC_O_MRXD 0x00000030 // Management Receive Data Reg |
#define MAC_O_NP 0x00000034 // Number of Packets Register |
#define MAC_O_TR 0x00000038 // Transmission Request Register |
#define MAC_O_TS 0x0000003C // Timer Support Register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_IACK register. |
// |
//***************************************************************************** |
#define MAC_IACK_PHYINT 0x00000040 // Clear PHY Interrupt |
#define MAC_IACK_MDINT 0x00000020 // Clear MDI Transaction Complete |
#define MAC_IACK_RXER 0x00000010 // Clear RX Error |
#define MAC_IACK_FOV 0x00000008 // Clear RX FIFO Overrun |
#define MAC_IACK_TXEMP 0x00000004 // Clear TX FIFO Empy |
#define MAC_IACK_TXER 0x00000002 // Clear TX Error |
#define MAC_IACK_RXINT 0x00000001 // Clear RX Packet Available |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_IM register. |
// |
//***************************************************************************** |
#define MAC_IM_PHYINTM 0x00000040 // Mask PHY Interrupt |
#define MAC_IM_MDINTM 0x00000020 // Mask MDI Transaction Complete |
#define MAC_IM_RXERM 0x00000010 // Mask RX Error |
#define MAC_IM_FOVM 0x00000008 // Mask RX FIFO Overrun |
#define MAC_IM_TXEMPM 0x00000004 // Mask TX FIFO Empy |
#define MAC_IM_TXERM 0x00000002 // Mask TX Error |
#define MAC_IM_RXINTM 0x00000001 // Mask RX Packet Available |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_RCTL register. |
// |
//***************************************************************************** |
#define MAC_RCTL_RSTFIFO 0x00000010 // Clear the Receive FIFO |
#define MAC_RCTL_BADCRC 0x00000008 // Reject Packets With Bad CRC |
#define MAC_RCTL_PRMS 0x00000004 // Enable Promiscuous Mode |
#define MAC_RCTL_AMUL 0x00000002 // Enable Multicast Packets |
#define MAC_RCTL_RXEN 0x00000001 // Enable Ethernet Receiver |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_TCTL register. |
// |
//***************************************************************************** |
#define MAC_TCTL_DUPLEX 0x00000010 // Enable Duplex mode |
#define MAC_TCTL_CRC 0x00000004 // Enable CRC Generation |
#define MAC_TCTL_PADEN 0x00000002 // Enable Automatic Padding |
#define MAC_TCTL_TXEN 0x00000001 // Enable Ethernet Transmitter |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_IA0 register. |
// |
//***************************************************************************** |
#define MAC_IA0_MACOCT4_M 0xFF000000 // MAC Address Octet 4. |
#define MAC_IA0_MACOCT3_M 0x00FF0000 // MAC Address Octet 3. |
#define MAC_IA0_MACOCT2_M 0x0000FF00 // MAC Address Octet 2. |
#define MAC_IA0_MACOCT1_M 0x000000FF // MAC Address Octet 1. |
#define MAC_IA0_MACOCT4_S 24 |
#define MAC_IA0_MACOCT3_S 16 |
#define MAC_IA0_MACOCT2_S 8 |
#define MAC_IA0_MACOCT1_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_IA1 register. |
// |
//***************************************************************************** |
#define MAC_IA1_MACOCT6_M 0x0000FF00 // MAC Address Octet 6. |
#define MAC_IA1_MACOCT5_M 0x000000FF // MAC Address Octet 5. |
#define MAC_IA1_MACOCT6_S 8 |
#define MAC_IA1_MACOCT5_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_TXTH register. |
// |
//***************************************************************************** |
#define MAC_THR_THRESH_M 0x0000003F // Threshold Value. |
#define MAC_THR_THRESH_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_MCTL register. |
// |
//***************************************************************************** |
#define MAC_MCTL_REGADR_M 0x000000F8 // MII Register Address. |
#define MAC_MCTL_WRITE 0x00000002 // Next MII Transaction is Write |
#define MAC_MCTL_START 0x00000001 // Start MII Transaction |
#define MAC_MCTL_REGADR_S 3 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_MDV register. |
// |
//***************************************************************************** |
#define MAC_MDV_DIV_M 0x000000FF // Clock Divider. |
#define MAC_MDV_DIV_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_MTXD register. |
// |
//***************************************************************************** |
#define MAC_MTXD_MDTX_M 0x0000FFFF // MII Register Transmit Data. |
#define MAC_MTXD_MDTX_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_MRXD register. |
// |
//***************************************************************************** |
#define MAC_MRXD_MDRX_M 0x0000FFFF // MII Register Receive Data. |
#define MAC_MRXD_MDRX_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_NP register. |
// |
//***************************************************************************** |
#define MAC_NP_NPR_M 0x0000003F // Number of Packets in Receive |
// FIFO. |
#define MAC_NP_NPR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_TXRQ register. |
// |
//***************************************************************************** |
#define MAC_TR_NEWTX 0x00000001 // Start an Ethernet Transmission |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_TS register. |
// |
//***************************************************************************** |
#define MAC_TS_TSEN 0x00000001 // Enable Timestamp Logic |
|
//***************************************************************************** |
// |
// The following are defines for the Ethernet Controller PHY registers. |
// |
//***************************************************************************** |
#define PHY_MR24 0x00000018 // Ethernet PHY Management Register |
// 24 -MDI/MDIX Control |
#define PHY_MR23 0x00000017 // Ethernet PHY Management Register |
// 23 - LED Configuration |
#define PHY_MR19 0x00000013 // Ethernet PHY Management Register |
// 19 - Transceiver Control |
#define PHY_MR18 0x00000012 // Ethernet PHY Management Register |
// 18 - Diagnostic |
#define PHY_MR17 0x00000011 // Ethernet PHY Management Register |
// 17 - Interrupt Control/Status |
#define PHY_MR16 0x00000010 // Ethernet PHY Management Register |
// 16 - Vendor-Specific |
#define PHY_MR6 0x00000006 // Ethernet PHY Management Register |
// 6 - Auto-Negotiation Expansion |
#define PHY_MR5 0x00000005 // Ethernet PHY Management Register |
// 5 - Auto-Negotiation Link |
// Partner Base Page Ability |
#define PHY_MR4 0x00000004 // Ethernet PHY Management Register |
// 4 - Auto-Negotiation |
// Advertisement |
#define PHY_MR3 0x00000003 // Ethernet PHY Management Register |
// 3 - PHY Identifier 2 |
#define PHY_MR2 0x00000002 // Ethernet PHY Management Register |
// 2 - PHY Identifier 1 |
#define PHY_MR1 0x00000001 // Ethernet PHY Management Register |
// 1 - Status |
#define PHY_MR0 0x00000000 // Ethernet PHY Management Register |
// 0 - Control |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR0 register. |
// |
//***************************************************************************** |
#define PHY_MR0_RESET 0x00008000 // Reset Registers. |
#define PHY_MR0_LOOPBK 0x00004000 // Loopback Mode. |
#define PHY_MR0_SPEEDSL 0x00002000 // Speed Select. |
#define PHY_MR0_ANEGEN 0x00001000 // Auto-Negotiation Enable. |
#define PHY_MR0_PWRDN 0x00000800 // Power Down. |
#define PHY_MR0_ISO 0x00000400 // Isolate. |
#define PHY_MR0_RANEG 0x00000200 // Restart Auto-Negotiation. |
#define PHY_MR0_DUPLEX 0x00000100 // Set Duplex Mode. |
#define PHY_MR0_COLT 0x00000080 // Collision Test. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_O_RIS register. |
// |
//***************************************************************************** |
#define MAC_RIS_PHYINT 0x00000040 // PHY Interrupt. |
#define MAC_RIS_MDINT 0x00000020 // MII Transaction Complete. |
#define MAC_RIS_RXER 0x00000010 // Receive Error. |
#define MAC_RIS_FOV 0x00000008 // FIFO Overrrun. |
#define MAC_RIS_TXEMP 0x00000004 // Transmit FIFO Empty. |
#define MAC_RIS_TXER 0x00000002 // Transmit Error. |
#define MAC_RIS_RXINT 0x00000001 // Packet Received. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR1 register. |
// |
//***************************************************************************** |
#define PHY_MR1_100X_F 0x00004000 // 100BASE-TX Full-Duplex Mode. |
#define PHY_MR1_100X_H 0x00002000 // 100BASE-TX Half-Duplex Mode. |
#define PHY_MR1_10T_F 0x00001000 // 10BASE-T Full-Duplex Mode. |
#define PHY_MR1_10T_H 0x00000800 // 10BASE-T Half-Duplex Mode. |
#define PHY_MR1_MFPS 0x00000040 // Management Frames with Preamble |
// Suppressed. |
#define PHY_MR1_ANEGC 0x00000020 // Auto-Negotiation Complete. |
#define PHY_MR1_RFAULT 0x00000010 // Remote Fault. |
#define PHY_MR1_ANEGA 0x00000008 // Auto-Negotiation. |
#define PHY_MR1_LINK 0x00000004 // Link Made. |
#define PHY_MR1_JAB 0x00000002 // Jabber Condition. |
#define PHY_MR1_EXTD 0x00000001 // Extended Capabilities. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR2 register. |
// |
//***************************************************************************** |
#define PHY_MR2_OUI_M 0x0000FFFF // Organizationally Unique |
// Identifier[21:6]. |
#define PHY_MR2_OUI_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR3 register. |
// |
//***************************************************************************** |
#define PHY_MR3_OUI_M 0x0000FC00 // Organizationally Unique |
// Identifier[5:0]. |
#define PHY_MR3_MN_M 0x000003F0 // Model Number. |
#define PHY_MR3_RN_M 0x0000000F // Revision Number. |
#define PHY_MR3_OUI_S 10 |
#define PHY_MR3_MN_S 4 |
#define PHY_MR3_RN_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR4 register. |
// |
//***************************************************************************** |
#define PHY_MR4_NP 0x00008000 // Next Page. |
#define PHY_MR4_RF 0x00002000 // Remote Fault. |
#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3]. |
#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2]. |
#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1]. |
#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0]. |
#define PHY_MR4_S_M 0x0000001F // Selector Field. |
#define PHY_MR4_S_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR5 register. |
// |
//***************************************************************************** |
#define PHY_MR5_NP 0x00008000 // Next Page. |
#define PHY_MR5_ACK 0x00004000 // Acknowledge. |
#define PHY_MR5_RF 0x00002000 // Remote Fault. |
#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field. |
#define PHY_MR5_S_M 0x0000001F // Selector Field. |
#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3 |
#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T |
#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5 |
#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394 |
#define PHY_MR5_A_S 5 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR6 register. |
// |
//***************************************************************************** |
#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault. |
#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able. |
#define PHY_MR6_PRX 0x00000002 // New Page Received. |
#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation |
// Able. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the MAC_O_DATA register. |
// |
//***************************************************************************** |
#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data. |
#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data. |
#define MAC_DATA_RXDATA_S 0 |
#define MAC_DATA_TXDATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR16 register. |
// |
//***************************************************************************** |
#define PHY_MR16_RPTR 0x00008000 // Repeater Mode. |
#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity. |
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode. |
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing. |
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode. |
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable. |
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity. |
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass. |
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR17 register. |
// |
//***************************************************************************** |
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable. |
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable. |
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable. |
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault |
// Interrupt Enable. |
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable. |
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt |
// Enable. |
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable. |
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete |
// Interrupt Enable. |
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt. |
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt. |
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt. |
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault |
// Interrupt. |
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt. |
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt. |
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt. |
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete |
// Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR18 register. |
// |
//***************************************************************************** |
#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure. |
#define PHY_MR18_DPLX 0x00000800 // Duplex Mode. |
#define PHY_MR18_RATE 0x00000400 // Rate. |
#define PHY_MR18_RXSD 0x00000200 // Receive Detection. |
#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR19 register. |
// |
//***************************************************************************** |
#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection. |
#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion |
// loss |
#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion |
// loss |
#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion |
// loss |
#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion |
// loss |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR23 register. |
// |
//***************************************************************************** |
#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source. |
#define PHY_MR23_LED1_LINK 0x00000000 // Link OK |
#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1) |
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity |
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity |
#define PHY_MR23_LED1_COL 0x00000040 // Collision |
#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode |
#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode |
#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex |
#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX |
// Activity |
#define PHY_MR23_LED0_M 0x0000000F // LED0 Source. |
#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0) |
#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity |
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity |
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity |
#define PHY_MR23_LED0_COL 0x00000004 // Collision |
#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode |
#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode |
#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex |
#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX |
// Activity |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PHY_MR24 register. |
// |
//***************************************************************************** |
#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode. |
#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable. |
#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration. |
#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete. |
#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed. |
#define PHY_MR24_MDIX_SD_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the MAC register offsets in the |
// Ethernet Controller. |
// |
//***************************************************************************** |
#define MAC_O_IS 0x00000000 // Interrupt Status Register |
#define MAC_O_MADD 0x00000028 // Management Address Register |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values of the MAC |
// registers. |
// |
//***************************************************************************** |
#define MAC_RV_MDV 0x00000080 |
#define MAC_RV_IM 0x0000007F |
#define MAC_RV_THR 0x0000003F |
#define MAC_RV_RCTL 0x00000008 |
#define MAC_RV_IA0 0x00000000 |
#define MAC_RV_TCTL 0x00000000 |
#define MAC_RV_DATA 0x00000000 |
#define MAC_RV_MRXD 0x00000000 |
#define MAC_RV_TR 0x00000000 |
#define MAC_RV_IS 0x00000000 |
#define MAC_RV_NP 0x00000000 |
#define MAC_RV_MCTL 0x00000000 |
#define MAC_RV_MTXD 0x00000000 |
#define MAC_RV_IA1 0x00000000 |
#define MAC_RV_IACK 0x00000000 |
#define MAC_RV_MADD 0x00000000 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_IS |
// register. |
// |
//***************************************************************************** |
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt |
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete |
#define MAC_IS_RXER 0x00000010 // RX Error |
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun |
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy |
#define MAC_IS_TXER 0x00000002 // TX Error |
#define MAC_IS_RXINT 0x00000001 // RX Packet Available |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_IA0 |
// register. |
// |
//***************************************************************************** |
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address |
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address |
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address |
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_IA1 |
// register. |
// |
//***************************************************************************** |
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address |
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_TXTH |
// register. |
// |
//***************************************************************************** |
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_MCTL |
// register. |
// |
//***************************************************************************** |
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_MDV |
// register. |
// |
//***************************************************************************** |
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_MTXD |
// register. |
// |
//***************************************************************************** |
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_MRXD |
// register. |
// |
//***************************************************************************** |
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the MAC_NP |
// register. |
// |
//***************************************************************************** |
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO |
|
#endif |
|
#endif // __HW_ETHERNET_H__ |
/drivers/LuminaryMicro/i2c.h
0,0 → 1,156
//***************************************************************************** |
// |
// i2c.h - Prototypes for the I2C Driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __I2C_H__ |
#define __I2C_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Defines for the API. |
// |
//***************************************************************************** |
|
//***************************************************************************** |
// |
// Interrupt defines. |
// |
//***************************************************************************** |
#define I2C_INT_MASTER 0x00000001 |
#define I2C_INT_SLAVE 0x00000002 |
|
//***************************************************************************** |
// |
// I2C Master commands. |
// |
//***************************************************************************** |
#define I2C_MASTER_CMD_SINGLE_SEND 0x00000007 |
#define I2C_MASTER_CMD_SINGLE_RECEIVE 0x00000007 |
#define I2C_MASTER_CMD_BURST_SEND_START 0x00000003 |
#define I2C_MASTER_CMD_BURST_SEND_CONT 0x00000001 |
#define I2C_MASTER_CMD_BURST_SEND_FINISH 0x00000005 |
#define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP 0x00000004 |
#define I2C_MASTER_CMD_BURST_RECEIVE_START 0x0000000b |
#define I2C_MASTER_CMD_BURST_RECEIVE_CONT 0x00000009 |
#define I2C_MASTER_CMD_BURST_RECEIVE_FINISH 0x00000005 |
#define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP 0x00000005 |
|
//***************************************************************************** |
// |
// I2C Master error status. |
// |
//***************************************************************************** |
#define I2C_MASTER_ERR_NONE 0 |
#define I2C_MASTER_ERR_ADDR_ACK 0x00000004 |
#define I2C_MASTER_ERR_DATA_ACK 0x00000008 |
#define I2C_MASTER_ERR_ARB_LOST 0x00000010 |
|
//***************************************************************************** |
// |
// I2C Slave action requests |
// |
//***************************************************************************** |
#define I2C_SLAVE_ACT_NONE 0 |
#define I2C_SLAVE_ACT_RREQ 0x00000001 // Master has sent data |
#define I2C_SLAVE_ACT_TREQ 0x00000002 // Master has requested data |
#define I2C_SLAVE_ACT_RREQ_FBR 0x00000005 // Master has sent first byte |
|
//***************************************************************************** |
// |
// Miscellaneous I2C driver definitions. |
// |
//***************************************************************************** |
#define I2C_MASTER_MAX_RETRIES 1000 // Number of retries |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void I2CIntRegister(unsigned long ulBase, void(fnHandler)(void)); |
extern void I2CIntUnregister(unsigned long ulBase); |
extern tBoolean I2CMasterBusBusy(unsigned long ulBase); |
extern tBoolean I2CMasterBusy(unsigned long ulBase); |
extern void I2CMasterControl(unsigned long ulBase, unsigned long ulCmd); |
extern unsigned long I2CMasterDataGet(unsigned long ulBase); |
extern void I2CMasterDataPut(unsigned long ulBase, unsigned char ucData); |
extern void I2CMasterDisable(unsigned long ulBase); |
extern void I2CMasterEnable(unsigned long ulBase); |
extern unsigned long I2CMasterErr(unsigned long ulBase); |
extern void I2CMasterInitExpClk(unsigned long ulBase, unsigned long ulI2CClk, |
tBoolean bFast); |
extern void I2CMasterIntClear(unsigned long ulBase); |
extern void I2CMasterIntDisable(unsigned long ulBase); |
extern void I2CMasterIntEnable(unsigned long ulBase); |
extern tBoolean I2CMasterIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void I2CMasterSlaveAddrSet(unsigned long ulBase, |
unsigned char ucSlaveAddr, |
tBoolean bReceive); |
extern unsigned long I2CSlaveDataGet(unsigned long ulBase); |
extern void I2CSlaveDataPut(unsigned long ulBase, unsigned char ucData); |
extern void I2CSlaveDisable(unsigned long ulBase); |
extern void I2CSlaveEnable(unsigned long ulBase); |
extern void I2CSlaveInit(unsigned long ulBase, unsigned char ucSlaveAddr); |
extern void I2CSlaveIntClear(unsigned long ulBase); |
extern void I2CSlaveIntDisable(unsigned long ulBase); |
extern void I2CSlaveIntEnable(unsigned long ulBase); |
extern tBoolean I2CSlaveIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern unsigned long I2CSlaveStatus(unsigned long ulBase); |
|
//***************************************************************************** |
// |
// Several I2C APIs have been renamed, with the original function name being |
// deprecated. These defines provide backward compatibility. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#include "sysctl.h" |
#define I2CMasterInit(a, b) \ |
I2CMasterInitExpClk(a, SysCtlClockGet(), b) |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __I2C_H__ |
/drivers/LuminaryMicro/hw_timer.h
0,0 → 1,407
//***************************************************************************** |
// |
// hw_timer.h - Defines and macros used when accessing the timer. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_TIMER_H__ |
#define __HW_TIMER_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the timer register offsets. |
// |
//***************************************************************************** |
#define TIMER_O_CFG 0x00000000 // Configuration register |
#define TIMER_O_TAMR 0x00000004 // TimerA mode register |
#define TIMER_O_TBMR 0x00000008 // TimerB mode register |
#define TIMER_O_CTL 0x0000000C // Control register |
#define TIMER_O_IMR 0x00000018 // Interrupt mask register |
#define TIMER_O_RIS 0x0000001C // Interrupt status register |
#define TIMER_O_MIS 0x00000020 // Masked interrupt status reg. |
#define TIMER_O_ICR 0x00000024 // Interrupt clear register |
#define TIMER_O_TAILR 0x00000028 // TimerA interval load register |
#define TIMER_O_TBILR 0x0000002C // TimerB interval load register |
#define TIMER_O_TAMATCHR 0x00000030 // TimerA match register |
#define TIMER_O_TBMATCHR 0x00000034 // TimerB match register |
#define TIMER_O_TAPR 0x00000038 // TimerA prescale register |
#define TIMER_O_TBPR 0x0000003C // TimerB prescale register |
#define TIMER_O_TAPMR 0x00000040 // TimerA prescale match register |
#define TIMER_O_TBPMR 0x00000044 // TimerB prescale match register |
#define TIMER_O_TAR 0x00000048 // TimerA register |
#define TIMER_O_TBR 0x0000004C // TimerB register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_CFG register. |
// |
//***************************************************************************** |
#define TIMER_CFG_M 0x00000007 // GPTM Configuration. |
#define TIMER_CFG_16_BIT 0x00000004 // Two 16 bit timers |
#define TIMER_CFG_32_BIT_RTC 0x00000001 // 32 bit RTC |
#define TIMER_CFG_32_BIT_TIMER 0x00000000 // 32 bit timer |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_CTL register. |
// |
//***************************************************************************** |
#define TIMER_CTL_TBPWML 0x00004000 // TimerB PWM output level invert |
#define TIMER_CTL_TBOTE 0x00002000 // TimerB output trigger enable |
#define TIMER_CTL_TBEVENT_POS 0x00000000 // TimerB event mode - pos edge |
#define TIMER_CTL_TBEVENT_NEG 0x00000400 // TimerB event mode - neg edge |
#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // TimerB event mode - both edges |
#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM TimerB Event Mode. |
#define TIMER_CTL_TBSTALL 0x00000200 // TimerB stall enable |
#define TIMER_CTL_TBEN 0x00000100 // TimerB enable |
#define TIMER_CTL_TAPWML 0x00000040 // TimerA PWM output level invert |
#define TIMER_CTL_TAOTE 0x00000020 // TimerA output trigger enable |
#define TIMER_CTL_RTCEN 0x00000010 // RTC counter enable |
#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM TimerA Event Mode. |
#define TIMER_CTL_TAEVENT_POS 0x00000000 // TimerA event mode - pos edge |
#define TIMER_CTL_TAEVENT_NEG 0x00000004 // TimerA event mode - neg edge |
#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // TimerA event mode - both edges |
#define TIMER_CTL_TASTALL 0x00000002 // TimerA stall enable |
#define TIMER_CTL_TAEN 0x00000001 // TimerA enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_IMR register. |
// |
//***************************************************************************** |
#define TIMER_IMR_CBEIM 0x00000400 // CaptureB event interrupt mask |
#define TIMER_IMR_CBMIM 0x00000200 // CaptureB match interrupt mask |
#define TIMER_IMR_TBTOIM 0x00000100 // TimerB time out interrupt mask |
#define TIMER_IMR_RTCIM 0x00000008 // RTC interrupt mask |
#define TIMER_IMR_CAEIM 0x00000004 // CaptureA event interrupt mask |
#define TIMER_IMR_CAMIM 0x00000002 // CaptureA match interrupt mask |
#define TIMER_IMR_TATOIM 0x00000001 // TimerA time out interrupt mask |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_RIS register. |
// |
//***************************************************************************** |
#define TIMER_RIS_CBERIS 0x00000400 // CaptureB event raw int status |
#define TIMER_RIS_CBMRIS 0x00000200 // CaptureB match raw int status |
#define TIMER_RIS_TBTORIS 0x00000100 // TimerB time out raw int status |
#define TIMER_RIS_RTCRIS 0x00000008 // RTC raw int status |
#define TIMER_RIS_CAERIS 0x00000004 // CaptureA event raw int status |
#define TIMER_RIS_CAMRIS 0x00000002 // CaptureA match raw int status |
#define TIMER_RIS_TATORIS 0x00000001 // TimerA time out raw int status |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_ICR register. |
// |
//***************************************************************************** |
#define TIMER_ICR_CBECINT 0x00000400 // CaptureB event interrupt clear |
#define TIMER_ICR_CBMCINT 0x00000200 // CaptureB match interrupt clear |
#define TIMER_ICR_TBTOCINT 0x00000100 // TimerB time out interrupt clear |
#define TIMER_ICR_RTCCINT 0x00000008 // RTC interrupt clear |
#define TIMER_ICR_CAECINT 0x00000004 // CaptureA event interrupt clear |
#define TIMER_ICR_CAMCINT 0x00000002 // CaptureA match interrupt clear |
#define TIMER_ICR_TATOCINT 0x00000001 // TimerA time out interrupt clear |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TAILR register. |
// |
//***************************************************************************** |
#define TIMER_TAILR_TAILRH_M 0xFFFF0000 // GPTM TimerA Interval Load |
// Register High. |
#define TIMER_TAILR_TAILRL_M 0x0000FFFF // GPTM TimerA Interval Load |
// Register Low. |
#define TIMER_TAILR_TAILRH_S 16 |
#define TIMER_TAILR_TAILRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TBILR register. |
// |
//***************************************************************************** |
#define TIMER_TBILR_TBILRL_M 0x0000FFFF // GPTM TimerB Interval Load |
// Register. |
#define TIMER_TBILR_TBILRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TAMATCHR register. |
// |
//***************************************************************************** |
#define TIMER_TAMATCHR_TAMRH_M 0xFFFF0000 // GPTM TimerA Match Register High. |
#define TIMER_TAMATCHR_TAMRL_M 0x0000FFFF // GPTM TimerA Match Register Low. |
#define TIMER_TAMATCHR_TAMRH_S 16 |
#define TIMER_TAMATCHR_TAMRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TBMATCHR register. |
// |
//***************************************************************************** |
#define TIMER_TBMATCHR_TBMRL_M 0x0000FFFF // GPTM TimerB Match Register Low. |
#define TIMER_TBMATCHR_TBMRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TAR register. |
// |
//***************************************************************************** |
#define TIMER_TAR_TARH_M 0xFFFF0000 // GPTM TimerA Register High. |
#define TIMER_TAR_TARL_M 0x0000FFFF // GPTM TimerA Register Low. |
#define TIMER_TAR_TARH_S 16 |
#define TIMER_TAR_TARL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_TBR register. |
// |
//***************************************************************************** |
#define TIMER_TBR_TBRL_M 0x0000FFFF // GPTM TimerB. |
#define TIMER_TBR_TBRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TAMR register. |
// |
//***************************************************************************** |
#define TIMER_TAMR_TAAMS 0x00000008 // GPTM TimerA Alternate Mode |
// Select. |
#define TIMER_TAMR_TACMR 0x00000004 // GPTM TimerA Capture Mode. |
#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM TimerA Mode. |
#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode. |
#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode. |
#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TBMR register. |
// |
//***************************************************************************** |
#define TIMER_TBMR_TBAMS 0x00000008 // GPTM TimerB Alternate Mode |
// Select. |
#define TIMER_TBMR_TBCMR 0x00000004 // GPTM TimerB Capture Mode. |
#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM TimerB Mode. |
#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode. |
#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode. |
#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_MIS register. |
// |
//***************************************************************************** |
#define TIMER_MIS_CBEMIS 0x00000400 // GPTM CaptureB Event Masked |
// Interrupt. |
#define TIMER_MIS_CBMMIS 0x00000200 // GPTM CaptureB Match Masked |
// Interrupt. |
#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM TimerB Time-Out Masked |
// Interrupt. |
#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt. |
#define TIMER_MIS_CAEMIS 0x00000004 // GPTM CaptureA Event Masked |
// Interrupt. |
#define TIMER_MIS_CAMMIS 0x00000002 // GPTM CaptureA Match Masked |
// Interrupt. |
#define TIMER_MIS_TATOMIS 0x00000001 // GPTM TimerA Time-Out Masked |
// Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TAPR register. |
// |
//***************************************************************************** |
#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM TimerA Prescale. |
#define TIMER_TAPR_TAPSR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TBPR register. |
// |
//***************************************************************************** |
#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM TimerB Prescale. |
#define TIMER_TBPR_TBPSR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TAPMR register. |
// |
//***************************************************************************** |
#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match. |
#define TIMER_TAPMR_TAPSMR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the TIMER_O_TBPMR register. |
// |
//***************************************************************************** |
#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match. |
#define TIMER_TBPMR_TBPSMR_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values of the timer |
// registers. |
// |
//***************************************************************************** |
#define TIMER_RV_TAILR 0xFFFFFFFF // TimerA interval load reg RV |
#define TIMER_RV_TAR 0xFFFFFFFF // TimerA register RV |
#define TIMER_RV_TAMATCHR 0xFFFFFFFF // TimerA match register RV |
#define TIMER_RV_TBILR 0x0000FFFF // TimerB interval load reg RV |
#define TIMER_RV_TBMATCHR 0x0000FFFF // TimerB match register RV |
#define TIMER_RV_TBR 0x0000FFFF // TimerB register RV |
#define TIMER_RV_TAPR 0x00000000 // TimerA prescale register RV |
#define TIMER_RV_CFG 0x00000000 // Configuration register RV |
#define TIMER_RV_TBPMR 0x00000000 // TimerB prescale match regi RV |
#define TIMER_RV_TAPMR 0x00000000 // TimerA prescale match reg RV |
#define TIMER_RV_CTL 0x00000000 // Control register RV |
#define TIMER_RV_ICR 0x00000000 // Interrupt clear register RV |
#define TIMER_RV_TBMR 0x00000000 // TimerB mode register RV |
#define TIMER_RV_MIS 0x00000000 // Masked interrupt status reg RV |
#define TIMER_RV_RIS 0x00000000 // Interrupt status register RV |
#define TIMER_RV_TBPR 0x00000000 // TimerB prescale register RV |
#define TIMER_RV_IMR 0x00000000 // Interrupt mask register RV |
#define TIMER_RV_TAMR 0x00000000 // TimerA mode register RV |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_CFG |
// register. |
// |
//***************************************************************************** |
#define TIMER_CFG_CFG_MSK 0x00000007 // Configuration options mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TnMR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TNMR_TNAMS 0x00000008 // Alternate mode select |
#define TIMER_TNMR_TNCMR 0x00000004 // Capture mode - count or time |
#define TIMER_TNMR_TNTMR_MSK 0x00000003 // Timer mode mask |
#define TIMER_TNMR_TNTMR_1_SHOT 0x00000001 // Mode - one shot |
#define TIMER_TNMR_TNTMR_PERIOD 0x00000002 // Mode - periodic |
#define TIMER_TNMR_TNTMR_CAP 0x00000003 // Mode - capture |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_CTL |
// register. |
// |
//***************************************************************************** |
#define TIMER_CTL_TBEVENT_MSK 0x00000C00 // TimerB event mode mask |
#define TIMER_CTL_TAEVENT_MSK 0x0000000C // TimerA event mode mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_MIS |
// register. |
// |
//***************************************************************************** |
#define TIMER_RIS_CBEMIS 0x00000400 // CaptureB event masked int status |
#define TIMER_RIS_CBMMIS 0x00000200 // CaptureB match masked int status |
#define TIMER_RIS_TBTOMIS 0x00000100 // TimerB time out masked int stat |
#define TIMER_RIS_RTCMIS 0x00000008 // RTC masked int status |
#define TIMER_RIS_CAEMIS 0x00000004 // CaptureA event masked int status |
#define TIMER_RIS_CAMMIS 0x00000002 // CaptureA match masked int status |
#define TIMER_RIS_TATOMIS 0x00000001 // TimerA time out masked int stat |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TAILR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TAILR_TAILRH 0xFFFF0000 // TimerB load val in 32 bit mode |
#define TIMER_TAILR_TAILRL 0x0000FFFF // TimerA interval load value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TBILR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TBILR_TBILRL 0x0000FFFF // TimerB interval load value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// TIMER_TAMATCHR register. |
// |
//***************************************************************************** |
#define TIMER_TAMATCHR_TAMRH 0xFFFF0000 // TimerB match val in 32 bit mode |
#define TIMER_TAMATCHR_TAMRL 0x0000FFFF // TimerA match value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// TIMER_TBMATCHR register. |
// |
//***************************************************************************** |
#define TIMER_TBMATCHR_TBMRL 0x0000FFFF // TimerB match load value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TnPR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TNPR_TNPSR 0x000000FF // TimerN prescale value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TnPMR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TNPMR_TNPSMR 0x000000FF // TimerN prescale match value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TAR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TAR_TARH 0xFFFF0000 // TimerB val in 32 bit mode |
#define TIMER_TAR_TARL 0x0000FFFF // TimerA value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the TIMER_TBR |
// register. |
// |
//***************************************************************************** |
#define TIMER_TBR_TBRL 0x0000FFFF // TimerB value |
|
#endif |
|
#endif // __HW_TIMER_H__ |
/drivers/LuminaryMicro/EULA.txt
0,0 → 1,145
IMPORTANT. Read the following LMI Software License Agreement ("Agreement") |
completely. |
|
In summary, this license agreement allows you to use this software only on |
Luminary Micro microcontrollers, on an as-is basis, with no warranties. |
|
LUMINARY MICRO SOFTWARE LICENSE AGREEMENT |
|
This is a legal agreement between you (either as an individual or as an |
authorized representative of your employer) and Luminary Micro, Inc. ("LMI"). |
It concerns your rights to use this file and any accompanying written materials |
(the "Software"). In consideration for LMI allowing you to access the Software, |
you are agreeing to be bound by the terms of this Agreement. If you do not |
agree to all of the terms of this Agreement, do not download the Software. If |
you change your mind later, stop using the Software and delete all copies of |
the Software in your possession or control. Any copies of the Software that you |
have already distributed, where permitted, and do not destroy will continue to |
be governed by this Agreement. Your prior use will also continue to be governed |
by this Agreement. |
|
1. LICENSE GRANT. LMI grants to you, free of charge, the non-exclusive, |
non-transferable rights solely and exclusively on or for LMI's microcontroller |
products: (1) to use and reproduce the Software, (2) to prepare derivative |
works of the Software, (3) to distribute the Software and derivative works |
thereof in source (human-readable) form and object (machine-readable) form, (4) |
to sublicense to others the right to use the distributed Software, (5) permit |
the Software and derivative works thereof to communicate with "viral open |
source" software (as defined below); provided however that you may not combine |
the two separate and independent works to form a larger program, and (6) |
combine the Software and derivative works thereof with "non-viral open source" |
software (as defined below). For the purposes of this Agreement, "viral open |
source" software means open source software made available on license terms, |
such as the GNU General Public License (GPL), that would alter the foregoing |
license grant restrictions if combined with the Software. For the purposes of |
this Agreement, "non-viral open source" software means open source software |
made available on license terms that would not alter the foregoing license |
grant restrictions if combined with the Software. For the avoidance of any |
doubt, the foregoing license grant does not permit you to combine the Software |
and derivative works thereof with "viral open-source" software in order to |
sublicense to others the right to use the combined software product. If you |
violate any of the terms or restrictions of this Agreement, LMI may immediately |
terminate this Agreement, and require that you stop using and delete all copies |
of the Software in your possession or control. |
|
2. COPYRIGHT. The Software is licensed to you, not sold. LMI owns the Software, |
and United States copyright laws and international treaty provisions protect |
the Software. Therefore, you must treat the Software like any other copyrighted |
material (e.g. a book or musical recording). You may not use or copy the |
Software for any other purpose than what is described in this Agreement. Except |
as expressly provided herein, LMI does not grant to you any express or implied |
rights under any LMI or third-party patents, copyrights, trademarks, or trade |
secrets. Additionally, you must reproduce and apply any copyright or other |
proprietary rights notices included on or embedded in the Software to any |
copies or derivative works made thereof, in whole or in part, if any. |
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3. SUPPORT. LMI is NOT obligated to provide any support, upgrades or new |
releases of the Software. If you wish, you may contact LMI and report problems |
and provide suggestions regarding the Software. LMI has no obligation |
whatsoever to respond in any way to such a problem report or suggestion. LMI |
may make changes to the Software at any time, without any obligation to notify |
or provide updated versions of the Software to you. |
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4. INDEMNITY. You agree to fully defend and indemnify LMI from any and all |
claims, liabilities, and costs (including reasonable attorney's fees) related |
to (1) your use (including your sub-licensee's use, if permitted) of the |
Software or (2) your violation of the terms and conditions of this Agreement. |
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5. HIGH RISK ACTIVITIES. You acknowledge that the Software is not fault |
tolerant and is not designed, manufactured or intended by LMI for incorporation |
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/drivers/LuminaryMicro/hw_sysctl.h
0,0 → 1,1334
//***************************************************************************** |
// |
// hw_sysctl.h - Macros used when accessing the system control hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_SYSCTL_H__ |
#define __HW_SYSCTL_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the system control register addresses. |
// |
//***************************************************************************** |
#define SYSCTL_DID0 0x400FE000 // Device identification register 0 |
#define SYSCTL_DID1 0x400FE004 // Device identification register 1 |
#define SYSCTL_DC0 0x400FE008 // Device capabilities register 0 |
#define SYSCTL_DC1 0x400FE010 // Device capabilities register 1 |
#define SYSCTL_DC2 0x400FE014 // Device capabilities register 2 |
#define SYSCTL_DC3 0x400FE018 // Device capabilities register 3 |
#define SYSCTL_DC4 0x400FE01C // Device capabilities register 4 |
#define SYSCTL_DC5 0x400FE020 // Device capabilities register 5 |
#define SYSCTL_DC6 0x400FE024 // Device capabilities register 6 |
#define SYSCTL_DC7 0x400FE028 // Device capabilities register 7 |
#define SYSCTL_PBORCTL 0x400FE030 // POR/BOR reset control register |
#define SYSCTL_LDOPCTL 0x400FE034 // LDO power control register |
#define SYSCTL_SRCR0 0x400FE040 // Software reset control reg 0 |
#define SYSCTL_SRCR1 0x400FE044 // Software reset control reg 1 |
#define SYSCTL_SRCR2 0x400FE048 // Software reset control reg 2 |
#define SYSCTL_RIS 0x400FE050 // Raw interrupt status register |
#define SYSCTL_IMC 0x400FE054 // Interrupt mask/control register |
#define SYSCTL_MISC 0x400FE058 // Interrupt status register |
#define SYSCTL_RESC 0x400FE05C // Reset cause register |
#define SYSCTL_RCC 0x400FE060 // Run-mode clock config register |
#define SYSCTL_PLLCFG 0x400FE064 // PLL configuration register |
#define SYSCTL_GPIOHSCTL 0x400FE06C // GPIO High Speed Control |
#define SYSCTL_RCC2 0x400FE070 // Run-mode clock config register 2 |
#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control |
#define SYSCTL_RCGC0 0x400FE100 // Run-mode clock gating register 0 |
#define SYSCTL_RCGC1 0x400FE104 // Run-mode clock gating register 1 |
#define SYSCTL_RCGC2 0x400FE108 // Run-mode clock gating register 2 |
#define SYSCTL_SCGC0 0x400FE110 // Sleep-mode clock gating reg 0 |
#define SYSCTL_SCGC1 0x400FE114 // Sleep-mode clock gating reg 1 |
#define SYSCTL_SCGC2 0x400FE118 // Sleep-mode clock gating reg 2 |
#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep-mode clock gate reg 0 |
#define SYSCTL_DCGC1 0x400FE124 // Deep Sleep-mode clock gate reg 1 |
#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep-mode clock gate reg 2 |
#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep-mode clock config reg |
#define SYSCTL_CLKVCLR 0x400FE150 // Clock verifcation clear register |
#define SYSCTL_LDOARST 0x400FE160 // LDO reset control register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DID0 register. |
// |
//***************************************************************************** |
#define SYSCTL_DID0_VER_M 0x70000000 // DID0 version mask |
#define SYSCTL_DID0_VER_0 0x00000000 // DID0 version 0 |
#define SYSCTL_DID0_VER_1 0x10000000 // DID0 version 1 |
#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class |
#define SYSCTL_DID0_CLASS_SANDSTORM \ |
0x00000000 // Sandstorm-class Device |
#define SYSCTL_DID0_CLASS_FURY 0x00010000 // Fury-class Device |
#define SYSCTL_DID0_CLASS_DUSTDEVIL \ |
0x00030000 // DustDevil-class Device |
#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major revision mask |
#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device) |
#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer |
// revision) |
#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer |
// revision) |
#define SYSCTL_DID0_MIN_M 0x000000FF // Minor revision mask |
#define SYSCTL_DID0_MIN_0 0x00000000 // Minor revision 0 |
#define SYSCTL_DID0_MIN_1 0x00000001 // Minor revision 1 |
#define SYSCTL_DID0_MIN_2 0x00000002 // Minor revision 2 |
#define SYSCTL_DID0_MIN_3 0x00000003 // Minor revision 3 |
#define SYSCTL_DID0_MIN_4 0x00000004 // Minor revision 4 |
#define SYSCTL_DID0_MIN_5 0x00000005 // Minor revision 5 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DID1 register. |
// |
//***************************************************************************** |
#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version. |
#define SYSCTL_DID1_VER_0 0x00000000 // Initial DID1 register format |
// definition, indicating a |
// Stellaris LM3Snnn device. |
#define SYSCTL_DID1_VER_1 0x10000000 // First revision of the DID1 |
// register format, indicating a |
// Stellaris Fury-class device. |
#define SYSCTL_DID1_FAM_M 0x0F000000 // Family. |
#define SYSCTL_DID1_FAM_STELLARIS \ |
0x00000000 // Stellaris family of |
// microcontollers, that is, all |
// devices with external part |
// numbers starting with LM3S. |
#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part number mask |
#define SYSCTL_DID1_PRTNO_101 0x00010000 // LM3S101 |
#define SYSCTL_DID1_PRTNO_102 0x00020000 // LM3S102 |
#define SYSCTL_DID1_PRTNO_300 0x00190000 // LM3S300 |
#define SYSCTL_DID1_PRTNO_301 0x00110000 // LM3S301 |
#define SYSCTL_DID1_PRTNO_308 0x001A0000 // LM3S308 |
#define SYSCTL_DID1_PRTNO_310 0x00120000 // LM3S310 |
#define SYSCTL_DID1_PRTNO_315 0x00130000 // LM3S315 |
#define SYSCTL_DID1_PRTNO_316 0x00140000 // LM3S316 |
#define SYSCTL_DID1_PRTNO_317 0x00170000 // LM3S317 |
#define SYSCTL_DID1_PRTNO_328 0x00150000 // LM3S328 |
#define SYSCTL_DID1_PRTNO_600 0x002A0000 // LM3S600 |
#define SYSCTL_DID1_PRTNO_601 0x00210000 // LM3S601 |
#define SYSCTL_DID1_PRTNO_608 0x002B0000 // LM3S608 |
#define SYSCTL_DID1_PRTNO_610 0x00220000 // LM3S610 |
#define SYSCTL_DID1_PRTNO_611 0x00230000 // LM3S611 |
#define SYSCTL_DID1_PRTNO_612 0x00240000 // LM3S612 |
#define SYSCTL_DID1_PRTNO_613 0x00250000 // LM3S613 |
#define SYSCTL_DID1_PRTNO_615 0x00260000 // LM3S615 |
#define SYSCTL_DID1_PRTNO_617 0x00280000 // LM3S617 |
#define SYSCTL_DID1_PRTNO_618 0x00290000 // LM3S618 |
#define SYSCTL_DID1_PRTNO_628 0x00270000 // LM3S628 |
#define SYSCTL_DID1_PRTNO_800 0x00380000 // LM3S800 |
#define SYSCTL_DID1_PRTNO_801 0x00310000 // LM3S801 |
#define SYSCTL_DID1_PRTNO_808 0x00390000 // LM3S808 |
#define SYSCTL_DID1_PRTNO_811 0x00320000 // LM3S811 |
#define SYSCTL_DID1_PRTNO_812 0x00330000 // LM3S812 |
#define SYSCTL_DID1_PRTNO_815 0x00340000 // LM3S815 |
#define SYSCTL_DID1_PRTNO_817 0x00360000 // LM3S817 |
#define SYSCTL_DID1_PRTNO_818 0x00370000 // LM3S818 |
#define SYSCTL_DID1_PRTNO_828 0x00350000 // LM3S828 |
#define SYSCTL_DID1_PRTNO_1110 0x00BF0000 // LM3S1110 |
#define SYSCTL_DID1_PRTNO_1133 0x00C30000 // LM3S1133 |
#define SYSCTL_DID1_PRTNO_1138 0x00C50000 // LM3S1138 |
#define SYSCTL_DID1_PRTNO_1150 0x00C10000 // LM3S1150 |
#define SYSCTL_DID1_PRTNO_1162 0x00C40000 // LM3S1162 |
#define SYSCTL_DID1_PRTNO_1165 0x00C20000 // LM3S1165 |
#define SYSCTL_DID1_PRTNO_1332 0x00C60000 // LM3S1332 |
#define SYSCTL_DID1_PRTNO_1435 0x00BC0000 // LM3S1435 |
#define SYSCTL_DID1_PRTNO_1439 0x00BA0000 // LM3S1439 |
#define SYSCTL_DID1_PRTNO_1512 0x00BB0000 // LM3S1512 |
#define SYSCTL_DID1_PRTNO_1538 0x00C70000 // LM3S1538 |
#define SYSCTL_DID1_PRTNO_1601 0x00DB0000 // LM3S1601 |
#define SYSCTL_DID1_PRTNO_1607 0x00060000 // LM3S1607 |
#define SYSCTL_DID1_PRTNO_1608 0x00DA0000 // LM3S1608 |
#define SYSCTL_DID1_PRTNO_1620 0x00C00000 // LM3S1620 |
#define SYSCTL_DID1_PRTNO_1625 0x00030000 // LM3S1625 |
#define SYSCTL_DID1_PRTNO_1626 0x00040000 // LM3S1626 |
#define SYSCTL_DID1_PRTNO_1627 0x00050000 // LM3S1627 |
#define SYSCTL_DID1_PRTNO_1635 0x00B30000 // LM3S1635 |
#define SYSCTL_DID1_PRTNO_1637 0x00BD0000 // LM3S1637 |
#define SYSCTL_DID1_PRTNO_1751 0x00B90000 // LM3S1751 |
#define SYSCTL_DID1_PRTNO_1776 0x00100000 // LM3S1776 |
#define SYSCTL_DID1_PRTNO_1850 0x00B40000 // LM3S1850 |
#define SYSCTL_DID1_PRTNO_1911 0x00DD0000 // LM3S1911 |
#define SYSCTL_DID1_PRTNO_1918 0x00DC0000 // LM3S1918 |
#define SYSCTL_DID1_PRTNO_1937 0x00B70000 // LM3S1937 |
#define SYSCTL_DID1_PRTNO_1958 0x00BE0000 // LM3S1958 |
#define SYSCTL_DID1_PRTNO_1960 0x00B50000 // LM3S1960 |
#define SYSCTL_DID1_PRTNO_1968 0x00B80000 // LM3S1968 |
#define SYSCTL_DID1_PRTNO_2110 0x00510000 // LM3S2110 |
#define SYSCTL_DID1_PRTNO_2139 0x00840000 // LM3S2139 |
#define SYSCTL_DID1_PRTNO_2276 0x00390000 // LM3S2276 |
#define SYSCTL_DID1_PRTNO_2410 0x00A20000 // LM3S2410 |
#define SYSCTL_DID1_PRTNO_2412 0x00590000 // LM3S2412 |
#define SYSCTL_DID1_PRTNO_2432 0x00560000 // LM3S2432 |
#define SYSCTL_DID1_PRTNO_2533 0x005A0000 // LM3S2533 |
#define SYSCTL_DID1_PRTNO_2601 0x00E10000 // LM3S2601 |
#define SYSCTL_DID1_PRTNO_2608 0x00E00000 // LM3S2608 |
#define SYSCTL_DID1_PRTNO_2616 0x00330000 // LM3S2616 |
#define SYSCTL_DID1_PRTNO_2620 0x00570000 // LM3S2620 |
#define SYSCTL_DID1_PRTNO_2637 0x00850000 // LM3S2637 |
#define SYSCTL_DID1_PRTNO_2651 0x00530000 // LM3S2651 |
#define SYSCTL_DID1_PRTNO_2671 0x00800000 // LM3S2671 |
#define SYSCTL_DID1_PRTNO_2678 0x00500000 // LM3S2678 |
#define SYSCTL_DID1_PRTNO_2730 0x00A40000 // LM3S2730 |
#define SYSCTL_DID1_PRTNO_2739 0x00520000 // LM3S2739 |
#define SYSCTL_DID1_PRTNO_2776 0x003A0000 // LM3S2776 |
#define SYSCTL_DID1_PRTNO_2911 0x00E30000 // LM3S2911 |
#define SYSCTL_DID1_PRTNO_2918 0x00E20000 // LM3S2918 |
#define SYSCTL_DID1_PRTNO_2939 0x00540000 // LM3S2939 |
#define SYSCTL_DID1_PRTNO_2948 0x008F0000 // LM3S2948 |
#define SYSCTL_DID1_PRTNO_2950 0x00580000 // LM3S2950 |
#define SYSCTL_DID1_PRTNO_2965 0x00550000 // LM3S2965 |
#define SYSCTL_DID1_PRTNO_3651 0x00430000 // LM3S3651 |
#define SYSCTL_DID1_PRTNO_3739 0x00440000 // LM3S3739 |
#define SYSCTL_DID1_PRTNO_3748 0x00490000 // LM3S3748 |
#define SYSCTL_DID1_PRTNO_3749 0x00450000 // LM3S3749 |
#define SYSCTL_DID1_PRTNO_3759 0x00460000 // LM3S3759 |
#define SYSCTL_DID1_PRTNO_3768 0x00480000 // LM3S3768 |
#define SYSCTL_DID1_PRTNO_5632 0x00810000 // LM3S5632 |
#define SYSCTL_DID1_PRTNO_5652 0x008A0000 // LM3S5652 |
#define SYSCTL_DID1_PRTNO_5662 0x00910000 // LM3S5662 |
#define SYSCTL_DID1_PRTNO_5732 0x00960000 // LM3S5732 |
#define SYSCTL_DID1_PRTNO_5737 0x00970000 // LM3S5737 |
#define SYSCTL_DID1_PRTNO_5739 0x00A00000 // LM3S5739 |
#define SYSCTL_DID1_PRTNO_5747 0x00990000 // LM3S5747 |
#define SYSCTL_DID1_PRTNO_5749 0x00A70000 // LM3S5749 |
#define SYSCTL_DID1_PRTNO_5752 0x009A0000 // LM3S5752 |
#define SYSCTL_DID1_PRTNO_5757 0x009B0000 // LM3S5757 |
#define SYSCTL_DID1_PRTNO_5762 0x009C0000 // LM3S5762 |
#define SYSCTL_DID1_PRTNO_5767 0x009D0000 // LM3S5767 |
#define SYSCTL_DID1_PRTNO_5768 0x00A90000 // LM3S5768 |
#define SYSCTL_DID1_PRTNO_5769 0x00A80000 // LM3S5769 |
#define SYSCTL_DID1_PRTNO_6100 0x00A10000 // LM3S6100 |
#define SYSCTL_DID1_PRTNO_6110 0x00740000 // LM3S6110 |
#define SYSCTL_DID1_PRTNO_6420 0x00A50000 // LM3S6420 |
#define SYSCTL_DID1_PRTNO_6422 0x00820000 // LM3S6422 |
#define SYSCTL_DID1_PRTNO_6432 0x00750000 // LM3S6432 |
#define SYSCTL_DID1_PRTNO_6537 0x00760000 // LM3S6537 |
#define SYSCTL_DID1_PRTNO_6610 0x00710000 // LM3S6610 |
#define SYSCTL_DID1_PRTNO_6611 0x00E70000 // LM3S6611 |
#define SYSCTL_DID1_PRTNO_6618 0x00E60000 // LM3S6618 |
#define SYSCTL_DID1_PRTNO_6633 0x00830000 // LM3S6633 |
#define SYSCTL_DID1_PRTNO_6637 0x008B0000 // LM3S6637 |
#define SYSCTL_DID1_PRTNO_6730 0x00A30000 // LM3S6730 |
#define SYSCTL_DID1_PRTNO_6753 0x00770000 // LM3S6753 |
#define SYSCTL_DID1_PRTNO_6911 0x00E90000 // LM3S6911 |
#define SYSCTL_DID1_PRTNO_6918 0x00E80000 // LM3S6918 |
#define SYSCTL_DID1_PRTNO_6938 0x00890000 // LM3S6938 |
#define SYSCTL_DID1_PRTNO_6950 0x00720000 // LM3S6950 |
#define SYSCTL_DID1_PRTNO_6952 0x00780000 // LM3S6952 |
#define SYSCTL_DID1_PRTNO_6965 0x00730000 // LM3S6965 |
#define SYSCTL_DID1_PRTNO_8530 0x00640000 // LM3S8530 |
#define SYSCTL_DID1_PRTNO_8538 0x008E0000 // LM3S8538 |
#define SYSCTL_DID1_PRTNO_8630 0x00610000 // LM3S8630 |
#define SYSCTL_DID1_PRTNO_8730 0x00630000 // LM3S8730 |
#define SYSCTL_DID1_PRTNO_8733 0x008D0000 // LM3S8733 |
#define SYSCTL_DID1_PRTNO_8738 0x00860000 // LM3S8738 |
#define SYSCTL_DID1_PRTNO_8930 0x00650000 // LM3S8930 |
#define SYSCTL_DID1_PRTNO_8933 0x008C0000 // LM3S8933 |
#define SYSCTL_DID1_PRTNO_8938 0x00880000 // LM3S8938 |
#define SYSCTL_DID1_PRTNO_8962 0x00A60000 // LM3S8962 |
#define SYSCTL_DID1_PRTNO_8970 0x00620000 // LM3S8970 |
#define SYSCTL_DID1_PRTNO_8971 0x00D70000 // LM3S8971 |
#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count. |
#define SYSCTL_DID1_PINCNT_28 0x00000000 // 28 pin package |
#define SYSCTL_DID1_PINCNT_48 0x00002000 // 48 pin package |
#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100 pin package |
#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64 pin package |
#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature range mask |
#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temp range (0..70C) |
#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temp range (-40..85C) |
#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range (-40C |
// to 105C) |
#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type. |
#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package |
#define SYSCTL_DID1_PKG_28SOIC 0x00000000 // 28-pin SOIC |
#define SYSCTL_DID1_PKG_48QFP 0x00000008 // 48-pin QFP |
#define SYSCTL_DID1_ROHS 0x00000004 // Part is RoHS compliant |
#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification status mask |
#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering sample (unqualified) |
#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot production (unqualified) |
#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully qualified |
#define SYSCTL_DID1_PRTNO_S 16 // Part number shift |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC0 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM size mask |
#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM |
#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM |
#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM |
#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM |
#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM |
#define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 // 64 KB of SRAM |
#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash size mask |
#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of flash |
#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of flash |
#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of flash |
#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of flash |
#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of flash |
#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of flash |
#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of flash |
#define SYSCTL_DC0_SRAMSZ_S 16 // SRAM size shift |
#define SYSCTL_DC0_FLASHSZ_S 0 // Flash size shift |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC1 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC1_CAN2 0x04000000 // CAN2 module present |
#define SYSCTL_DC1_CAN1 0x02000000 // CAN1 module present |
#define SYSCTL_DC1_CAN0 0x01000000 // CAN0 module present |
#define SYSCTL_DC1_PWM 0x00100000 // PWM module present |
#define SYSCTL_DC1_ADC 0x00010000 // ADC module present |
#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider. |
#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock |
// with a PLL divider of 4. |
#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a |
// PLL divider of 8. |
#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a |
// PLL divider of 10. |
#define SYSCTL_DC1_ADCSPD_M 0x00000F00 // ADC speed mask |
#define SYSCTL_DC1_ADCSPD_125K 0x00000000 // 125Ksps ADC |
#define SYSCTL_DC1_ADCSPD_250K 0x00000100 // 250Ksps ADC |
#define SYSCTL_DC1_ADCSPD_500K 0x00000200 // 500Ksps ADC |
#define SYSCTL_DC1_ADCSPD_1M 0x00000300 // 1Msps ADC |
#define SYSCTL_DC1_MPU 0x00000080 // Cortex M3 MPU present |
#define SYSCTL_DC1_HIB 0x00000040 // Hibernation module present |
#define SYSCTL_DC1_TEMP 0x00000020 // Temperature sensor present |
#define SYSCTL_DC1_PLL 0x00000010 // PLL present |
#define SYSCTL_DC1_WDT 0x00000008 // Watchdog Timer Present. |
#define SYSCTL_DC1_SWO 0x00000004 // Serial wire output present |
#define SYSCTL_DC1_SWD 0x00000002 // Serial wire debug present |
#define SYSCTL_DC1_JTAG 0x00000001 // JTAG debug present |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC2 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC2_COMP2 0x04000000 // Analog comparator 2 present |
#define SYSCTL_DC2_COMP1 0x02000000 // Analog comparator 1 present |
#define SYSCTL_DC2_COMP0 0x01000000 // Analog comparator 0 present |
#define SYSCTL_DC2_TIMER3 0x00080000 // Timer 3 present |
#define SYSCTL_DC2_TIMER2 0x00040000 // Timer 2 present |
#define SYSCTL_DC2_TIMER1 0x00020000 // Timer 1 present |
#define SYSCTL_DC2_TIMER0 0x00010000 // Timer 0 present |
#define SYSCTL_DC2_I2C1 0x00004000 // I2C 1 present |
#define SYSCTL_DC2_I2C0 0x00001000 // I2C 0 present |
#define SYSCTL_DC2_QEI1 0x00000200 // QEI 1 present |
#define SYSCTL_DC2_QEI0 0x00000100 // QEI 0 present |
#define SYSCTL_DC2_SSI1 0x00000020 // SSI 1 present |
#define SYSCTL_DC2_SSI0 0x00000010 // SSI 0 present |
#define SYSCTL_DC2_UART2 0x00000004 // UART 2 present |
#define SYSCTL_DC2_UART1 0x00000002 // UART 1 present |
#define SYSCTL_DC2_UART0 0x00000001 // UART 0 present |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC3 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Pin Present. |
#define SYSCTL_DC3_CCP5 0x20000000 // CCP5 pin present |
#define SYSCTL_DC3_CCP4 0x10000000 // CCP4 pin present |
#define SYSCTL_DC3_CCP3 0x08000000 // CCP3 pin present |
#define SYSCTL_DC3_CCP2 0x04000000 // CCP2 pin present |
#define SYSCTL_DC3_CCP1 0x02000000 // CCP1 pin present |
#define SYSCTL_DC3_CCP0 0x01000000 // CCP0 pin present |
#define SYSCTL_DC3_ADC7 0x00800000 // ADC7 pin present |
#define SYSCTL_DC3_ADC6 0x00400000 // ADC6 pin present |
#define SYSCTL_DC3_ADC5 0x00200000 // ADC5 pin present |
#define SYSCTL_DC3_ADC4 0x00100000 // ADC4 pin present |
#define SYSCTL_DC3_ADC3 0x00080000 // ADC3 pin present |
#define SYSCTL_DC3_ADC2 0x00040000 // ADC2 pin present |
#define SYSCTL_DC3_ADC1 0x00020000 // ADC1 pin present |
#define SYSCTL_DC3_ADC0 0x00010000 // ADC0 pin present |
#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present. |
#define SYSCTL_DC3_C2O 0x00004000 // C2o pin present |
#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ pin present |
#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- pin present |
#define SYSCTL_DC3_C1O 0x00000800 // C1o pin present |
#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ pin present |
#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- pin present |
#define SYSCTL_DC3_C0O 0x00000100 // C0o pin present |
#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ pin present |
#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- pin present |
#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 pin present |
#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 pin present |
#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 pin present |
#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 pin present |
#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 pin present |
#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 pin present |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC4 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC4_ETH 0x50000000 // Ethernet present |
#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY0 Present. |
#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC0 Present. |
#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable. |
#define SYSCTL_DC4_CCP7 0x00008000 // CCP7 Pin Present. |
#define SYSCTL_DC4_CCP6 0x00004000 // CCP6 Pin Present. |
#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA is present. |
#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM is present. |
#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO port H present |
#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO port G present |
#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO port F present |
#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO port E present |
#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO port D present |
#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO port C present |
#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO port B present |
#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO port A present |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_PBORCTL register. |
// |
//***************************************************************************** |
#define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC // BOR Time Delay. |
#define SYSCTL_PBORCTL_BORIOR 0x00000002 // BOR interrupt or reset |
#define SYSCTL_PBORCTL_BORWT 0x00000001 // BOR wait and check for noise |
#define SYSCTL_PBORCTL_BORTIM_S 2 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_LDOPCTL register. |
// |
//***************************************************************************** |
#define SYSCTL_LDOPCTL_M 0x0000003F // LDO Output Voltage. |
#define SYSCTL_LDOPCTL_2_55V 0x0000001F // LDO output of 2.55V |
#define SYSCTL_LDOPCTL_2_60V 0x0000001E // LDO output of 2.60V |
#define SYSCTL_LDOPCTL_2_65V 0x0000001D // LDO output of 2.65V |
#define SYSCTL_LDOPCTL_2_70V 0x0000001C // LDO output of 2.70V |
#define SYSCTL_LDOPCTL_2_75V 0x0000001B // LDO output of 2.75V |
#define SYSCTL_LDOPCTL_2_25V 0x00000005 // LDO output of 2.25V |
#define SYSCTL_LDOPCTL_2_30V 0x00000004 // LDO output of 2.30V |
#define SYSCTL_LDOPCTL_2_35V 0x00000003 // LDO output of 2.35V |
#define SYSCTL_LDOPCTL_2_40V 0x00000002 // LDO output of 2.40V |
#define SYSCTL_LDOPCTL_2_45V 0x00000001 // LDO output of 2.45V |
#define SYSCTL_LDOPCTL_2_50V 0x00000000 // LDO output of 2.50V |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RESC register. |
// |
//***************************************************************************** |
#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset. |
#define SYSCTL_RESC_LDO 0x00000020 // LDO power OK lost reset |
#define SYSCTL_RESC_SW 0x00000010 // Software reset |
#define SYSCTL_RESC_WDT 0x00000008 // Watchdog Timer Reset. |
#define SYSCTL_RESC_BOR 0x00000004 // Brown-out reset |
#define SYSCTL_RESC_POR 0x00000002 // Power on reset |
#define SYSCTL_RESC_EXT 0x00000001 // External reset |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RCC register. |
// |
//***************************************************************************** |
#define SYSCTL_RCC_ACG 0x08000000 // Automatic clock gating |
#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor. |
#define SYSCTL_RCC_SYSDIV_2 0x00800000 // System clock /2 |
#define SYSCTL_RCC_SYSDIV_3 0x01000000 // System clock /3 |
#define SYSCTL_RCC_SYSDIV_4 0x01800000 // System clock /4 |
#define SYSCTL_RCC_SYSDIV_5 0x02000000 // System clock /5 |
#define SYSCTL_RCC_SYSDIV_6 0x02800000 // System clock /6 |
#define SYSCTL_RCC_SYSDIV_7 0x03000000 // System clock /7 |
#define SYSCTL_RCC_SYSDIV_8 0x03800000 // System clock /8 |
#define SYSCTL_RCC_SYSDIV_9 0x04000000 // System clock /9 |
#define SYSCTL_RCC_SYSDIV_10 0x04800000 // System clock /10 |
#define SYSCTL_RCC_SYSDIV_11 0x05000000 // System clock /11 |
#define SYSCTL_RCC_SYSDIV_12 0x05800000 // System clock /12 |
#define SYSCTL_RCC_SYSDIV_13 0x06000000 // System clock /13 |
#define SYSCTL_RCC_SYSDIV_14 0x06800000 // System clock /14 |
#define SYSCTL_RCC_SYSDIV_15 0x07000000 // System clock /15 |
#define SYSCTL_RCC_SYSDIV_16 0x07800000 // System clock /16 |
#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider. |
#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor. |
#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM clock divider |
#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2 |
#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4 |
#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8 |
#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16 |
#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32 |
#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64 |
#define SYSCTL_RCC_PWRDN 0x00002000 // PLL power down |
#define SYSCTL_RCC_OEN 0x00001000 // PLL Output Enable. |
#define SYSCTL_RCC_BYPASS 0x00000800 // PLL bypass |
#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal attached to main osc |
#define SYSCTL_RCC_XTAL_1MHZ 0x00000000 // Using a 1MHz crystal |
#define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 // Using a 1.8432MHz crystal |
#define SYSCTL_RCC_XTAL_2MHZ 0x00000080 // Using a 2MHz crystal |
#define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 // Using a 2.4576MHz crystal |
#define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 // Using a 3.579545MHz crystal |
#define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 // Using a 3.6864MHz crystal |
#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // Using a 4MHz crystal |
#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // Using a 4.096MHz crystal |
#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // Using a 4.9152MHz crystal |
#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // Using a 5MHz crystal |
#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // Using a 5.12MHz crystal |
#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // Using a 6MHz crystal |
#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // Using a 6.144MHz crystal |
#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // Using a 7.3728MHz crystal |
#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // Using a 8MHz crystal |
#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // Using a 8.192MHz crystal |
#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10.0 MHz (USB) |
#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12.0 MHz (USB) |
#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz |
#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz |
#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz |
#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16.0 MHz (USB) |
#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz |
#define SYSCTL_RCC_PLLVER 0x00000400 // PLL verification timer enable |
#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator input select |
#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // Use the main oscillator |
#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // Use the internal oscillator |
#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // Use the internal oscillator / 4 |
#define SYSCTL_RCC_OSCSRC_30 0x00000030 // 30 KHz internal oscillator |
#define SYSCTL_RCC_IOSCVER 0x00000008 // Int. osc. verification timer en |
#define SYSCTL_RCC_MOSCVER 0x00000004 // Main osc. verification timer en |
#define SYSCTL_RCC_IOSCDIS 0x00000002 // Internal oscillator disable |
#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main oscillator disable |
#define SYSCTL_RCC_SYSDIV_S 23 // Shift to the SYSDIV field |
#define SYSCTL_RCC_PWMDIV_S 17 // Shift to the PWMDIV field |
#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field |
#define SYSCTL_RCC_OSCSRC_S 4 // Shift to the OSCSRC field |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_PLLCFG register. |
// |
//***************************************************************************** |
#define SYSCTL_PLLCFG_OD_M 0x0000C000 // Output divider |
#define SYSCTL_PLLCFG_OD_1 0x00000000 // Output divider is 1 |
#define SYSCTL_PLLCFG_OD_2 0x00004000 // Output divider is 2 |
#define SYSCTL_PLLCFG_OD_4 0x00008000 // Output divider is 4 |
#define SYSCTL_PLLCFG_F_M 0x00003FE0 // PLL F Value. |
#define SYSCTL_PLLCFG_R_M 0x0000001F // PLL R Value. |
#define SYSCTL_PLLCFG_F_S 5 |
#define SYSCTL_PLLCFG_R_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RCC2 register. |
// |
//***************************************************************************** |
#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2 |
#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System clock divider |
#define SYSCTL_RCC2_SYSDIV2_2 0x00800000 // System clock /2 |
#define SYSCTL_RCC2_SYSDIV2_3 0x01000000 // System clock /3 |
#define SYSCTL_RCC2_SYSDIV2_4 0x01800000 // System clock /4 |
#define SYSCTL_RCC2_SYSDIV2_5 0x02000000 // System clock /5 |
#define SYSCTL_RCC2_SYSDIV2_6 0x02800000 // System clock /6 |
#define SYSCTL_RCC2_SYSDIV2_7 0x03000000 // System clock /7 |
#define SYSCTL_RCC2_SYSDIV2_8 0x03800000 // System clock /8 |
#define SYSCTL_RCC2_SYSDIV2_9 0x04000000 // System clock /9 |
#define SYSCTL_RCC2_SYSDIV2_10 0x04800000 // System clock /10 |
#define SYSCTL_RCC2_SYSDIV2_11 0x05000000 // System clock /11 |
#define SYSCTL_RCC2_SYSDIV2_12 0x05800000 // System clock /12 |
#define SYSCTL_RCC2_SYSDIV2_13 0x06000000 // System clock /13 |
#define SYSCTL_RCC2_SYSDIV2_14 0x06800000 // System clock /14 |
#define SYSCTL_RCC2_SYSDIV2_15 0x07000000 // System clock /15 |
#define SYSCTL_RCC2_SYSDIV2_16 0x07800000 // System clock /16 |
#define SYSCTL_RCC2_SYSDIV2_17 0x08000000 // System clock /17 |
#define SYSCTL_RCC2_SYSDIV2_18 0x08800000 // System clock /18 |
#define SYSCTL_RCC2_SYSDIV2_19 0x09000000 // System clock /19 |
#define SYSCTL_RCC2_SYSDIV2_20 0x09800000 // System clock /20 |
#define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 // System clock /21 |
#define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 // System clock /22 |
#define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 // System clock /23 |
#define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 // System clock /24 |
#define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 // System clock /25 |
#define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 // System clock /26 |
#define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 // System clock /27 |
#define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 // System clock /28 |
#define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 // System clock /29 |
#define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 // System clock /30 |
#define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 // System clock /31 |
#define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 // System clock /32 |
#define SYSCTL_RCC2_SYSDIV2_33 0x10000000 // System clock /33 |
#define SYSCTL_RCC2_SYSDIV2_34 0x10800000 // System clock /34 |
#define SYSCTL_RCC2_SYSDIV2_35 0x11000000 // System clock /35 |
#define SYSCTL_RCC2_SYSDIV2_36 0x11800000 // System clock /36 |
#define SYSCTL_RCC2_SYSDIV2_37 0x12000000 // System clock /37 |
#define SYSCTL_RCC2_SYSDIV2_38 0x12800000 // System clock /38 |
#define SYSCTL_RCC2_SYSDIV2_39 0x13000000 // System clock /39 |
#define SYSCTL_RCC2_SYSDIV2_40 0x13800000 // System clock /40 |
#define SYSCTL_RCC2_SYSDIV2_41 0x14000000 // System clock /41 |
#define SYSCTL_RCC2_SYSDIV2_42 0x14800000 // System clock /42 |
#define SYSCTL_RCC2_SYSDIV2_43 0x15000000 // System clock /43 |
#define SYSCTL_RCC2_SYSDIV2_44 0x15800000 // System clock /44 |
#define SYSCTL_RCC2_SYSDIV2_45 0x16000000 // System clock /45 |
#define SYSCTL_RCC2_SYSDIV2_46 0x16800000 // System clock /46 |
#define SYSCTL_RCC2_SYSDIV2_47 0x17000000 // System clock /47 |
#define SYSCTL_RCC2_SYSDIV2_48 0x17800000 // System clock /48 |
#define SYSCTL_RCC2_SYSDIV2_49 0x18000000 // System clock /49 |
#define SYSCTL_RCC2_SYSDIV2_50 0x18800000 // System clock /50 |
#define SYSCTL_RCC2_SYSDIV2_51 0x19000000 // System clock /51 |
#define SYSCTL_RCC2_SYSDIV2_52 0x19800000 // System clock /52 |
#define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 // System clock /53 |
#define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 // System clock /54 |
#define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 // System clock /55 |
#define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 // System clock /56 |
#define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 // System clock /57 |
#define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 // System clock /58 |
#define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 // System clock /59 |
#define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 // System clock /60 |
#define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 // System clock /61 |
#define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 // System clock /62 |
#define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 // System clock /63 |
#define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 // System clock /64 |
#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL. |
#define SYSCTL_RCC2_PWRDN2 0x00002000 // PLL power down |
#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL bypass |
#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // System Clock Source. |
#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // Use the main oscillator |
#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // Use the internal oscillator |
#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // Use the internal oscillator / 4 |
#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // Use the 30 KHz internal osc. |
#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // Use the 32 KHz external osc. |
#define SYSCTL_RCC2_SYSDIV2_S 23 // Shift to the SYSDIV2 field |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override. |
#define SYSCTL_DSLPCLKCFG_D_2 0x00800000 // System clock /2 |
#define SYSCTL_DSLPCLKCFG_D_3 0x01000000 // System clock /3 |
#define SYSCTL_DSLPCLKCFG_D_4 0x01800000 // System clock /4 |
#define SYSCTL_DSLPCLKCFG_D_5 0x02000000 // System clock /5 |
#define SYSCTL_DSLPCLKCFG_D_6 0x02800000 // System clock /6 |
#define SYSCTL_DSLPCLKCFG_D_7 0x03000000 // System clock /7 |
#define SYSCTL_DSLPCLKCFG_D_8 0x03800000 // System clock /8 |
#define SYSCTL_DSLPCLKCFG_D_9 0x04000000 // System clock /9 |
#define SYSCTL_DSLPCLKCFG_D_10 0x04800000 // System clock /10 |
#define SYSCTL_DSLPCLKCFG_D_11 0x05000000 // System clock /11 |
#define SYSCTL_DSLPCLKCFG_D_12 0x05800000 // System clock /12 |
#define SYSCTL_DSLPCLKCFG_D_13 0x06000000 // System clock /13 |
#define SYSCTL_DSLPCLKCFG_D_14 0x06800000 // System clock /14 |
#define SYSCTL_DSLPCLKCFG_D_15 0x07000000 // System clock /15 |
#define SYSCTL_DSLPCLKCFG_D_16 0x07800000 // System clock /16 |
#define SYSCTL_DSLPCLKCFG_D_17 0x08000000 // System clock /17 |
#define SYSCTL_DSLPCLKCFG_D_18 0x08800000 // System clock /18 |
#define SYSCTL_DSLPCLKCFG_D_19 0x09000000 // System clock /19 |
#define SYSCTL_DSLPCLKCFG_D_20 0x09800000 // System clock /20 |
#define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 // System clock /21 |
#define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 // System clock /22 |
#define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 // System clock /23 |
#define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 // System clock /24 |
#define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 // System clock /25 |
#define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 // System clock /26 |
#define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 // System clock /27 |
#define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 // System clock /28 |
#define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 // System clock /29 |
#define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 // System clock /30 |
#define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 // System clock /31 |
#define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 // System clock /32 |
#define SYSCTL_DSLPCLKCFG_D_33 0x10000000 // System clock /33 |
#define SYSCTL_DSLPCLKCFG_D_34 0x10800000 // System clock /34 |
#define SYSCTL_DSLPCLKCFG_D_35 0x11000000 // System clock /35 |
#define SYSCTL_DSLPCLKCFG_D_36 0x11800000 // System clock /36 |
#define SYSCTL_DSLPCLKCFG_D_37 0x12000000 // System clock /37 |
#define SYSCTL_DSLPCLKCFG_D_38 0x12800000 // System clock /38 |
#define SYSCTL_DSLPCLKCFG_D_39 0x13000000 // System clock /39 |
#define SYSCTL_DSLPCLKCFG_D_40 0x13800000 // System clock /40 |
#define SYSCTL_DSLPCLKCFG_D_41 0x14000000 // System clock /41 |
#define SYSCTL_DSLPCLKCFG_D_42 0x14800000 // System clock /42 |
#define SYSCTL_DSLPCLKCFG_D_43 0x15000000 // System clock /43 |
#define SYSCTL_DSLPCLKCFG_D_44 0x15800000 // System clock /44 |
#define SYSCTL_DSLPCLKCFG_D_45 0x16000000 // System clock /45 |
#define SYSCTL_DSLPCLKCFG_D_46 0x16800000 // System clock /46 |
#define SYSCTL_DSLPCLKCFG_D_47 0x17000000 // System clock /47 |
#define SYSCTL_DSLPCLKCFG_D_48 0x17800000 // System clock /48 |
#define SYSCTL_DSLPCLKCFG_D_49 0x18000000 // System clock /49 |
#define SYSCTL_DSLPCLKCFG_D_50 0x18800000 // System clock /50 |
#define SYSCTL_DSLPCLKCFG_D_51 0x19000000 // System clock /51 |
#define SYSCTL_DSLPCLKCFG_D_52 0x19800000 // System clock /52 |
#define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 // System clock /53 |
#define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 // System clock /54 |
#define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 // System clock /55 |
#define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 // System clock /56 |
#define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 // System clock /57 |
#define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 // System clock /58 |
#define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 // System clock /59 |
#define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 // System clock /60 |
#define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 // System clock /61 |
#define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 // System clock /62 |
#define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 // System clock /63 |
#define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 // System clock /64 |
#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source. |
#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // Do not override |
#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // Use the internal oscillator |
#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // Use the 30 KHz internal osc. |
#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // Use the 32 KHz external osc. |
#define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 // IOSC Clock Source. |
#define SYSCTL_DSLPCLKCFG_D_S 23 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_CLKVCLR register. |
// |
//***************************************************************************** |
#define SYSCTL_CLKVCLR_VERCLR 0x00000001 // Clock Verification Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_LDOARST register. |
// |
//***************************************************************************** |
#define SYSCTL_LDOARST_LDOARST 0x00000001 // LDO Reset. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SRCR0 register. |
// |
//***************************************************************************** |
#define SYSCTL_SRCR0_CAN2 0x04000000 // CAN2 Reset Control. |
#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control. |
#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control. |
#define SYSCTL_SRCR0_PWM 0x00100000 // PWM Reset Control. |
#define SYSCTL_SRCR0_ADC 0x00010000 // ADC0 Reset Control. |
#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control. |
#define SYSCTL_SRCR0_WDT 0x00000008 // WDT Reset Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SRCR1 register. |
// |
//***************************************************************************** |
#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control. |
#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control. |
#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control. |
#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control. |
#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control. |
#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control. |
#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control. |
#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control. |
#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control. |
#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control. |
#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control. |
#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control. |
#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control. |
#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control. |
#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control. |
#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SRCR2 register. |
// |
//***************************************************************************** |
#define SYSCTL_SRCR2_EPHY0 0x40000000 // PHY0 Reset Control. |
#define SYSCTL_SRCR2_EMAC0 0x10000000 // MAC0 Reset Control. |
#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control. |
#define SYSCTL_SRCR2_UDMA 0x00002000 // UDMA Reset Control. |
#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control. |
#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control. |
#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control. |
#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control. |
#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control. |
#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control. |
#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control. |
#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RIS register. |
// |
//***************************************************************************** |
#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt |
// Status. |
#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt |
// Status. |
#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status. |
#define SYSCTL_RIS_CLRIS 0x00000020 // Current Limit Raw Interrupt |
// Status. |
#define SYSCTL_RIS_IOFRIS 0x00000010 // Internal Oscillator Fault Raw |
// Interrupt Status. |
#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Fault Raw |
// Interrupt Status. |
#define SYSCTL_RIS_LDORIS 0x00000004 // LDO Power Unregulated Raw |
// Interrupt Status. |
#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt |
// Status. |
#define SYSCTL_RIS_PLLFRIS 0x00000001 // PLL Fault Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_IMC register. |
// |
//***************************************************************************** |
#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask. |
#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask. |
#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask. |
#define SYSCTL_IMC_CLIM 0x00000020 // Current Limit Interrupt Mask. |
#define SYSCTL_IMC_IOFIM 0x00000010 // Internal Oscillator Fault |
// Interrupt Mask. |
#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Fault Interrupt |
// Mask. |
#define SYSCTL_IMC_LDOIM 0x00000004 // LDO Power Unregulated Interrupt |
// Mask. |
#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask. |
#define SYSCTL_IMC_PLLFIM 0x00000001 // PLL Fault Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_MISC register. |
// |
//***************************************************************************** |
#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt |
// Status. |
#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt |
// Status. |
#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt |
// Status. |
#define SYSCTL_MISC_CLMIS 0x00000020 // Current Limit Masked Interrupt |
// Status. |
#define SYSCTL_MISC_IOFMIS 0x00000010 // Internal Oscillator Fault Masked |
// Interrupt Status. |
#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Fault Masked |
// Interrupt Status. |
#define SYSCTL_MISC_LDOMIS 0x00000004 // LDO Power Unregulated Masked |
// Interrupt Status. |
#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RCGC0 register. |
// |
//***************************************************************************** |
#define SYSCTL_RCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. |
#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. |
#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. |
#define SYSCTL_RCGC0_PWM 0x00100000 // PWM Clock Gating Control. |
#define SYSCTL_RCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. |
#define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. |
#define SYSCTL_RCGC0_ADCSPD125K 0x00000000 // 125K samples/second |
#define SYSCTL_RCGC0_ADCSPD250K 0x00000100 // 250K samples/second |
#define SYSCTL_RCGC0_ADCSPD500K 0x00000200 // 500K samples/second |
#define SYSCTL_RCGC0_ADCSPD1M 0x00000300 // 1M samples/second |
#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control. |
#define SYSCTL_RCGC0_WDT 0x00000008 // WDT Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RCGC1 register. |
// |
//***************************************************************************** |
#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock |
// Gating. |
#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock |
// Gating. |
#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock |
// Gating. |
#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. |
#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. |
#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. |
#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. |
#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. |
#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. |
#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. |
#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. |
#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. |
#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. |
#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control. |
#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control. |
#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_RCGC2 register. |
// |
//***************************************************************************** |
#define SYSCTL_RCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. |
#define SYSCTL_RCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. |
#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control. |
#define SYSCTL_RCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. |
#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SCGC0 register. |
// |
//***************************************************************************** |
#define SYSCTL_SCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. |
#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. |
#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. |
#define SYSCTL_SCGC0_PWM 0x00100000 // PWM Clock Gating Control. |
#define SYSCTL_SCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. |
#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. |
#define SYSCTL_SCGC0_ADCSPD125K 0x00000000 // 125K samples/second |
#define SYSCTL_SCGC0_ADCSPD250K 0x00000100 // 250K samples/second |
#define SYSCTL_SCGC0_ADCSPD500K 0x00000200 // 500K samples/second |
#define SYSCTL_SCGC0_ADCSPD1M 0x00000300 // 1M samples/second |
#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control. |
#define SYSCTL_SCGC0_WDT 0x00000008 // WDT Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SCGC1 register. |
// |
//***************************************************************************** |
#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock |
// Gating. |
#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock |
// Gating. |
#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock |
// Gating. |
#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. |
#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. |
#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. |
#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. |
#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. |
#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. |
#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. |
#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. |
#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. |
#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. |
#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control. |
#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control. |
#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_SCGC2 register. |
// |
//***************************************************************************** |
#define SYSCTL_SCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. |
#define SYSCTL_SCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. |
#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control. |
#define SYSCTL_SCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. |
#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DCGC0 register. |
// |
//***************************************************************************** |
#define SYSCTL_DCGC0_CAN2 0x04000000 // CAN2 Clock Gating Control. |
#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control. |
#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control. |
#define SYSCTL_DCGC0_PWM 0x00100000 // PWM Clock Gating Control. |
#define SYSCTL_DCGC0_ADC 0x00010000 // ADC0 Clock Gating Control. |
#define SYSCTL_DCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed. |
#define SYSCTL_DCGC0_ADCSPD125K 0x00000000 // 125K samples/second |
#define SYSCTL_DCGC0_ADCSPD250K 0x00000100 // 250K samples/second |
#define SYSCTL_DCGC0_ADCSPD500K 0x00000200 // 500K samples/second |
#define SYSCTL_DCGC0_ADCSPD1M 0x00000300 // 1M samples/second |
#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control. |
#define SYSCTL_DCGC0_WDT 0x00000008 // WDT Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DCGC1 register. |
// |
//***************************************************************************** |
#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock |
// Gating. |
#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock |
// Gating. |
#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock |
// Gating. |
#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control. |
#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control. |
#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control. |
#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control. |
#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control. |
#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control. |
#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control. |
#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control. |
#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control. |
#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control. |
#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control. |
#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control. |
#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DCGC2 register. |
// |
//***************************************************************************** |
#define SYSCTL_DCGC2_EPHY0 0x40000000 // PHY0 Clock Gating Control. |
#define SYSCTL_DCGC2_EMAC0 0x10000000 // MAC0 Clock Gating Control. |
#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control. |
#define SYSCTL_DCGC2_UDMA 0x00002000 // UDMA Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control. |
#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC5 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present. |
#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present. |
#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present. |
#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present. |
#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault feature is |
// active. |
#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC feature is |
// active. |
#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present. |
#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present. |
#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present. |
#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present. |
#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present. |
#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present. |
#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present. |
#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC6 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC6_USB0_M 0x00000003 // This specifies that USB0 is |
// present and its capability. |
#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is DEVICE or HOST |
#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB is OTG |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_GPIOHSCTL |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_GPIOHSCTL_PORTH 0x00000080 // Port H High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTG 0x00000040 // Port G High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTF 0x00000020 // Port F High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTE 0x00000010 // Port E High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTD 0x00000008 // Port D High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTC 0x00000004 // Port C High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTB 0x00000002 // Port B High-Speed. |
#define SYSCTL_GPIOHSCTL_PORTA 0x00000001 // Port A High-Speed. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_MOSCCTL register. |
// |
//***************************************************************************** |
#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SYSCTL_DC7 register. |
// |
//***************************************************************************** |
#define SYSCTL_DC7_SSI1_TX 0x02000000 // SSI1 TX on uDMA Ch25. |
#define SYSCTL_DC7_SSI1_RX 0x01000000 // SSI1 RX on uDMA Ch24. |
#define SYSCTL_DC7_UART1_TX 0x00800000 // UART1 TX on uDMA Ch23. |
#define SYSCTL_DC7_UART1_RX 0x00400000 // UART1 RX on uDMA Ch22. |
#define SYSCTL_DC7_SSI0_TX 0x00000800 // SSI0 TX on uDMA Ch11. |
#define SYSCTL_DC7_SSI0_RX 0x00000400 // SSI0 RX on uDMA Ch10. |
#define SYSCTL_DC7_UART0_TX 0x00000200 // UART0 TX on uDMA Ch9. |
#define SYSCTL_DC7_UART0_RX 0x00000100 // UART0 RX on uDMA Ch8. |
#define SYSCTL_DC7_USB_EP3_TX 0x00000020 // USB EP3 TX on uDMA Ch5. |
#define SYSCTL_DC7_USB_EP3_RX 0x00000010 // USB EP3 RX on uDMA Ch4. |
#define SYSCTL_DC7_USB_EP2_TX 0x00000008 // USB EP2 TX on uDMA Ch3. |
#define SYSCTL_DC7_USB_EP2_RX 0x00000004 // USB EP2 RX on uDMA Ch2. |
#define SYSCTL_DC7_USB_EP1_TX 0x00000002 // USB EP1 TX on uDMA Ch1. |
#define SYSCTL_DC7_USB_EP1_RX 0x00000001 // USB EP1 RX on uDMA Ch0. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the system control register |
// addresses. |
// |
//***************************************************************************** |
#define SYSCTL_USER0 0x400FE1E0 // NV User Register 0 |
#define SYSCTL_USER1 0x400FE1E4 // NV User Register 1 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DID0 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DID0_VER_MASK 0x70000000 // DID0 version mask |
#define SYSCTL_DID0_CLASS_MASK 0x00FF0000 // Device Class |
#define SYSCTL_DID0_MAJ_MASK 0x0000FF00 // Major revision mask |
#define SYSCTL_DID0_MAJ_A 0x00000000 // Major revision A |
#define SYSCTL_DID0_MAJ_B 0x00000100 // Major revision B |
#define SYSCTL_DID0_MAJ_C 0x00000200 // Major revision C |
#define SYSCTL_DID0_MIN_MASK 0x000000FF // Minor revision mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DID1 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DID1_VER_MASK 0xF0000000 // Register version mask |
#define SYSCTL_DID1_FAM_MASK 0x0F000000 // Family mask |
#define SYSCTL_DID1_FAM_S 0x00000000 // Stellaris family |
#define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 // Part number mask |
#define SYSCTL_DID1_PINCNT_MASK 0x0000E000 // Pin count |
#define SYSCTL_DID1_TEMP_MASK 0x000000E0 // Temperature range mask |
#define SYSCTL_DID1_PKG_MASK 0x00000018 // Package mask |
#define SYSCTL_DID1_QUAL_MASK 0x00000003 // Qualification status mask |
#define SYSCTL_DID1_PRTNO_SHIFT 16 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DC0 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 // SRAM size mask |
#define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF // Flash size mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DC1 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 // Minimum system divider mask |
#define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 // ADC speed mask |
#define SYSCTL_DC1_WDOG 0x00000008 // Watchdog present |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DC2 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DC2_I2C 0x00001000 // I2C present |
#define SYSCTL_DC2_QEI 0x00000100 // QEI present |
#define SYSCTL_DC2_SSI 0x00000010 // SSI present |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_DC3 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_DC3_MC_FAULT0 0x00008000 // MC0 fault pin present |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// SYSCTL_PBORCTL register. |
// |
//***************************************************************************** |
#define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC // BOR wait timer |
#define SYSCTL_PBORCTL_BOR_SH 2 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// SYSCTL_LDOPCTL register. |
// |
//***************************************************************************** |
#define SYSCTL_LDOPCTL_MASK 0x0000003F // Voltage adjust mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR0, |
// SYSCTL_RCGC0, SYSCTL_SCGC0, and SYSCTL_DCGC0 registers. |
// |
//***************************************************************************** |
#define SYSCTL_SET0_CAN2 0x04000000 // CAN 2 module |
#define SYSCTL_SET0_CAN1 0x02000000 // CAN 1 module |
#define SYSCTL_SET0_CAN0 0x01000000 // CAN 0 module |
#define SYSCTL_SET0_PWM 0x00100000 // PWM module |
#define SYSCTL_SET0_ADC 0x00010000 // ADC module |
#define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 // ADC speed mask |
#define SYSCTL_SET0_ADCSPD_125K 0x00000000 // 125Ksps ADC |
#define SYSCTL_SET0_ADCSPD_250K 0x00000100 // 250Ksps ADC |
#define SYSCTL_SET0_ADCSPD_500K 0x00000200 // 500Ksps ADC |
#define SYSCTL_SET0_ADCSPD_1M 0x00000300 // 1Msps ADC |
#define SYSCTL_SET0_HIB 0x00000040 // Hibernation module |
#define SYSCTL_SET0_WDOG 0x00000008 // Watchdog module |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR1, |
// SYSCTL_RCGC1, SYSCTL_SCGC1, and SYSCTL_DCGC1 registers. |
// |
//***************************************************************************** |
#define SYSCTL_SET1_COMP2 0x04000000 // Analog comparator module 2 |
#define SYSCTL_SET1_COMP1 0x02000000 // Analog comparator module 1 |
#define SYSCTL_SET1_COMP0 0x01000000 // Analog comparator module 0 |
#define SYSCTL_SET1_TIMER3 0x00080000 // Timer module 3 |
#define SYSCTL_SET1_TIMER2 0x00040000 // Timer module 2 |
#define SYSCTL_SET1_TIMER1 0x00020000 // Timer module 1 |
#define SYSCTL_SET1_TIMER0 0x00010000 // Timer module 0 |
#define SYSCTL_SET1_I2C1 0x00002000 // I2C module 1 |
#define SYSCTL_SET1_I2C0 0x00001000 // I2C module 0 |
#define SYSCTL_SET1_I2C 0x00001000 // I2C module |
#define SYSCTL_SET1_QEI1 0x00000200 // QEI module 1 |
#define SYSCTL_SET1_QEI 0x00000100 // QEI module |
#define SYSCTL_SET1_QEI0 0x00000100 // QEI module 0 |
#define SYSCTL_SET1_SSI1 0x00000020 // SSI module 1 |
#define SYSCTL_SET1_SSI0 0x00000010 // SSI module 0 |
#define SYSCTL_SET1_SSI 0x00000010 // SSI module |
#define SYSCTL_SET1_UART2 0x00000004 // UART module 2 |
#define SYSCTL_SET1_UART1 0x00000002 // UART module 1 |
#define SYSCTL_SET1_UART0 0x00000001 // UART module 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_SRCR2, |
// SYSCTL_RCGC2, SYSCTL_SCGC2, and SYSCTL_DCGC2 registers. |
// |
//***************************************************************************** |
#define SYSCTL_SET2_ETH 0x50000000 // ETH module |
#define SYSCTL_SET2_GPIOH 0x00000080 // GPIO H module |
#define SYSCTL_SET2_GPIOG 0x00000040 // GPIO G module |
#define SYSCTL_SET2_GPIOF 0x00000020 // GPIO F module |
#define SYSCTL_SET2_GPIOE 0x00000010 // GPIO E module |
#define SYSCTL_SET2_GPIOD 0x00000008 // GPIO D module |
#define SYSCTL_SET2_GPIOC 0x00000004 // GPIO C module |
#define SYSCTL_SET2_GPIOB 0x00000002 // GPIO B module |
#define SYSCTL_SET2_GPIOA 0x00000001 // GIPO A module |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_RIS, |
// SYSCTL_IMC, and SYSCTL_IMS registers. |
// |
//***************************************************************************** |
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt |
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt |
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int |
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int |
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt |
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt |
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_RESC |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_RESC_WDOG 0x00000008 // Watchdog reset |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_RCC |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_RCC_SYSDIV_MASK 0x07800000 // System clock divider |
#define SYSCTL_RCC_USE_SYSDIV 0x00400000 // Use sytem clock divider |
#define SYSCTL_RCC_USE_PWMDIV 0x00100000 // Use PWM clock divider |
#define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 // PWM clock divider |
#define SYSCTL_RCC_OE 0x00001000 // PLL output enable |
#define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 // Using a 3.6864 MHz crystal |
#define SYSCTL_RCC_XTAL_4MHz 0x00000180 // Using a 4 MHz crystal |
#define SYSCTL_RCC_XTAL_MASK 0x000003C0 // Crystal attached to main osc |
#define SYSCTL_RCC_OSCSRC_MASK 0x00000030 // Oscillator input select |
#define SYSCTL_RCC_SYSDIV_SHIFT 23 // Shift to the SYSDIV field |
#define SYSCTL_RCC_PWMDIV_SHIFT 17 // Shift to the PWMDIV field |
#define SYSCTL_RCC_XTAL_SHIFT 6 // Shift to the XTAL field |
#define SYSCTL_RCC_OSCSRC_SHIFT 4 // Shift to the OSCSRC field |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_PLLCFG |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_PLLCFG_OD_MASK 0x0000C000 // Output divider |
#define SYSCTL_PLLCFG_F_MASK 0x00003FE0 // PLL multiplier |
#define SYSCTL_PLLCFG_R_MASK 0x0000001F // Input predivider |
#define SYSCTL_PLLCFG_F_SHIFT 5 |
#define SYSCTL_PLLCFG_R_SHIFT 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SYSCTL_RCC2 |
// register. |
// |
//***************************************************************************** |
#define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 // System clock divider |
#define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 // Oscillator input select |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// SYSCTL_DSLPCLKCFG register. |
// |
//***************************************************************************** |
#define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 // Deep sleep system clock override |
#define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 // Deep sleep oscillator override |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// SYSCTL_CLKVCLR register. |
// |
//***************************************************************************** |
#define SYSCTL_CLKVCLR_CLR 0x00000001 // Clear clock verification fault |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the |
// SYSCTL_LDOARST register. |
// |
//***************************************************************************** |
#define SYSCTL_LDOARST_ARST 0x00000001 // Allow LDO to reset device |
|
#endif |
|
#endif // __HW_SYSCTL_H__ |
/drivers/LuminaryMicro/lmi_timer.h
0,0 → 1,137
//***************************************************************************** |
// |
// timer.h - Prototypes for the timer module |
// |
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. Any use in violation |
// of the foregoing restrictions may subject the user to criminal sanctions |
// under applicable laws, as well as to civil liability for the breach of the |
// terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 1582 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __TIMER_H__ |
#define __TIMER_H__ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerConfigure as the ulConfig parameter. |
// |
//***************************************************************************** |
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer |
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer |
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer |
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers |
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer |
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer |
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter |
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer |
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output |
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer |
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer |
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter |
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer |
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerIntEnable, TimerIntDisable, and |
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. |
// |
//***************************************************************************** |
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt |
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt |
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt |
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask |
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt |
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt |
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerControlEvent as the ulEvent parameter. |
// |
//***************************************************************************** |
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges |
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges |
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges |
|
//***************************************************************************** |
// |
// Values that can be passed to most of the timer APIs as the ulTimer |
// parameter. |
// |
//***************************************************************************** |
#define TIMER_A 0x000000ff // Timer A |
#define TIMER_B 0x0000ff00 // Timer B |
#define TIMER_BOTH 0x0000ffff // Timer Both |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); |
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bInvert); |
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bEnable); |
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulEvent); |
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bStall); |
extern void TimerRTCEnable(unsigned long ulBase); |
extern void TimerRTCDisable(unsigned long ulBase); |
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerPrescaleGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerPrescaleMatchSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerPrescaleMatchGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); |
extern unsigned long TimerValueGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerMatchGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, |
void (*pfnHandler)(void)); |
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
extern void TimerQuiesce(unsigned long ulBase); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif // __TIMER_H__ |
/drivers/LuminaryMicro/hw_udma.h
0,0 → 1,312
//***************************************************************************** |
// |
// hw_udma.h - Macros for use in accessing the UDMA registers. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_UDMA_H__ |
#define __HW_UDMA_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the Micro Direct Memory Access (uDMA) offsets. |
// |
//***************************************************************************** |
#define UDMA_STAT 0x400FF000 // DMA Status |
#define UDMA_CFG 0x400FF004 // DMA Configuration |
#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer |
#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control |
// Base Pointer |
#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait on Request |
// Status |
#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request |
#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set |
#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear |
#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set |
#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear |
#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set |
#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear |
#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate |
// Set |
#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate |
// Clear |
#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set |
#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear |
#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear |
|
//***************************************************************************** |
// |
// Micro Direct Memory Access (uDMA) offsets. |
// |
//***************************************************************************** |
#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End |
// Pointer |
#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address |
// End Pointer |
#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_O_SRCENDP register. |
// |
//***************************************************************************** |
#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer. |
#define UDMA_SRCENDP_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_STAT register. |
// |
//***************************************************************************** |
#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available DMA Channels Minus 1. |
#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine State. |
#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle |
#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data |
#define UDMA_STAT_STATE_RD_SRCENDP \ |
0x00000020 // Reading source end pointer |
#define UDMA_STAT_STATE_RD_DSTENDP \ |
0x00000030 // Reading destination end pointer |
#define UDMA_STAT_STATE_RD_SRCDAT \ |
0x00000040 // Reading source data |
#define UDMA_STAT_STATE_WR_DSTDAT \ |
0x00000050 // Writing destination data |
#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for DMA request to clear |
#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data |
#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled |
#define UDMA_STAT_STATE_DONE 0x00000090 // Done |
#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined |
#define UDMA_STAT_MASTEN 0x00000001 // Master Enable. |
#define UDMA_STAT_DMACHANS_S 16 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_O_DSTENDP register. |
// |
//***************************************************************************** |
#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer. |
#define UDMA_DSTENDP_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_CFG register. |
// |
//***************************************************************************** |
#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_CTLBASE register. |
// |
//***************************************************************************** |
#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address. |
#define UDMA_CTLBASE_ADDR_S 10 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_O_CHCTL register. |
// |
//***************************************************************************** |
#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment. |
#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte |
#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word |
#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word |
#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment |
#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size. |
#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte |
#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word |
#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word |
#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment. |
#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte |
#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word |
#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word |
#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment |
#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size. |
#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte |
#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word |
#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word |
#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size. |
#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer |
#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers |
#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers |
#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers |
#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers |
#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers |
#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers |
#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers |
#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers |
#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers |
#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers |
#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1). |
#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst. |
#define UDMA_CHCTL_XFERMODE_M 0x00000007 // DMA Transfer Mode. |
#define UDMA_CHCTL_XFERMODE_STOP \ |
0x00000000 // Stop |
#define UDMA_CHCTL_XFERMODE_BASIC \ |
0x00000001 // Basic |
#define UDMA_CHCTL_XFERMODE_AUTO \ |
0x00000002 // Auto-Request |
#define UDMA_CHCTL_XFERMODE_PINGPONG \ |
0x00000003 // Ping-Pong |
#define UDMA_CHCTL_XFERMODE_MEM_SG \ |
0x00000004 // Memory Scatter-Gather |
#define UDMA_CHCTL_XFERMODE_MEM_SGA \ |
0x00000005 // Alternate Memory Scatter-Gather |
#define UDMA_CHCTL_XFERMODE_PER_SG \ |
0x00000006 // Peripheral Scatter-Gather |
#define UDMA_CHCTL_XFERMODE_PER_SGA \ |
0x00000007 // Alternate Peripheral |
// Scatter-Gather |
#define UDMA_CHCTL_XFERSIZE_S 4 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ALTBASE register. |
// |
//***************************************************************************** |
#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address |
// Pointer. |
#define UDMA_ALTBASE_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_WAITSTAT register. |
// |
//***************************************************************************** |
#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status. |
#define UDMA_WAITSTAT_WAITREQ_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_SWREQ register. |
// |
//***************************************************************************** |
#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request. |
#define UDMA_SWREQ_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_USEBURSTSET |
// register. |
// |
//***************************************************************************** |
#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set. |
#define UDMA_USEBURSTSET_SET__0 0x00000000 // No Effect |
#define UDMA_USEBURSTSET_SET__1 0x00000001 // Burst Only |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_USEBURSTCLR |
// register. |
// |
//***************************************************************************** |
#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear. |
#define UDMA_USEBURSTCLR_CLR__0 0x00000000 // No Effect |
#define UDMA_USEBURSTCLR_CLR__1 0x00000001 // Single and Burst |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_REQMASKSET |
// register. |
// |
//***************************************************************************** |
#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set. |
#define UDMA_REQMASKSET_SET__0 0x00000000 // No Effect |
#define UDMA_REQMASKSET_SET__1 0x00000001 // Masked |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_REQMASKCLR |
// register. |
// |
//***************************************************************************** |
#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear. |
#define UDMA_REQMASKCLR_CLR__0 0x00000000 // No Effect |
#define UDMA_REQMASKCLR_CLR__1 0x00000001 // Clear Mask |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ENASET register. |
// |
//***************************************************************************** |
#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set. |
#define UDMA_ENASET_SET__0 0x00000000 // Disabled |
#define UDMA_ENASET_SET__1 0x00000001 // Enabled |
#define UDMA_ENASET_CHENSET_M 0xFFFFFFFF // Channel [n] Enable Set. |
#define UDMA_ENASET_CHENSET__0 0x00000000 // No Effect |
#define UDMA_ENASET_CHENSET__1 0x00000001 // Enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ENACLR register. |
// |
//***************************************************************************** |
#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable. |
#define UDMA_ENACLR_CLR__0 0x00000000 // No Effect |
#define UDMA_ENACLR_CLR__1 0x00000001 // Disable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ALTSET register. |
// |
//***************************************************************************** |
#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set. |
#define UDMA_ALTSET_SET__0 0x00000000 // No Effect |
#define UDMA_ALTSET_SET__1 0x00000001 // Alternate |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ALTCLR register. |
// |
//***************************************************************************** |
#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear. |
#define UDMA_ALTCLR_CLR__0 0x00000000 // No Effect |
#define UDMA_ALTCLR_CLR__1 0x00000001 // Primary |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_PRIOSET register. |
// |
//***************************************************************************** |
#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set. |
#define UDMA_PRIOSET_SET__0 0x00000000 // No Effect |
#define UDMA_PRIOSET_SET__1 0x00000001 // High Priority |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_PRIOCLR register. |
// |
//***************************************************************************** |
#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear. |
#define UDMA_PRIOCLR_CLR__0 0x00000000 // No Effect |
#define UDMA_PRIOCLR_CLR__1 0x00000001 // Default Priority |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the UDMA_ERRCLR register. |
// |
//***************************************************************************** |
#define UDMA_ERRCLR_ERRCLR 0x00000001 // DMA Bus Error Status. |
|
#endif // __HW_UDMA_H__ |
/drivers/LuminaryMicro/hw_adc.h
0,0 → 1,614
//***************************************************************************** |
// |
// hw_adc.h - Macros used when accessing the ADC hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_ADC_H__ |
#define __HW_ADC_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the ADC register offsets. |
// |
//***************************************************************************** |
#define ADC_O_ACTSS 0x00000000 // Active sample register |
#define ADC_O_RIS 0x00000004 // Raw interrupt status register |
#define ADC_O_IM 0x00000008 // Interrupt mask register |
#define ADC_O_ISC 0x0000000C // Interrupt status/clear register |
#define ADC_O_OSTAT 0x00000010 // Overflow status register |
#define ADC_O_EMUX 0x00000014 // Event multiplexer select reg. |
#define ADC_O_USTAT 0x00000018 // Underflow status register |
#define ADC_O_SSPRI 0x00000020 // Channel priority register |
#define ADC_O_PSSI 0x00000028 // Processor sample initiate reg. |
#define ADC_O_SAC 0x00000030 // Sample Averaging Control reg. |
#define ADC_O_SSMUX0 0x00000040 // Multiplexer select 0 register |
#define ADC_O_SSCTL0 0x00000044 // Sample sequence control 0 reg. |
#define ADC_O_SSFIFO0 0x00000048 // Result FIFO 0 register |
#define ADC_O_SSFSTAT0 0x0000004C // FIFO 0 status register |
#define ADC_O_SSMUX1 0x00000060 // Multiplexer select 1 register |
#define ADC_O_SSCTL1 0x00000064 // Sample sequence control 1 reg. |
#define ADC_O_SSFIFO1 0x00000068 // Result FIFO 1 register |
#define ADC_O_SSFSTAT1 0x0000006C // FIFO 1 status register |
#define ADC_O_SSMUX2 0x00000080 // Multiplexer select 2 register |
#define ADC_O_SSCTL2 0x00000084 // Sample sequence control 2 reg. |
#define ADC_O_SSFIFO2 0x00000088 // Result FIFO 2 register |
#define ADC_O_SSFSTAT2 0x0000008C // FIFO 2 status register |
#define ADC_O_SSMUX3 0x000000A0 // Multiplexer select 3 register |
#define ADC_O_SSCTL3 0x000000A4 // Sample sequence control 3 reg. |
#define ADC_O_SSFIFO3 0x000000A8 // Result FIFO 3 register |
#define ADC_O_SSFSTAT3 0x000000AC // FIFO 3 status register |
#define ADC_O_TMLB 0x00000100 // Test mode loopback register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_ACTSS register. |
// |
//***************************************************************************** |
#define ADC_ACTSS_ASEN3 0x00000008 // Sample sequence 3 enable |
#define ADC_ACTSS_ASEN2 0x00000004 // Sample sequence 2 enable |
#define ADC_ACTSS_ASEN1 0x00000002 // Sample sequence 1 enable |
#define ADC_ACTSS_ASEN0 0x00000001 // Sample sequence 0 enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_RIS register. |
// |
//***************************************************************************** |
#define ADC_RIS_INR3 0x00000008 // Sample sequence 3 interrupt |
#define ADC_RIS_INR2 0x00000004 // Sample sequence 2 interrupt |
#define ADC_RIS_INR1 0x00000002 // Sample sequence 1 interrupt |
#define ADC_RIS_INR0 0x00000001 // Sample sequence 0 interrupt |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_IM register. |
// |
//***************************************************************************** |
#define ADC_IM_MASK3 0x00000008 // Sample sequence 3 mask |
#define ADC_IM_MASK2 0x00000004 // Sample sequence 2 mask |
#define ADC_IM_MASK1 0x00000002 // Sample sequence 1 mask |
#define ADC_IM_MASK0 0x00000001 // Sample sequence 0 mask |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_ISC register. |
// |
//***************************************************************************** |
#define ADC_ISC_IN3 0x00000008 // Sample sequence 3 interrupt |
#define ADC_ISC_IN2 0x00000004 // Sample sequence 2 interrupt |
#define ADC_ISC_IN1 0x00000002 // Sample sequence 1 interrupt |
#define ADC_ISC_IN0 0x00000001 // Sample sequence 0 interrupt |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_OSTAT register. |
// |
//***************************************************************************** |
#define ADC_OSTAT_OV3 0x00000008 // Sample sequence 3 overflow |
#define ADC_OSTAT_OV2 0x00000004 // Sample sequence 2 overflow |
#define ADC_OSTAT_OV1 0x00000002 // Sample sequence 1 overflow |
#define ADC_OSTAT_OV0 0x00000001 // Sample sequence 0 overflow |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_EMUX register. |
// |
//***************************************************************************** |
#define ADC_EMUX_EM3_M 0x0000F000 // Event mux 3 mask |
#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor event |
#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog comparator 0 event |
#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog comparator 1 event |
#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog comparator 2 event |
#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External event |
#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer event |
#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM0 event |
#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM1 event |
#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM2 event |
#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always event |
#define ADC_EMUX_EM2_M 0x00000F00 // Event mux 2 mask |
#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor event |
#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog comparator 0 event |
#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog comparator 1 event |
#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog comparator 2 event |
#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External event |
#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer event |
#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM0 event |
#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM1 event |
#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM2 event |
#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always event |
#define ADC_EMUX_EM1_M 0x000000F0 // Event mux 1 mask |
#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor event |
#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog comparator 0 event |
#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog comparator 1 event |
#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog comparator 2 event |
#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External event |
#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer event |
#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM0 event |
#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM1 event |
#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM2 event |
#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always event |
#define ADC_EMUX_EM0_M 0x0000000F // Event mux 0 mask |
#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor event |
#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog comparator 0 event |
#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog comparator 1 event |
#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog comparator 2 event |
#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External event |
#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer event |
#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM0 event |
#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM1 event |
#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM2 event |
#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always event |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_USTAT register. |
// |
//***************************************************************************** |
#define ADC_USTAT_UV3 0x00000008 // Sample sequence 3 underflow |
#define ADC_USTAT_UV2 0x00000004 // Sample sequence 2 underflow |
#define ADC_USTAT_UV1 0x00000002 // Sample sequence 1 underflow |
#define ADC_USTAT_UV0 0x00000001 // Sample sequence 0 underflow |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_SSPRI register. |
// |
//***************************************************************************** |
#define ADC_SSPRI_SS3_M 0x00003000 // Sequencer 3 priority mask |
#define ADC_SSPRI_SS3_1ST 0x00000000 // First priority |
#define ADC_SSPRI_SS3_2ND 0x00001000 // Second priority |
#define ADC_SSPRI_SS3_3RD 0x00002000 // Third priority |
#define ADC_SSPRI_SS3_4TH 0x00003000 // Fourth priority |
#define ADC_SSPRI_SS2_M 0x00000300 // Sequencer 2 priority mask |
#define ADC_SSPRI_SS2_1ST 0x00000000 // First priority |
#define ADC_SSPRI_SS2_2ND 0x00000100 // Second priority |
#define ADC_SSPRI_SS2_3RD 0x00000200 // Third priority |
#define ADC_SSPRI_SS2_4TH 0x00000300 // Fourth priority |
#define ADC_SSPRI_SS1_M 0x00000030 // Sequencer 1 priority mask |
#define ADC_SSPRI_SS1_1ST 0x00000000 // First priority |
#define ADC_SSPRI_SS1_2ND 0x00000010 // Second priority |
#define ADC_SSPRI_SS1_3RD 0x00000020 // Third priority |
#define ADC_SSPRI_SS1_4TH 0x00000030 // Fourth priority |
#define ADC_SSPRI_SS0_M 0x00000003 // Sequencer 0 priority mask |
#define ADC_SSPRI_SS0_1ST 0x00000000 // First priority |
#define ADC_SSPRI_SS0_2ND 0x00000001 // Second priority |
#define ADC_SSPRI_SS0_3RD 0x00000002 // Third priority |
#define ADC_SSPRI_SS0_4TH 0x00000003 // Fourth priority |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_PSSI register. |
// |
//***************************************************************************** |
#define ADC_PSSI_SS3 0x00000008 // Trigger sample sequencer 3 |
#define ADC_PSSI_SS2 0x00000004 // Trigger sample sequencer 2 |
#define ADC_PSSI_SS1 0x00000002 // Trigger sample sequencer 1 |
#define ADC_PSSI_SS0 0x00000001 // Trigger sample sequencer 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_SAC register. |
// |
//***************************************************************************** |
#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control. |
#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling |
#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling |
#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling |
#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling |
#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling |
#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling |
#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_TMLB register. |
// |
//***************************************************************************** |
#define ADC_TMLB_CNT_M 0x000003C0 // Continuous Sample Counter. |
#define ADC_TMLB_CONT 0x00000020 // Continuation Sample Indicator. |
#define ADC_TMLB_DIFF 0x00000010 // Differential Sample Indicator. |
#define ADC_TMLB_TS 0x00000008 // Temp Sensor Sample Indicator. |
#define ADC_TMLB_MUX_M 0x00000007 // Analog Input Indicator. |
#define ADC_TMLB_LB 0x00000001 // Loopback control signals |
#define ADC_TMLB_CNT_S 6 // Sample counter shift |
#define ADC_TMLB_MUX_S 0 // Input channel number shift |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSMUX0 register. |
// |
//***************************************************************************** |
#define ADC_SSMUX0_MUX7_M 0x70000000 // 8th Sample Input Select. |
#define ADC_SSMUX0_MUX6_M 0x07000000 // 7th Sample Input Select. |
#define ADC_SSMUX0_MUX5_M 0x00700000 // 6th Sample Input Select. |
#define ADC_SSMUX0_MUX4_M 0x00070000 // 5th Sample Input Select. |
#define ADC_SSMUX0_MUX3_M 0x00007000 // 4th Sample Input Select. |
#define ADC_SSMUX0_MUX2_M 0x00000700 // 3rd Sample Input Select. |
#define ADC_SSMUX0_MUX1_M 0x00000070 // 2nd Sample Input Select. |
#define ADC_SSMUX0_MUX0_M 0x00000007 // 1st Sample Input Select. |
#define ADC_SSMUX0_MUX7_S 28 |
#define ADC_SSMUX0_MUX6_S 24 |
#define ADC_SSMUX0_MUX5_S 20 |
#define ADC_SSMUX0_MUX4_S 16 |
#define ADC_SSMUX0_MUX3_S 12 |
#define ADC_SSMUX0_MUX2_S 8 |
#define ADC_SSMUX0_MUX1_S 4 |
#define ADC_SSMUX0_MUX0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSCTL0 register. |
// |
//***************************************************************************** |
#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable. |
#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence. |
#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Diff Input Select. |
#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable. |
#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence. |
#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Diff Input Select. |
#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable. |
#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence. |
#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Diff Input Select. |
#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable. |
#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence. |
#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Diff Input Select. |
#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable. |
#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence. |
#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Diff Input Select. |
#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable. |
#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence. |
#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Diff Input Select. |
#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable. |
#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence. |
#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Diff Input Select. |
#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select. |
#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable. |
#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence. |
#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Diff Input Select. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFIFO0 register. |
// |
//***************************************************************************** |
#define ADC_SSFIFO0_DATA_M 0x000003FF // Conversion Result Data. |
#define ADC_SSFIFO0_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register. |
// |
//***************************************************************************** |
#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full. |
#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty. |
#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer. |
#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer. |
#define ADC_SSFSTAT0_HPTR_S 4 |
#define ADC_SSFSTAT0_TPTR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSMUX1 register. |
// |
//***************************************************************************** |
#define ADC_SSMUX1_MUX3_M 0x00007000 // 4th Sample Input Select. |
#define ADC_SSMUX1_MUX2_M 0x00000700 // 3rd Sample Input Select. |
#define ADC_SSMUX1_MUX1_M 0x00000070 // 2nd Sample Input Select. |
#define ADC_SSMUX1_MUX0_M 0x00000007 // 1st Sample Input Select. |
#define ADC_SSMUX1_MUX3_S 12 |
#define ADC_SSMUX1_MUX2_S 8 |
#define ADC_SSMUX1_MUX1_S 4 |
#define ADC_SSMUX1_MUX0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSCTL1 register. |
// |
//***************************************************************************** |
#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select. |
#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable. |
#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence. |
#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Diff Input Select. |
#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select. |
#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable. |
#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence. |
#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Diff Input Select. |
#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select. |
#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable. |
#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence. |
#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Diff Input Select. |
#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select. |
#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable. |
#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence. |
#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Diff Input Select. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFIFO1 register. |
// |
//***************************************************************************** |
#define ADC_SSFIFO1_DATA_M 0x000003FF // Conversion Result Data. |
#define ADC_SSFIFO1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register. |
// |
//***************************************************************************** |
#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full. |
#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty. |
#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer. |
#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer. |
#define ADC_SSFSTAT1_HPTR_S 4 |
#define ADC_SSFSTAT1_TPTR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSMUX2 register. |
// |
//***************************************************************************** |
#define ADC_SSMUX2_MUX3_M 0x00007000 // 4th Sample Input Select. |
#define ADC_SSMUX2_MUX2_M 0x00000700 // 3rd Sample Input Select. |
#define ADC_SSMUX2_MUX1_M 0x00000070 // 2nd Sample Input Select. |
#define ADC_SSMUX2_MUX0_M 0x00000007 // 1st Sample Input Select. |
#define ADC_SSMUX2_MUX3_S 12 |
#define ADC_SSMUX2_MUX2_S 8 |
#define ADC_SSMUX2_MUX1_S 4 |
#define ADC_SSMUX2_MUX0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSCTL2 register. |
// |
//***************************************************************************** |
#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select. |
#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable. |
#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence. |
#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Diff Input Select. |
#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select. |
#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable. |
#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence. |
#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Diff Input Select. |
#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select. |
#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable. |
#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence. |
#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Diff Input Select. |
#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select. |
#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable. |
#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence. |
#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Diff Input Select. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFIFO2 register. |
// |
//***************************************************************************** |
#define ADC_SSFIFO2_DATA_M 0x000003FF // Conversion Result Data. |
#define ADC_SSFIFO2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register. |
// |
//***************************************************************************** |
#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full. |
#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty. |
#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer. |
#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer. |
#define ADC_SSFSTAT2_HPTR_S 4 |
#define ADC_SSFSTAT2_TPTR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSMUX3 register. |
// |
//***************************************************************************** |
#define ADC_SSMUX3_MUX0_M 0x00000007 // 1st Sample Input Select. |
#define ADC_SSMUX3_MUX0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSCTL3 register. |
// |
//***************************************************************************** |
#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select. |
#define ADC_SSCTL3_IE0 0x00000004 // 1st Sample Interrupt Enable. |
#define ADC_SSCTL3_END0 0x00000002 // 1st Sample is End of Sequence. |
#define ADC_SSCTL3_D0 0x00000001 // 1st Sample Diff Input Select. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFIFO3 register. |
// |
//***************************************************************************** |
#define ADC_SSFIFO3_DATA_M 0x000003FF // Conversion Result Data. |
#define ADC_SSFIFO3_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register. |
// |
//***************************************************************************** |
#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full. |
#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty. |
#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer. |
#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer. |
#define ADC_SSFSTAT3_HPTR_S 4 |
#define ADC_SSFSTAT3_TPTR_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the ADC sequence register offsets. |
// |
//***************************************************************************** |
#define ADC_O_SEQ 0x00000040 // Offset to the first sequence |
#define ADC_O_SEQ_STEP 0x00000020 // Increment to the next sequence |
#define ADC_O_X_SSFSTAT 0x0000000C // FIFO status register |
#define ADC_O_X_SSFIFO 0x00000008 // Result FIFO register |
#define ADC_O_X_SSCTL 0x00000004 // Sample sequence control register |
#define ADC_O_X_SSMUX 0x00000000 // Multiplexer select register |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_EMUX |
// register. |
// |
//***************************************************************************** |
#define ADC_EMUX_EM3_MASK 0x0000F000 // Event mux 3 mask |
#define ADC_EMUX_EM2_MASK 0x00000F00 // Event mux 2 mask |
#define ADC_EMUX_EM1_MASK 0x000000F0 // Event mux 1 mask |
#define ADC_EMUX_EM0_MASK 0x0000000F // Event mux 0 mask |
#define ADC_EMUX_EM3_SHIFT 12 // The shift for the fourth event |
#define ADC_EMUX_EM2_SHIFT 8 // The shift for the third event |
#define ADC_EMUX_EM1_SHIFT 4 // The shift for the second event |
#define ADC_EMUX_EM0_SHIFT 0 // The shift for the first event |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_SSPRI |
// register. |
// |
//***************************************************************************** |
#define ADC_SSPRI_SS3_MASK 0x00003000 // Sequencer 3 priority mask |
#define ADC_SSPRI_SS2_MASK 0x00000300 // Sequencer 2 priority mask |
#define ADC_SSPRI_SS1_MASK 0x00000030 // Sequencer 1 priority mask |
#define ADC_SSPRI_SS0_MASK 0x00000003 // Sequencer 0 priority mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_SSMUX0, |
// ADC_SSMUX1, ADC_SSMUX2, and ADC_SSMUX3 registers. Not all fields are present |
// in all registers. |
// |
//***************************************************************************** |
#define ADC_SSMUX_MUX7_MASK 0x70000000 // 8th mux select mask |
#define ADC_SSMUX_MUX6_MASK 0x07000000 // 7th mux select mask |
#define ADC_SSMUX_MUX5_MASK 0x00700000 // 6th mux select mask |
#define ADC_SSMUX_MUX4_MASK 0x00070000 // 5th mux select mask |
#define ADC_SSMUX_MUX3_MASK 0x00007000 // 4th mux select mask |
#define ADC_SSMUX_MUX2_MASK 0x00000700 // 3rd mux select mask |
#define ADC_SSMUX_MUX1_MASK 0x00000070 // 2nd mux select mask |
#define ADC_SSMUX_MUX0_MASK 0x00000007 // 1st mux select mask |
#define ADC_SSMUX_MUX7_SHIFT 28 |
#define ADC_SSMUX_MUX6_SHIFT 24 |
#define ADC_SSMUX_MUX5_SHIFT 20 |
#define ADC_SSMUX_MUX4_SHIFT 16 |
#define ADC_SSMUX_MUX3_SHIFT 12 |
#define ADC_SSMUX_MUX2_SHIFT 8 |
#define ADC_SSMUX_MUX1_SHIFT 4 |
#define ADC_SSMUX_MUX0_SHIFT 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_SSCTL0, |
// ADC_SSCTL1, ADC_SSCTL2, and ADC_SSCTL3 registers. Not all fields are present |
// in all registers. |
// |
//***************************************************************************** |
#define ADC_SSCTL_TS7 0x80000000 // 8th temperature sensor select |
#define ADC_SSCTL_IE7 0x40000000 // 8th interrupt enable |
#define ADC_SSCTL_END7 0x20000000 // 8th sequence end select |
#define ADC_SSCTL_D7 0x10000000 // 8th differential select |
#define ADC_SSCTL_TS6 0x08000000 // 7th temperature sensor select |
#define ADC_SSCTL_IE6 0x04000000 // 7th interrupt enable |
#define ADC_SSCTL_END6 0x02000000 // 7th sequence end select |
#define ADC_SSCTL_D6 0x01000000 // 7th differential select |
#define ADC_SSCTL_TS5 0x00800000 // 6th temperature sensor select |
#define ADC_SSCTL_IE5 0x00400000 // 6th interrupt enable |
#define ADC_SSCTL_END5 0x00200000 // 6th sequence end select |
#define ADC_SSCTL_D5 0x00100000 // 6th differential select |
#define ADC_SSCTL_TS4 0x00080000 // 5th temperature sensor select |
#define ADC_SSCTL_IE4 0x00040000 // 5th interrupt enable |
#define ADC_SSCTL_END4 0x00020000 // 5th sequence end select |
#define ADC_SSCTL_D4 0x00010000 // 5th differential select |
#define ADC_SSCTL_TS3 0x00008000 // 4th temperature sensor select |
#define ADC_SSCTL_IE3 0x00004000 // 4th interrupt enable |
#define ADC_SSCTL_END3 0x00002000 // 4th sequence end select |
#define ADC_SSCTL_D3 0x00001000 // 4th differential select |
#define ADC_SSCTL_TS2 0x00000800 // 3rd temperature sensor select |
#define ADC_SSCTL_IE2 0x00000400 // 3rd interrupt enable |
#define ADC_SSCTL_END2 0x00000200 // 3rd sequence end select |
#define ADC_SSCTL_D2 0x00000100 // 3rd differential select |
#define ADC_SSCTL_TS1 0x00000080 // 2nd temperature sensor select |
#define ADC_SSCTL_IE1 0x00000040 // 2nd interrupt enable |
#define ADC_SSCTL_END1 0x00000020 // 2nd sequence end select |
#define ADC_SSCTL_D1 0x00000010 // 2nd differential select |
#define ADC_SSCTL_TS0 0x00000008 // 1st temperature sensor select |
#define ADC_SSCTL_IE0 0x00000004 // 1st interrupt enable |
#define ADC_SSCTL_END0 0x00000002 // 1st sequence end select |
#define ADC_SSCTL_D0 0x00000001 // 1st differential select |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_SSFIFO0, |
// ADC_SSFIFO1, ADC_SSFIFO2, and ADC_SSFIFO3 registers. |
// |
//***************************************************************************** |
#define ADC_SSFIFO_DATA_MASK 0x000003FF // Sample data |
#define ADC_SSFIFO_DATA_SHIFT 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the ADC_SSFSTAT0, |
// ADC_SSFSTAT1, ADC_SSFSTAT2, and ADC_SSFSTAT3 registers. |
// |
//***************************************************************************** |
#define ADC_SSFSTAT_FULL 0x00001000 // FIFO is full |
#define ADC_SSFSTAT_EMPTY 0x00000100 // FIFO is empty |
#define ADC_SSFSTAT_HPTR 0x000000F0 // FIFO head pointer |
#define ADC_SSFSTAT_TPTR 0x0000000F // FIFO tail pointer |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the loopback ADC |
// data. |
// |
//***************************************************************************** |
#define ADC_LB_CNT_MASK 0x000003C0 // Sample counter mask |
#define ADC_LB_CONT 0x00000020 // Continuation sample |
#define ADC_LB_DIFF 0x00000010 // Differential sample |
#define ADC_LB_TS 0x00000008 // Temperature sensor sample |
#define ADC_LB_MUX_MASK 0x00000007 // Input channel number mask |
#define ADC_LB_CNT_SHIFT 6 // Sample counter shift |
#define ADC_LB_MUX_SHIFT 0 // Input channel number shift |
|
#endif |
|
#endif // __HW_ADC_H__ |
/drivers/LuminaryMicro/debug.h
0,0 → 1,57
//***************************************************************************** |
// |
// debug.h - Macros for assisting debug of the driver library. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __DEBUG_H__ |
#define __DEBUG_H__ |
|
//***************************************************************************** |
// |
// Prototype for the function that is called when an invalid argument is passed |
// to an API. This is only used when doing a DEBUG build. |
// |
//***************************************************************************** |
extern void __error__(char *pcFilename, unsigned long ulLine); |
|
//***************************************************************************** |
// |
// The ASSERT macro, which does the actual assertion checking. Typically, this |
// will be for procedure arguments. |
// |
//***************************************************************************** |
#ifdef DEBUG |
#define ASSERT(expr) { \ |
if(!(expr)) \ |
{ \ |
__error__(__FILE__, __LINE__); \ |
} \ |
} |
#else |
#define ASSERT(expr) |
#endif |
|
#endif // __DEBUG_H__ |
/drivers/LuminaryMicro/hw_usb.h
0,0 → 1,1309
//***************************************************************************** |
// |
// hw_usb.h - Macros for use in accessing the USB registers. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_USB_H__ |
#define __HW_USB_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the Univeral Serial Bus (USB) Controller |
// offsets. |
// |
//***************************************************************************** |
#define USB_O_FADDR 0x00000000 // USB Device Functional Address |
#define USB_O_POWER 0x00000001 // USB Power |
#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status |
#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status |
#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable |
#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable |
#define USB_O_IS 0x0000000A // USB General Interrupt Status |
#define USB_O_IE 0x0000000B // USB Interrupt Enable |
#define USB_O_FRAME 0x0000000C // USB Frame Value |
#define USB_O_EPIDX 0x0000000E // USB Endpoint Index |
#define USB_O_TEST 0x0000000F // USB Test Mode |
#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 |
#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 |
#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 |
#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 |
#define USB_O_DEVCTL 0x00000060 // USB Device Control |
#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing |
#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing |
#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address |
#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address |
#define USB_O_CONTIM 0x0000007A // USB Connect Timing |
#define USB_O_VPLEN 0x0000007B // USB OTG VBus Pulse Timing |
#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction |
// to End of Frame Timing |
#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction |
// to End of Frame Timing |
#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address |
// Endpoint 0 |
#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address |
// Endpoint 0 |
#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 |
#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address |
// Endpoint 1 |
#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address |
// Endpoint 1 |
#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 |
#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address |
// Endpoint 1 |
#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint |
// 1 |
#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 |
#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address |
// Endpoint 2 |
#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address |
// Endpoint 2 |
#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 |
#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address |
// Endpoint 2 |
#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint |
// 2 |
#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 |
#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address |
// Endpoint 3 |
#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address |
// Endpoint 3 |
#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 |
#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address |
// Endpoint 3 |
#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint |
// 3 |
#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 |
#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint |
// 0 Low |
#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint |
// 0 High |
#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint |
// 0 |
#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 |
#define USB_O_NAKLMT 0x0000010B // USB NAK Limit |
#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data |
// Endpoint 1 |
#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status |
// Endpoint 1 Low |
#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status |
// Endpoint 1 High |
#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data |
// Endpoint 1 |
#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status |
// Endpoint 1 Low |
#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status |
// Endpoint 1 High |
#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint |
// 1 |
#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type |
// Endpoint 1 |
#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval |
// Endpoint 1 |
#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type |
// Endpoint 1 |
#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling |
// Interval Endpoint 1 |
#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data |
// Endpoint 2 |
#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status |
// Endpoint 2 Low |
#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status |
// Endpoint 2 High |
#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data |
// Endpoint 2 |
#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status |
// Endpoint 2 Low |
#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status |
// Endpoint 2 High |
#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint |
// 2 |
#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type |
// Endpoint 2 |
#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval |
// Endpoint 2 |
#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type |
// Endpoint 2 |
#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling |
// Interval Endpoint 2 |
#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data |
// Endpoint 3 |
#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status |
// Endpoint 3 Low |
#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status |
// Endpoint 3 High |
#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data |
// Endpoint 3 |
#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status |
// Endpoint 3 Low |
#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status |
// Endpoint 3 High |
#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint |
// 3 |
#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type |
// Endpoint 3 |
#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval |
// Endpoint 3 |
#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type |
// Endpoint 3 |
#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling |
// Interval Endpoint 3 |
#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in |
// Block Transfer Endpoint 1 |
#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in |
// Block Transfer Endpoint 2 |
#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in |
// Block Transfer Endpoint 3 |
#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer |
// Disable |
#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet |
// Buffer Disable |
#define USB_O_EPC 0x00000400 // USB External Power Control |
#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw |
// Interrupt Status |
#define USB_O_EPCIM 0x00000408 // USB External Power Control |
// Interrupt Mask |
#define USB_O_EPCISC 0x0000040C // USB External Power Control |
// Interrupt Status and Clear |
#define USB_O_DRRIS 0x00000410 // USB Device Resume Raw Interrupt |
// Status |
#define USB_O_DRIM 0x00000414 // USB Device Resume Interrupt Mask |
#define USB_O_DRISC 0x00000418 // USB Device Resume Interrupt |
// Status and Clear |
#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and |
// Status |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FADDR register. |
// |
//***************************************************************************** |
#define USB_FADDR_M 0x0000007F // Function Address. |
#define USB_FADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_POWER register. |
// |
//***************************************************************************** |
#define USB_POWER_ISOUP 0x00000080 // ISO Update. |
#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect. |
#define USB_POWER_RESET 0x00000008 // Reset. |
#define USB_POWER_RESUME 0x00000004 // Resume Signaling. |
#define USB_POWER_SUSPEND 0x00000002 // Suspend Mode. |
#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXIS register. |
// |
//***************************************************************************** |
#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt. |
#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt. |
#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt. |
#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXIS register. |
// |
//***************************************************************************** |
#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt. |
#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt. |
#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXIE register. |
// |
//***************************************************************************** |
#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable. |
#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable. |
#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable. |
#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt |
// Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXIE register. |
// |
//***************************************************************************** |
#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable. |
#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable. |
#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_IS register. |
// |
//***************************************************************************** |
#define USB_IS_VBUSERR 0x00000080 // VBus Error. |
#define USB_IS_SESREQ 0x00000040 // Session Request. |
#define USB_IS_DISCON 0x00000020 // Session Disconnect. |
#define USB_IS_CONN 0x00000010 // Session Connect. |
#define USB_IS_SOF 0x00000008 // Start of Frame. |
#define USB_IS_BABBLE 0x00000004 // Babble Detected. |
#define USB_IS_RESET 0x00000004 // Reset Signal Detected. |
#define USB_IS_RESUME 0x00000002 // Resume Signal Detected. |
#define USB_IS_SUSPEND 0x00000001 // Suspend Signal Detected. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_IE register. |
// |
//***************************************************************************** |
#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt. |
#define USB_IE_SESREQ 0x00000040 // Enable Session Request |
// Interrupt. |
#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt. |
#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt. |
#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt. |
#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt. |
#define USB_IE_RESET 0x00000004 // Enable Reset Interrupt. |
#define USB_IE_RESUME 0x00000002 // Enable Resume Interrupt. |
#define USB_IE_SUSPND 0x00000001 // Enable Suspend Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FRAME register. |
// |
//***************************************************************************** |
#define USB_FRAME_M 0x000007FF // Frame Number. |
#define USB_FRAME_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_EPIDX register. |
// |
//***************************************************************************** |
#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index. |
#define USB_EPIDX_EPIDX_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TEST register. |
// |
//***************************************************************************** |
#define USB_TEST_FORCEH 0x00000080 // Force Host Mode. |
#define USB_TEST_FIFOACC 0x00000040 // FIFO Access. |
#define USB_TEST_FORCEFS 0x00000020 // Force Full Speed. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FIFO0 register. |
// |
//***************************************************************************** |
#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data. |
#define USB_FIFO0_EPDATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FIFO1 register. |
// |
//***************************************************************************** |
#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data. |
#define USB_FIFO1_EPDATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FIFO2 register. |
// |
//***************************************************************************** |
#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data. |
#define USB_FIFO2_EPDATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FIFO3 register. |
// |
//***************************************************************************** |
#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data. |
#define USB_FIFO3_EPDATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_DEVCTL register. |
// |
//***************************************************************************** |
#define USB_DEVCTL_DEV 0x00000080 // Device Mode. |
#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected. |
#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected. |
#define USB_DEVCTL_VBUS_M 0x00000018 // VBus Level. |
#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd |
#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid |
#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBusValid |
#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBusValid |
#define USB_DEVCTL_HOST 0x00000004 // Host Mode. |
#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request. |
#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. |
// |
//***************************************************************************** |
#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. |
#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. |
#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 |
#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 |
#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 |
#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 |
#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 |
#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 |
#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 |
#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 |
#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. |
// |
//***************************************************************************** |
#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support. |
#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size. |
#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 |
#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 |
#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 |
#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 |
#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 |
#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 |
#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 |
#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 |
#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFIFOADD |
// register. |
// |
//***************************************************************************** |
#define USB_TXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. |
#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 |
#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 |
#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 |
#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 |
#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 |
#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 |
#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 |
#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 |
#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 |
#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXFIFOADD |
// register. |
// |
//***************************************************************************** |
#define USB_RXFIFOADD_ADDR_M 0x00001FFF // Transmit/Receive Start Address. |
#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 |
#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 |
#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 |
#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 |
#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 |
#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 |
#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 |
#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 |
#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 |
#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_CONTIM register. |
// |
//***************************************************************************** |
#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait. |
#define USB_CONTIM_WTID_M 0x0000000F // Wait ID. |
#define USB_CONTIM_WTCON_S 4 |
#define USB_CONTIM_WTID_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_FSEOF register. |
// |
//***************************************************************************** |
#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap. |
#define USB_FSEOF_FSEOFG_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_LSEOF register. |
// |
//***************************************************************************** |
#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap. |
#define USB_LSEOF_LSEOFG_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 |
// register. |
// |
//***************************************************************************** |
#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address. |
#define USB_TXFUNCADDR0_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBADDR0 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBADDR0_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address. |
#define USB_TXHUBADDR0_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBPORT0 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port. |
#define USB_TXHUBPORT0_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 |
// register. |
// |
//***************************************************************************** |
#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address. |
#define USB_TXFUNCADDR1_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBADDR1 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address. |
#define USB_TXHUBADDR1_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBPORT1 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port. |
#define USB_TXHUBPORT1_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 |
// register. |
// |
//***************************************************************************** |
#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address. |
#define USB_RXFUNCADDR1_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBADDR1 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBADDR1_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address. |
#define USB_RXHUBADDR1_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBPORT1 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port. |
#define USB_RXHUBPORT1_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 |
// register. |
// |
//***************************************************************************** |
#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address. |
#define USB_TXFUNCADDR2_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBADDR2 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address. |
#define USB_TXHUBADDR2_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBPORT2 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port. |
#define USB_TXHUBPORT2_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 |
// register. |
// |
//***************************************************************************** |
#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address. |
#define USB_RXFUNCADDR2_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBADDR2 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBADDR2_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address. |
#define USB_RXHUBADDR2_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBPORT2 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port. |
#define USB_RXHUBPORT2_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 |
// register. |
// |
//***************************************************************************** |
#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address. |
#define USB_TXFUNCADDR3_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBADDR3 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address. |
#define USB_TXHUBADDR3_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXHUBPORT3 |
// register. |
// |
//***************************************************************************** |
#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port. |
#define USB_TXHUBPORT3_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 |
// register. |
// |
//***************************************************************************** |
#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address. |
#define USB_RXFUNCADDR3_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBADDR3 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBADDR3_MULTTRAN 0x00000080 // Multiple Translators. |
#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address. |
#define USB_RXHUBADDR3_ADDR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXHUBPORT3 |
// register. |
// |
//***************************************************************************** |
#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port. |
#define USB_RXHUBPORT3_PORT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_CSRL0 register. |
// |
//***************************************************************************** |
#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout. |
#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear. |
#define USB_CSRL0_STATUS 0x00000040 // Status Packet. |
#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear. |
#define USB_CSRL0_REQPKT 0x00000020 // Request Packet. |
#define USB_CSRL0_STALL 0x00000020 // Send Stall. |
#define USB_CSRL0_SETEND 0x00000010 // Setup End. |
#define USB_CSRL0_ERROR 0x00000010 // Error. |
#define USB_CSRL0_DATAEND 0x00000008 // Data End. |
#define USB_CSRL0_SETUP 0x00000008 // Setup Packet. |
#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled. |
#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready. |
#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_CSRH0 register. |
// |
//***************************************************************************** |
#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable. |
#define USB_CSRH0_DT 0x00000002 // Data Toggle. |
#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_COUNT0 register. |
// |
//***************************************************************************** |
#define USB_COUNT0_COUNT_M 0x0000007F // Count. |
#define USB_COUNT0_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TYPE0 register. |
// |
//***************************************************************************** |
#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_TYPE0_SPEED_FULL 0x00000080 // Full |
#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_NAKLMT register. |
// |
//***************************************************************************** |
#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit. |
#define USB_NAKLMT_NAKLMT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXMAXP1 register. |
// |
//***************************************************************************** |
#define USB_TXMAXP1_MULT_M 0x0000F800 // Multiplier. |
#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_TXMAXP1_MULT_S 11 |
#define USB_TXMAXP1_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRL1 register. |
// |
//***************************************************************************** |
#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout |
#define USB_TXCSRL1_INCTX 0x00000080 // Incomplete Transmit. |
#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle. |
#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled. |
#define USB_TXCSRL1_STALL 0x00000010 // Send Stall. |
#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet. |
#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO. |
#define USB_TXCSRL1_ERROR 0x00000004 // Error. |
#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun. |
#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty. |
#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRH1 register. |
// |
//***************************************************************************** |
#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set. |
#define USB_TXCSRH1_ISO 0x00000040 // ISO. |
#define USB_TXCSRH1_MODE 0x00000020 // Mode. |
#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable. |
#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle. |
#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode. |
#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable. |
#define USB_TXCSRH1_DT 0x00000001 // Data Toggle. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXMAXP1 register. |
// |
//***************************************************************************** |
#define USB_RXMAXP1_MULT_M 0x0000F800 // Multiplier. |
#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_RXMAXP1_MULT_S 11 |
#define USB_RXMAXP1_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRL1 register. |
// |
//***************************************************************************** |
#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle. |
#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled. |
#define USB_RXCSRL1_STALL 0x00000020 // Send Stall. |
#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet. |
#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO. |
#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error. |
#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout. |
#define USB_RXCSRL1_OVER 0x00000004 // Overrun. |
#define USB_RXCSRL1_ERROR 0x00000004 // Error. |
#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full. |
#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRH1 register. |
// |
//***************************************************************************** |
#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear. |
#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request. |
#define USB_RXCSRH1_ISO 0x00000040 // ISO. |
#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable. |
#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET |
#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error. |
#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode. |
#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable. |
#define USB_RXCSRH1_DT 0x00000002 // Data Toggle. |
#define USB_RXCSRH1_INCRX 0x00000001 // Incomplete Receive. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. |
// |
//***************************************************************************** |
#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count. |
#define USB_RXCOUNT1_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXTYPE1 register. |
// |
//***************************************************************************** |
#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default |
#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full |
#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low |
#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol. |
#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control |
#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk |
#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt |
#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_TXTYPE1_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXINTERVAL1 |
// register. |
// |
//***************************************************************************** |
#define USB_TXINTERVAL1_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_TXINTERVAL1_TXPOLL_M \ |
0x000000FF // TX Polling |
#define USB_TXINTERVAL1_TXPOLL_S \ |
0 |
#define USB_TXINTERVAL1_NAKLMT_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXTYPE1 register. |
// |
//***************************************************************************** |
#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default |
#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full |
#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low |
#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol. |
#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control |
#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk |
#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt |
#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_RXTYPE1_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXINTERVAL1 |
// register. |
// |
//***************************************************************************** |
#define USB_RXINTERVAL1_TXPOLL_M \ |
0x000000FF // RX Polling |
#define USB_RXINTERVAL1_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_RXINTERVAL1_TXPOLL_S \ |
0 |
#define USB_RXINTERVAL1_NAKLMT_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXMAXP2 register. |
// |
//***************************************************************************** |
#define USB_TXMAXP2_MULT_M 0x0000F800 // Multiplier. |
#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_TXMAXP2_MULT_S 11 |
#define USB_TXMAXP2_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRL2 register. |
// |
//***************************************************************************** |
#define USB_TXCSRL2_INCTX 0x00000080 // Incomplete Transmit. |
#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout |
#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle. |
#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled. |
#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet. |
#define USB_TXCSRL2_STALL 0x00000010 // Send Stall. |
#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO. |
#define USB_TXCSRL2_ERROR 0x00000004 // Error. |
#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun. |
#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty. |
#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRH2 register. |
// |
//***************************************************************************** |
#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set. |
#define USB_TXCSRH2_ISO 0x00000040 // ISO. |
#define USB_TXCSRH2_MODE 0x00000020 // Mode. |
#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable. |
#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle. |
#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode. |
#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable. |
#define USB_TXCSRH2_DT 0x00000001 // Data Toggle. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXMAXP2 register. |
// |
//***************************************************************************** |
#define USB_RXMAXP2_MULT_M 0x0000F800 // Multiplier. |
#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_RXMAXP2_MULT_S 11 |
#define USB_RXMAXP2_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRL2 register. |
// |
//***************************************************************************** |
#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle. |
#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled. |
#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet. |
#define USB_RXCSRL2_STALL 0x00000020 // Send Stall. |
#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO. |
#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error. |
#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout. |
#define USB_RXCSRL2_ERROR 0x00000004 // Error. |
#define USB_RXCSRL2_OVER 0x00000004 // Overrun. |
#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full. |
#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRH2 register. |
// |
//***************************************************************************** |
#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear. |
#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request. |
#define USB_RXCSRH2_ISO 0x00000040 // ISO. |
#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable. |
#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET |
#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error. |
#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode. |
#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable. |
#define USB_RXCSRH2_DT 0x00000002 // Data Toggle. |
#define USB_RXCSRH2_INCRX 0x00000001 // Incomplete Receive. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. |
// |
//***************************************************************************** |
#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count. |
#define USB_RXCOUNT2_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXTYPE2 register. |
// |
//***************************************************************************** |
#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default |
#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full |
#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low |
#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol. |
#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control |
#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk |
#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt |
#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_TXTYPE2_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXINTERVAL2 |
// register. |
// |
//***************************************************************************** |
#define USB_TXINTERVAL2_TXPOLL_M \ |
0x000000FF // TX Polling |
#define USB_TXINTERVAL2_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_TXINTERVAL2_NAKLMT_S \ |
0 |
#define USB_TXINTERVAL2_TXPOLL_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXTYPE2 register. |
// |
//***************************************************************************** |
#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default |
#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full |
#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low |
#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol. |
#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control |
#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk |
#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt |
#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_RXTYPE2_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXINTERVAL2 |
// register. |
// |
//***************************************************************************** |
#define USB_RXINTERVAL2_TXPOLL_M \ |
0x000000FF // RX Polling |
#define USB_RXINTERVAL2_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_RXINTERVAL2_TXPOLL_S \ |
0 |
#define USB_RXINTERVAL2_NAKLMT_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXMAXP3 register. |
// |
//***************************************************************************** |
#define USB_TXMAXP3_MULT_M 0x0000F800 // Multiplier. |
#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_TXMAXP3_MULT_S 11 |
#define USB_TXMAXP3_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRL3 register. |
// |
//***************************************************************************** |
#define USB_TXCSRL3_INCTX 0x00000080 // Incomplete Transmit. |
#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout |
#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle. |
#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled. |
#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet. |
#define USB_TXCSRL3_STALL 0x00000010 // Send Stall. |
#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO. |
#define USB_TXCSRL3_ERROR 0x00000004 // Error. |
#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun. |
#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty. |
#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXCSRH3 register. |
// |
//***************************************************************************** |
#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set. |
#define USB_TXCSRH3_ISO 0x00000040 // ISO. |
#define USB_TXCSRH3_MODE 0x00000020 // Mode. |
#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable. |
#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle. |
#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode. |
#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable. |
#define USB_TXCSRH3_DT 0x00000001 // Data Toggle. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXMAXP3 register. |
// |
//***************************************************************************** |
#define USB_RXMAXP3_MULT_M 0x0000F800 // Multiplier. |
#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload. |
#define USB_RXMAXP3_MULT_S 11 |
#define USB_RXMAXP3_MAXLOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRL3 register. |
// |
//***************************************************************************** |
#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle. |
#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled. |
#define USB_RXCSRL3_STALL 0x00000020 // Send Stall. |
#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet. |
#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO. |
#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error. |
#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout. |
#define USB_RXCSRL3_ERROR 0x00000004 // Error. |
#define USB_RXCSRL3_OVER 0x00000004 // Overrun. |
#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full. |
#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCSRH3 register. |
// |
//***************************************************************************** |
#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear. |
#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request. |
#define USB_RXCSRH3_ISO 0x00000040 // ISO. |
#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable. |
#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET |
#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error. |
#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode. |
#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable. |
#define USB_RXCSRH3_DT 0x00000002 // Data Toggle. |
#define USB_RXCSRH3_INCRX 0x00000001 // Incomplete Receive. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. |
// |
//***************************************************************************** |
#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count. |
#define USB_RXCOUNT3_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXTYPE3 register. |
// |
//***************************************************************************** |
#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default |
#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full |
#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low |
#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol. |
#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control |
#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk |
#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt |
#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_TXTYPE3_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXINTERVAL3 |
// register. |
// |
//***************************************************************************** |
#define USB_TXINTERVAL3_TXPOLL_M \ |
0x000000FF // TX Polling |
#define USB_TXINTERVAL3_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_TXINTERVAL3_TXPOLL_S \ |
0 |
#define USB_TXINTERVAL3_NAKLMT_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXTYPE3 register. |
// |
//***************************************************************************** |
#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed. |
#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default |
#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full |
#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low |
#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol. |
#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control |
#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous |
#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk |
#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt |
#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number. |
#define USB_RXTYPE3_TEP_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXINTERVAL3 |
// register. |
// |
//***************************************************************************** |
#define USB_RXINTERVAL3_TXPOLL_M \ |
0x000000FF // RX Polling |
#define USB_RXINTERVAL3_NAKLMT_M \ |
0x000000FF // NAK Limit. |
#define USB_RXINTERVAL3_TXPOLL_S \ |
0 |
#define USB_RXINTERVAL3_NAKLMT_S \ |
0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 |
// register. |
// |
//***************************************************************************** |
#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count. |
#define USB_RQPKTCOUNT1_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 |
// register. |
// |
//***************************************************************************** |
#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count. |
#define USB_RQPKTCOUNT2_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 |
// register. |
// |
//***************************************************************************** |
#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count. |
#define USB_RQPKTCOUNT3_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS |
// register. |
// |
//***************************************************************************** |
#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer |
// Disable. |
#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer |
// Disable. |
#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer |
// Disable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS |
// register. |
// |
//***************************************************************************** |
#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer |
// Disable. |
#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer |
// Disable. |
#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer |
// Disable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_EPC register. |
// |
//***************************************************************************** |
#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action. |
#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged |
#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate |
#define USB_EPC_PFLTACT_LOW 0x00000200 // Low |
#define USB_EPC_PFLTACT_HIGH 0x00000300 // High |
#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable. |
#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense. |
#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable. |
#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable. |
#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable |
// Configuration. |
#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low |
#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High |
#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low |
#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_EPCRIS register. |
// |
//***************************************************************************** |
#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt |
// Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_EPCIM register. |
// |
//***************************************************************************** |
#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_EPCISC register. |
// |
//***************************************************************************** |
#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status |
// and Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_DRRIS register. |
// |
//***************************************************************************** |
#define USB_DRRIS_RESUME 0x00000001 // Resume Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_DRIM register. |
// |
//***************************************************************************** |
#define USB_DRIM_RESUME 0x00000001 // Resume Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_DRISC register. |
// |
//***************************************************************************** |
#define USB_DRISC_RESUME 0x00000001 // Resume Interrupt Status and |
// Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_GPCS register. |
// |
//***************************************************************************** |
#define USB_GPCS_DEVMOD 0x00000001 // Device Mode. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the USB_O_VPLEN register. |
// |
//***************************************************************************** |
#define USB_VPLEN_VPLEN_M 0x000000FF // VBus Pulse Length. |
#define USB_VPLEN_VPLEN_S 0 |
|
#endif // __HW_USB_H__ |
/drivers/LuminaryMicro/cpu.h
0,0 → 1,61
//***************************************************************************** |
// |
// cpu.h - Prototypes for the CPU instruction wrapper functions. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __CPU_H__ |
#define __CPU_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Prototypes. |
// |
//***************************************************************************** |
extern unsigned long CPUcpsid(void); |
extern unsigned long CPUcpsie(void); |
extern void CPUwfi(void); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __CPU_H__ |
/drivers/LuminaryMicro/systick.h
0,0 → 1,67
//***************************************************************************** |
// |
// systick.h - Prototypes for the SysTick driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __SYSTICK_H__ |
#define __SYSTICK_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void SysTickEnable(void); |
extern void SysTickDisable(void); |
extern void SysTickIntRegister(void (*pfnHandler)(void)); |
extern void SysTickIntUnregister(void); |
extern void SysTickIntEnable(void); |
extern void SysTickIntDisable(void); |
extern void SysTickPeriodSet(unsigned long ulPeriod); |
extern unsigned long SysTickPeriodGet(void); |
extern unsigned long SysTickValueGet(void); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __SYSTICK_H__ |
/drivers/LuminaryMicro/hw_flash.h
0,0 → 1,296
//***************************************************************************** |
// |
// hw_flash.h - Macros used when accessing the flash controller. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_FLASH_H__ |
#define __HW_FLASH_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the FLASH register offsets. |
// |
//***************************************************************************** |
#define FLASH_FMA 0x400FD000 // Memory address register |
#define FLASH_FMD 0x400FD004 // Memory data register |
#define FLASH_FMC 0x400FD008 // Memory control register |
#define FLASH_FCRIS 0x400FD00C // Raw interrupt status register |
#define FLASH_FCIM 0x400FD010 // Interrupt mask register |
#define FLASH_FCMISC 0x400FD014 // Interrupt status register |
#define FLASH_RMCTL 0x400FE0F0 // ROM Control |
#define FLASH_RMVER 0x400FE0F4 // ROM Version Register |
#define FLASH_FMPRE 0x400FE130 // FLASH read protect register |
#define FLASH_FMPPE 0x400FE134 // FLASH program protect register |
#define FLASH_USECRL 0x400FE140 // uSec reload register |
#define FLASH_USERDBG 0x400FE1D0 // User Debug |
#define FLASH_USERREG0 0x400FE1E0 // User Register 0 |
#define FLASH_USERREG1 0x400FE1E4 // User Register 1 |
#define FLASH_USERREG2 0x400FE1E8 // User Register 2 |
#define FLASH_USERREG3 0x400FE1EC // User Register 3 |
#define FLASH_FMPRE0 0x400FE200 // FLASH read protect register 0 |
#define FLASH_FMPRE1 0x400FE204 // FLASH read protect register 1 |
#define FLASH_FMPRE2 0x400FE208 // FLASH read protect register 2 |
#define FLASH_FMPRE3 0x400FE20C // FLASH read protect register 3 |
#define FLASH_FMPPE0 0x400FE400 // FLASH program protect register 0 |
#define FLASH_FMPPE1 0x400FE404 // FLASH program protect register 1 |
#define FLASH_FMPPE2 0x400FE408 // FLASH program protect register 2 |
#define FLASH_FMPPE3 0x400FE40C // FLASH program protect register 3 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FMC register. |
// |
//***************************************************************************** |
#define FLASH_FMC_WRKEY_M 0xFFFF0000 // FLASH write key mask |
#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key |
#define FLASH_FMC_COMT 0x00000008 // Commit user register |
#define FLASH_FMC_MERASE 0x00000004 // Mass erase FLASH |
#define FLASH_FMC_ERASE 0x00000002 // Erase FLASH page |
#define FLASH_FMC_WRITE 0x00000001 // Write FLASH word |
#define FLASH_FMC_WRKEY_S 16 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FCRIS register. |
// |
//***************************************************************************** |
#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt |
// Status. |
#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FCIM register. |
// |
//***************************************************************************** |
#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask. |
#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FMIS register. |
// |
//***************************************************************************** |
#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt |
// Status and Clear. |
#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status |
// and Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FMPRE and |
// FLASH_FMPPE registers. |
// |
//***************************************************************************** |
#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31 |
#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30 |
#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29 |
#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28 |
#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27 |
#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26 |
#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25 |
#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24 |
#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23 |
#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22 |
#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21 |
#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20 |
#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19 |
#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18 |
#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17 |
#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16 |
#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15 |
#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14 |
#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13 |
#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12 |
#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11 |
#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10 |
#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9 |
#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8 |
#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7 |
#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6 |
#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5 |
#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4 |
#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3 |
#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2 |
#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1 |
#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USECRL register. |
// |
//***************************************************************************** |
#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value. |
#define FLASH_USECRL_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the erase size of the FLASH block that is |
// erased by an erase operation, and the protect size is the size of the FLASH |
// block that is protected by each protection register. |
// |
//***************************************************************************** |
#define FLASH_PROTECT_SIZE 0x00000800 |
#define FLASH_ERASE_SIZE 0x00000400 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FMA register. |
// |
//***************************************************************************** |
#define FLASH_FMA_OFFSET_M 0x0003FFFF // Address Offset. |
#define FLASH_FMA_OFFSET_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_FMD register. |
// |
//***************************************************************************** |
#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value. |
#define FLASH_FMD_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USERDBG register. |
// |
//***************************************************************************** |
#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written. |
#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data. |
#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1. |
#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0. |
#define FLASH_USERDBG_DATA_S 2 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USERREG0 register. |
// |
//***************************************************************************** |
#define FLASH_USERREG0_NW 0x80000000 // Not Written. |
#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data. |
#define FLASH_USERREG0_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USERREG1 register. |
// |
//***************************************************************************** |
#define FLASH_USERREG1_NW 0x80000000 // Not Written. |
#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data. |
#define FLASH_USERREG1_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_RMCTL register. |
// |
//***************************************************************************** |
#define FLASH_RMCTL_BA 0x00000001 // Boot Alias. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_RMVER register. |
// |
//***************************************************************************** |
#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents. |
#define FLASH_RMVER_CONT_LM 0x00000000 // Boot Loader & DriverLib |
#define FLASH_RMVER_SIZE_M 0x00FF0000 // ROM Size. |
#define FLASH_RMVER_SIZE_11K 0x00000000 // 11KB Size |
#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version. |
#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision. |
#define FLASH_RMVER_VER_S 8 |
#define FLASH_RMVER_REV_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USERREG2 register. |
// |
//***************************************************************************** |
#define FLASH_USERREG2_NW 0x80000000 // Not Written. |
#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data. |
#define FLASH_USERREG2_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the FLASH_USERREG3 register. |
// |
//***************************************************************************** |
#define FLASH_USERREG3_NW 0x80000000 // Not Written. |
#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data. |
#define FLASH_USERREG3_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the FLASH_FMC |
// register. |
// |
//***************************************************************************** |
#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the FLASH_FCRIS |
// register. |
// |
//***************************************************************************** |
#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status |
#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the FLASH_FCIM |
// register. |
// |
//***************************************************************************** |
#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask |
#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the FLASH_FMIS |
// register. |
// |
//***************************************************************************** |
#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status |
#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the FLASH_USECRL |
// register. |
// |
//***************************************************************************** |
#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec |
#define FLASH_USECRL_SHIFT 0 |
|
#endif |
|
#endif // __HW_FLASH_H__ |
/drivers/LuminaryMicro/hw_gpio.h
0,0 → 1,136
//***************************************************************************** |
// |
// hw_gpio.h - Defines and Macros for GPIO hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_GPIO_H__ |
#define __HW_GPIO_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the GPIO Register offsets. |
// |
//***************************************************************************** |
#define GPIO_O_DATA 0x00000000 // Data register. |
#define GPIO_O_DIR 0x00000400 // Data direction register. |
#define GPIO_O_IS 0x00000404 // Interrupt sense register. |
#define GPIO_O_IBE 0x00000408 // Interrupt both edges register. |
#define GPIO_O_IEV 0x0000040C // Interrupt event register. |
#define GPIO_O_IM 0x00000410 // Interrupt mask register. |
#define GPIO_O_RIS 0x00000414 // Raw interrupt status register. |
#define GPIO_O_MIS 0x00000418 // Masked interrupt status reg. |
#define GPIO_O_ICR 0x0000041C // Interrupt clear register. |
#define GPIO_O_AFSEL 0x00000420 // Mode control select register. |
#define GPIO_O_DR2R 0x00000500 // 2ma drive select register. |
#define GPIO_O_DR4R 0x00000504 // 4ma drive select register. |
#define GPIO_O_DR8R 0x00000508 // 8ma drive select register. |
#define GPIO_O_ODR 0x0000050C // Open drain select register. |
#define GPIO_O_PUR 0x00000510 // Pull up select register. |
#define GPIO_O_PDR 0x00000514 // Pull down select register. |
#define GPIO_O_SLR 0x00000518 // Slew rate control enable reg. |
#define GPIO_O_DEN 0x0000051C // Digital input enable register. |
#define GPIO_O_LOCK 0x00000520 // Lock register. |
#define GPIO_O_CR 0x00000524 // Commit register. |
#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the GPIO_LOCK register. |
// |
//***************************************************************************** |
#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock. |
#define GPIO_LOCK_UNLOCKED 0x00000000 // GPIO_CR register is unlocked |
#define GPIO_LOCK_LOCKED 0x00000001 // GPIO_CR register is locked |
#define GPIO_LOCK_KEY 0x1ACCE551 // Unlocks the GPIO_CR register |
#define GPIO_LOCK_KEY_DD 0x4C4F434B // Unlocks the GPIO_CR register on |
// DustDevil-class devices and |
// later. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the GPIO Register offsets. |
// |
//***************************************************************************** |
#define GPIO_O_PeriphID4 0x00000FD0 |
#define GPIO_O_PeriphID5 0x00000FD4 |
#define GPIO_O_PeriphID6 0x00000FD8 |
#define GPIO_O_PeriphID7 0x00000FDC |
#define GPIO_O_PeriphID0 0x00000FE0 |
#define GPIO_O_PeriphID1 0x00000FE4 |
#define GPIO_O_PeriphID2 0x00000FE8 |
#define GPIO_O_PeriphID3 0x00000FEC |
#define GPIO_O_PCellID0 0x00000FF0 |
#define GPIO_O_PCellID1 0x00000FF4 |
#define GPIO_O_PCellID2 0x00000FF8 |
#define GPIO_O_PCellID3 0x00000FFC |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the GPIO Register reset values. |
// |
//***************************************************************************** |
#define GPIO_RV_DEN 0x000000FF // Digital input enable reg RV. |
#define GPIO_RV_PUR 0x000000FF // Pull up select reg RV. |
#define GPIO_RV_DR2R 0x000000FF // 2ma drive select reg RV. |
#define GPIO_RV_PCellID1 0x000000F0 |
#define GPIO_RV_PCellID3 0x000000B1 |
#define GPIO_RV_PeriphID0 0x00000061 |
#define GPIO_RV_PeriphID1 0x00000010 |
#define GPIO_RV_PCellID0 0x0000000D |
#define GPIO_RV_PCellID2 0x00000005 |
#define GPIO_RV_PeriphID2 0x00000004 |
#define GPIO_RV_LOCK 0x00000001 // Lock register RV. |
#define GPIO_RV_PeriphID7 0x00000000 |
#define GPIO_RV_PDR 0x00000000 // Pull down select reg RV. |
#define GPIO_RV_IC 0x00000000 // Interrupt clear reg RV. |
#define GPIO_RV_SLR 0x00000000 // Slew rate control enable reg RV. |
#define GPIO_RV_ODR 0x00000000 // Open drain select reg RV. |
#define GPIO_RV_IBE 0x00000000 // Interrupt both edges reg RV. |
#define GPIO_RV_AFSEL 0x00000000 // Mode control select reg RV. |
#define GPIO_RV_IS 0x00000000 // Interrupt sense reg RV. |
#define GPIO_RV_IM 0x00000000 // Interrupt mask reg RV. |
#define GPIO_RV_PeriphID4 0x00000000 |
#define GPIO_RV_PeriphID5 0x00000000 |
#define GPIO_RV_DR8R 0x00000000 // 8ma drive select reg RV. |
#define GPIO_RV_RIS 0x00000000 // Raw interrupt status reg RV. |
#define GPIO_RV_DR4R 0x00000000 // 4ma drive select reg RV. |
#define GPIO_RV_IEV 0x00000000 // Intterupt event reg RV. |
#define GPIO_RV_DIR 0x00000000 // Data direction reg RV. |
#define GPIO_RV_PeriphID6 0x00000000 |
#define GPIO_RV_PeriphID3 0x00000000 |
#define GPIO_RV_DATA 0x00000000 // Data register reset value. |
#define GPIO_RV_MIS 0x00000000 // Masked interrupt status reg RV. |
|
#endif |
|
#endif // __HW_GPIO_H__ |
/drivers/LuminaryMicro/hw_comp.h
0,0 → 1,278
//***************************************************************************** |
// |
// hw_comp.h - Macros used when accessing the comparator hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_COMP_H__ |
#define __HW_COMP_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the comparator register offsets. |
// |
//***************************************************************************** |
#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked |
// Interrupt Status |
#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt |
// Status |
#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt |
// Enable |
#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference |
// Voltage Control |
#define COMP_O_ACSTAT0 0x00000020 // Comp0 status register |
#define COMP_O_ACCTL0 0x00000024 // Comp0 control register |
#define COMP_O_ACSTAT1 0x00000040 // Comp1 status register |
#define COMP_O_ACCTL1 0x00000044 // Comp1 control register |
#define COMP_O_ACSTAT2 0x00000060 // Comp2 status register |
#define COMP_O_ACCTL2 0x00000064 // Comp2 control register |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACMIS register. |
// |
//***************************************************************************** |
#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt |
// Status. |
#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt |
// Status. |
#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt |
// Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACRIS register. |
// |
//***************************************************************************** |
#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status. |
#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status. |
#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACINTEN register. |
// |
//***************************************************************************** |
#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable. |
#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable. |
#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACREFCTL |
// register. |
// |
//***************************************************************************** |
#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable. |
#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range. |
#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref. |
#define COMP_ACREFCTL_VREF_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACSTAT0 register. |
// |
//***************************************************************************** |
#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACCTL0 register. |
// |
//***************************************************************************** |
#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable. |
#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive. |
#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value |
#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+ |
#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference |
#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value. |
#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense. |
#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL |
#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge |
#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge |
#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge |
#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value. |
#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense. |
#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL |
#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge |
#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge |
#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge |
#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACSTAT1 register. |
// |
//***************************************************************************** |
#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACCTL1 register. |
// |
//***************************************************************************** |
#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable. |
#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive. |
#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value |
#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+ |
#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference |
#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value. |
#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense. |
#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL |
#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge |
#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge |
#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge |
#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value. |
#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense. |
#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL |
#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge |
#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge |
#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge |
#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACSTAT2 register. |
// |
//***************************************************************************** |
#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the COMP_O_ACCTL2 register. |
// |
//***************************************************************************** |
#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable. |
#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive. |
#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value |
#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+ |
#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference |
#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value. |
#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense. |
#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL |
#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge |
#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge |
#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge |
#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value. |
#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense. |
#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL |
#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge |
#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge |
#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge |
#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the comparator register offsets. |
// |
//***************************************************************************** |
#define COMP_O_MIS 0x00000000 // Interrupt status register |
#define COMP_O_RIS 0x00000004 // Raw interrupt status register |
#define COMP_O_INTEN 0x00000008 // Interrupt enable register |
#define COMP_O_REFCTL 0x00000010 // Reference voltage control reg. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the COMP_MIS, |
// COMP_RIS, and COMP_INTEN registers. |
// |
//***************************************************************************** |
#define COMP_INT_2 0x00000004 // Comp2 interrupt |
#define COMP_INT_1 0x00000002 // Comp1 interrupt |
#define COMP_INT_0 0x00000001 // Comp0 interrupt |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the COMP_REFCTL |
// register. |
// |
//***************************************************************************** |
#define COMP_REFCTL_EN 0x00000200 // Reference voltage enable |
#define COMP_REFCTL_RNG 0x00000100 // Reference voltage range |
#define COMP_REFCTL_VREF_MASK 0x0000000F // Reference voltage select mask |
#define COMP_REFCTL_VREF_SHIFT 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the COMP_ACSTAT0, |
// COMP_ACSTAT1, and COMP_ACSTAT2 registers. |
// |
//***************************************************************************** |
#define COMP_ACSTAT_OVAL 0x00000002 // Comparator output value |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the COMP_ACCTL0, |
// COMP_ACCTL1, and COMP_ACCTL2 registers. |
// |
//***************************************************************************** |
#define COMP_ACCTL_TMASK 0x00000800 // Trigger enable |
#define COMP_ACCTL_ASRCP_MASK 0x00000600 // Vin+ source select mask |
#define COMP_ACCTL_ASRCP_PIN 0x00000000 // Dedicated Comp+ pin |
#define COMP_ACCTL_ASRCP_PIN0 0x00000200 // Comp0+ pin |
#define COMP_ACCTL_ASRCP_REF 0x00000400 // Internal voltage reference |
#define COMP_ACCTL_ASRCP_RES 0x00000600 // Reserved |
#define COMP_ACCTL_OEN 0x00000100 // Comparator output enable |
#define COMP_ACCTL_TSVAL 0x00000080 // Trigger polarity select |
#define COMP_ACCTL_TSEN_MASK 0x00000060 // Trigger sense mask |
#define COMP_ACCTL_TSEN_LEVEL 0x00000000 // Trigger is level sense |
#define COMP_ACCTL_TSEN_FALL 0x00000020 // Trigger is falling edge |
#define COMP_ACCTL_TSEN_RISE 0x00000040 // Trigger is rising edge |
#define COMP_ACCTL_TSEN_BOTH 0x00000060 // Trigger is both edges |
#define COMP_ACCTL_ISLVAL 0x00000010 // Interrupt polarity select |
#define COMP_ACCTL_ISEN_MASK 0x0000000C // Interrupt sense mask |
#define COMP_ACCTL_ISEN_LEVEL 0x00000000 // Interrupt is level sense |
#define COMP_ACCTL_ISEN_FALL 0x00000004 // Interrupt is falling edge |
#define COMP_ACCTL_ISEN_RISE 0x00000008 // Interrupt is rising edge |
#define COMP_ACCTL_ISEN_BOTH 0x0000000C // Interrupt is both edges |
#define COMP_ACCTL_CINV 0x00000002 // Comparator output invert |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the reset values for the comparator |
// registers. |
// |
//***************************************************************************** |
#define COMP_RV_ACCTL1 0x00000000 // Comp1 control register |
#define COMP_RV_ACSTAT2 0x00000000 // Comp2 status register |
#define COMP_RV_ACSTAT0 0x00000000 // Comp0 status register |
#define COMP_RV_RIS 0x00000000 // Raw interrupt status register |
#define COMP_RV_INTEN 0x00000000 // Interrupt enable register |
#define COMP_RV_ACCTL2 0x00000000 // Comp2 control register |
#define COMP_RV_MIS 0x00000000 // Interrupt status register |
#define COMP_RV_ACCTL0 0x00000000 // Comp0 control register |
#define COMP_RV_ACSTAT1 0x00000000 // Comp1 status register |
#define COMP_RV_REFCTL 0x00000000 // Reference voltage control reg. |
|
#endif |
|
#endif // __HW_COMP_H__ |
/drivers/LuminaryMicro/hw_ssi.h
0,0 → 1,220
//***************************************************************************** |
// |
// hw_ssi.h - Macros used when accessing the SSI hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_SSI_H__ |
#define __HW_SSI_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the SSI register offsets. |
// |
//***************************************************************************** |
#define SSI_O_CR0 0x00000000 // Control register 0 |
#define SSI_O_CR1 0x00000004 // Control register 1 |
#define SSI_O_DR 0x00000008 // Data register |
#define SSI_O_SR 0x0000000C // Status register |
#define SSI_O_CPSR 0x00000010 // Clock prescale register |
#define SSI_O_IM 0x00000014 // Int mask set and clear register |
#define SSI_O_RIS 0x00000018 // Raw interrupt register |
#define SSI_O_MIS 0x0000001C // Masked interrupt register |
#define SSI_O_ICR 0x00000020 // Interrupt clear register |
#define SSI_O_DMACTL 0x00000024 // SSI DMA Control |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI Control register 0. |
// |
//***************************************************************************** |
#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate. |
#define SSI_CR0_SPH 0x00000080 // SSPCLKOUT phase |
#define SSI_CR0_SPO 0x00000040 // SSPCLKOUT polarity |
#define SSI_CR0_FRF_M 0x00000030 // Frame format mask |
#define SSI_CR0_FRF_MOTO 0x00000000 // Motorola SPI frame format |
#define SSI_CR0_FRF_TI 0x00000010 // TI sync serial frame format |
#define SSI_CR0_FRF_NMW 0x00000020 // National Microwire frame format |
#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select. |
#define SSI_CR0_DSS_4 0x00000003 // 4 bit data |
#define SSI_CR0_DSS_5 0x00000004 // 5 bit data |
#define SSI_CR0_DSS_6 0x00000005 // 6 bit data |
#define SSI_CR0_DSS_7 0x00000006 // 7 bit data |
#define SSI_CR0_DSS_8 0x00000007 // 8 bit data |
#define SSI_CR0_DSS_9 0x00000008 // 9 bit data |
#define SSI_CR0_DSS_10 0x00000009 // 10 bit data |
#define SSI_CR0_DSS_11 0x0000000A // 11 bit data |
#define SSI_CR0_DSS_12 0x0000000B // 12 bit data |
#define SSI_CR0_DSS_13 0x0000000C // 13 bit data |
#define SSI_CR0_DSS_14 0x0000000D // 14 bit data |
#define SSI_CR0_DSS_15 0x0000000E // 15 bit data |
#define SSI_CR0_DSS_16 0x0000000F // 16 bit data |
#define SSI_CR0_SCR_S 8 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI Control register 1. |
// |
//***************************************************************************** |
#define SSI_CR1_SOD 0x00000008 // Slave mode output disable |
#define SSI_CR1_MS 0x00000004 // Master or slave mode select |
#define SSI_CR1_SSE 0x00000002 // Sync serial port enable |
#define SSI_CR1_LBM 0x00000001 // Loopback mode |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI Status register. |
// |
//***************************************************************************** |
#define SSI_SR_BSY 0x00000010 // SSI busy |
#define SSI_SR_RFF 0x00000008 // RX FIFO full |
#define SSI_SR_RNE 0x00000004 // RX FIFO not empty |
#define SSI_SR_TNF 0x00000002 // TX FIFO not full |
#define SSI_SR_TFE 0x00000001 // TX FIFO empty |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI clock prescale |
// register. |
// |
//***************************************************************************** |
#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor. |
#define SSI_CPSR_CPSDVSR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_DR register. |
// |
//***************************************************************************** |
#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data. |
#define SSI_DR_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_IM register. |
// |
//***************************************************************************** |
#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt |
// Mask. |
#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask. |
#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt |
// Mask. |
#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt |
// Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_RIS register. |
// |
//***************************************************************************** |
#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt |
// Status. |
#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt |
// Status. |
#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw |
// Interrupt Status. |
#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw |
// Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_MIS register. |
// |
//***************************************************************************** |
#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked |
// Interrupt Status. |
#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked |
// Interrupt Status. |
#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked |
// Interrupt Status. |
#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked |
// Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_ICR register. |
// |
//***************************************************************************** |
#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt |
// Clear. |
#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt |
// Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the SSI_O_DMACTL register. |
// |
//***************************************************************************** |
#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable. |
#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SSI Control |
// register 0. |
// |
//***************************************************************************** |
#define SSI_CR0_SCR 0x0000FF00 // Serial clock rate |
#define SSI_CR0_FRF_MASK 0x00000030 // Frame format mask |
#define SSI_CR0_DSS 0x0000000F // Data size select |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the SSI clock |
// prescale register. |
// |
//***************************************************************************** |
#define SSI_CPSR_CPSDVSR_MASK 0x000000FF // Clock prescale |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the SSI controller's FIFO size. |
// |
//***************************************************************************** |
#define TX_FIFO_SIZE (8) // Number of entries in the TX FIFO |
#define RX_FIFO_SIZE (8) // Number of entries in the RX FIFO |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the interrupt |
// mask set and clear, raw interrupt, masked interrupt, and interrupt clear |
// registers. |
// |
//***************************************************************************** |
#define SSI_INT_TXFF 0x00000008 // TX FIFO interrupt |
#define SSI_INT_RXFF 0x00000004 // RX FIFO interrupt |
#define SSI_INT_RXTO 0x00000002 // RX timeout interrupt |
#define SSI_INT_RXOR 0x00000001 // RX overrun interrupt |
|
#endif |
|
#endif // __HW_SSI_H__ |
/drivers/LuminaryMicro/interrupt.h
0,0 → 1,77
//***************************************************************************** |
// |
// interrupt.h - Prototypes for the NVIC Interrupt Controller Driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __INTERRUPT_H__ |
#define __INTERRUPT_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Macro to generate an interrupt priority mask based on the number of bits |
// of priority supported by the hardware. |
// |
//***************************************************************************** |
#define INT_PRIORITY_MASK ((0xFF << (8 - NUM_PRIORITY_BITS)) & 0xFF) |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern tBoolean IntMasterEnable(void); |
extern tBoolean IntMasterDisable(void); |
extern void IntRegister(unsigned long ulInterrupt, void (*pfnHandler)(void)); |
extern void IntUnregister(unsigned long ulInterrupt); |
extern void IntPriorityGroupingSet(unsigned long ulBits); |
extern unsigned long IntPriorityGroupingGet(void); |
extern void IntPrioritySet(unsigned long ulInterrupt, |
unsigned char ucPriority); |
extern long IntPriorityGet(unsigned long ulInterrupt); |
extern void IntEnable(unsigned long ulInterrupt); |
extern void IntDisable(unsigned long ulInterrupt); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __INTERRUPT_H__ |
/drivers/LuminaryMicro/lmi_flash.h
0,0 → 1,78
//***************************************************************************** |
// |
// flash.h - Prototypes for the flash driver. |
// |
// Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. Any use in violation |
// of the foregoing restrictions may subject the user to criminal sanctions |
// under applicable laws, as well as to civil liability for the breach of the |
// terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 1582 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __FLASH_H__ |
#define __FLASH_H__ |
|
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to FlashProtectSet(), and returned by |
// FlashProtectGet(). |
// |
//***************************************************************************** |
typedef enum |
{ |
FlashReadWrite, // Flash can be read and written |
FlashReadOnly, // Flash can only be read |
FlashExecuteOnly // Flash can only be executed |
} |
tFlashProtection; |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern unsigned long FlashUsecGet(void); |
extern void FlashUsecSet(unsigned long ulClocks); |
extern long FlashErase(unsigned long ulAddress); |
extern long FlashProgram(unsigned long *pulData, unsigned long ulAddress, |
unsigned long ulCount); |
extern tFlashProtection FlashProtectGet(unsigned long ulAddress); |
extern long FlashProtectSet(unsigned long ulAddress, |
tFlashProtection eProtect); |
extern long FlashProtectSave(void); |
extern long FlashUserGet(unsigned long *pulUser0, unsigned long *pulUser1); |
extern long FlashUserSet(unsigned long ulUser0, unsigned long ulUser1); |
extern long FlashUserSave(void); |
extern void FlashIntRegister(void (*pfnHandler)(void)); |
extern void FlashIntUnregister(void); |
extern void FlashIntEnable(unsigned long ulIntFlags); |
extern void FlashIntDisable(unsigned long ulIntFlags); |
extern unsigned long FlashIntGetStatus(tBoolean bMasked); |
extern void FlashIntClear(unsigned long ulIntFlags); |
|
#ifdef __cplusplus |
} |
#endif |
|
#endif // __FLASH_H__ |
/drivers/LuminaryMicro/hw_hibernate.h
0,0 → 1,245
//***************************************************************************** |
// |
// hw_hibernate.h - Defines and Macros for the Hibernation module. |
// |
// Copyright (c) 2007-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_HIBERNATE_H__ |
#define __HW_HIBERNATE_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the Hibernation module register addresses. |
// |
//***************************************************************************** |
#define HIB_RTCC 0x400FC000 // Hibernate RTC counter |
#define HIB_RTCM0 0x400FC004 // Hibernate RTC match 0 |
#define HIB_RTCM1 0x400FC008 // Hibernate RTC match 1 |
#define HIB_RTCLD 0x400FC00C // Hibernate RTC load |
#define HIB_CTL 0x400FC010 // Hibernate RTC control |
#define HIB_IM 0x400FC014 // Hibernate interrupt mask |
#define HIB_RIS 0x400FC018 // Hibernate raw interrupt status |
#define HIB_MIS 0x400FC01C // Hibernate masked interrupt stat |
#define HIB_IC 0x400FC020 // Hibernate interrupt clear |
#define HIB_RTCT 0x400FC024 // Hibernate RTC trim |
#define HIB_DATA 0x400FC030 // Hibernate data area |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate RTC counter |
// register. |
// |
//***************************************************************************** |
#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter. |
#define HIB_RTCC_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate RTC match 0 |
// register. |
// |
//***************************************************************************** |
#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0. |
#define HIB_RTCM0_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate RTC match 1 |
// register. |
// |
//***************************************************************************** |
#define HIB_RTCM1_M 0xFFFFFFFF // RTC Match 1. |
#define HIB_RTCM1_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate RTC load |
// register. |
// |
//***************************************************************************** |
#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load. |
#define HIB_RTCLD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate control |
// register |
// |
//***************************************************************************** |
#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable. |
#define HIB_CTL_VABORT 0x00000080 // low bat abort |
#define HIB_CTL_CLK32EN 0x00000040 // enable clock/oscillator |
#define HIB_CTL_LOWBATEN 0x00000020 // enable low battery detect |
#define HIB_CTL_PINWEN 0x00000010 // enable wake on WAKE pin |
#define HIB_CTL_RTCWEN 0x00000008 // enable wake on RTC match |
#define HIB_CTL_CLKSEL 0x00000004 // clock input selection |
#define HIB_CTL_HIBREQ 0x00000002 // request hibernation |
#define HIB_CTL_RTCEN 0x00000001 // RTC enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate interrupt mask |
// reg. |
// |
//***************************************************************************** |
#define HIB_IM_EXTW 0x00000008 // wake from external pin interrupt |
#define HIB_IM_LOWBAT 0x00000004 // low battery interrupt |
#define HIB_IM_RTCALT1 0x00000002 // RTC match 1 interrupt |
#define HIB_IM_RTCALT0 0x00000001 // RTC match 0 interrupt |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate raw interrupt |
// status. |
// |
//***************************************************************************** |
#define HIB_RIS_EXTW 0x00000008 // wake from external pin interrupt |
#define HIB_RIS_LOWBAT 0x00000004 // low battery interrupt |
#define HIB_RIS_RTCALT1 0x00000002 // RTC match 1 interrupt |
#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert0 Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate masked int |
// status. |
// |
//***************************************************************************** |
#define HIB_MIS_EXTW 0x00000008 // wake from external pin interrupt |
#define HIB_MIS_LOWBAT 0x00000004 // low battery interrupt |
#define HIB_MIS_RTCALT1 0x00000002 // RTC match 1 interrupt |
#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt |
// Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate interrupt |
// clear reg. |
// |
//***************************************************************************** |
#define HIB_IC_EXTW 0x00000008 // wake from external pin interrupt |
#define HIB_IC_LOWBAT 0x00000004 // low battery interrupt |
#define HIB_IC_RTCALT1 0x00000002 // RTC match 1 interrupt |
#define HIB_IC_RTCALT0 0x00000001 // RTC match 0 interrupt |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate RTC trim |
// register. |
// |
//***************************************************************************** |
#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value. |
#define HIB_RTCT_TRIM_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the Hibernate data register. |
// |
//***************************************************************************** |
#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV |
// Registers[63:0]. |
#define HIB_DATA_RTD_S 0 |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the Hibernation module register |
// addresses. |
// |
//***************************************************************************** |
#define HIB_DATA_END 0x400FC130 // end of data area, exclusive |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate RTC |
// counter register. |
// |
//***************************************************************************** |
#define HIB_RTCC_MASK 0xFFFFFFFF // RTC counter mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate RTC |
// match 0 register. |
// |
//***************************************************************************** |
#define HIB_RTCM0_MASK 0xFFFFFFFF // RTC match 0 mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate RTC |
// match 1 register. |
// |
//***************************************************************************** |
#define HIB_RTCM1_MASK 0xFFFFFFFF // RTC match 1 mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate RTC |
// load register. |
// |
//***************************************************************************** |
#define HIB_RTCLD_MASK 0xFFFFFFFF // RTC load mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate raw |
// interrupt status. |
// |
//***************************************************************************** |
#define HIB_RID_RTCALT0 0x00000001 // RTC match 0 interrupt |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate |
// masked int status. |
// |
//***************************************************************************** |
#define HIB_MID_RTCALT0 0x00000001 // RTC match 0 interrupt |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate RTC |
// trim register. |
// |
//***************************************************************************** |
#define HIB_RTCT_MASK 0x0000FFFF // RTC trim mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the Hibernate |
// data register. |
// |
//***************************************************************************** |
#define HIB_DATA_MASK 0xFFFFFFFF // NV memory data mask |
|
#endif |
|
#endif // __HW_HIBERNATE_H__ |
/drivers/LuminaryMicro/watchdog.h
0,0 → 1,75
//***************************************************************************** |
// |
// watchdog.h - Prototypes for the Watchdog Timer API |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __WATCHDOG_H__ |
#define __WATCHDOG_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern tBoolean WatchdogRunning(unsigned long ulBase); |
extern void WatchdogEnable(unsigned long ulBase); |
extern void WatchdogResetEnable(unsigned long ulBase); |
extern void WatchdogResetDisable(unsigned long ulBase); |
extern void WatchdogLock(unsigned long ulBase); |
extern void WatchdogUnlock(unsigned long ulBase); |
extern tBoolean WatchdogLockState(unsigned long ulBase); |
extern void WatchdogReloadSet(unsigned long ulBase, unsigned long ulLoadVal); |
extern unsigned long WatchdogReloadGet(unsigned long ulBase); |
extern unsigned long WatchdogValueGet(unsigned long ulBase); |
extern void WatchdogIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); |
extern void WatchdogIntUnregister(unsigned long ulBase); |
extern void WatchdogIntEnable(unsigned long ulBase); |
extern unsigned long WatchdogIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void WatchdogIntClear(unsigned long ulBase); |
extern void WatchdogStallEnable(unsigned long ulBase); |
extern void WatchdogStallDisable(unsigned long ulBase); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __WATCHDOG_H__ |
/drivers/LuminaryMicro/hw_pwm.h
0,0 → 1,677
//***************************************************************************** |
// |
// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_PWM_H__ |
#define __HW_PWM_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the PWM Module Register offsets. |
// |
//***************************************************************************** |
#define PWM_O_CTL 0x00000000 // PWM Master Control register |
#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync register |
#define PWM_O_ENABLE 0x00000008 // PWM Output Enable register |
#define PWM_O_INVERT 0x0000000C // PWM Output Inversion register |
#define PWM_O_FAULT 0x00000010 // PWM Output Fault register |
#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable register |
#define PWM_O_RIS 0x00000018 // PWM Interrupt Raw Status reg. |
#define PWM_O_ISC 0x0000001C // PWM Interrupt Status register |
#define PWM_O_STATUS 0x00000020 // PWM Status register |
#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value |
#define PWM_O_0_CTL 0x00000040 // PWM0 Control |
#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger |
// Enable |
#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status |
#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear |
#define PWM_O_0_LOAD 0x00000050 // PWM0 Load |
#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter |
#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A |
#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B |
#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control |
#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control |
#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control |
#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay |
#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band |
// Falling-Edge-Delay |
#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0 |
#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period |
#define PWM_O_1_CTL 0x00000080 // PWM1 Control |
#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt Enable |
#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status |
#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear |
#define PWM_O_1_LOAD 0x00000090 // PWM1 Load |
#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter |
#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A |
#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B |
#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control |
#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control |
#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control |
#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay |
#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band |
// Falling-Edge-Delay |
#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0 |
#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period |
#define PWM_O_2_CTL 0x000000C0 // PWM2 Control |
#define PWM_O_2_INTEN 0x000000C4 // PWM2 InterruptEnable |
#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status |
#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear |
#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load |
#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter |
#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A |
#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B |
#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control |
#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control |
#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control |
#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay |
#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band |
// Falling-Edge-Delay |
#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0 |
#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period |
#define PWM_O_3_CTL 0x00000100 // PWM3 Control |
#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger |
// Enable |
#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status |
#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear |
#define PWM_O_3_LOAD 0x00000110 // PWM3 Load |
#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter |
#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A |
#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B |
#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control |
#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control |
#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control |
#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay |
#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band |
// Falling-Edge-Delay |
#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0 |
#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period |
#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense |
#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0 |
#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense |
#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0 |
#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense |
#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0 |
#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense |
#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Master Control |
// register. |
// |
//***************************************************************************** |
#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3. |
#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2. |
#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1. |
#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Time Base Sync |
// register. |
// |
//***************************************************************************** |
#define PWM_SYNC_SYNC3 0x00000008 // Reset generator 3 counter |
#define PWM_SYNC_SYNC2 0x00000004 // Reset generator 2 counter |
#define PWM_SYNC_SYNC1 0x00000002 // Reset generator 1 counter |
#define PWM_SYNC_SYNC0 0x00000001 // Reset generator 0 counter |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Output Enable |
// register. |
// |
//***************************************************************************** |
#define PWM_ENABLE_PWM7EN 0x00000080 // PWM7 pin enable |
#define PWM_ENABLE_PWM6EN 0x00000040 // PWM6 pin enable |
#define PWM_ENABLE_PWM5EN 0x00000020 // PWM5 pin enable |
#define PWM_ENABLE_PWM4EN 0x00000010 // PWM4 pin enable |
#define PWM_ENABLE_PWM3EN 0x00000008 // PWM3 pin enable |
#define PWM_ENABLE_PWM2EN 0x00000004 // PWM2 pin enable |
#define PWM_ENABLE_PWM1EN 0x00000002 // PWM1 pin enable |
#define PWM_ENABLE_PWM0EN 0x00000001 // PWM0 pin enable |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Inversion register. |
// |
//***************************************************************************** |
#define PWM_INVERT_PWM7INV 0x00000080 // PWM7 pin invert |
#define PWM_INVERT_PWM6INV 0x00000040 // PWM6 pin invert |
#define PWM_INVERT_PWM5INV 0x00000020 // PWM5 pin invert |
#define PWM_INVERT_PWM4INV 0x00000010 // PWM4 pin invert |
#define PWM_INVERT_PWM3INV 0x00000008 // PWM3 pin invert |
#define PWM_INVERT_PWM2INV 0x00000004 // PWM2 pin invert |
#define PWM_INVERT_PWM1INV 0x00000002 // PWM1 pin invert |
#define PWM_INVERT_PWM0INV 0x00000001 // PWM0 pin invert |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Fault register. |
// |
//***************************************************************************** |
#define PWM_FAULT_FAULT7 0x00000080 // PWM7 pin fault |
#define PWM_FAULT_FAULT6 0x00000040 // PWM6 pin fault |
#define PWM_FAULT_FAULT5 0x00000020 // PWM5 pin fault |
#define PWM_FAULT_FAULT4 0x00000010 // PWM4 pin fault |
#define PWM_FAULT_FAULT3 0x00000008 // PWM3 pin fault |
#define PWM_FAULT_FAULT2 0x00000004 // PWM2 pin fault |
#define PWM_FAULT_FAULT1 0x00000002 // PWM1 pin fault |
#define PWM_FAULT_FAULT0 0x00000001 // PWM0 pin fault |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM Status register. |
// |
//***************************************************************************** |
#define PWM_STATUS_FAULT3 0x00000008 // Fault3 Interrupt Status. |
#define PWM_STATUS_FAULT2 0x00000004 // Fault2 Interrupt Status. |
#define PWM_STATUS_FAULT1 0x00000002 // Fault1 Interrupt Status. |
#define PWM_STATUS_FAULT0 0x00000001 // Fault0 Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the PWM Generator standard offsets. |
// |
//***************************************************************************** |
#define PWM_O_X_CTL 0x00000000 // Gen Control Reg |
#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg |
#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg |
#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg |
#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg |
#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg |
#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg |
#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg |
#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg |
#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg |
#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg |
#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg |
#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg |
#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition |
#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension |
#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base |
#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base |
#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base |
#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base |
|
//***************************************************************************** |
// |
// The following are defines for the PWM_X Control Register bit definitions. |
// |
//***************************************************************************** |
#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input. |
#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum fault period enabled |
#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source. |
#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // Specifies the update mode for |
// the PWMnDBFALL register. |
#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate |
#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized |
#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized |
#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode. |
#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate |
#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized |
#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized |
#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode. |
#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate |
#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized |
#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized |
#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode. |
#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate |
#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized |
#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized |
#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode. |
#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate |
#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized |
#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized |
#define PWM_X_CTL_CMPBUPD 0x00000020 // Update mode for comp B reg |
#define PWM_X_CTL_CMPAUPD 0x00000010 // Update mode for comp A reg |
#define PWM_X_CTL_LOADUPD 0x00000008 // Update mode for the load reg |
#define PWM_X_CTL_DEBUG 0x00000004 // Debug mode |
#define PWM_X_CTL_MODE 0x00000002 // Counter mode, down or up/down |
#define PWM_X_CTL_ENABLE 0x00000001 // Master enable for gen block |
|
//***************************************************************************** |
// |
// The following are defines for the PWM Generator extended offsets. |
// |
//***************************************************************************** |
#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense |
#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status |
#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base |
#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base |
#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base |
#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base |
|
//***************************************************************************** |
// |
// The following are defines for the PWM_X Interrupt/Trigger Enable Register |
// bit definitions. |
// |
//***************************************************************************** |
#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trig if COUNT = CMPA D |
#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trig if COUNT = CMPA U |
#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trig if COUNT = CMPA D |
#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trig if COUNT = CMPA U |
#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trig if COUNT = LOAD |
#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trig if COUNT = 0 |
#define PWM_X_INTEN_INTCMPBD 0x00000020 // Int if COUNT = CMPA D |
#define PWM_X_INTEN_INTCMPBU 0x00000010 // Int if COUNT = CMPA U |
#define PWM_X_INTEN_INTCMPAD 0x00000008 // Int if COUNT = CMPA D |
#define PWM_X_INTEN_INTCMPAU 0x00000004 // Int if COUNT = CMPA U |
#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Int if COUNT = LOAD |
#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Int if COUNT = 0 |
|
//***************************************************************************** |
// |
// The following are defines for the PWM_X Raw Interrupt Status Register bit |
// definitions. |
// |
//***************************************************************************** |
#define PWM_X_RIS_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D int |
#define PWM_X_RIS_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U int |
#define PWM_X_RIS_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D int |
#define PWM_X_RIS_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U int |
#define PWM_X_RIS_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD int |
#define PWM_X_RIS_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 int |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_INTEN register. |
// |
//***************************************************************************** |
#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3. |
#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2. |
#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1. |
#define PWM_INTEN_INTFAULT 0x00010000 // Fault Interrupt Enable. |
#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0. |
#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable. |
#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable. |
#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable. |
#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_RIS register. |
// |
//***************************************************************************** |
#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3. |
#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2. |
#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1. |
#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0. |
#define PWM_RIS_INTFAULT 0x00010000 // Fault Interrupt Asserted. |
#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted. |
#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted. |
#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted. |
#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_ISC register. |
// |
//***************************************************************************** |
#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted. |
#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted. |
#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted. |
#define PWM_ISC_INTFAULT 0x00010000 // Fault Interrupt Asserted. |
#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted. |
#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status. |
#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status. |
#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status. |
#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_ISC register. |
// |
//***************************************************************************** |
#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt. |
#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt. |
#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt. |
#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt. |
#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt. |
#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_LOAD register. |
// |
//***************************************************************************** |
#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value. |
#define PWM_X_LOAD_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_COUNT register. |
// |
//***************************************************************************** |
#define PWM_X_COUNT_M 0x0000FFFF // Counter Value. |
#define PWM_X_COUNT_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_CMPA register. |
// |
//***************************************************************************** |
#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value. |
#define PWM_X_CMPA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_CMPB register. |
// |
//***************************************************************************** |
#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value. |
#define PWM_X_CMPB_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_GENA register. |
// |
//***************************************************************************** |
#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. |
#define PWM_X_GENA_ACTCMPBD_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert the output signal. |
#define PWM_X_GENA_ACTCMPBD_ZERO \ |
0x00000800 // Set the output signal to 0. |
#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. |
#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. |
#define PWM_X_GENA_ACTCMPBU_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert the output signal. |
#define PWM_X_GENA_ACTCMPBU_ZERO \ |
0x00000200 // Set the output signal to 0. |
#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. |
#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. |
#define PWM_X_GENA_ACTCMPAD_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert the output signal. |
#define PWM_X_GENA_ACTCMPAD_ZERO \ |
0x00000080 // Set the output signal to 0. |
#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. |
#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. |
#define PWM_X_GENA_ACTCMPAU_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert the output signal. |
#define PWM_X_GENA_ACTCMPAU_ZERO \ |
0x00000020 // Set the output signal to 0. |
#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. |
#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=Load. |
#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert the output signal. |
#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. |
#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. |
#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0. |
#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing. |
#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert the output signal. |
#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. |
#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Set the output signal to 1. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_GENB register. |
// |
//***************************************************************************** |
#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down. |
#define PWM_X_GENB_ACTCMPBD_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert the output signal. |
#define PWM_X_GENB_ACTCMPBD_ZERO \ |
0x00000800 // Set the output signal to 0. |
#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Set the output signal to 1. |
#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up. |
#define PWM_X_GENB_ACTCMPBU_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert the output signal. |
#define PWM_X_GENB_ACTCMPBU_ZERO \ |
0x00000200 // Set the output signal to 0. |
#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Set the output signal to 1. |
#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down. |
#define PWM_X_GENB_ACTCMPAD_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert the output signal. |
#define PWM_X_GENB_ACTCMPAD_ZERO \ |
0x00000080 // Set the output signal to 0. |
#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Set the output signal to 1. |
#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up. |
#define PWM_X_GENB_ACTCMPAU_NONE \ |
0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert the output signal. |
#define PWM_X_GENB_ACTCMPAU_ZERO \ |
0x00000020 // Set the output signal to 0. |
#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Set the output signal to 1. |
#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=Load. |
#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert the output signal. |
#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Set the output signal to 0. |
#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Set the output signal to 1. |
#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0. |
#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing. |
#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert the output signal. |
#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Set the output signal to 0. |
#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Set the output signal to 1. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_DBCTL register. |
// |
//***************************************************************************** |
#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_DBRISE register. |
// |
//***************************************************************************** |
#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay. |
#define PWM_X_DBRISE_DELAY_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_DBFALL register. |
// |
//***************************************************************************** |
#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay. |
#define PWM_X_DBFALL_DELAY_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_FAULTVAL register. |
// |
//***************************************************************************** |
#define PWM_FAULTVAL_PWM7 0x00000080 // PWM7 Fault Value. |
#define PWM_FAULTVAL_PWM6 0x00000040 // PWM6 Fault Value. |
#define PWM_FAULTVAL_PWM5 0x00000020 // PWM5 Fault Value. |
#define PWM_FAULTVAL_PWM4 0x00000010 // PWM4 Fault Value. |
#define PWM_FAULTVAL_PWM3 0x00000008 // PWM3 Fault Value. |
#define PWM_FAULTVAL_PWM2 0x00000004 // PWM2 Fault Value. |
#define PWM_FAULTVAL_PWM1 0x00000002 // PWM1 Fault Value. |
#define PWM_FAULTVAL_PWM0 0x00000001 // PWM0 Fault Value. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_MINFLTPER |
// register. |
// |
//***************************************************************************** |
#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period. |
#define PWM_X_MINFLTPER_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_FLTSEN register. |
// |
//***************************************************************************** |
#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense. |
#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense. |
#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense. |
#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_FLTSRC0 |
// register. |
// |
//***************************************************************************** |
#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3. |
#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2. |
#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1. |
#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0 |
// register. |
// |
//***************************************************************************** |
#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3. |
#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2. |
#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1. |
#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the PWM Master |
// Control register. |
// |
//***************************************************************************** |
#define PWM_CTL_GLOBAL_SYNC2 0x00000004 // Global sync generator 2 |
#define PWM_CTL_GLOBAL_SYNC1 0x00000002 // Global sync generator 1 |
#define PWM_CTL_GLOBAL_SYNC0 0x00000001 // Global sync generator 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM Interrupt Register bit |
// definitions. |
// |
//***************************************************************************** |
#define PWM_INT_INTFAULT 0x00010000 // Fault interrupt pending |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the PWM Status |
// register. |
// |
//***************************************************************************** |
#define PWM_STATUS_FAULT 0x00000001 // Fault status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM_X Interrupt Status Register |
// bit definitions. |
// |
//***************************************************************************** |
#define PWM_X_INT_INTCMPBD 0x00000020 // PWM_X_COUNT = PWM_X_CMPB D rcvd |
#define PWM_X_INT_INTCMPBU 0x00000010 // PWM_X_COUNT = PWM_X_CMPB U rcvd |
#define PWM_X_INT_INTCMPAD 0x00000008 // PWM_X_COUNT = PWM_X_CMPA D rcvd |
#define PWM_X_INT_INTCMPAU 0x00000004 // PWM_X_COUNT = PWM_X_CMPA U rcvd |
#define PWM_X_INT_INTCNTLOAD 0x00000002 // PWM_X_COUNT = PWM_X_LOAD rcvd |
#define PWM_X_INT_INTCNTZERO 0x00000001 // PWM_X_COUNT = 0 received |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM_X Generator A/B Control |
// Register bit definitions. |
// |
//***************************************************************************** |
#define PWM_X_GEN_Y_ACTCMPBD 0x00000C00 // Act PWM_X_COUNT = PWM_X_CMPB D |
#define PWM_X_GEN_Y_ACTCMPBU 0x00000300 // Act PWM_X_COUNT = PWM_X_CMPB U |
#define PWM_X_GEN_Y_ACTCMPAD 0x000000C0 // Act PWM_X_COUNT = PWM_X_CMPA D |
#define PWM_X_GEN_Y_ACTCMPAU 0x00000030 // Act PWM_X_COUNT = PWM_X_CMPA U |
#define PWM_X_GEN_Y_ACTLOAD 0x0000000C // Act PWM_X_COUNT = PWM_X_LOAD |
#define PWM_X_GEN_Y_ACTZERO 0x00000003 // Act PWM_X_COUNT = 0 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM_X Generator A/B Control |
// Register action definitions. |
// |
//***************************************************************************** |
#define PWM_GEN_ACT_ONE 0x00000003 // Set the output signal to one |
#define PWM_GEN_ACT_ZERO 0x00000002 // Set the output signal to zero |
#define PWM_GEN_ACT_INV 0x00000001 // Invert the output signal |
#define PWM_GEN_ACT_NONE 0x00000000 // Do nothing |
#define PWM_GEN_ACT_B_DN_SHIFT 10 // Shift amount for the B dn action |
#define PWM_GEN_ACT_B_UP_SHIFT 8 // Shift amount for the B up action |
#define PWM_GEN_ACT_A_DN_SHIFT 6 // Shift amount for the A dn action |
#define PWM_GEN_ACT_A_UP_SHIFT 4 // Shift amount for the A up action |
#define PWM_GEN_ACT_LOAD_SHIFT 2 // Shift amount for the load action |
#define PWM_GEN_ACT_ZERO_SHIFT 0 // Shift amount for the zero action |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM_X Dead Band Control |
// Register bit definitions. |
// |
//***************************************************************************** |
#define PWM_DBCTL_ENABLE 0x00000001 // Enable dead band insertion |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the PWM Register reset values. |
// |
//***************************************************************************** |
#define PWM_RV_X_DBCTL 0x00000000 // Control the dead band generator |
#define PWM_RV_STATUS 0x00000000 // Status |
#define PWM_RV_X_ISC 0x00000000 // Interrupt status and clearing |
#define PWM_RV_X_RIS 0x00000000 // Raw interrupt status |
#define PWM_RV_X_CTL 0x00000000 // Master control of the PWM |
// generator block |
#define PWM_RV_SYNC 0x00000000 // Counter synch for PWM generators |
#define PWM_RV_X_DBFALL 0x00000000 // The dead band falling edge delay |
// count |
#define PWM_RV_X_INTEN 0x00000000 // Interrupt and trigger enable |
#define PWM_RV_X_LOAD 0x00000000 // The load value for the counter |
#define PWM_RV_X_GENA 0x00000000 // Controls PWM generator A |
#define PWM_RV_CTL 0x00000000 // Master control of the PWM module |
#define PWM_RV_FAULT 0x00000000 // Fault handling for the PWM |
// output pins |
#define PWM_RV_RIS 0x00000000 // Raw interrupt status |
#define PWM_RV_X_CMPA 0x00000000 // The comparator A value |
#define PWM_RV_INVERT 0x00000000 // Inversion control for PWM output |
// pins |
#define PWM_RV_X_DBRISE 0x00000000 // The dead band rising edge delay |
// count |
#define PWM_RV_ENABLE 0x00000000 // Master enable for the PWM output |
// pins |
#define PWM_RV_X_GENB 0x00000000 // Controls PWM generator B |
#define PWM_RV_X_CMPB 0x00000000 // The comparator B value |
#define PWM_RV_ISC 0x00000000 // Interrupt status and clearing |
#define PWM_RV_INTEN 0x00000000 // Interrupt enable |
#define PWM_RV_X_COUNT 0x00000000 // The current counter value |
|
#endif |
|
#endif // __HW_PWM_H__ |
/drivers/LuminaryMicro/can.h
0,0 → 1,453
//***************************************************************************** |
// |
// can.h - Defines and Macros for the CAN controller. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __CAN_H__ |
#define __CAN_H__ |
|
//***************************************************************************** |
// |
//! \addtogroup can_api |
//! @{ |
// |
//***************************************************************************** |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Miscellaneous defines for Message ID Types |
// |
//***************************************************************************** |
|
//***************************************************************************** |
// |
//! These are the flags used by the tCANMsgObject variable when calling the |
//! CANMessageSet() and CANMessageGet() functions. |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! This indicates that transmit interrupts should be enabled, or are |
//! enabled. |
// |
MSG_OBJ_TX_INT_ENABLE = 0x00000001, |
|
// |
//! This indicates that receive interrupts should be enabled, or are |
//! enabled. |
// |
MSG_OBJ_RX_INT_ENABLE = 0x00000002, |
|
// |
//! This indicates that a message object will use or is using an extended |
//! identifier. |
// |
MSG_OBJ_EXTENDED_ID = 0x00000004, |
|
// |
//! This indicates that a message object will use or is using filtering |
//! based on the object's message identifier. |
// |
MSG_OBJ_USE_ID_FILTER = 0x00000008, |
|
// |
//! This indicates that new data was available in the message object. |
// |
MSG_OBJ_NEW_DATA = 0x00000080, |
|
// |
//! This indicates that data was lost since this message object was last |
//! read. |
// |
MSG_OBJ_DATA_LOST = 0x00000100, |
|
// |
//! This indicates that a message object will use or is using filtering |
//! based on the direction of the transfer. If the direction filtering is |
//! used, then ID filtering must also be enabled. |
// |
MSG_OBJ_USE_DIR_FILTER = (0x00000010 | MSG_OBJ_USE_ID_FILTER), |
|
// |
//! This indicates that a message object will use or is using message |
//! identifier filtering based on the extended identifier. If the extended |
//! identifier filtering is used, then ID filtering must also be enabled. |
// |
MSG_OBJ_USE_EXT_FILTER = (0x00000020 | MSG_OBJ_USE_ID_FILTER), |
|
// |
//! This indicates that a message object is a remote frame. |
// |
MSG_OBJ_REMOTE_FRAME = 0x00000040, |
|
// |
//! This indicates that a message object has no flags set. |
// |
MSG_OBJ_NO_FLAGS = 0x00000000 |
} |
tCANObjFlags; |
|
//***************************************************************************** |
// |
//! This define is used with the #tCANObjFlags enumerated values to allow |
//! checking only status flags and not configuration flags. |
// |
//***************************************************************************** |
#define MSG_OBJ_STATUS_MASK (MSG_OBJ_NEW_DATA | MSG_OBJ_DATA_LOST) |
|
//***************************************************************************** |
// |
//! The structure used for encapsulating all the items associated with a CAN |
//! message object in the CAN controller. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! The CAN message identifier used for 11 or 29 bit identifiers. |
// |
unsigned long ulMsgID; |
|
// |
//! The message identifier mask used when identifier filtering is enabled. |
// |
unsigned long ulMsgIDMask; |
|
// |
//! This value holds various status flags and settings specified by |
//! tCANObjFlags. |
// |
unsigned long ulFlags; |
|
// |
//! This value is the number of bytes of data in the message object. |
// |
unsigned long ulMsgLen; |
|
// |
//! This is a pointer to the message object's data. |
// |
unsigned char *pucMsgData; |
} |
tCANMsgObject; |
|
//***************************************************************************** |
// |
//! This structure is used for encapsulating the values associated with setting |
//! up the bit timing for a CAN controller. The structure is used when calling |
//! the CANGetBitTiming and CANSetBitTiming functions. |
// |
//***************************************************************************** |
typedef struct |
{ |
// |
//! This value holds the sum of the Synchronization, Propagation, and Phase |
//! Buffer 1 segments, measured in time quanta. The valid values for this |
//! setting range from 2 to 16. |
// |
unsigned int uSyncPropPhase1Seg; |
|
// |
//! This value holds the Phase Buffer 2 segment in time quanta. The valid |
//! values for this setting range from 1 to 8. |
// |
unsigned int uPhase2Seg; |
|
// |
//! This value holds the Resynchronization Jump Width in time quanta. The |
//! valid values for this setting range from 1 to 4. |
// |
unsigned int uSJW; |
|
// |
//! This value holds the CAN_CLK divider used to determine time quanta. |
//! The valid values for this setting range from 1 to 1023. |
// |
unsigned int uQuantumPrescaler; |
|
} |
tCANBitClkParms; |
|
//***************************************************************************** |
// |
//! This data type is used to identify the interrupt status register. This is |
//! used when calling the CANIntStatus() function. |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! Read the CAN interrupt status information. |
// |
CAN_INT_STS_CAUSE, |
|
// |
//! Read a message object's interrupt status. |
// |
CAN_INT_STS_OBJECT |
} |
tCANIntStsReg; |
|
//***************************************************************************** |
// |
//! This data type is used to identify which of several status registers to |
//! read when calling the CANStatusGet() function. |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! Read the full CAN controller status. |
// |
CAN_STS_CONTROL, |
|
// |
//! Read the full 32-bit mask of message objects with a transmit request |
//! set. |
// |
CAN_STS_TXREQUEST, |
|
// |
//! Read the full 32-bit mask of message objects with new data available. |
// |
CAN_STS_NEWDAT, |
|
// |
//! Read the full 32-bit mask of message objects that are enabled. |
// |
CAN_STS_MSGVAL |
} |
tCANStsReg; |
|
//***************************************************************************** |
// |
//! These definitions are used to specify interrupt sources to CANIntEnable() |
//! and CANIntDisable(). |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! This flag is used to allow a CAN controller to generate error |
//! interrupts. |
// |
CAN_INT_ERROR = 0x00000008, |
|
// |
//! This flag is used to allow a CAN controller to generate status |
//! interrupts. |
// |
CAN_INT_STATUS = 0x00000004, |
|
// |
//! This flag is used to allow a CAN controller to generate any CAN |
//! interrupts. If this is not set, then no interrupts will be generated |
//! by the CAN controller. |
// |
CAN_INT_MASTER = 0x00000002 |
} |
tCANIntFlags; |
|
//***************************************************************************** |
// |
//! This definition is used to determine the type of message object that will |
//! be set up via a call to the CANMessageSet() API. |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! Transmit message object. |
// |
MSG_OBJ_TYPE_TX, |
|
// |
//! Transmit remote request message object |
// |
MSG_OBJ_TYPE_TX_REMOTE, |
|
// |
//! Receive message object. |
// |
MSG_OBJ_TYPE_RX, |
|
// |
//! Receive remote request message object. |
// |
MSG_OBJ_TYPE_RX_REMOTE, |
|
// |
//! Remote frame receive remote, with auto-transmit message object. |
// |
MSG_OBJ_TYPE_RXTX_REMOTE |
} |
tMsgObjType; |
|
//***************************************************************************** |
// |
//! The following enumeration contains all error or status indicators that can |
//! be returned when calling the CANStatusGet() function. |
// |
//***************************************************************************** |
typedef enum |
{ |
// |
//! CAN controller has entered a Bus Off state. |
// |
CAN_STATUS_BUS_OFF = 0x00000080, |
|
// |
//! CAN controller error level has reached warning level. |
// |
CAN_STATUS_EWARN = 0x00000040, |
|
// |
//! CAN controller error level has reached error passive level. |
// |
CAN_STATUS_EPASS = 0x00000020, |
|
// |
//! A message was received successfully since the last read of this status. |
// |
CAN_STATUS_RXOK = 0x00000010, |
|
// |
//! A message was transmitted successfully since the last read of this |
//! status. |
// |
CAN_STATUS_TXOK = 0x00000008, |
|
// |
//! This is the mask for the last error code field. |
// |
CAN_STATUS_LEC_MSK = 0x00000007, |
|
// |
//! There was no error. |
// |
CAN_STATUS_LEC_NONE = 0x00000000, |
|
// |
//! A bit stuffing error has occurred. |
// |
CAN_STATUS_LEC_STUFF = 0x00000001, |
|
// |
//! A formatting error has occurred. |
// |
CAN_STATUS_LEC_FORM = 0x00000002, |
|
// |
//! An acknowledge error has occurred. |
// |
CAN_STATUS_LEC_ACK = 0x00000003, |
|
// |
//! The bus remained a bit level of 1 for longer than is allowed. |
// |
CAN_STATUS_LEC_BIT1 = 0x00000004, |
|
// |
//! The bus remained a bit level of 0 for longer than is allowed. |
// |
CAN_STATUS_LEC_BIT0 = 0x00000005, |
|
// |
//! A CRC error has occurred. |
// |
CAN_STATUS_LEC_CRC = 0x00000006, |
|
// |
//! This is the mask for the CAN Last Error Code (LEC). |
// |
CAN_STATUS_LEC_MASK = 0x00000007 |
} |
tCANStatusCtrl; |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void CANInit(unsigned long ulBase); |
extern void CANEnable(unsigned long ulBase); |
extern void CANDisable(unsigned long ulBase); |
extern void CANSetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); |
extern void CANGetBitTiming(unsigned long ulBase, tCANBitClkParms *pClkParms); |
extern unsigned long CANReadReg(unsigned long ulRegAddress); |
extern void CANWriteReg(unsigned long ulRegAddress, unsigned long ulRegValue); |
extern void CANMessageSet(unsigned long ulBase, unsigned long ulObjID, |
tCANMsgObject *pMsgObject, tMsgObjType eMsgType); |
extern void CANMessageGet(unsigned long ulBase, unsigned long ulObjID, |
tCANMsgObject *pMsgObject, tBoolean bClrPendingInt); |
extern unsigned long CANStatusGet(unsigned long ulBase, tCANStsReg eStatusReg); |
extern void CANMessageClear(unsigned long ulBase, unsigned long ulObjID); |
extern void CANIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); |
extern void CANIntUnregister(unsigned long ulBase); |
extern void CANIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void CANIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void CANIntClear(unsigned long ulBase, unsigned long ulIntClr); |
extern unsigned long CANIntStatus(unsigned long ulBase, |
tCANIntStsReg eIntStsReg); |
extern tBoolean CANRetryGet(unsigned long ulBase); |
extern void CANRetrySet(unsigned long ulBase, tBoolean bAutoRetry); |
extern tBoolean CANErrCntrGet(unsigned long ulBase, unsigned long *pulRxCount, |
unsigned long *pulTxCount); |
extern long CANGetIntNumber(unsigned long ulBase); |
extern void CANReadDataReg(unsigned char *pucData, unsigned long *pulRegister, |
int iSize); |
extern void CANWriteDataReg(unsigned char *pucData, unsigned long *pulRegister, |
int iSize); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
//***************************************************************************** |
// |
// Close the Doxygen group. |
//! @} |
// |
//***************************************************************************** |
|
#endif // __CAN_H__ |
/drivers/LuminaryMicro/mpu.h
0,0 → 1,151
//***************************************************************************** |
// |
// mpu.h - Defines and Macros for the memory protection unit. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __MPU_H__ |
#define __MPU_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Flags that can be passed to MPUEnable.. |
// |
//***************************************************************************** |
#define MPU_CONFIG_PRIV_DEFAULT 4 |
#define MPU_CONFIG_HARDFLT_NMI 2 |
#define MPU_CONFIG_NONE 0 |
|
//***************************************************************************** |
// |
// Flags for the region size to be passed to MPURegionSet. |
// |
//***************************************************************************** |
#define MPU_RGN_SIZE_32B (4 << 1) |
#define MPU_RGN_SIZE_64B (5 << 1) |
#define MPU_RGN_SIZE_128B (6 << 1) |
#define MPU_RGN_SIZE_256B (7 << 1) |
#define MPU_RGN_SIZE_512B (8 << 1) |
|
#define MPU_RGN_SIZE_1K (9 << 1) |
#define MPU_RGN_SIZE_2K (10 << 1) |
#define MPU_RGN_SIZE_4K (11 << 1) |
#define MPU_RGN_SIZE_8K (12 << 1) |
#define MPU_RGN_SIZE_16K (13 << 1) |
#define MPU_RGN_SIZE_32K (14 << 1) |
#define MPU_RGN_SIZE_64K (15 << 1) |
#define MPU_RGN_SIZE_128K (16 << 1) |
#define MPU_RGN_SIZE_256K (17 << 1) |
#define MPU_RGN_SIZE_512K (18 << 1) |
|
#define MPU_RGN_SIZE_1M (19 << 1) |
#define MPU_RGN_SIZE_2M (20 << 1) |
#define MPU_RGN_SIZE_4M (21 << 1) |
#define MPU_RGN_SIZE_8M (22 << 1) |
#define MPU_RGN_SIZE_16M (23 << 1) |
#define MPU_RGN_SIZE_32M (24 << 1) |
#define MPU_RGN_SIZE_64M (25 << 1) |
#define MPU_RGN_SIZE_128M (26 << 1) |
#define MPU_RGN_SIZE_256M (27 << 1) |
#define MPU_RGN_SIZE_512M (28 << 1) |
|
#define MPU_RGN_SIZE_1G (29 << 1) |
#define MPU_RGN_SIZE_2G (30 << 1) |
#define MPU_RGN_SIZE_4G (31 << 1) |
|
//***************************************************************************** |
// |
// Flags for the permissions to be passed to MPURegionSet. |
// |
//***************************************************************************** |
#define MPU_RGN_PERM_EXEC 0x00000000 |
#define MPU_RGN_PERM_NOEXEC 0x10000000 |
#define MPU_RGN_PERM_PRV_NO_USR_NO 0x00000000 |
#define MPU_RGN_PERM_PRV_RW_USR_NO 0x01000000 |
#define MPU_RGN_PERM_PRV_RW_USR_RO 0x02000000 |
#define MPU_RGN_PERM_PRV_RW_USR_RW 0x03000000 |
#define MPU_RGN_PERM_PRV_RO_USR_NO 0x05000000 |
#define MPU_RGN_PERM_PRV_RO_USR_RO 0x06000000 |
|
//***************************************************************************** |
// |
// Flags for the sub-region to be passed to MPURegionSet. |
// |
//***************************************************************************** |
#define MPU_SUB_RGN_DISABLE_0 0x00000100 |
#define MPU_SUB_RGN_DISABLE_1 0x00000200 |
#define MPU_SUB_RGN_DISABLE_2 0x00000400 |
#define MPU_SUB_RGN_DISABLE_3 0x00000800 |
#define MPU_SUB_RGN_DISABLE_4 0x00001000 |
#define MPU_SUB_RGN_DISABLE_5 0x00002000 |
#define MPU_SUB_RGN_DISABLE_6 0x00004000 |
#define MPU_SUB_RGN_DISABLE_7 0x00008000 |
|
//***************************************************************************** |
// |
// Flags to enable or disable a region, to be passed to MPURegionSet. |
// |
//***************************************************************************** |
#define MPU_RGN_ENABLE 1 |
#define MPU_RGN_DISABLE 0 |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void MPUEnable(unsigned long ulMPUConfig); |
extern void MPUDisable(void); |
extern unsigned long MPURegionCountGet(void); |
extern void MPURegionEnable(unsigned long ulRegion); |
extern void MPURegionDisable(unsigned long ulRegion); |
extern void MPURegionSet(unsigned long ulRegion, unsigned long ulAddr, |
unsigned long ulFlags); |
extern void MPURegionGet(unsigned long ulRegion, unsigned long *pulAddr, |
unsigned long *pulFlags); |
extern void MPUIntRegister(void (*pfnHandler)(void)); |
extern void MPUIntUnregister(void); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __MPU_H__ |
/drivers/LuminaryMicro/hw_types.h
0,0 → 1,153
//***************************************************************************** |
// |
// hw_types.h - Common types and macros. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_TYPES_H__ |
#define __HW_TYPES_H__ |
|
//***************************************************************************** |
// |
// Define a boolean type, and values for true and false. |
// |
//***************************************************************************** |
typedef unsigned char tBoolean; |
|
#ifndef true |
#define true 1 |
#endif |
|
#ifndef false |
#define false 0 |
#endif |
|
//***************************************************************************** |
// |
// Macros for hardware access, both direct and via the bit-band region. |
// |
//***************************************************************************** |
#define HWREG(x) \ |
(*((volatile unsigned long *)(x))) |
#define HWREGH(x) \ |
(*((volatile unsigned short *)(x))) |
#define HWREGB(x) \ |
(*((volatile unsigned char *)(x))) |
#define HWREGBITW(x, b) \ |
HWREG(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ |
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) |
#define HWREGBITH(x, b) \ |
HWREGH(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ |
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) |
#define HWREGBITB(x, b) \ |
HWREGB(((unsigned long)(x) & 0xF0000000) | 0x02000000 | \ |
(((unsigned long)(x) & 0x000FFFFF) << 5) | ((b) << 2)) |
|
//***************************************************************************** |
// |
// Helper Macros for determining silicon revisions, etc. |
// |
// These macros will be used by Driverlib at "run-time" to create necessary |
// conditional code blocks that will allow a single version of the Driverlib |
// "binary" code to support multiple(all) Stellaris silicon revisions. |
// |
// It is expected that these macros will be used inside of a standard 'C' |
// conditional block of code, e.g. |
// |
// if(CLASS_IS_SANDSTORM) |
// { |
// do some Sandstorm-class specific code here. |
// } |
// |
// By default, these macros will be defined as run-time checks of the |
// appropriate register(s) to allow creation of run-time conditional code |
// blocks for a common DriverLib across the entire Stellaris family. |
// |
// However, if code-space optimization is required, these macros can be "hard- |
// coded" for a specific version of Stellaris silicon. Many compilers will |
// then detect the "hard-coded" conditionals, and appropriately optimize the |
// code blocks, eliminating any "unreachable" code. This would result in |
// a smaller Driverlib, thus producing a smaller final application size, but |
// at the cost of limiting the Driverlib binary to a specific Stellaris |
// silicon revision. |
// |
//***************************************************************************** |
#ifndef CLASS_IS_SANDSTORM |
#define CLASS_IS_SANDSTORM \ |
(((HWREG(SYSCTL_DID0) & SYSCTL_DID0_VER_M) == SYSCTL_DID0_VER_0) || \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ |
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_SANDSTORM))) |
#endif |
|
#ifndef CLASS_IS_FURY |
#define CLASS_IS_FURY \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ |
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_FURY)) |
#endif |
|
#ifndef CLASS_IS_DUSTDEVIL |
#define CLASS_IS_DUSTDEVIL \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \ |
(SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_DUSTDEVIL)) |
#endif |
|
#ifndef REVISION_IS_A0 |
#define REVISION_IS_A0 \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ |
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0)) |
#endif |
|
#ifndef REVISION_IS_A2 |
#define REVISION_IS_A2 \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ |
(SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2)) |
#endif |
|
#ifndef REVISION_IS_C1 |
#define REVISION_IS_C1 \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ |
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_1)) |
#endif |
|
#ifndef REVISION_IS_C2 |
#define REVISION_IS_C2 \ |
((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \ |
(SYSCTL_DID0_MAJ_REVC | SYSCTL_DID0_MIN_2)) |
#endif |
|
//***************************************************************************** |
// |
// Deprecated silicon class and revision detection macros. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#define DEVICE_IS_SANDSTORM CLASS_IS_SANDSTORM |
#define DEVICE_IS_FURY CLASS_IS_FURY |
#define DEVICE_IS_REVA2 REVISION_IS_A2 |
#define DEVICE_IS_REVC1 REVISION_IS_C1 |
#define DEVICE_IS_REVC2 REVISION_IS_C2 |
#endif |
|
#endif // __HW_TYPES_H__ |
/drivers/LuminaryMicro/hw_i2c.h
0,0 → 1,413
//***************************************************************************** |
// |
// hw_i2c.h - Macros used when accessing the I2C master and slave hardware. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __HW_I2C_H__ |
#define __HW_I2C_H__ |
|
//***************************************************************************** |
// |
// The following are defines for the offsets between the I2C master and slave |
// registers. |
// |
//***************************************************************************** |
#define I2C_O_MSA 0x00000000 // I2C Master Slave Address |
#define I2C_O_SOAR 0x00000000 // I2C Slave Own Address |
#define I2C_O_SCSR 0x00000004 // I2C Slave Control/Status |
#define I2C_O_MCS 0x00000004 // I2C Master Control/Status |
#define I2C_O_SDR 0x00000008 // I2C Slave Data |
#define I2C_O_MDR 0x00000008 // I2C Master Data |
#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period |
#define I2C_O_SIMR 0x0000000C // I2C Slave Interrupt Mask |
#define I2C_O_SRIS 0x00000010 // I2C Slave Raw Interrupt Status |
#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask |
#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status |
#define I2C_O_SMIS 0x00000014 // I2C Slave Masked Interrupt |
// Status |
#define I2C_O_SICR 0x00000018 // I2C Slave Interrupt Clear |
#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt |
// Status |
#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear |
#define I2C_O_MCR 0x00000020 // I2C Master Configuration |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MSA register. |
// |
//***************************************************************************** |
#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address. |
#define I2C_MSA_RS 0x00000001 // Receive not Send |
#define I2C_MSA_SA_S 1 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SOAR register. |
// |
//***************************************************************************** |
#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address. |
#define I2C_SOAR_OAR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SCSR register. |
// |
//***************************************************************************** |
#define I2C_SCSR_FBR 0x00000004 // First Byte Received. |
#define I2C_SCSR_TREQ 0x00000002 // Transmit Request. |
#define I2C_SCSR_DA 0x00000001 // Device Active. |
#define I2C_SCSR_RREQ 0x00000001 // Receive Request. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MCS register. |
// |
//***************************************************************************** |
#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy. |
#define I2C_MCS_IDLE 0x00000020 // I2C Idle. |
#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost. |
#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable. |
#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data. |
#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address. |
#define I2C_MCS_STOP 0x00000004 // Generate STOP. |
#define I2C_MCS_START 0x00000002 // Generate START. |
#define I2C_MCS_ERROR 0x00000002 // Error. |
#define I2C_MCS_RUN 0x00000001 // I2C Master Enable. |
#define I2C_MCS_BUSY 0x00000001 // I2C Busy. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SDR register. |
// |
//***************************************************************************** |
#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer. |
#define I2C_SDR_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MDR register. |
// |
//***************************************************************************** |
#define I2C_MDR_DATA_M 0x000000FF // Data Transferred. |
#define I2C_MDR_DATA_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MTPR register. |
// |
//***************************************************************************** |
#define I2C_MTPR_TPR_M 0x000000FF // SCL Clock Period. |
#define I2C_MTPR_TPR_S 0 |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SIMR register. |
// |
//***************************************************************************** |
#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask. |
#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask. |
#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SRIS register. |
// |
//***************************************************************************** |
#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt |
// Status. |
#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt |
// Status. |
#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MIMR register. |
// |
//***************************************************************************** |
#define I2C_MIMR_IM 0x00000001 // Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MRIS register. |
// |
//***************************************************************************** |
#define I2C_MRIS_RIS 0x00000001 // Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SMIS register. |
// |
//***************************************************************************** |
#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt |
// Status. |
#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt |
// Status. |
#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_SICR register. |
// |
//***************************************************************************** |
#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear. |
#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear. |
#define I2C_SICR_DATAIC 0x00000001 // Data Clear Interrupt. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MMIS register. |
// |
//***************************************************************************** |
#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MICR register. |
// |
//***************************************************************************** |
#define I2C_MICR_IC 0x00000001 // Interrupt Clear. |
|
//***************************************************************************** |
// |
// The following are defines for the bit fields in the I2C_O_MCR register. |
// |
//***************************************************************************** |
#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable. |
#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable. |
#define I2C_MCR_LPBK 0x00000001 // I2C Loopback. |
|
//***************************************************************************** |
// |
// The following definitions are deprecated. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the offsets between the I2C master |
// and slave registers. |
// |
//***************************************************************************** |
#define I2C_O_SLAVE 0x00000800 // Offset from master to slave |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the I2C master register offsets. |
// |
//***************************************************************************** |
#define I2C_MASTER_O_SA 0x00000000 // Slave address register |
#define I2C_MASTER_O_CS 0x00000004 // Control and Status register |
#define I2C_MASTER_O_DR 0x00000008 // Data register |
#define I2C_MASTER_O_TPR 0x0000000C // Timer period register |
#define I2C_MASTER_O_IMR 0x00000010 // Interrupt mask register |
#define I2C_MASTER_O_RIS 0x00000014 // Raw interrupt status register |
#define I2C_MASTER_O_MIS 0x00000018 // Masked interrupt status reg |
#define I2C_MASTER_O_MICR 0x0000001C // Interrupt clear register |
#define I2C_MASTER_O_CR 0x00000020 // Configuration register |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the I2C slave register offsets. |
// |
//***************************************************************************** |
#define I2C_SLAVE_O_SICR 0x00000018 // Interrupt clear register |
#define I2C_SLAVE_O_MIS 0x00000014 // Masked interrupt status reg |
#define I2C_SLAVE_O_RIS 0x00000010 // Raw interrupt status register |
#define I2C_SLAVE_O_IM 0x0000000C // Interrupt mask register |
#define I2C_SLAVE_O_DR 0x00000008 // Data register |
#define I2C_SLAVE_O_CSR 0x00000004 // Control/Status register |
#define I2C_SLAVE_O_OAR 0x00000000 // Own address register |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C master |
// slave address register. |
// |
//***************************************************************************** |
#define I2C_MASTER_SA_SA_MASK 0x000000FE // Slave address |
#define I2C_MASTER_SA_RS 0x00000001 // Receive/send |
#define I2C_MASTER_SA_SA_SHIFT 1 |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Control and Status register. |
// |
//***************************************************************************** |
#define I2C_MASTER_CS_BUS_BUSY 0x00000040 // Bus busy |
#define I2C_MASTER_CS_IDLE 0x00000020 // Idle |
#define I2C_MASTER_CS_ERR_MASK 0x0000001C |
#define I2C_MASTER_CS_BUSY 0x00000001 // Controller is TX/RX data |
#define I2C_MASTER_CS_ERROR 0x00000002 // Error occurred |
#define I2C_MASTER_CS_ADDR_ACK 0x00000004 // Address byte not acknowledged |
#define I2C_MASTER_CS_DATA_ACK 0x00000008 // Data byte not acknowledged |
#define I2C_MASTER_CS_ARB_LOST 0x00000010 // Lost arbitration |
#define I2C_MASTER_CS_ACK 0x00000008 // Acknowlegde |
#define I2C_MASTER_CS_STOP 0x00000004 // Stop |
#define I2C_MASTER_CS_START 0x00000002 // Start |
#define I2C_MASTER_CS_RUN 0x00000001 // Run |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the values used in determining the |
// contents of the I2C Master Timer Period register. |
// |
//***************************************************************************** |
#define I2C_SCL_FAST 400000 // SCL fast frequency |
#define I2C_SCL_STANDARD 100000 // SCL standard frequency |
#define I2C_MASTER_TPR_SCL_LP 0x00000006 // SCL low period |
#define I2C_MASTER_TPR_SCL_HP 0x00000004 // SCL high period |
#define I2C_MASTER_TPR_SCL (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP) |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Interrupt Mask register. |
// |
//***************************************************************************** |
#define I2C_MASTER_IMR_IM 0x00000001 // Master interrupt mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Raw Interrupt Status register. |
// |
//***************************************************************************** |
#define I2C_MASTER_RIS_RIS 0x00000001 // Master raw interrupt status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Masked Interrupt Status register. |
// |
//***************************************************************************** |
#define I2C_MASTER_MIS_MIS 0x00000001 // Master masked interrupt status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Interrupt Clear register. |
// |
//***************************************************************************** |
#define I2C_MASTER_MICR_IC 0x00000001 // Master interrupt clear |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Master |
// Configuration register. |
// |
//***************************************************************************** |
#define I2C_MASTER_CR_SFE 0x00000020 // Slave function enable |
#define I2C_MASTER_CR_MFE 0x00000010 // Master function enable |
#define I2C_MASTER_CR_LPBK 0x00000001 // Loopback enable |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave Own |
// Address register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F // Slave address |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave |
// Control/Status register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_CSR_FBR 0x00000004 // First byte received from master |
#define I2C_SLAVE_CSR_TREQ 0x00000002 // Transmit request received |
#define I2C_SLAVE_CSR_DA 0x00000001 // Enable the device |
#define I2C_SLAVE_CSR_RREQ 0x00000001 // Receive data from I2C master |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave |
// Interrupt Mask register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_IMR_IM 0x00000001 // Slave interrupt mask |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave Raw |
// Interrupt Status register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_RIS_RIS 0x00000001 // Slave raw interrupt status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave |
// Masked Interrupt Status register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_MIS_MIS 0x00000001 // Slave masked interrupt status |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C Slave |
// Interrupt Clear register. |
// |
//***************************************************************************** |
#define I2C_SLAVE_SICR_IC 0x00000001 // Slave interrupt clear |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C_O_SIMR |
// register. |
// |
//***************************************************************************** |
#define I2C_SIMR_IM 0x00000001 // Interrupt Mask. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C_O_SRIS |
// register. |
// |
//***************************************************************************** |
#define I2C_SRIS_RIS 0x00000001 // Raw Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C_O_SMIS |
// register. |
// |
//***************************************************************************** |
#define I2C_SMIS_MIS 0x00000001 // Masked Interrupt Status. |
|
//***************************************************************************** |
// |
// The following are deprecated defines for the bit fields in the I2C_O_SICR |
// register. |
// |
//***************************************************************************** |
#define I2C_SICR_IC 0x00000001 // Clear Interrupt. |
|
#endif |
|
#endif // __HW_I2C_H__ |
/drivers/LuminaryMicro/uart.h
0,0 → 1,178
//***************************************************************************** |
// |
// uart.h - Defines and Macros for the UART. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __UART_H__ |
#define __UART_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to UARTIntEnable, UARTIntDisable, and UARTIntClear |
// as the ulIntFlags parameter, and returned from UARTIntStatus. |
// |
//***************************************************************************** |
#define UART_INT_OE 0x400 // Overrun Error Interrupt Mask |
#define UART_INT_BE 0x200 // Break Error Interrupt Mask |
#define UART_INT_PE 0x100 // Parity Error Interrupt Mask |
#define UART_INT_FE 0x080 // Framing Error Interrupt Mask |
#define UART_INT_RT 0x040 // Receive Timeout Interrupt Mask |
#define UART_INT_TX 0x020 // Transmit Interrupt Mask |
#define UART_INT_RX 0x010 // Receive Interrupt Mask |
|
//***************************************************************************** |
// |
// Values that can be passed to UARTConfigSetExpClk as the ulConfig parameter |
// and returned by UARTConfigGetExpClk in the pulConfig parameter. |
// Additionally, the UART_CONFIG_PAR_* subset can be passed to |
// UARTParityModeSet as the ulParity parameter, and are returned by |
// UARTParityModeGet. |
// |
//***************************************************************************** |
#define UART_CONFIG_WLEN_MASK 0x00000060 // Mask for extracting word length |
#define UART_CONFIG_WLEN_8 0x00000060 // 8 bit data |
#define UART_CONFIG_WLEN_7 0x00000040 // 7 bit data |
#define UART_CONFIG_WLEN_6 0x00000020 // 6 bit data |
#define UART_CONFIG_WLEN_5 0x00000000 // 5 bit data |
#define UART_CONFIG_STOP_MASK 0x00000008 // Mask for extracting stop bits |
#define UART_CONFIG_STOP_ONE 0x00000000 // One stop bit |
#define UART_CONFIG_STOP_TWO 0x00000008 // Two stop bits |
#define UART_CONFIG_PAR_MASK 0x00000086 // Mask for extracting parity |
#define UART_CONFIG_PAR_NONE 0x00000000 // No parity |
#define UART_CONFIG_PAR_EVEN 0x00000006 // Even parity |
#define UART_CONFIG_PAR_ODD 0x00000002 // Odd parity |
#define UART_CONFIG_PAR_ONE 0x00000086 // Parity bit is one |
#define UART_CONFIG_PAR_ZERO 0x00000082 // Parity bit is zero |
|
//***************************************************************************** |
// |
// Values that can be passed to UARTFIFOLevelSet as the ulTxLevel parameter and |
// returned by UARTFIFOLevelGet in the pulTxLevel. |
// |
//***************************************************************************** |
#define UART_FIFO_TX1_8 0x00000000 // Transmit interrupt at 1/8 Full |
#define UART_FIFO_TX2_8 0x00000001 // Transmit interrupt at 1/4 Full |
#define UART_FIFO_TX4_8 0x00000002 // Transmit interrupt at 1/2 Full |
#define UART_FIFO_TX6_8 0x00000003 // Transmit interrupt at 3/4 Full |
#define UART_FIFO_TX7_8 0x00000004 // Transmit interrupt at 7/8 Full |
|
//***************************************************************************** |
// |
// Values that can be passed to UARTFIFOLevelSet as the ulRxLevel parameter and |
// returned by UARTFIFOLevelGet in the pulRxLevel. |
// |
//***************************************************************************** |
#define UART_FIFO_RX1_8 0x00000000 // Receive interrupt at 1/8 Full |
#define UART_FIFO_RX2_8 0x00000008 // Receive interrupt at 1/4 Full |
#define UART_FIFO_RX4_8 0x00000010 // Receive interrupt at 1/2 Full |
#define UART_FIFO_RX6_8 0x00000018 // Receive interrupt at 3/4 Full |
#define UART_FIFO_RX7_8 0x00000020 // Receive interrupt at 7/8 Full |
|
//***************************************************************************** |
// |
// Values that can be passed to UARTDMAEnable() and UARTDMADisable(). |
// |
//***************************************************************************** |
#define UART_DMA_ERR_RXSTOP 0x00000004 // Stop DMA receive if UART error |
#define UART_DMA_TX 0x00000002 // Enable DMA for transmit |
#define UART_DMA_RX 0x00000001 // Enable DMA for receive |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void UARTParityModeSet(unsigned long ulBase, unsigned long ulParity); |
extern unsigned long UARTParityModeGet(unsigned long ulBase); |
extern void UARTFIFOLevelSet(unsigned long ulBase, unsigned long ulTxLevel, |
unsigned long ulRxLevel); |
extern void UARTFIFOLevelGet(unsigned long ulBase, unsigned long *pulTxLevel, |
unsigned long *pulRxLevel); |
extern void UARTConfigSetExpClk(unsigned long ulBase, unsigned long ulUARTClk, |
unsigned long ulBaud, unsigned long ulConfig); |
extern void UARTConfigGetExpClk(unsigned long ulBase, unsigned long ulUARTClk, |
unsigned long *pulBaud, |
unsigned long *pulConfig); |
extern void UARTEnable(unsigned long ulBase); |
extern void UARTDisable(unsigned long ulBase); |
extern void UARTEnableSIR(unsigned long ulBase, tBoolean bLowPower); |
extern void UARTDisableSIR(unsigned long ulBase); |
extern tBoolean UARTCharsAvail(unsigned long ulBase); |
extern tBoolean UARTSpaceAvail(unsigned long ulBase); |
extern long UARTCharGetNonBlocking(unsigned long ulBase); |
extern long UARTCharGet(unsigned long ulBase); |
extern tBoolean UARTCharPutNonBlocking(unsigned long ulBase, |
unsigned char ucData); |
extern void UARTCharPut(unsigned long ulBase, unsigned char ucData); |
extern void UARTBreakCtl(unsigned long ulBase, tBoolean bBreakState); |
extern void UARTIntRegister(unsigned long ulBase, void(*pfnHandler)(void)); |
extern void UARTIntUnregister(unsigned long ulBase); |
extern void UARTIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void UARTIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern unsigned long UARTIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void UARTIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
extern void UARTDMAEnable(unsigned long ulBase, unsigned long ulDMAFlags); |
extern void UARTDMADisable(unsigned long ulBase, unsigned long ulDMAFlags); |
|
//***************************************************************************** |
// |
// Several UART APIs have been renamed, with the original function name being |
// deprecated. These defines provide backward compatibility. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#include "sysctl.h" |
#define UARTConfigSet(a, b, c) \ |
UARTConfigSetExpClk(a, SysCtlClockGet(), b, c) |
#define UARTConfigGet(a, b, c) \ |
UARTConfigGetExpClk(a, SysCtlClockGet(), b, c) |
#define UARTCharNonBlockingGet(a) \ |
UARTCharGetNonBlocking(a) |
#define UARTCharNonBlockingPut(a, b) \ |
UARTCharPutNonBlocking(a, b) |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __UART_H__ |
/drivers/LuminaryMicro/rit128x96x4.h
0,0 → 1,53
//***************************************************************************** |
// |
// rit128x96x4.h - Prototypes for the driver for the RITEK 128x96x4 graphical |
// OLED display. |
// |
// Copyright (c) 2007 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. Any use in violation |
// of the foregoing restrictions may subject the user to criminal sanctions |
// under applicable laws, as well as to civil liability for the breach of the |
// terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 1582 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __RIT128X96X4_H__ |
#define __RIT128X96X4_H__ |
|
//***************************************************************************** |
// |
// Prototypes for the driver APIs. |
// |
//***************************************************************************** |
extern void RIT128x96x4Clear(void); |
extern void RIT128x96x4StringDraw(const char *pcStr, |
unsigned long ulX, |
unsigned long ulY, |
unsigned char ucLevel); |
extern void RIT128x96x4ImageDraw(const unsigned char *pucImage, |
unsigned long ulX, |
unsigned long ulY, |
unsigned long ulWidth, |
unsigned long ulHeight); |
extern void RIT128x96x4Init(unsigned long ulFrequency); |
extern void RIT128x96x4Enable(unsigned long ulFrequency); |
extern void RIT128x96x4Disable(void); |
extern void RIT128x96x4DisplayOn(void); |
extern void RIT128x96x4DisplayOff(void); |
|
#endif // __RIT128X96X4_H__ |
/drivers/LuminaryMicro/ethernet.h
0,0 → 1,173
//***************************************************************************** |
// |
// ethernet.h - Defines and Macros for the ethernet module. |
// |
// Copyright (c) 2006-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __ETHERNET_H__ |
#define __ETHERNET_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to EthernetConfigSet as the ulConfig value, and |
// returned from EthernetConfigGet. |
// |
//***************************************************************************** |
#define ETH_CFG_TS_TSEN 0x010000 // Enable Timestamp (CCP) |
#define ETH_CFG_RX_BADCRCDIS 0x000800 // Disable RX BAD CRC Packets |
#define ETH_CFG_RX_PRMSEN 0x000400 // Enable RX Promiscuous |
#define ETH_CFG_RX_AMULEN 0x000200 // Enable RX Multicast |
#define ETH_CFG_TX_DPLXEN 0x000010 // Enable TX Duplex Mode |
#define ETH_CFG_TX_CRCEN 0x000004 // Enable TX CRC Generation |
#define ETH_CFG_TX_PADEN 0x000002 // Enable TX Padding |
|
//***************************************************************************** |
// |
// Values that can be passed to EthernetIntEnable, EthernetIntDisable, and |
// EthernetIntClear as the ulIntFlags parameter, and returned from |
// EthernetIntStatus. |
// |
//***************************************************************************** |
#define ETH_INT_PHY 0x040 // PHY Event/Interrupt |
#define ETH_INT_MDIO 0x020 // Management Transaction |
#define ETH_INT_RXER 0x010 // RX Error |
#define ETH_INT_RXOF 0x008 // RX FIFO Overrun |
#define ETH_INT_TX 0x004 // TX Complete |
#define ETH_INT_TXER 0x002 // TX Error |
#define ETH_INT_RX 0x001 // RX Complete |
|
//***************************************************************************** |
// |
// Helper Macros for Ethernet Processing |
// |
//***************************************************************************** |
// |
// htonl/ntohl - big endian/little endian byte swapping macros for |
// 32-bit (long) values |
// |
//***************************************************************************** |
#ifndef htonl |
#define htonl(a) \ |
((((a) >> 24) & 0x000000ff) | \ |
(((a) >> 8) & 0x0000ff00) | \ |
(((a) << 8) & 0x00ff0000) | \ |
(((a) << 24) & 0xff000000)) |
#endif |
|
#ifndef ntohl |
#define ntohl(a) htonl((a)) |
#endif |
|
//***************************************************************************** |
// |
// htons/ntohs - big endian/little endian byte swapping macros for |
// 16-bit (short) values |
// |
//***************************************************************************** |
#ifndef htons |
#define htons(a) \ |
((((a) >> 8) & 0x00ff) | \ |
(((a) << 8) & 0xff00)) |
#endif |
|
#ifndef ntohs |
#define ntohs(a) htons((a)) |
#endif |
|
//***************************************************************************** |
// |
// API Function prototypes |
// |
//***************************************************************************** |
extern void EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk); |
extern void EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig); |
extern unsigned long EthernetConfigGet(unsigned long ulBase); |
extern void EthernetMACAddrSet(unsigned long ulBase, |
unsigned char *pucMACAddr); |
extern void EthernetMACAddrGet(unsigned long ulBase, |
unsigned char *pucMACAddr); |
extern void EthernetEnable(unsigned long ulBase); |
extern void EthernetDisable(unsigned long ulBase); |
extern tBoolean EthernetPacketAvail(unsigned long ulBase); |
extern tBoolean EthernetSpaceAvail(unsigned long ulBase); |
extern long EthernetPacketGetNonBlocking(unsigned long ulBase, |
unsigned char *pucBuf, |
long lBufLen); |
extern long EthernetPacketGet(unsigned long ulBase, unsigned char *pucBuf, |
long lBufLen); |
extern long EthernetPacketPutNonBlocking(unsigned long ulBase, |
unsigned char *pucBuf, |
long lBufLen); |
extern long EthernetPacketPut(unsigned long ulBase, unsigned char *pucBuf, |
long lBufLen); |
extern void EthernetIntRegister(unsigned long ulBase, |
void (*pfnHandler)(void)); |
extern void EthernetIntUnregister(unsigned long ulBase); |
extern void EthernetIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void EthernetIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern unsigned long EthernetIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void EthernetIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
extern void EthernetPHYWrite(unsigned long ulBase, unsigned char ucRegAddr, |
unsigned long ulData); |
extern unsigned long EthernetPHYRead(unsigned long ulBase, |
unsigned char ucRegAddr); |
|
//***************************************************************************** |
// |
// Several Ethernet APIs have been renamed, with the original function name |
// being deprecated. These defines provide backward compatibility. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
#include "sysctl.h" |
#define EthernetInit(a) \ |
EthernetInitExpClk(a, SysCtlClockGet()) |
#define EthernetPacketNonBlockingGet(a, b, c) \ |
EthernetPacketGetNonBlocking(a, b, c) |
#define EthernetPacketNonBlockingPut(a, b, c) \ |
EthernetPacketPutNonBlocking(a, b, c) |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __ETHERNET_H__ |
/drivers/LuminaryMicro/qei.h
0,0 → 1,116
//***************************************************************************** |
// |
// qei.h - Prototypes for the Quadrature Encoder Driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __QEI_H__ |
#define __QEI_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to QEIConfigure as the ulConfig paramater. |
// |
//***************************************************************************** |
#define QEI_CONFIG_CAPTURE_A 0x00000000 // Count on ChA edges only |
#define QEI_CONFIG_CAPTURE_A_B 0x00000008 // Count on ChA and ChB edges |
#define QEI_CONFIG_NO_RESET 0x00000000 // Do not reset on index pulse |
#define QEI_CONFIG_RESET_IDX 0x00000010 // Reset position on index pulse |
#define QEI_CONFIG_QUADRATURE 0x00000000 // ChA and ChB are quadrature |
#define QEI_CONFIG_CLOCK_DIR 0x00000004 // ChA and ChB are clock and dir |
#define QEI_CONFIG_NO_SWAP 0x00000000 // Do not swap ChA and ChB |
#define QEI_CONFIG_SWAP 0x00000002 // Swap ChA and ChB |
|
//***************************************************************************** |
// |
// Values that can be passed to QEIVelocityConfigure as the ulPreDiv parameter. |
// |
//***************************************************************************** |
#define QEI_VELDIV_1 0x00000000 // Predivide by 1 |
#define QEI_VELDIV_2 0x00000040 // Predivide by 2 |
#define QEI_VELDIV_4 0x00000080 // Predivide by 4 |
#define QEI_VELDIV_8 0x000000C0 // Predivide by 8 |
#define QEI_VELDIV_16 0x00000100 // Predivide by 16 |
#define QEI_VELDIV_32 0x00000140 // Predivide by 32 |
#define QEI_VELDIV_64 0x00000180 // Predivide by 64 |
#define QEI_VELDIV_128 0x000001C0 // Predivide by 128 |
|
//***************************************************************************** |
// |
// Values that can be passed to QEIEnableInts, QEIDisableInts, and QEIClearInts |
// as the ulIntFlags parameter, and returned by QEIGetIntStatus. |
// |
//***************************************************************************** |
#define QEI_INTERROR 0x00000008 // Phase error detected |
#define QEI_INTDIR 0x00000004 // Direction change |
#define QEI_INTTIMER 0x00000002 // Velocity timer expired |
#define QEI_INTINDEX 0x00000001 // Index pulse detected |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void QEIEnable(unsigned long ulBase); |
extern void QEIDisable(unsigned long ulBase); |
extern void QEIConfigure(unsigned long ulBase, unsigned long ulConfig, |
unsigned long ulMaxPosition); |
extern unsigned long QEIPositionGet(unsigned long ulBase); |
extern void QEIPositionSet(unsigned long ulBase, unsigned long ulPosition); |
extern long QEIDirectionGet(unsigned long ulBase); |
extern tBoolean QEIErrorGet(unsigned long ulBase); |
extern void QEIVelocityEnable(unsigned long ulBase); |
extern void QEIVelocityDisable(unsigned long ulBase); |
extern void QEIVelocityConfigure(unsigned long ulBase, unsigned long ulPreDiv, |
unsigned long ulPeriod); |
extern unsigned long QEIVelocityGet(unsigned long ulBase); |
extern void QEIIntRegister(unsigned long ulBase, void (*pfnHandler)(void)); |
extern void QEIIntUnregister(unsigned long ulBase); |
extern void QEIIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void QEIIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern unsigned long QEIIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void QEIIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __QEI_H__ |
/drivers/LuminaryMicro/timer.h
0,0 → 1,154
//***************************************************************************** |
// |
// timer.h - Prototypes for the timer module |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __TIMER_H__ |
#define __TIMER_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerConfigure as the ulConfig parameter. |
// |
//***************************************************************************** |
#define TIMER_CFG_32_BIT_OS 0x00000001 // 32-bit one-shot timer |
#define TIMER_CFG_32_BIT_PER 0x00000002 // 32-bit periodic timer |
#define TIMER_CFG_32_RTC 0x01000000 // 32-bit RTC timer |
#define TIMER_CFG_16_BIT_PAIR 0x04000000 // Two 16-bit timers |
#define TIMER_CFG_A_ONE_SHOT 0x00000001 // Timer A one-shot timer |
#define TIMER_CFG_A_PERIODIC 0x00000002 // Timer A periodic timer |
#define TIMER_CFG_A_CAP_COUNT 0x00000003 // Timer A event counter |
#define TIMER_CFG_A_CAP_TIME 0x00000007 // Timer A event timer |
#define TIMER_CFG_A_PWM 0x0000000A // Timer A PWM output |
#define TIMER_CFG_B_ONE_SHOT 0x00000100 // Timer B one-shot timer |
#define TIMER_CFG_B_PERIODIC 0x00000200 // Timer B periodic timer |
#define TIMER_CFG_B_CAP_COUNT 0x00000300 // Timer B event counter |
#define TIMER_CFG_B_CAP_TIME 0x00000700 // Timer B event timer |
#define TIMER_CFG_B_PWM 0x00000A00 // Timer B PWM output |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerIntEnable, TimerIntDisable, and |
// TimerIntClear as the ulIntFlags parameter, and returned from TimerIntStatus. |
// |
//***************************************************************************** |
#define TIMER_CAPB_EVENT 0x00000400 // CaptureB event interrupt |
#define TIMER_CAPB_MATCH 0x00000200 // CaptureB match interrupt |
#define TIMER_TIMB_TIMEOUT 0x00000100 // TimerB time out interrupt |
#define TIMER_RTC_MATCH 0x00000008 // RTC interrupt mask |
#define TIMER_CAPA_EVENT 0x00000004 // CaptureA event interrupt |
#define TIMER_CAPA_MATCH 0x00000002 // CaptureA match interrupt |
#define TIMER_TIMA_TIMEOUT 0x00000001 // TimerA time out interrupt |
|
//***************************************************************************** |
// |
// Values that can be passed to TimerControlEvent as the ulEvent parameter. |
// |
//***************************************************************************** |
#define TIMER_EVENT_POS_EDGE 0x00000000 // Count positive edges |
#define TIMER_EVENT_NEG_EDGE 0x00000404 // Count negative edges |
#define TIMER_EVENT_BOTH_EDGES 0x00000C0C // Count both edges |
|
//***************************************************************************** |
// |
// Values that can be passed to most of the timer APIs as the ulTimer |
// parameter. |
// |
//***************************************************************************** |
#define TIMER_A 0x000000ff // Timer A |
#define TIMER_B 0x0000ff00 // Timer B |
#define TIMER_BOTH 0x0000ffff // Timer Both |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void TimerEnable(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerDisable(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerConfigure(unsigned long ulBase, unsigned long ulConfig); |
extern void TimerControlLevel(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bInvert); |
extern void TimerControlTrigger(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bEnable); |
extern void TimerControlEvent(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulEvent); |
extern void TimerControlStall(unsigned long ulBase, unsigned long ulTimer, |
tBoolean bStall); |
extern void TimerRTCEnable(unsigned long ulBase); |
extern void TimerRTCDisable(unsigned long ulBase); |
extern void TimerPrescaleSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerPrescaleGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerLoadSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerLoadGet(unsigned long ulBase, unsigned long ulTimer); |
extern unsigned long TimerValueGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerMatchSet(unsigned long ulBase, unsigned long ulTimer, |
unsigned long ulValue); |
extern unsigned long TimerMatchGet(unsigned long ulBase, |
unsigned long ulTimer); |
extern void TimerIntRegister(unsigned long ulBase, unsigned long ulTimer, |
void (*pfnHandler)(void)); |
extern void TimerIntUnregister(unsigned long ulBase, unsigned long ulTimer); |
extern void TimerIntEnable(unsigned long ulBase, unsigned long ulIntFlags); |
extern void TimerIntDisable(unsigned long ulBase, unsigned long ulIntFlags); |
extern unsigned long TimerIntStatus(unsigned long ulBase, tBoolean bMasked); |
extern void TimerIntClear(unsigned long ulBase, unsigned long ulIntFlags); |
|
//***************************************************************************** |
// |
// TimerQuiesce() has been deprecated. SysCtlPeripheralReset() should be used |
// instead to return the timer to its reset state. |
// |
//***************************************************************************** |
#ifndef DEPRECATED |
extern void TimerQuiesce(unsigned long ulBase); |
#endif |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __TIMER_H__ |
/drivers/LuminaryMicro/sysctl.h
0,0 → 1,391
//***************************************************************************** |
// |
// sysctl.h - Prototypes for the system control driver. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __SYSCTL_H__ |
#define __SYSCTL_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the |
// SysCtlPeripheralPresent(), SysCtlPeripheralEnable(), |
// SysCtlPeripheralDisable(), and SysCtlPeripheralReset() APIs as the |
// ulPeripheral parameter. The peripherals in the fourth group (upper nibble |
// is 3) can only be used with the SysCtlPeripheralPresent() API. |
// |
//***************************************************************************** |
#define SYSCTL_PERIPH_WDOG 0x00000008 // Watchdog |
#define SYSCTL_PERIPH_HIBERNATE 0x00000040 // Hibernation module |
#define SYSCTL_PERIPH_ADC 0x00100001 // ADC |
#define SYSCTL_PERIPH_PWM 0x00100010 // PWM |
#define SYSCTL_PERIPH_CAN0 0x00100100 // CAN 0 |
#define SYSCTL_PERIPH_CAN1 0x00100200 // CAN 1 |
#define SYSCTL_PERIPH_CAN2 0x00100400 // CAN 2 |
#define SYSCTL_PERIPH_UART0 0x10000001 // UART 0 |
#define SYSCTL_PERIPH_UART1 0x10000002 // UART 1 |
#define SYSCTL_PERIPH_UART2 0x10000004 // UART 2 |
#ifndef DEPRECATED |
#define SYSCTL_PERIPH_SSI 0x10000010 // SSI |
#endif |
#define SYSCTL_PERIPH_SSI0 0x10000010 // SSI 0 |
#define SYSCTL_PERIPH_SSI1 0x10000020 // SSI 1 |
#ifndef DEPRECATED |
#define SYSCTL_PERIPH_QEI 0x10000100 // QEI |
#endif |
#define SYSCTL_PERIPH_QEI0 0x10000100 // QEI 0 |
#define SYSCTL_PERIPH_QEI1 0x10000200 // QEI 1 |
#ifndef DEPRECATED |
#define SYSCTL_PERIPH_I2C 0x10001000 // I2C |
#endif |
#define SYSCTL_PERIPH_I2C0 0x10001000 // I2C 0 |
#define SYSCTL_PERIPH_I2C1 0x10004000 // I2C 1 |
#define SYSCTL_PERIPH_TIMER0 0x10100001 // Timer 0 |
#define SYSCTL_PERIPH_TIMER1 0x10100002 // Timer 1 |
#define SYSCTL_PERIPH_TIMER2 0x10100004 // Timer 2 |
#define SYSCTL_PERIPH_TIMER3 0x10100008 // Timer 3 |
#define SYSCTL_PERIPH_COMP0 0x10100100 // Analog comparator 0 |
#define SYSCTL_PERIPH_COMP1 0x10100200 // Analog comparator 1 |
#define SYSCTL_PERIPH_COMP2 0x10100400 // Analog comparator 2 |
#define SYSCTL_PERIPH_GPIOA 0x20000001 // GPIO A |
#define SYSCTL_PERIPH_GPIOB 0x20000002 // GPIO B |
#define SYSCTL_PERIPH_GPIOC 0x20000004 // GPIO C |
#define SYSCTL_PERIPH_GPIOD 0x20000008 // GPIO D |
#define SYSCTL_PERIPH_GPIOE 0x20000010 // GPIO E |
#define SYSCTL_PERIPH_GPIOF 0x20000020 // GPIO F |
#define SYSCTL_PERIPH_GPIOG 0x20000040 // GPIO G |
#define SYSCTL_PERIPH_GPIOH 0x20000080 // GPIO H |
#define SYSCTL_PERIPH_UDMA 0x20002000 // uDMA |
#define SYSCTL_PERIPH_USB0 0x20100001 // USB0 |
#define SYSCTL_PERIPH_ETH 0x20105000 // ETH |
#define SYSCTL_PERIPH_IEEE1588 0x20100100 // IEEE1588 |
#define SYSCTL_PERIPH_PLL 0x30000010 // PLL |
#define SYSCTL_PERIPH_TEMP 0x30000020 // Temperature sensor |
#define SYSCTL_PERIPH_MPU 0x30000080 // Cortex M3 MPU |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlPinPresent() API |
// as the ulPin parameter. |
// |
//***************************************************************************** |
#define SYSCTL_PIN_PWM0 0x00000001 // PWM0 pin |
#define SYSCTL_PIN_PWM1 0x00000002 // PWM1 pin |
#define SYSCTL_PIN_PWM2 0x00000004 // PWM2 pin |
#define SYSCTL_PIN_PWM3 0x00000008 // PWM3 pin |
#define SYSCTL_PIN_PWM4 0x00000010 // PWM4 pin |
#define SYSCTL_PIN_PWM5 0x00000020 // PWM5 pin |
#define SYSCTL_PIN_PWM6 0x00000040 // PWM6 pin |
#define SYSCTL_PIN_PWM7 0x00000080 // PWM7 pin |
#define SYSCTL_PIN_C0MINUS 0x00000040 // C0- pin |
#define SYSCTL_PIN_C0PLUS 0x00000080 // C0+ pin |
#define SYSCTL_PIN_C0O 0x00000100 // C0o pin |
#define SYSCTL_PIN_C1MINUS 0x00000200 // C1- pin |
#define SYSCTL_PIN_C1PLUS 0x00000400 // C1+ pin |
#define SYSCTL_PIN_C1O 0x00000800 // C1o pin |
#define SYSCTL_PIN_C2MINUS 0x00001000 // C2- pin |
#define SYSCTL_PIN_C2PLUS 0x00002000 // C2+ pin |
#define SYSCTL_PIN_C2O 0x00004000 // C2o pin |
#define SYSCTL_PIN_MC_FAULT0 0x00008000 // MC0 Fault pin |
#define SYSCTL_PIN_ADC0 0x00010000 // ADC0 pin |
#define SYSCTL_PIN_ADC1 0x00020000 // ADC1 pin |
#define SYSCTL_PIN_ADC2 0x00040000 // ADC2 pin |
#define SYSCTL_PIN_ADC3 0x00080000 // ADC3 pin |
#define SYSCTL_PIN_ADC4 0x00100000 // ADC4 pin |
#define SYSCTL_PIN_ADC5 0x00200000 // ADC5 pin |
#define SYSCTL_PIN_ADC6 0x00400000 // ADC6 pin |
#define SYSCTL_PIN_ADC7 0x00800000 // ADC7 pin |
#define SYSCTL_PIN_CCP0 0x01000000 // CCP0 pin |
#define SYSCTL_PIN_CCP1 0x02000000 // CCP1 pin |
#define SYSCTL_PIN_CCP2 0x04000000 // CCP2 pin |
#define SYSCTL_PIN_CCP3 0x08000000 // CCP3 pin |
#define SYSCTL_PIN_CCP4 0x10000000 // CCP4 pin |
#define SYSCTL_PIN_CCP5 0x20000000 // CCP5 pin |
#define SYSCTL_PIN_32KHZ 0x80000000 // 32kHz pin |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlLDOSet() API as |
// the ulVoltage value, or returned by the SysCtlLDOGet() API. |
// |
//***************************************************************************** |
#define SYSCTL_LDO_2_25V 0x00000005 // LDO output of 2.25V |
#define SYSCTL_LDO_2_30V 0x00000004 // LDO output of 2.30V |
#define SYSCTL_LDO_2_35V 0x00000003 // LDO output of 2.35V |
#define SYSCTL_LDO_2_40V 0x00000002 // LDO output of 2.40V |
#define SYSCTL_LDO_2_45V 0x00000001 // LDO output of 2.45V |
#define SYSCTL_LDO_2_50V 0x00000000 // LDO output of 2.50V |
#define SYSCTL_LDO_2_55V 0x0000001f // LDO output of 2.55V |
#define SYSCTL_LDO_2_60V 0x0000001e // LDO output of 2.60V |
#define SYSCTL_LDO_2_65V 0x0000001d // LDO output of 2.65V |
#define SYSCTL_LDO_2_70V 0x0000001c // LDO output of 2.70V |
#define SYSCTL_LDO_2_75V 0x0000001b // LDO output of 2.75V |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlLDOConfigSet() API. |
// |
//***************************************************************************** |
#define SYSCTL_LDOCFG_ARST 0x00000001 // Allow LDO failure to reset |
#define SYSCTL_LDOCFG_NORST 0x00000000 // Do not reset on LDO failure |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlIntEnable(), |
// SysCtlIntDisable(), and SysCtlIntClear() APIs, or returned in the bit mask |
// by the SysCtlIntStatus() API. |
// |
//***************************************************************************** |
#define SYSCTL_INT_PLL_LOCK 0x00000040 // PLL lock interrupt |
#define SYSCTL_INT_CUR_LIMIT 0x00000020 // Current limit interrupt |
#define SYSCTL_INT_IOSC_FAIL 0x00000010 // Internal oscillator failure int |
#define SYSCTL_INT_MOSC_FAIL 0x00000008 // Main oscillator failure int |
#define SYSCTL_INT_POR 0x00000004 // Power on reset interrupt |
#define SYSCTL_INT_BOR 0x00000002 // Brown out interrupt |
#define SYSCTL_INT_PLL_FAIL 0x00000001 // PLL failure interrupt |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlResetCauseClear() |
// API or returned by the SysCtlResetCauseGet() API. |
// |
//***************************************************************************** |
#define SYSCTL_CAUSE_LDO 0x00000020 // LDO power not OK reset |
#define SYSCTL_CAUSE_SW 0x00000010 // Software reset |
#define SYSCTL_CAUSE_WDOG 0x00000008 // Watchdog reset |
#define SYSCTL_CAUSE_BOR 0x00000004 // Brown-out reset |
#define SYSCTL_CAUSE_POR 0x00000002 // Power on reset |
#define SYSCTL_CAUSE_EXT 0x00000001 // External reset |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlBrownOutConfigSet() |
// API as the ulConfig parameter. |
// |
//***************************************************************************** |
#define SYSCTL_BOR_RESET 0x00000002 // Reset instead of interrupting |
#define SYSCTL_BOR_RESAMPLE 0x00000001 // Resample BOR before asserting |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlPWMClockSet() API |
// as the ulConfig parameter, and can be returned by the SysCtlPWMClockGet() |
// API. |
// |
//***************************************************************************** |
#define SYSCTL_PWMDIV_1 0x00000000 // PWM clock is processor clock /1 |
#define SYSCTL_PWMDIV_2 0x00100000 // PWM clock is processor clock /2 |
#define SYSCTL_PWMDIV_4 0x00120000 // PWM clock is processor clock /4 |
#define SYSCTL_PWMDIV_8 0x00140000 // PWM clock is processor clock /8 |
#define SYSCTL_PWMDIV_16 0x00160000 // PWM clock is processor clock /16 |
#define SYSCTL_PWMDIV_32 0x00180000 // PWM clock is processor clock /32 |
#define SYSCTL_PWMDIV_64 0x001A0000 // PWM clock is processor clock /64 |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlADCSpeedSet() API |
// as the ulSpeed parameter, and can be returned by the SyCtlADCSpeedGet() |
// API. |
// |
//***************************************************************************** |
#define SYSCTL_ADCSPEED_1MSPS 0x00000300 // 1,000,000 samples per second |
#define SYSCTL_ADCSPEED_500KSPS 0x00000200 // 500,000 samples per second |
#define SYSCTL_ADCSPEED_250KSPS 0x00000100 // 250,000 samples per second |
#define SYSCTL_ADCSPEED_125KSPS 0x00000000 // 125,000 samples per second |
|
//***************************************************************************** |
// |
// The following are values that can be passed to the SysCtlClockSet() API as |
// the ulConfig parameter. |
// |
//***************************************************************************** |
#define SYSCTL_SYSDIV_1 0x07800000 // Processor clock is osc/pll /1 |
#define SYSCTL_SYSDIV_2 0x00C00000 // Processor clock is osc/pll /2 |
#define SYSCTL_SYSDIV_3 0x01400000 // Processor clock is osc/pll /3 |
#define SYSCTL_SYSDIV_4 0x01C00000 // Processor clock is osc/pll /4 |
#define SYSCTL_SYSDIV_5 0x02400000 // Processor clock is osc/pll /5 |
#define SYSCTL_SYSDIV_6 0x02C00000 // Processor clock is osc/pll /6 |
#define SYSCTL_SYSDIV_7 0x03400000 // Processor clock is osc/pll /7 |
#define SYSCTL_SYSDIV_8 0x03C00000 // Processor clock is osc/pll /8 |
#define SYSCTL_SYSDIV_9 0x04400000 // Processor clock is osc/pll /9 |
#define SYSCTL_SYSDIV_10 0x04C00000 // Processor clock is osc/pll /10 |
#define SYSCTL_SYSDIV_11 0x05400000 // Processor clock is osc/pll /11 |
#define SYSCTL_SYSDIV_12 0x05C00000 // Processor clock is osc/pll /12 |
#define SYSCTL_SYSDIV_13 0x06400000 // Processor clock is osc/pll /13 |
#define SYSCTL_SYSDIV_14 0x06C00000 // Processor clock is osc/pll /14 |
#define SYSCTL_SYSDIV_15 0x07400000 // Processor clock is osc/pll /15 |
#define SYSCTL_SYSDIV_16 0x07C00000 // Processor clock is osc/pll /16 |
#define SYSCTL_SYSDIV_17 0x88400000 // Processor clock is osc/pll /17 |
#define SYSCTL_SYSDIV_18 0x88C00000 // Processor clock is osc/pll /18 |
#define SYSCTL_SYSDIV_19 0x89400000 // Processor clock is osc/pll /19 |
#define SYSCTL_SYSDIV_20 0x89C00000 // Processor clock is osc/pll /20 |
#define SYSCTL_SYSDIV_21 0x8A400000 // Processor clock is osc/pll /21 |
#define SYSCTL_SYSDIV_22 0x8AC00000 // Processor clock is osc/pll /22 |
#define SYSCTL_SYSDIV_23 0x8B400000 // Processor clock is osc/pll /23 |
#define SYSCTL_SYSDIV_24 0x8BC00000 // Processor clock is osc/pll /24 |
#define SYSCTL_SYSDIV_25 0x8C400000 // Processor clock is osc/pll /25 |
#define SYSCTL_SYSDIV_26 0x8CC00000 // Processor clock is osc/pll /26 |
#define SYSCTL_SYSDIV_27 0x8D400000 // Processor clock is osc/pll /27 |
#define SYSCTL_SYSDIV_28 0x8DC00000 // Processor clock is osc/pll /28 |
#define SYSCTL_SYSDIV_29 0x8E400000 // Processor clock is osc/pll /29 |
#define SYSCTL_SYSDIV_30 0x8EC00000 // Processor clock is osc/pll /30 |
#define SYSCTL_SYSDIV_31 0x8F400000 // Processor clock is osc/pll /31 |
#define SYSCTL_SYSDIV_32 0x8FC00000 // Processor clock is osc/pll /32 |
#define SYSCTL_SYSDIV_33 0x90400000 // Processor clock is osc/pll /33 |
#define SYSCTL_SYSDIV_34 0x90C00000 // Processor clock is osc/pll /34 |
#define SYSCTL_SYSDIV_35 0x91400000 // Processor clock is osc/pll /35 |
#define SYSCTL_SYSDIV_36 0x91C00000 // Processor clock is osc/pll /36 |
#define SYSCTL_SYSDIV_37 0x92400000 // Processor clock is osc/pll /37 |
#define SYSCTL_SYSDIV_38 0x92C00000 // Processor clock is osc/pll /38 |
#define SYSCTL_SYSDIV_39 0x93400000 // Processor clock is osc/pll /39 |
#define SYSCTL_SYSDIV_40 0x93C00000 // Processor clock is osc/pll /40 |
#define SYSCTL_SYSDIV_41 0x94400000 // Processor clock is osc/pll /41 |
#define SYSCTL_SYSDIV_42 0x94C00000 // Processor clock is osc/pll /42 |
#define SYSCTL_SYSDIV_43 0x95400000 // Processor clock is osc/pll /43 |
#define SYSCTL_SYSDIV_44 0x95C00000 // Processor clock is osc/pll /44 |
#define SYSCTL_SYSDIV_45 0x96400000 // Processor clock is osc/pll /45 |
#define SYSCTL_SYSDIV_46 0x96C00000 // Processor clock is osc/pll /46 |
#define SYSCTL_SYSDIV_47 0x97400000 // Processor clock is osc/pll /47 |
#define SYSCTL_SYSDIV_48 0x97C00000 // Processor clock is osc/pll /48 |
#define SYSCTL_SYSDIV_49 0x98400000 // Processor clock is osc/pll /49 |
#define SYSCTL_SYSDIV_50 0x98C00000 // Processor clock is osc/pll /50 |
#define SYSCTL_SYSDIV_51 0x99400000 // Processor clock is osc/pll /51 |
#define SYSCTL_SYSDIV_52 0x99C00000 // Processor clock is osc/pll /52 |
#define SYSCTL_SYSDIV_53 0x9A400000 // Processor clock is osc/pll /53 |
#define SYSCTL_SYSDIV_54 0x9AC00000 // Processor clock is osc/pll /54 |
#define SYSCTL_SYSDIV_55 0x9B400000 // Processor clock is osc/pll /55 |
#define SYSCTL_SYSDIV_56 0x9BC00000 // Processor clock is osc/pll /56 |
#define SYSCTL_SYSDIV_57 0x9C400000 // Processor clock is osc/pll /57 |
#define SYSCTL_SYSDIV_58 0x9CC00000 // Processor clock is osc/pll /58 |
#define SYSCTL_SYSDIV_59 0x9D400000 // Processor clock is osc/pll /59 |
#define SYSCTL_SYSDIV_60 0x9DC00000 // Processor clock is osc/pll /60 |
#define SYSCTL_SYSDIV_61 0x9E400000 // Processor clock is osc/pll /61 |
#define SYSCTL_SYSDIV_62 0x9EC00000 // Processor clock is osc/pll /62 |
#define SYSCTL_SYSDIV_63 0x9F400000 // Processor clock is osc/pll /63 |
#define SYSCTL_SYSDIV_64 0x9FC00000 // Processor clock is osc/pll /64 |
#define SYSCTL_USE_PLL 0x00000000 // System clock is the PLL clock |
#define SYSCTL_USE_OSC 0x00003800 // System clock is the osc clock |
#define SYSCTL_XTAL_1MHZ 0x00000000 // External crystal is 1MHz |
#define SYSCTL_XTAL_1_84MHZ 0x00000040 // External crystal is 1.8432MHz |
#define SYSCTL_XTAL_2MHZ 0x00000080 // External crystal is 2MHz |
#define SYSCTL_XTAL_2_45MHZ 0x000000C0 // External crystal is 2.4576MHz |
#define SYSCTL_XTAL_3_57MHZ 0x00000100 // External crystal is 3.579545MHz |
#define SYSCTL_XTAL_3_68MHZ 0x00000140 // External crystal is 3.6864MHz |
#define SYSCTL_XTAL_4MHZ 0x00000180 // External crystal is 4MHz |
#define SYSCTL_XTAL_4_09MHZ 0x000001C0 // External crystal is 4.096MHz |
#define SYSCTL_XTAL_4_91MHZ 0x00000200 // External crystal is 4.9152MHz |
#define SYSCTL_XTAL_5MHZ 0x00000240 // External crystal is 5MHz |
#define SYSCTL_XTAL_5_12MHZ 0x00000280 // External crystal is 5.12MHz |
#define SYSCTL_XTAL_6MHZ 0x000002C0 // External crystal is 6MHz |
#define SYSCTL_XTAL_6_14MHZ 0x00000300 // External crystal is 6.144MHz |
#define SYSCTL_XTAL_7_37MHZ 0x00000340 // External crystal is 7.3728MHz |
#define SYSCTL_XTAL_8MHZ 0x00000380 // External crystal is 8MHz |
#define SYSCTL_XTAL_8_19MHZ 0x000003C0 // External crystal is 8.192MHz |
#define SYSCTL_XTAL_10MHZ 0x00000400 // External crystal is 10 MHz |
#define SYSCTL_XTAL_12MHZ 0x00000440 // External crystal is 12 MHz |
#define SYSCTL_XTAL_12_2MHZ 0x00000480 // External crystal is 12.288 MHz |
#define SYSCTL_XTAL_13_5MHZ 0x000004C0 // External crystal is 13.56 MHz |
#define SYSCTL_XTAL_14_3MHZ 0x00000500 // External crystal is 14.31818 MHz |
#define SYSCTL_XTAL_16MHZ 0x00000540 // External crystal is 16 MHz |
#define SYSCTL_XTAL_16_3MHZ 0x00000580 // External crystal is 16.384 MHz |
#define SYSCTL_OSC_MAIN 0x00000000 // Oscillator source is main osc |
#define SYSCTL_OSC_INT 0x00000010 // Oscillator source is int. osc |
#define SYSCTL_OSC_INT4 0x00000020 // Oscillator source is int. osc /4 |
#define SYSCTL_OSC_INT30 0x80000030 // Oscillator source is int. 30 KHz |
#define SYSCTL_OSC_EXT32 0x80000038 // Oscillator source is ext. 32 KHz |
#define SYSCTL_INT_OSC_DIS 0x00000002 // Disable internal oscillator |
#define SYSCTL_MAIN_OSC_DIS 0x00000001 // Disable main oscillator |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern unsigned long SysCtlSRAMSizeGet(void); |
extern unsigned long SysCtlFlashSizeGet(void); |
extern tBoolean SysCtlPinPresent(unsigned long ulPin); |
extern tBoolean SysCtlPeripheralPresent(unsigned long ulPeripheral); |
extern void SysCtlPeripheralReset(unsigned long ulPeripheral); |
extern void SysCtlPeripheralEnable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralDisable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralSleepEnable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralSleepDisable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralDeepSleepEnable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralDeepSleepDisable(unsigned long ulPeripheral); |
extern void SysCtlPeripheralClockGating(tBoolean bEnable); |
extern void SysCtlIntRegister(void (*pfnHandler)(void)); |
extern void SysCtlIntUnregister(void); |
extern void SysCtlIntEnable(unsigned long ulInts); |
extern void SysCtlIntDisable(unsigned long ulInts); |
extern void SysCtlIntClear(unsigned long ulInts); |
extern unsigned long SysCtlIntStatus(tBoolean bMasked); |
extern void SysCtlLDOSet(unsigned long ulVoltage); |
extern unsigned long SysCtlLDOGet(void); |
extern void SysCtlLDOConfigSet(unsigned long ulConfig); |
extern void SysCtlReset(void); |
extern void SysCtlSleep(void); |
extern void SysCtlDeepSleep(void); |
extern unsigned long SysCtlResetCauseGet(void); |
extern void SysCtlResetCauseClear(unsigned long ulCauses); |
extern void SysCtlBrownOutConfigSet(unsigned long ulConfig, |
unsigned long ulDelay); |
extern void SysCtlDelay(unsigned long ulCount); |
extern void SysCtlClockSet(unsigned long ulConfig); |
extern unsigned long SysCtlClockGet(void); |
extern void SysCtlPWMClockSet(unsigned long ulConfig); |
extern unsigned long SysCtlPWMClockGet(void); |
extern void SysCtlADCSpeedSet(unsigned long ulSpeed); |
extern unsigned long SysCtlADCSpeedGet(void); |
extern void SysCtlIOSCVerificationSet(tBoolean bEnable); |
extern void SysCtlMOSCVerificationSet(tBoolean bEnable); |
extern void SysCtlPLLVerificationSet(tBoolean bEnable); |
extern void SysCtlClkVerificationClear(void); |
extern void SysCtlGPIOAHBEnable(unsigned long ulGPIOPeripheral); |
extern void SysCtlGPIOAHBDisable(unsigned long ulGPIOPeripheral); |
extern void SysCtlUSBPLLEnable(void); |
extern void SysCtlUSBPLLDisable(void); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __SYSCTL_H__ |
/drivers/LuminaryMicro/adc.h
0,0 → 1,142
//***************************************************************************** |
// |
// adc.h - ADC headers for using the ADC driver functions. |
// |
// Copyright (c) 2005-2008 Luminary Micro, Inc. All rights reserved. |
// |
// Software License Agreement |
// |
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and |
// exclusively on LMI's microcontroller products. |
// |
// The software is owned by LMI and/or its suppliers, and is protected under |
// applicable copyright laws. All rights are reserved. You may not combine |
// this software with "viral" open-source software in order to form a larger |
// program. Any use in violation of the foregoing restrictions may subject |
// the user to criminal sanctions under applicable laws, as well as to civil |
// liability for the breach of the terms and conditions of this license. |
// |
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED |
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF |
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. |
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR |
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. |
// |
// This is part of revision 2523 of the Stellaris Peripheral Driver Library. |
// |
//***************************************************************************** |
|
#ifndef __ADC_H__ |
#define __ADC_H__ |
|
//***************************************************************************** |
// |
// If building with a C++ compiler, make all of the definitions in this header |
// have a C binding. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
extern "C" |
{ |
#endif |
|
//***************************************************************************** |
// |
// Values that can be passed to ADCSequenceConfigure as the ulTrigger |
// parameter. |
// |
//***************************************************************************** |
#define ADC_TRIGGER_PROCESSOR 0x00000000 // Processor event |
#define ADC_TRIGGER_COMP0 0x00000001 // Analog comparator 0 event |
#define ADC_TRIGGER_COMP1 0x00000002 // Analog comparator 1 event |
#define ADC_TRIGGER_COMP2 0x00000003 // Analog comparator 2 event |
#define ADC_TRIGGER_EXTERNAL 0x00000004 // External event |
#define ADC_TRIGGER_TIMER 0x00000005 // Timer event |
#define ADC_TRIGGER_PWM0 0x00000006 // PWM0 event |
#define ADC_TRIGGER_PWM1 0x00000007 // PWM1 event |
#define ADC_TRIGGER_PWM2 0x00000008 // PWM2 event |
#define ADC_TRIGGER_ALWAYS 0x0000000F // Always event |
|
//***************************************************************************** |
// |
// Values that can be passed to ADCSequenceStepConfigure as the ulConfig |
// parameter. |
// |
//***************************************************************************** |
#define ADC_CTL_TS 0x00000080 // Temperature sensor select |
#define ADC_CTL_IE 0x00000040 // Interrupt enable |
#define ADC_CTL_END 0x00000020 // Sequence end select |
#define ADC_CTL_D 0x00000010 // Differential select |
#define ADC_CTL_CH0 0x00000000 // Input channel 0 |
#define ADC_CTL_CH1 0x00000001 // Input channel 1 |
#define ADC_CTL_CH2 0x00000002 // Input channel 2 |
#define ADC_CTL_CH3 0x00000003 // Input channel 3 |
#define ADC_CTL_CH4 0x00000004 // Input channel 4 |
#define ADC_CTL_CH5 0x00000005 // Input channel 5 |
#define ADC_CTL_CH6 0x00000006 // Input channel 6 |
#define ADC_CTL_CH7 0x00000007 // Input channel 7 |
|
//***************************************************************************** |
// |
// Prototypes for the APIs. |
// |
//***************************************************************************** |
extern void ADCIntRegister(unsigned long ulBase, unsigned long ulSequenceNum, |
void (*pfnHandler)(void)); |
extern void ADCIntUnregister(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCIntDisable(unsigned long ulBase, unsigned long ulSequenceNum); |
extern void ADCIntEnable(unsigned long ulBase, unsigned long ulSequenceNum); |
extern unsigned long ADCIntStatus(unsigned long ulBase, |
unsigned long ulSequenceNum, |
tBoolean bMasked); |
extern void ADCIntClear(unsigned long ulBase, unsigned long ulSequenceNum); |
extern void ADCSequenceEnable(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCSequenceDisable(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCSequenceConfigure(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long ulTrigger, |
unsigned long ulPriority); |
extern void ADCSequenceStepConfigure(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long ulStep, |
unsigned long ulConfig); |
extern long ADCSequenceOverflow(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCSequenceOverflowClear(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern long ADCSequenceUnderflow(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCSequenceUnderflowClear(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern long ADCSequenceDataGet(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long *pulBuffer); |
extern void ADCProcessorTrigger(unsigned long ulBase, |
unsigned long ulSequenceNum); |
extern void ADCSoftwareOversampleConfigure(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long ulFactor); |
extern void ADCSoftwareOversampleStepConfigure(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long ulStep, |
unsigned long ulConfig); |
extern void ADCSoftwareOversampleDataGet(unsigned long ulBase, |
unsigned long ulSequenceNum, |
unsigned long *pulBuffer, |
unsigned long ulCount); |
extern void ADCHardwareOversampleConfigure(unsigned long ulBase, |
unsigned long ulFactor); |
|
//***************************************************************************** |
// |
// Mark the end of the C bindings section for C++ compilers. |
// |
//***************************************************************************** |
#ifdef __cplusplus |
} |
#endif |
|
#endif // __ADC_H__ |