URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/arch
- from Rev 621 to Rev 623
- ↔ Reverse comparison
Rev 621 → Rev 623
/support.h
10,9 → 10,9
#include <limits.h> |
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/* Register access macros */ |
#define REG8(add) *((volatile unsigned char *)(add)) |
#define REG16(add) *((volatile unsigned short *)(add)) |
#define REG32(add) *((volatile unsigned long *)(add)) |
#define REG8(add) *((volatile unsigned char *)(add)) |
#define REG16(add) *((volatile unsigned short *)(add)) |
#define REG32(add) *((volatile unsigned long *)(add)) |
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/* For writing into SPR. */ |
void mtspr(unsigned long spr, unsigned long value); |
29,24 → 29,4
/* return value by making a syscall */ |
extern void or32_exit (int i) __attribute__ ((__noreturn__)); |
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/* Timer functions */ |
extern void start_timer(int); |
extern unsigned int read_timer(int); |
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extern unsigned long excpt_buserr; |
extern unsigned long excpt_dpfault; |
extern unsigned long excpt_ipfault; |
extern unsigned long excpt_tick; |
extern unsigned long excpt_align; |
extern unsigned long excpt_illinsn; |
extern unsigned long excpt_int; |
extern unsigned long excpt_dtlbmiss; |
extern unsigned long excpt_itlbmiss; |
extern unsigned long excpt_range; |
extern unsigned long excpt_syscall; |
extern unsigned long excpt_break; |
extern unsigned long excpt_trap; |
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#endif /* SUPPORT_H */ |
/interrupts.h
12,3 → 12,9
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/* Initialize routine */ |
int int_init(void); |
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/* Disable interrupt */ |
int int_disable(unsigned long vect); |
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/* Enable interrupt */ |
int int_enable(unsigned long vect); |
/link.ld
1,7 → 1,7
MEMORY |
{ |
vectors : ORIGIN = 0x00000000, LENGTH = 0x00001100 |
ram : ORIGIN = 0x00001200, LENGTH = 0x00080000 - 0x00001200 |
vectors : ORIGIN = 0x00000000, LENGTH = 0x00001000 |
ram : ORIGIN = 0x00001000, LENGTH = 0x00080000 - 0x00001000 |
} |
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SECTIONS |
/board.h
3,19 → 3,25
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#define MC_ENABLED 0 |
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#define IC_ENABLE 1 |
#define IC_ENABLE 0 |
#define IC_SIZE 8192 |
#define DC_ENABLE 1 |
#define DC_ENABLE 0 |
#define DC_SIZE 8192 |
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#define SYS_CLK 25000000 |
#define IN_CLK 25000000 |
#define TICKS_PER_SEC 100 |
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#define UART_BAUD_RATE 115200 |
//#define UART_NUM_CORES 2 |
#undef UART_NUM_CORES |
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#define UART_BASE 0x90000000 |
#define UART0_BAUD_RATE 115200 |
#define UART0_BASE 0x90000000 |
#define UART0_IRQ 2 |
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#define UART_IRQ 2 |
//#define GPIO_NUM_CORES 2 |
#undef GPIO_NUM_CORES |
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#define GPIO0_BASE 0x91000000 |
#define GPIO0_IRQ 3 |
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#endif |