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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers
    from Rev 623 to Rev 800
    ↔ Reverse comparison
  •

Rev 623 → Rev 800

/dma.c
0,0 → 1,134
#include "board.h"
#include "dma.h"
#include "support.h"
 
static void dma_clear(void);
static volatile struct dma_t *_dma;
 
void dma_init(void *dma_base)
{
_dma = (struct dma_t *)dma_base;
dma_clear();
}
 
unsigned int dma_irq_src_a(void)
{
return _dma->int_src_a;
}
 
unsigned int dma_irq_src_b(void)
{
return _dma->int_src_b;
}
 
unsigned int dma_irq_msk_a(void)
{
return _dma->int_msk_a;
}
 
unsigned int dma_irq_msk_b(void)
{
return _dma->int_msk_b;
}
 
// enable DMA
// mask all interrupt
// disable all DMA channels
static void dma_clear(void)
{
int i;
 
_dma->control = DMA_CSR_GO; // enable DMA
 
_dma->int_msk_a = 0x00000000; // mask interrupt for interface A
_dma->int_msk_b = 0x00000000; // mask interrupt for interface B
// diable all DMA channles
for(i = 0; i < DMA_CHAN_NUMBER; i++) {
_dma->channels[i].control = 0x0;
_dma->channels[i].tranfer_size = 0x0;
_dma->channels[i].src_addr = 0x0;
// _dma->channels[i].src_mask = 0xFFFFFFFC;
_dma->channels[i].dst_addr = 0x0;
// _dma->channels[i].dat_mask = 0xFFFFFFFC;
_dma->channels[i].list_desc = 0x0;
_dma->channels[i].sw_ptr = 0x0;
}
}
 
// FIXME comments
int dma_channel_set(int channel,
unsigned int src_interface, unsigned int src_addr, unsigned int src_addr_incr,
unsigned int dst_interface, unsigned int dst_addr, unsigned int dst_addr_incr,
unsigned int chunk_word, unsigned int transfer_word,
int handshake_mode, int int_enable)
{
unsigned int channel_control = 0x0;
unsigned int channel_transfer_size = 0x0;
 
if(channel < 0 || channel > 31)
return 1;
if(chunk_word > 0x100) // 256 words max
return 1;
if(transfer_word > 0x1000) // 4096 words max
return 1;
// wait until channel is free
do { } while((_dma->channels[channel].control & DMA_CHAN_BUSY_MSK));
 
channel_control = (0x1 << DMA_CHAN_ENABLE_SHT) |
(src_interface << DMA_CHAN_SRC_SEL_SHT ) & DMA_CHAN_SRC_SEL_MSK |
(dst_interface << DMA_CHAN_DST_SEL_SHT ) & DMA_CHAN_SRC_SEL_MSK |
(src_addr_incr << DMA_CHAN_INC_SRC_SHT ) & DMA_CHAN_INC_SRC_MSK |
(dst_addr_incr << DMA_CHAN_INC_DST_SHT ) & DMA_CHAN_INC_DST_MSK |
(handshake_mode << DMA_CHAN_MODE_SHT ) & DMA_CHAN_MODE_MSK |
(int_enable << DMA_CHAN_INE_ERR_SHT ) & DMA_CHAN_INE_ERR_MSK |
(int_enable << DMA_CHAN_INE_DONE_SHT) & DMA_CHAN_INE_DONE_MSK;
 
channel_transfer_size = (transfer_word << DMA_CHAN_TOT_SZ_SHT) & DMA_CHAN_TOT_SZ_MSK |
(chunk_word << DMA_CHAN_CHK_SZ_SHT) & DMA_CHAN_CHK_SZ_MSK ;
// set channel go
_dma->channels[channel].src_addr = src_addr;
_dma->channels[channel].dst_addr = dst_addr;
_dma->channels[channel].tranfer_size = channel_transfer_size;
_dma->channels[channel].control = channel_control;
 
// uart_print_str("setting \n\r");
// uart_print_int(_dma->channels[channel].src_addr); uart_print_str("\n\r");
// uart_print_int(_dma->channels[channel].dst_addr); uart_print_str("\n\r");
// uart_print_int(_dma->channels[channel].tranfer_size); uart_print_str("\n\r");
// uart_print_int(_dma->channels[channel].control); uart_print_str("\n\r");
// uart_print_str("gg \n\r");
 
if(int_enable)
return 0;
 
// wait until dma is done if interrupt is not used
do { } while(!(_dma->channels[channel].control & (DMA_CHAN_DONE_MSK | DMA_CHAN_ERR_MSK)));
channel_control = _dma->channels[channel].control;
if(channel_control & DMA_CHAN_DONE_MSK)
return 0;
 
if(channel_control & DMA_CHAN_ERR_MSK)
return 2;
}
 
 
// FIXME comments
int dma_block_transfer(int channel,
unsigned int src_interface, unsigned int src_addr,
unsigned int dst_interface, unsigned int dst_addr,
unsigned int chunk_word, unsigned int transfer_word,
int int_enable)
{
return dma_channel_set(channel,
src_interface, src_addr, 1,
dst_interface, dst_addr, 1,
chunk_word, transfer_word,
0, int_enable);
}
/dma.h
0,0 → 1,98
#ifndef _DMA_H_
#define _DMA_H_
 
struct dma_channel_descriptor {
unsigned int control;
unsigned int tranfer_size;
unsigned int src_addr;
unsigned int src_mask;
unsigned int dst_addr;
unsigned int dat_mask;
unsigned int list_desc;
unsigned int sw_ptr;
};
 
#define DMA_CHAN_NUMBER (31)
 
struct dma_t {
unsigned int control;
unsigned int int_msk_a;
unsigned int int_msk_b;
unsigned int int_src_a;
unsigned int int_src_b;
unsigned int padding[3];
struct dma_channel_descriptor channels[DMA_CHAN_NUMBER];
};
 
// DMA main control register
#define DMA_CSR_PAUSE (0x1)
#define DMA_CSR_GO (0x0)
 
// DMA Channel controller register
#define DMA_CHAN_INT_SRC_MSK (0x7 << 20) // channel interrupt source
#define DMA_CHAN_INE_CHK_DONE_MSK (0x1 << 19) // enable channel interrupt on transfer done when 1
#define DMA_CHAN_INE_DONE_MSK (0x1 << 18) // enable channel interrupt on transfer done when 1
#define DMA_CHAN_INE_ERR_MSK (0x1 << 17) // enable channel interrupt on erros when 1
#define DMA_CHAN_RST_EN_MSK (0x1 << 16) // hadware reset enable when 1
#define DMA_CHAN_PRIORITY_MSK (0x7 << 13) // channel Priority, 0 is lowest
#define DMA_CHAN_ERR_MSK (0x1 << 12) // channel stopped due to error when 1
#define DMA_CHAN_DONE_MSK (0x1 << 11) // channel stopped due to error when 1
#define DMA_CHAN_BUSY_MSK (0x1 << 10) // channel is busy when 1
#define DMA_CHAN_STOP_MSK (0x1 << 9) // stop current transfer, and set the ERR bit
#define DMA_CHAN_SZ_WB_MSK (0x1 << 8) // if this bit is set, enables the writting back of
// remaining size of the DEST_CSR when USE_ED is set
#define DMA_CHAN_USE_ED_MSK (0x1 << 7) // use external descriptor linked list when 1
#define DMA_CHAN_ARS_MSK (0x1 << 6) // auto restart when 1
#define DMA_CHAN_MODE_MSK (0x1 << 5) // normal mode when 0, HW handshake mode when 1
#define DMA_CHAN_INC_SRC_MSK (0x1 << 4) // increment src addr when 1
#define DMA_CHAN_INC_DST_MSK (0x1 << 3) // increment dst addr when 1
#define DMA_CHAN_SRC_SEL_MSK (0x1 << 2) // interface 0 or 1
#define DMA_CHAN_DST_SEL_MSK (0x1 << 1) // interface 0 or 1
#define DMA_CHAN_ENABLE_MSK (0x1 ) // enable when 0
 
#define DMA_CHAN_INT_SRC_SHT (20)
#define DMA_CHAN_INE_CHK_DONE_SHT (19)
#define DMA_CHAN_INE_DONE_SHT (18)
#define DMA_CHAN_INE_ERR_SHT (17)
#define DMA_CHAN_RST_EN_SHT (16)
#define DMA_CHAN_PRIORITY_SHT (13)
#define DMA_CHAN_ERR_SHT (12)
#define DMA_CHAN_DONE_SHT (11)
#define DMA_CHAN_BUSY_SHT (10)
#define DMA_CHAN_STOP_SHT ( 9)
#define DMA_CHAN_SZ_WB_SHT ( 8)
#define DMA_CHAN_USE_ED_SHT ( 7)
#define DMA_CHAN_ARS_SHT ( 6)
#define DMA_CHAN_MODE_SHT ( 5)
#define DMA_CHAN_INC_SRC_SHT ( 4)
#define DMA_CHAN_INC_DST_SHT ( 3)
#define DMA_CHAN_SRC_SEL_SHT ( 2)
#define DMA_CHAN_DST_SEL_SHT ( 1)
#define DMA_CHAN_ENABLE_SHT ( 0)
 
// DMA Channel size register
#define DMA_CHAN_CHK_SZ_MSK (0x1FF << 16) // Chunk Trnasfer size. number of words(4 Bytes) to
// be transferred at one given time. Maximum size is 2K bytes
#define DMA_CHAN_TOT_SZ_MSK (0x7FF ) // Total Transfre Size, number of words(4 Bytes).
// Maximum size is 16K bytes
 
#define DMA_CHAN_CHK_SZ_SHT (16)
#define DMA_CHAN_TOT_SZ_SHT ( 0)
 
 
void dma_init(void *dma_base);
unsigned int dma_irq_src_a(void);
unsigned int dma_irq_src_b(void);
unsigned int dma_irq_msk_a(void);
unsigned int dma_irq_msk_b(void);
int dma_channel_set(int channel,
unsigned int src_interface, unsigned int src_addr, unsigned int src_addr_incr,
unsigned int dst_interface, unsigned int dst_addr, unsigned int dst_addr_incr,
unsigned int chunk_word, unsigned int transfer_word,
int handshake_mode, int int_enable);
int dma_block_transfer(int channel,
unsigned int src_interface, unsigned int src_addr,
unsigned int dst_interface, unsigned int dst_addr,
unsigned int chunk_word, unsigned int transfer_word,
int int_enable);
#endif
/Makefile
3,7 → 3,7
INCDIR = -I../arch
CFLAGS += $(INCDIR) -g
 
SRC_C = uart.c gpio.c
SRC_C = uart.c gpio.c dma.c
SRC_S =
 
OBJ_C = $(SRC_C:.c=.o)

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