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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/freertos-6.1.1
    from Rev 620 to Rev 621
    ↔ Reverse comparison
  •

Rev 620 → Rev 621

/Source/portable/GCC/OpenRISC/port.c
63,6 → 63,10
/* Processor constants. */
#include "port_spr_defs.h"
 
/* Jump buffer */
#include <setjmp.h>
static jmp_buf jmpbuf;
 
/* Tick Timer Interrupt handler */
void vTickHandler( void );
 
172,14 → 176,19
 
portBASE_TYPE xPortStartScheduler( void )
{
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
if(setjmp((void *)jmpbuf) == 0) {
/* Start the timer that generates the tick ISR. Interrupts are disabled
here already. */
prvSetupTimerInterrupt();
 
/* Start the first task. */
portRESTORE_CONTEXT();
/* Should not get here! */
/* Start the first task. */
portRESTORE_CONTEXT();
/* Should not get here! */
} else {
/* Retrun by vPortEndScheduler */
}
 
return 0;
}
 
186,6 → 195,7
void vPortEndScheduler( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) & (~SPR_SR_TEE)); // Tick stop
longjmp((void *)jmpbuf, 1); // return to xPortStartScheduler
}
 
/*
211,6 → 221,10
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_TEE);
}
 
/*
* naked attribute is ignored or32-elf-gcc 4.5.1-or32-1.0rc1
* use assemble routines in portasm.S
*/
#if 0
void vTickHandler( void )
{
/Source/portable/GCC/OpenRISC/portasm.S
30,11 → 30,76
l.jr r9
.size vPortEnableInterrupts, .-vPortEnableInterrupts
 
.text
.global vTickHandler
.type vTickHandler, %function
vTickHandler:
# portSAVE_CONTEXT
 
.macro portSAVE_REGISTER
l.addi r1, r1, -116
l.sw 0x00(r1), r3
l.sw 0x04(r1), r4
l.sw 0x08(r1), r5
l.sw 0x0c(r1), r6
l.sw 0x10(r1), r7
l.sw 0x14(r1), r8
l.sw 0x18(r1), r9
l.sw 0x1c(r1), r10
l.sw 0x20(r1), r11
l.sw 0x24(r1), r12
l.sw 0x28(r1), r13
l.sw 0x2c(r1), r14
l.sw 0x30(r1), r15
l.sw 0x34(r1), r16
l.sw 0x38(r1), r17
l.sw 0x3c(r1), r18
l.sw 0x40(r1), r19
l.sw 0x44(r1), r20
l.sw 0x48(r1), r21
l.sw 0x4c(r1), r22
l.sw 0x50(r1), r23
l.sw 0x54(r1), r24
l.sw 0x58(r1), r25
l.sw 0x5c(r1), r26
l.sw 0x60(r1), r27
l.sw 0x64(r1), r28
l.sw 0x68(r1), r29
l.sw 0x6c(r1), r30
l.sw 0x70(r1), r31
.endm
 
 
.macro portRESTORE_REGISTER
l.lwz r3 , 0x00(r1)
l.lwz r4 , 0x04(r1)
l.lwz r5 , 0x08(r1)
l.lwz r6 , 0x0c(r1)
l.lwz r7 , 0x10(r1)
l.lwz r8 , 0x14(r1)
l.lwz r9 , 0x18(r1)
l.lwz r10, 0x1c(r1)
l.lwz r11, 0x20(r1)
l.lwz r12, 0x24(r1)
l.lwz r13, 0x28(r1)
l.lwz r14, 0x2c(r1)
l.lwz r15, 0x30(r1)
l.lwz r16, 0x34(r1)
l.lwz r17, 0x38(r1)
l.lwz r18, 0x3c(r1)
l.lwz r19, 0x40(r1)
l.lwz r20, 0x44(r1)
l.lwz r21, 0x48(r1)
l.lwz r22, 0x4c(r1)
l.lwz r23, 0x50(r1)
l.lwz r24, 0x54(r1)
l.lwz r25, 0x58(r1)
l.lwz r26, 0x5c(r1)
l.lwz r27, 0x60(r1)
l.lwz r28, 0x64(r1)
l.lwz r29, 0x68(r1)
l.lwz r30, 0x6c(r1)
l.lwz r31, 0x70(r1)
l.addi r1, r1, 116
.endm
 
 
.macro portSAVE_CONTEXT
.global pxCurrentTCB
# make rooms in stack
l.addi r1, r1, -128
43,8 → 108,8
l.sw 0x0C(r1), r4
l.sw 0x10(r1), r5
# save SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
l.mfspr r3, r0, (0<<11) + 64
l.mfspr r4, r0, (0<<11) + 32
l.mfspr r3, r0, SPR_ESR_BASE
l.mfspr r4, r0, SPR_EPCR_BASE
l.sw 0x78(r1), r3
l.sw 0x7C(r1), r4
l.sw 0x00(r1), r9
84,24 → 149,10
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
l.lwz r5, 0x10(r1)
l.mfspr r3, r0, SPR_TTMR
l.movhi r4, hi(SPR_TTMR_IP)
l.ori r4, r4, lo(SPR_TTMR_IP)
l.xori r4, r4, 0xffffffff
l.and r3, r3, r4 # clear tick timer interrupt
l.mtspr r0, r3, SPR_TTMR
.endm
 
l.jal vTaskIncrementTick
l.nop
.if configUSE_PREEMPTION == 0
# do nothing
.else
l.jal vTaskSwitchContext
l.nop
.endif
# portRESTORE_CONTEXT
 
.macro portRESTORE_CONTEXT
l.movhi r3, hi(pxCurrentTCB)
l.ori r3, r3, lo(pxCurrentTCB)
l.lwz r3, 0x0(r3)
137,8 → 188,8
# restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
l.lwz r3, 0x78(r1)
l.lwz r4, 0x7C(r1)
l.mtspr r0, r3, (0<<11) + 64
l.mtspr r0, r4, (0<<11) + 32
l.mtspr r0, r3, SPR_ESR_BASE
l.mtspr r0, r4, SPR_EPCR_BASE
# restore clobber register
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
146,115 → 197,101
l.addi r1, r1, 128
l.rfe
l.nop
.endm
 
.size vTickHandler, .-vTickHandler
 
.text
.global vPortTickHandler
.type vPortTickHandler, %function
vPortTickHandler:
portSAVE_CONTEXT
l.mfspr r3, r0, SPR_TTMR
l.movhi r4, hi(SPR_TTMR_IP)
l.ori r4, r4, lo(SPR_TTMR_IP)
l.xori r4, r4, 0xffffffff
l.and r3, r3, r4 # clear tick timer interrupt
l.mtspr r0, r3, SPR_TTMR
 
l.jal vTaskIncrementTick
l.nop
.if configUSE_PREEMPTION == 0
# do nothing
.else
l.jal vTaskSwitchContext
l.nop
.endif
 
portRESTORE_CONTEXT
.size vPortTickHandler, .-vPortTickHandler
 
 
.text
.global PortCC
.type PortCC, %function
PortCC:
# portSAVE_CONTEXT
.global pxCurrentTCB
l.lwz r11, 0x0(r1)
l.addi r1, r1, 4
# make rooms in stack
l.addi r1, r1, -128
# early save r3-r5, these are clobber register
l.sw 0x08(r1), r3
l.sw 0x0C(r1), r4
l.sw 0x10(r1), r5
# save SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
l.mfspr r3, r0, (0<<11) + 64
l.mfspr r4, r0, (0<<11) + 32
l.sw 0x78(r1), r3
l.sw 0x7C(r1), r4
l.sw 0x00(r1), r9
# Save Context
l.sw 0x04(r1), r2
l.sw 0x14(r1), r6
l.sw 0x18(r1), r7
l.sw 0x1C(r1), r8
l.sw 0x20(r1), r10
l.sw 0x24(r1), r11
l.sw 0x28(r1), r12
l.sw 0x2C(r1), r13
l.sw 0x30(r1), r14
l.sw 0x34(r1), r15
l.sw 0x38(r1), r16
l.sw 0x3C(r1), r17
l.sw 0x40(r1), r18
l.sw 0x44(r1), r19
l.sw 0x48(r1), r20
l.sw 0x4C(r1), r21
l.sw 0x50(r1), r22
l.sw 0x54(r1), r23
l.sw 0x58(r1), r24
l.sw 0x5C(r1), r25
l.sw 0x60(r1), r26
l.sw 0x64(r1), r27
l.sw 0x68(r1), r28
l.sw 0x6C(r1), r29
l.sw 0x70(r1), r30
l.sw 0x74(r1), r31
# Save the top of stack in TCB
l.movhi r3, hi(pxCurrentTCB)
l.ori r3, r3, lo(pxCurrentTCB)
l.lwz r3, 0x0(r3)
l.sw 0x0(r3), r1
# restore clobber register
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
l.lwz r5, 0x10(r1)
.global vPortSystemCall
.type vPortSystemCall, %function
vPortSystemCall:
l.sfeqi r11, 0xFCC
l.bf 1f
l.nop
l.sw -120(r1), r11
l.lwz r11, -4(r1)
portSAVE_REGISTER
 
l.jal syscall_except
l.lwz r3, -4(r1)
 
portRESTORE_REGISTER
l.rfe
l.nop
 
1:
l.sw -132(r1), r11
l.lwz r11, -4(r1)
portSAVE_CONTEXT
l.jal syscall_except
l.lwz r3, -4(r1)
portRESTORE_CONTEXT
.size vPortSystemCall, .-vPortSystemCall
 
 
.text
.global vPortExtIntHandler
.type vPortExtIntHandler, %function
vPortExtIntHandler:
portSAVE_CONTEXT
 
l.jal int_main
l.nop
 
.if configUSE_PREEMPTION == 0
# do nothing
.else
l.jal vTaskSwitchContext
l.nop
.endif
# portRESTORE_CONTEXT
l.movhi r3, hi(pxCurrentTCB)
l.ori r3, r3, lo(pxCurrentTCB)
l.lwz r3, 0x0(r3)
l.lwz r1, 0x0(r3)
# restore context
l.lwz r9, 0x00(r1)
l.lwz r2, 0x04(r1)
l.lwz r6, 0x14(r1)
l.lwz r7, 0x18(r1)
l.lwz r8, 0x1C(r1)
l.lwz r10, 0x20(r1)
l.lwz r11, 0x24(r1)
l.lwz r12, 0x28(r1)
l.lwz r13, 0x2C(r1)
l.lwz r14, 0x30(r1)
l.lwz r15, 0x34(r1)
l.lwz r16, 0x38(r1)
l.lwz r17, 0x3C(r1)
l.lwz r18, 0x40(r1)
l.lwz r19, 0x44(r1)
l.lwz r20, 0x48(r1)
l.lwz r21, 0x4C(r1)
l.lwz r22, 0x50(r1)
l.lwz r23, 0x54(r1)
l.lwz r24, 0x58(r1)
l.lwz r25, 0x5C(r1)
l.lwz r26, 0x60(r1)
l.lwz r27, 0x64(r1)
l.lwz r28, 0x68(r1)
l.lwz r29, 0x6C(r1)
l.lwz r30, 0x70(r1)
l.lwz r31, 0x74(r1)
# restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
l.lwz r3, 0x78(r1)
l.lwz r4, 0x7C(r1)
l.mtspr r0, r3, (0<<11) + 64
l.mtspr r0, r4, (0<<11) + 32
# restore clobber register
l.lwz r3, 0x08(r1)
l.lwz r4, 0x0C(r1)
l.lwz r5, 0x10(r1)
l.addi r1, r1, 128
l.rfe
l.nop
portRESTORE_CONTEXT
.size vPortExtIntHandler, .-vPortExtIntHandler
 
.size PortCC, .-PortCC
 
.text
.global vPortMiscIntHandler
.type vPortMiscIntHandler, %function
vPortMiscIntHandler:
portSAVE_CONTEXT
 
l.jal misc_int_handler
l.lwz r3, -4(r1)
 
.if configUSE_PREEMPTION == 0
# do nothing
.else
l.jal vTaskSwitchContext
l.nop
.endif
portRESTORE_CONTEXT
.size vPortMiscIntHandler, .-vPortMiscIntHandler
/Source/portable/GCC/OpenRISC/portmacro.h
85,8 → 85,7
 
#define portYIELD_FROM_ISR() vTaskSwitchContext()
#define portYIELD() { \
__asm__ __volatile__ ( "l.addi r1, r1, -4" ); \
__asm__ __volatile__ ( "l.sw 0x0(r1), r11" ); \
__asm__ __volatile__ ( "l.sw -4(r1), r11" ); \
__asm__ __volatile__ ( "l.addi r11, r0, 0x0FCC" ); \
__asm__ __volatile__ ( "l.sys 0x0FCC" ); \
__asm__ __volatile__ ( "l.nop " ); \
115,8 → 114,7
// Critical section handling.
// switch supervisormode, disable tick interrupt and all external interrupt, switch back usermode
#define portENTER_CRITICAL() { \
__asm__ __volatile__ ( "l.addi r1, r1, -4" ); \
__asm__ __volatile__ ( "l.sw 0x0(r1), r11" ); \
__asm__ __volatile__ ( "l.sw -4(r1), r11" ); \
__asm__ __volatile__ ( "l.addi r11, r0, 0x0FCE" ); \
__asm__ __volatile__ ( "l.sys 0x0FCE" ); \
__asm__ __volatile__ ( "l.nop " ); \
124,8 → 122,7
 
// switch supervisormode, enable tick interrupt and all external interrupt, switch back usermode
#define portEXIT_CRITICAL() { \
__asm__ __volatile__ ( "l.addi r1, r1, -4" ); \
__asm__ __volatile__ ( "l.sw 0x0(r1), r11" ); \
__asm__ __volatile__ ( "l.sw -4(r1), r11" ); \
__asm__ __volatile__ ( "l.addi r11, r0, 0x0FCF" ); \
__asm__ __volatile__ ( "l.sys 0x0FCF" ); \
__asm__ __volatile__ ( "l.nop " ); \
144,7 → 141,7
asm volatile ( \
" .global pxCurrentTCB \n\t" \
" # make rooms in stack \n\t" \
" l.addi r1, r1, -132 \n\t" \
" l.addi r1, r1, -128 \n\t" \
" # early save r3-r5, these are clobber register\n\t" \
" l.sw 0x08(r1), r3 \n\t" \
" l.sw 0x0C(r1), r4 \n\t" \
240,6 → 237,7
" l.lwz r3, 0x08(r1) \n\t" \
" l.lwz r4, 0x0C(r1) \n\t" \
" l.lwz r5, 0x10(r1) \n\t" \
" l.addi r1, r1, 128 \n\t" \
" l.rfe \n\t" \
" l.nop \n\t" \
);
/Demo/OpenRISC_SIM_GCC/main.c
63,7 → 63,7
#include "task.h"
 
#include "uart.h"
#include "int.h"
#include "interrupts.h"
 
#define TASK_STACK_SIZE (configMINIMAL_STACK_SIZE)
 
117,13 → 117,13
 
portENTER_CRITICAL();
{
uart_put_int(hour);
uart_print_int(hour);
uart_print_str(" : ");
uart_put_int(min);
uart_print_int(min);
uart_print_str(" : ");
uart_put_int(sec);
uart_print_int(sec);
uart_print_str(" , ");
uart_put_int(ticks);
uart_print_int(ticks);
uart_print_str("\n\r");
}
portEXIT_CRITICAL();
142,11 → 142,11
portENTER_CRITICAL();
{
uart_print_str("vTask ");
uart_put_int(delay);
uart_print_int(delay);
uart_print_str(" : ");
// uart_put_int(priority);
// uart_print_int(priority);
// uart_print_str(" , ");
uart_put_int(ticks);
uart_print_int(ticks);
uart_print_str(" \n\r");
}
portEXIT_CRITICAL();
/Demo/OpenRISC_SIM_GCC/sim.cfg
1,887 → 1,473
/* sim.cfg -- Simulator configuration script file
 
Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
Copyright (C) 2010, Embecosm Limited
 
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
the simulator.
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This file is part of OpenRISC 1000 Architectural Simulator.
This program is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3 of the License, or (at your option)
any later version.
This program is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along
with this program. If not, see <http://www.gnu.org/licenses/>. */
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* -------------------------------------------------------------------------- */
/* The Ork1sim has various parameters, that can be set in configuration files
like this one. The user can specify a configuration file at startu[ with
the -f <filename.cfg> option.
 
The user guide (see the 'doc' directory) gives full details on
configuration files. This is a reference configuration, which may be used
as a starting point for customization.
 
/* INTRODUCTION
A number of peripherals are mapped at standard addresses (above 0x80000000)
in the Verilog RTL of ORPSoC standard sitribution. The same values should
be used in Or1ksim section definitions to match the behavior of the Verilog
 
The ork1sim has various parameters, that are set in configuration files
like this one. The user can switch between configurations at startup by
specifying the required configuration file with the -f <filename.cfg> option.
If no configuration file is specified or1ksim searches for the default
configuration file sim.cfg. First it searches for './sim.cfg'. If this
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
0x90000000 UART
0x91000000 GPIO
0x92000000 Ethernet
0x93000000 Memory controller
0x94000000 PS2 keyboard
0x97000000 Frame buffer
0x97100000 VGA
0x9a000000 DMA controller
0x9e000000 ATA disc
 
This file may contain (standard C) comments only - no // support.
Configure files may be be included, using:
include "file_name_to_include"
Section ordering matches that in the user guide. All optional peripherals
and functionality is disabled. Comments only list the possible entries and
values. Consult the user guide for their meaning.
 
Like normal configuration files, the included file is divided into
sections. Each section is described in detail also.
Unless otherwise indicated, the first named option is the default. */
/* -------------------------------------------------------------------------- */
 
Some section have subsections. One example of such a subsection is:
 
device <index>
instance specific parameters...
enddevice
/* Simulator section
 
which creates a device instance.
verbose = 0|1
debug = 0-9
profile = 0|1
prof_file = "<filename>" (default: "sim.profile")
mprofile = 0|1
mprof_file = "<filename>" (default: "sim.mprofile")
history = 0|1
exe_log = 0|1
exe_log_type = hardware|simple|software|default
exe_log_start = <value> (default: 0)
exe_log_end = <value> (default: never end)
exe_log_marker = <value> (default: no markers)
exe_log_file = "<filename>" (default: "executed.log")
exe_bin_insn_log = 0|1
exe_bin_insn_log_file = "<filename>" (default: "exe-insn.bin")
clkcycle = <value>[ps|ns|us|ms]
*/
section sim
clkcycle = 100ns
end
 
 
/* MEMORY SECTION
/* VAPI section
 
This section specifies how the memory is generated and the blocks
it consists of.
enabled = 0|1
server_port = <value> (default: 50000)
log_enabled = 0|1
hide_device_id = 0|1
vapi_log_file = "<filename>" (default "vapi.log")
*/
section VAPI
server_port = 50000
log_enabled = 0
vapi_log_file = "vapi.log"
end
 
type = random/unknown/pattern
Specifies the initial memory values.
'random' generates random memory using seed 'random_seed'.
'pattern' fills memory with 'pattern'.
'unknown' does not specify how memory should be generated,
leaving the memory in a undefined state. This is the fastest
option.
 
random_seed = <value>
random seed for randomizer, used if type = 'random'.
/* CUC section
 
pattern = <value>
pattern to fill memory, used if type = 'pattern'.
 
nmemories = <value>
number of memory instances connected
 
baseaddr = <hex_value>
memory start address
 
size = <hex_value>
memory size
 
name = "<string>"
memory block name
 
ce = <value>
chip enable index of the memory instance
 
mc = <value>
memory controller this memory is connected to
 
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
 
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
 
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
memory_order = none|weak|strong|exact (default: strong)
calling_convention = 0|1
enable_bursts = 0|1
no_multicycle = 0|1
timings_file = "<filename>" (default: virtex.tim)
*/
 
 
section memory
random_seed = 12345
type = random
pattern = 0x00
 
name = "FLASH"
ce = 0
mc = 0
baseaddr = 0x04000000
size = 0x00200000
delayr = 1
delayw = -1
section cuc
memory_order = weak
calling_convention = 1
enable_bursts = 1
no_multicycle = 1
end
 
section memory
random_seed = 12345
type = random
pattern = 0x00
 
name = "RAM"
ce = 1
mc = 0
baseaddr = 0x00000000
size = 0x00200000
delayr = 1
delayw = 5
end
/* CPU section
 
section memory
random_seed = 12345
type = random
pattern = 0x00
 
name = "ICM"
mc = 0
ce = 2
baseaddr = 0x00800000
size = 0x00004000
delayr = 1
delayw = 1
ver = <value> (default: 0)
cfg = <value> (default: 0)
rev = <value> (default: 0)
upr = <value> (see user manual for default settings)
cfgr = <value> (default: 0x00000020)
sr = <value> (default: 0x00008001)
superscalar = 0|1
hazards = 0|1
dependstats = 0|1
sbuf_len = <value> (default: 0)
hardfloat = 0|1
*/
section cpu
ver = 0x12
cfg = 0x00
rev = 0x0001
end
 
 
/* IMMU SECTION
/* Memory section
 
This section configures the Instruction Memory Manangement Unit
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of ITLB sets; must be power of two
 
nways = <value>
number of ITLB ways
 
pagesize = <value>
instruction page size; must be power of two
 
entrysize = <value>
instruction entry size in bytes
 
ustates = <value>
number of ITLB usage states (2, 3, 4 etc., max is 4)
hitdelay = <value>
number of cycles immu hit costs
missdelay = <value>
number of cycles immu miss costs
type = unknown|random|unknown|pattern
random_seed = <value> (default: -1)
pattern = <value> (default: 0)
baseaddr = <hex_value> (default: 0)
size = <hex_value> (default: 1024)
name = "<string>" (default: "anonymous memory block")
ce = <value> (default: -1)
mc = <value> (default: 0)
delayr = <value> (default: 1)
delayw = <value> (default: 1)
log = "<filename>" (default: NULL)
*/
 
section immu
enabled = 0
nsets = 32
nways = 1
pagesize = 8192
section memory
name = "RAM"
type = unknown
baseaddr = 0x00000000
size = 0x00080000
delayr = 1
delayw = 2
end
 
 
/* DMMU SECTION
/* Data MMU section
 
This section configures the Data Memory Manangement Unit
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DTLB sets; must be power of two
 
nways = <value>
number of DTLB ways
 
pagesize = <value>
data page size; must be power of two
 
entrysize = <value>
data entry size in bytes
 
ustates = <value>
number of DTLB usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles dmmu hit costs
 
missdelay = <value>
number of cycles dmmu miss costs
enabled = 0|1
nsets = <value> (default: 1)
nways = <value> (default: 1)
pagesize = <value> (default: 8192)
entrysize = <value> (default: 1)
ustates = <value> (default: 1)
hitdelay = <value> (default: 1)
missdelay = <value> (default: 1)
*/
 
section dmmu
enabled = 0
nsets = 32
nways = 1
pagesize = 8192
enabled = 0
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* IC SECTION
/* Instruction MMU section
 
This section configures the Instruction Cache
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of IC sets; must be power of two
 
nways = <value>
number of IC ways
 
blocksize = <value>
IC block size in bytes; must be power of two
 
ustates = <value>
number of IC usage states (2, 3, 4 etc., max is 4)
 
hitdelay = <value>
number of cycles ic hit costs
missdelay = <value>
number of cycles ic miss costs
enabled = 0|1
nsets = <value> (default: 1)
nways = <value> (default: 1)
pagesize = <value> (default: 8192)
entrysize = <value> (default: 1)
ustates = <value> (default: 1)
hitdelay = <value> (default: 1)
missdelay = <value> (default: 1)
*/
 
section ic
enabled = 0
nsets = 512
nways = 1
blocksize = 16
section immu
enabled = 0
nsets = 64
nways = 1
pagesize = 8192
hitdelay = 0
missdelay = 0
end
 
 
/* DC SECTION
/* Data cache section
 
This section configures the Data Cache
 
enabled = 0/1
'0': disabled
'1': enabled
(NOTE: UPR bit is set)
 
nsets = <value>
number of DC sets; must be power of two
 
nways = <value>
number of DC ways
 
blocksize = <value>
DC block size in bytes; must be power of two
 
ustates = <value>
number of DC usage states (2, 3, 4 etc., max is 4)
 
load_hitdelay = <value>
number of cycles dc load hit costs
load_missdelay = <value>
number of cycles dc load miss costs
store_hitdelay = <value>
number of cycles dc load hit costs
store_missdelay = <value>
number of cycles dc load miss costs
enabled = 0|1
nsets = <value> (default: 1)
nways = <value> (default: 1)
blocksize = <value> (default: 16)
ustates = <value> (default: 2)
load_hitdelay = <value> (default: 2)
load_missdelay = <value> (default: 2)
store_hitdelay = <value> (default: 0)
store_missdelay = <value> (default: 0)
*/
 
section dc
enabled = 0
nsets = 512
nways = 1
blocksize = 16
enabled = 0
nsets = 256
nways = 1
blocksize = 16
load_hitdelay = 0
load_missdelay = 0
store_hitdelay = 0
store_missdelay = 0
end
 
 
/* SIM SECTION
/* Instruction cache section
 
This section specifies how or1ksim should behave.
 
verbose = 0/1
'0': don't print extra messages
'1': print extra messages
 
debug = 0-9
0 : no debug messages
1-9: debug message level.
higher numbers produce more messages
 
profile = 0/1
'0': don't generate profiling file 'sim.profile'
'1': don't generate profiling file 'sim.profile'
 
prof_fn = "<filename>"
optional filename for the profiling file.
valid only if 'profile' is set
mprofile = 0/1
'0': don't generate memory profiling file 'sim.mprofile'
'1': generate memory profiling file 'sim.mprofile'
 
mprof_fn = "<filename>"
optional filename for the memory profiling file.
valid only if 'mprofile' is set
 
history = 0/1
'0': don't track execution flow
'1': track execution flow
Execution flow can be tracked for the simulator's
'hist' command. Useful for back-trace debugging.
 
iprompt = 0/1
'0': start in <not interactive prompt> (so what do we start in ???)
'1': start in interactive prompt.
 
exe_log = 0/1
'0': don't generate execution log.
'1': generate execution log.
exe_log = default/hardware/simple/software
type of execution log, default is used when not specified
exe_log_start = <value>
index of first instruction to start logging, default = 0
exe_log_end = <value>
index of last instruction to end logging; not limited, if omitted
exe_log_marker = <value>
<value> specifies number of instructions before horizontal marker is
printed; if zero, markers are disabled (default)
 
exe_log_fn = "<filename>"
filename for the exection log file.
valid only if 'exe_log' is set
 
clkcycle = <value>[ps|ns|us|ms]
specifies time measurement for one cycle
enabled = 0|1
nsets = <value> (default: 1)
nways = <value> (default: 1)
blocksize = <value> (default: 16)
ustates = <value> (default: 2)
hitdelay = <value> (default: 1)
missdelay = <value> (default: 1)
*/
 
section sim
verbose = 1
debug = 0
profile = 0
prof_fn = "sim.profile"
 
history = 1
/* iprompt = 0 */
exe_log = 0
exe_log_type = simple
/* exe_log_start = 0 */
/* exe_log_end = 2000000 */
/* exe_log_marker = 50 */
exe_log_fn = "executed.log"
 
/* clkcycle = 10000ns */
 
section ic
enabled = 0
nsets = 256
nways = 1
blocksize = 16
hitdelay = 0
missdelay = 0
end
 
 
/* SECTION VAPI
/* Programmable interrupt controller section
 
This section configures the Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
'0': disbable VAPI server
'1': enable/start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
'0': disable VAPI requests logging
'1': enable VAPI requests logging
 
hide_device_id = 0/1
'0': don't log device id (for compatability with old version)
'1': log device id
 
vapi_fn = <filename>
filename for the log file.
valid only if log_enabled is set
enabled = 0|1
edge_trigger = 0|1 (default: 1)
*/
 
section VAPI
enabled = 0
server_port = 9998
log_enabled = 0
vapi_log_fn = "vapi.log"
section pic
enabled = 1
end
 
 
/* CPU SECTION
/* Power management section
 
This section specifies various CPU parameters.
 
ver = <value>
rev = <value>
specifies version and revision of the CPU used
 
upr = <value>
changes the upr register
sr = <value>
sets the initial Supervision Register value
 
superscalar = 0/1
'0': CPU is scalar
'1': CPU is superscalar
(modify cpu/or32/execute.c to tune superscalar model)
 
hazards = 0/1
'0': don't track data hazards in superscalar CPU
'1': track data hazards in superscalar CPU
If tracked, data hazards can be displayed using the
simulator's 'r' command.
 
dependstats = 0/1
'0': don't calculate inter-instruction dependencies.
'1': calculate inter-instruction dependencies.
If calculated, inter-instruction dependencies can be
displayed using the simulator's 'stat' command.
 
sbuf_len = <value>
length of store buffer (<= 256), 0 = disabled
enabled = 0|1
*/
 
section cpu
ver = 0x1200
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 1
dependstats = 1
sbuf_len = 1
end
 
 
/* PM SECTION
 
This section specifies Power Management parameters
 
enabled = 0/1
'0': disable power management
'1': enable power management
*/
 
section pm
enabled = 0
end
 
 
/* BPB SECTION
 
This section specifies how branch prediction should behave.
/* Branch prediction section
enabled = 0/1
'0': disable branch prediction
'1': enable branch prediction
btic = 0/1
'0': disable branch target instruction cache model
'1': enable branch target instruction cache model
 
sbp_bf_fwd = 0/1
Static branch prediction for 'l.bf'
'0': don't use forward prediction
'1': use forward prediction
sbp_bnf_fwd = 0/1
Static branch prediction for 'l.bnf'
'0': don't use forward prediction
'1': use forward prediction
 
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
enabled = 0|1
btic = 0|1
sbp_bf_fwd = 0|1
sbp_bnf_fwd = 0|1
hitdelay = <value> (default: 0)
missdelay = <value> (default: 0)
*/
 
section bpb
enabled = 1
btic = 1
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
enabled = 0
end
 
 
/* DEBUG SECTION
/* Debug unit section
 
This sections specifies how the debug unit should behave.
 
enabled = 0/1
'0': disable debug unit
'1': enable debug unit
 
gdb_enabled = 0/1
'0': don't start gdb server
'1': start gdb server at port 'server_port'
 
server_port = <value>
TCP/IP port to start gdb server on
valid only if gdb_enabled is set
 
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
enabled = 0|1
rsp_enabled = 0|1
rsp_port = <value> (default: 51000)
vapi_id = <value> (default: 0)
*/
section debug
enabled = 1
gdb_enabled = 1
server_port = 9999
rsp_enabled = 1
rsp_port = 9999
end
 
/* MC SECTION
 
This section configures the memory controller
/* Memory controller section
 
enabled = 0/1
'0': disable memory controller
'1': enable memory controller
 
baseaddr = <hex_value>
address of first MC register
 
POC = <hex_value>
Power On Configuration register
 
index = <value>
Index of this memory controller amongst all the memory controllers
enabled = 0|1
baseaddr = <value> (default: 0)
POC = <value> (default: 0)
index = <value> (default: 0)
*/
 
section mc
enabled = 0
baseaddr = 0x60000000
POC = 0x00000008 /* Power on configuration register */
index = 0
enabled = 0
baseaddr = 0x93000000
POC = 0x0000000a /* 32 bit SSRAM */
index = 0
end
 
 
/* UART SECTION
/* UART section
 
This section configures the UARTs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first UART register for this device
 
channel = <channeltype>:<args>
The channel parameter indicates the source of received UART characters
and the sink for transmitted UART characters.
 
The <channeltype> can be either "file", "xterm", "tcp", "fd", or "tty"
(without quotes).
 
A) To send/receive characters from a pair of files, use a file
channel:
 
channel=file:<rxfile>,<txfile>
 
B) To create an interactive terminal window, use an xterm channel:
 
channel=xterm:[<xterm_arg>]*
 
C) To create a bidirectional tcp socket which one could, for example,
access via telnet, use a tcp channel:
 
channel=tcp:<port number>
 
D) To cause the UART to read/write from existing numeric file
descriptors, use an fd channel:
 
channel=fd:<rx file descriptor num>,<tx file descriptor num>
 
E) To connect the UART to a physical serial port, create a tty
channel:
 
channel=tty:device=/dev/ttyS0,baud=9600
 
irq = <value>
irq number for this device
 
16550 = 0/1
'0': this device is a UART16450
'1': this device is a UART16550
 
jitter = <value>
in msecs... time to block, -1 to disable it
 
vapi_id = <hex_value>
VAPI id of this instance
enabled = 0|1
baseaddr = <value> (default: 0)
channel = "value>" (default: "xterm:")
irq = <value> (default: 0)
16550 = 0|1
jitter = <value> (default: 0)
vapi_id = <value> (default: 0)
*/
 
section uart
enabled = 1
enabled = 1
baseaddr = 0x90000000
irq = 2
/*channel = "file:uart0.rx,uart0.tx"*/
/*channel = "tcp:10084" */
channel = "xterm:"
/*channel = "tcp:10000"*/
jitter = -1 /* async behaviour */
16550 = 1
irq = 2
16550 = 1
end
 
 
/* DMA SECTION
/* DMA section
 
This section configures the DMAs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
 
vapi_id = <hex_value>
VAPI id of this instance
enabled = 0|1
baseaddr = <value> (default: 0)
irq = <value> (default: 0)
vapi_id = <value> (default: 0)
*/
 
section dma
enabled = 0
enabled = 0
baseaddr = 0x9a000000
irq = 11
irq = 11
end
 
 
/* ETHERNET SECTION
/* Ethernet section
 
This section configures the ETHERNETs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
 
irq = <value>
ethernet mac IRQ level
 
rtx_type = <value>
use 0 - file interface, 1 - socket interface
 
rx_channel = <value>
DMA channel used for RX
 
tx_channel = <value>
DMA channel used for TX
 
rxfile = "<filename>"
filename, where to read data from
 
txfile = "<filename>"
filename, where to write data to
 
sockif = "<ifacename>"
interface name of ethernet socket
 
vapi_id = <hex_value>
VAPI id of this instance
enabled = 0|1
baseaddr = <value> (default: 0)
dma = <value> (default: 0)
irq = <value> (default: 0)
rtx_type = 0|1
rx_channel = <value> (default: 0)
tx_channel = <value> (default: 0)
rxfile = "<filename>" (default: "eth_rx")
txfile = "<filename>" (default: "eth_rx")
sockif = "<service>" (default: "or1ksim_eth")
vapi_id = <value> (default: 0)
*/
 
section ethernet
enabled = 0
enabled = 0
baseaddr = 0x92000000
dma = 0
irq = 4
irq = 4
rtx_type = 0
tx_channel = 0
rx_channel = 1
rxfile = "eth0.rx"
txfile = "eth0.tx"
sockif = "eth0"
end
 
 
/* GPIO SECTION
/* GPIO section
 
This section configures the GPIOs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first GPIO register for this device
 
irq = <value>
irq number for this device
 
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
enabled = 0|1
baseaddr = <value> (default: 0)
irq = <value> (default: 0)
base_vapi_id = <value> (default: 0)
*/
 
section gpio
enabled = 1
baseaddr = 0x91000000
irq = 3
enabled = 1
baseaddr = 0x91000000
irq = 3
base_vapi_id = 0x0200
end
 
/* VGA SECTION
/* VGA section
This section configures the VGA/LCD controller
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
enabled = 0|1
baseaddr = <value> (default: 0)
irq = <value> (default: 0)
refresh_rate = <value> (default: cycles equivalent to 50Hz)
filename = "<filename>" (default: "vga_out))
*/
 
section vga
enabled = 0
baseaddr = 0x97100000
irq = 8
refresh_rate = 100000
filename = "primary"
enabled = 0
baseaddr = 0x97100000
irq = 8
end
 
 
/* TICK TIMER SECTION
 
This section configures tick timer
 
enabled = 0/1
whether tick timer is enabled
*/
section tick
enabled = 1
irq = 3
end
 
section pic
enabled = 1
edge_trigger = 1
end
 
/* FB SECTION
/* Frame buffer section
This section configures the frame buffer
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
base address of frame buffer
paladdr = <hex_value>
base address of first palette entry
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
enabled = 0|1
baseaddr = <value> (default: 0)
refresh_rate = <value> (default: cycles equivalent to 50Hz)
filename = "<filename>" (default: "fb_out))
*/
section fb
enabled = 0
baseaddr = 0x97000000
refresh_rate = 1000000
filename = "primary"
enabled = 0
baseaddr = 0x97000000
end
 
/* KBD SECTION
 
/* PS2 keyboard section
 
This section configures the PS/2 compatible keyboard
baseaddr = <hex_value>
base address of the keyboard device
rxfile = "<filename>"
filename, where to read data from
enabled = 0|1
baseaddr = <value> (default: 0)
irq = <value> (default: 0)
rxfile = "<filename>" (default: "kbd_in")
*/
section kbd
enabled = 0
irq = 5
enabled = 0
baseaddr = 0x94000000
rxfile = "kbd.rx"
irq = 5
end
 
/* ATA SECTION
 
/* ATA disc section
This section configures the ATA/ATAPI host controller
baseaddr = <hex_value>
address of first ATA register
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
enabled = 0|1
baseaddr = <value> (default: 0)
irq = <value> (default: 0)
dev_id = 1|2|3
rev = 0-15 (default: 1)
pio_mode0_t1 = 0-255 (default: 6)
pio_mode0_t2 = 0-255 (default: 28)
pio_mode0_t4 = 0-255 (default: 2)
pio_mode0_teoc = 0-255 (default: 23)
dma_mode0_tm = 0-255 (default: 4)
dma_mode0_td = 0-255 (default: 21)
dma_mode0_teoc = 0-255 (default: 21)
device = 0|1
 
irq = <value>
irq number for this device
Device specific:
 
debug = <value>
debug level for ata models.
0: no debug messages
1: verbose messages
3: normal messages (more messages than verbose)
5: debug messages (normal debug messages)
7: flow control messages (debug statemachine flows)
9: low priority message (display everything the code does)
 
dev_type0/1 = <value>
ata device 0 type
0: NO_CONNeCT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
 
dev_file0/1 = "<filename>"
filename for simulated ATA device
valid only if dev_type0 == 1
 
dev_size0/1 = <value>
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
 
dev_packet0/1 = <value>
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
 
FIXME: irq number
type = 0|1|2
file = "<filename>" (default: "ata_file<type>")
size = <value> (default: 0)
packet = 0|1
firmware = "<string>" (default: "02207031")
heads = <value> (default: 7)
sectors = <value> (default: 32)
mwdma = 2|1|0|-1
pio = 4|3|2|1|0
*/
section ata
enabled = 0
enabled = 0
baseaddr = 0x9e000000
irq = 15
irq = 15
 
dev_type0 = 1
dev_file0 = "/tmp/sim_atadev0"
dev_size0 = 1
dev_packet0 = 0
device 0
type = 1
size = 1
enddevice
end
 
dev_type1 = 0
dev_file1 = ""
dev_size1 = 0
dev_packet1 = 0
 
/* Generic peripheral section
enabled = 0|1
baseaddr = <value> (default: 0)
size = <value> (default: 0)
name = "<string>" (default: "anonymous external peripheral")
byte_enabled = 1|0
hw_enabled = 1|0
word_enabled = 1|0
*/
section generic
enabled = 0
end
 
/Demo/OpenRISC_SIM_GCC/arch/int.c File deleted
/Demo/OpenRISC_SIM_GCC/arch/int.h File deleted
/Demo/OpenRISC_SIM_GCC/arch/interrupts.c
1,47 → 1,142
#include "../../../Source/portable/GCC/OpenRISC/portmacro.h"
/* This file is part of test microkernel for OpenRISC 1000. */
/* (C) 2001 Simon Srot, srot@opencores.org */
 
#include "support.h"
#include "spr_defs.h"
#include "interrupts.h"
 
/* Interrupt handlers table */
static struct ihnd int_handlers[MAX_INT_HANDLERS];
 
/* Initialize routine */
int int_init(void) {
int i;
// initialize Interrupt handler table
for(i = 0; i < MAX_INT_HANDLERS; i++) {
int_handlers[i].handler = 0;
int_handlers[i].arg = 0;
}
// mask all interrupt
mtspr(SPR_PICMR, 0x00000000);
 
// set OR1200 to accept exceptions (external interrupt enable)
mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE);
 
return 0;
}
 
/* Add interrupt handler */
int int_add(unsigned long vect, void (* handler)(void *), void *arg) {
if(vect >= MAX_INT_HANDLERS)
return -1;
 
int_handlers[vect].handler = handler;
int_handlers[vect].arg = arg;
 
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
 
return 0;
}
 
/* Disable interrupt */
int int_disable(unsigned long vect) {
if(vect >= MAX_INT_HANDLERS)
return -1;
 
mtspr(SPR_PICMR, mfspr(SPR_PICMR) & ~(0x00000001L << vect));
 
return 0;
}
 
/* Enable interrupt */
int int_enable(unsigned long vect) {
if(vect >= MAX_INT_HANDLERS)
return -1;
 
mtspr(SPR_PICMR, mfspr(SPR_PICMR) | (0x00000001L << vect));
 
return 0;
}
 
/* Main interrupt handler */
void int_main(void) {
unsigned long picsr = mfspr(SPR_PICSR); // process only the interrupts asserted at signal catch, ignore all during process
unsigned long i = 0;
 
while(i < 32) {
if((picsr & (0x01L << i)) && (int_handlers[i].handler != 0)) {
(*int_handlers[i].handler)(int_handlers[i].arg);
}
i++;
}
 
mtspr(SPR_PICSR, 0); // clear interrupt status: all modules have level interrupts, which have to be cleared by software,
} // thus this is safe, since non processed interrupts will get re-asserted soon enough
 
// Dummy or32 except vectors
void buserr_except(void) {
uart_print_str("buserr_except\n\r");
while(1) ;
}
 
void dpf_except(void) {
uart_print_str("dpf_except\n\r");
while(1) ;
}
 
void ipf_except(void) {
uart_print_str("ipf_except\n\r");
while(1) ;
}
 
void align_except(void) {
uart_print_str("align_except\n\r");
while(1) ;
}
 
void illegal_except(void) {
uart_print_str("illegal_except\n\r");
while(1) ;
}
 
void dtlbmiss_except(void) {
uart_print_str("dtlbmiss_except\n\r");
while(1) ;
}
 
void itlbmiss_except(void) {
uart_print_str("itlbmiss_except\n\r");
while(1) ;
}
 
void range_except(void) {
uart_print_str("range_except\n\r");
while(1) ;
}
 
void res1_except(void) {
uart_print_str("res1_except\n\r");
}
 
void trap_except(void) {
uart_print_str("trap_except\n\r");
}
 
void res2_except(void) {
uart_print_str("res2_except\n\r");
}
 
void misc_int_handler(int arg) {
switch(arg) {
case 0x200: { buserr_except(); break; }
case 0x300: { dpf_except(); break; }
case 0x400: { ipf_except(); break; }
case 0x600: { align_except(); break; }
case 0x700: { illegal_except(); break; }
case 0x900: { dtlbmiss_except(); break; }
case 0xa00: { itlbmiss_except(); break; }
case 0xb00: { range_except(); break; }
case 0xd00: { res1_except(); break; }
case 0xe00: { trap_except(); break; }
case 0xf00: { res2_except(); break; }
default: { break; }
}
}
 
static void syscall_enter_critical(void) {
unsigned int exception_sr = mfspr(SPR_ESR_BASE);
exception_sr &= (~SPR_SR_IEE); // disable all external interrupt
59,29 → 154,15
}
 
void syscall_except(int id) {
if(id == 0x0FCE) {
if(id == 0x0FCC) {
vTaskSwitchContext();
} else if(id == 0x0FCE) {
syscall_enter_critical();
} else if(id == 0x0FCF) {
syscall_exit_critical();
} else {
uart_put_int(id);
uart_print_int(id);
uart_print_str(" syscall is not impelmented yet....\n\r");
}
}
 
 
void res1_except(void) {
uart_print_str("res1_except\n\r");
while(1) ;
}
 
void trap_except(void) {
uart_print_str("trap_except\n\r");
while(1) ;
}
 
void res2_except(void) {
uart_print_str("res2_except\n\r");
while(1) ;
}
 
/Demo/OpenRISC_SIM_GCC/arch/reset.S
46,275 → 46,150
l.jr r3
l.nop
.org 0x200
_except_200:
l.nop
l.addi r1,r1,-116 // free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 // save register r9(return addr) to stack
l.jal store_regs // save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) // set return addr to end_except instruction
l.ori r9,r9,lo(end_except) // set return addr to end_except instruction
l.j buserr_except
l.sw -4(r1), r3
l.addi r3, r0, 0x200
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0x300
_except_300:
l.nop
l.addi r1,r1,-116 // free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 // save register r9(return addr) to stack
l.jal store_regs // save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) // set return addr to end_except instruction
l.ori r9,r9,lo(end_except) // set return addr to end_except instruction
l.j dpf_except
l.sw -4(r1), r3
l.addi r3, r0, 0x300
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0x400
_except_400:
l.nop
l.addi r1,r1,-116 // free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 // save register r9(return addr) to stack
l.jal store_regs // save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) // set return addr to end_except instruction
l.ori r9,r9,lo(end_except) // set return addr to end_except instruction
l.j ipf_except
l.sw -4(r1), r3
l.addi r3, r0, 0x400
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0x500
_except_500:
l.nop
l.j vTickHandler
l.j vPortTickHandler
l.nop
 
 
.org 0x600
_except_600:
l.nop
l.addi r1,r1,-116 // free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 // save register r9(return addr) to stack
l.jal store_regs // save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) // set return addr to end_except instruction
l.ori r9,r9,lo(end_except) // set return addr to end_except instruction
l.j align_except
l.sw -4(r1), r3
l.addi r3, r0, 0x600
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0x700
_except_700:
l.nop
l.addi r1,r1,-116 // free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 // save register r9(return addr) to stack
l.jal store_regs // save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j illegal_except
l.sw -4(r1), r3
l.addi r3, r0, 0x700
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0x800
_except_800:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.j vPortExtIntHandler
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j ext_except //jmp to C interrupt handler (returns later to end_except)
l.nop
 
 
.org 0x900
_except_900:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j dtlbmiss_except
l.sw -4(r1), r3
l.addi r3, r0, 0x900
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0xa00
_except_a00:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j itlbmiss_except
l.sw -4(r1), r3
l.addi r3, r0, 0xa00
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0xb00
_except_b00:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j range_except
l.sw -4(r1), r3
l.addi r3, r0, 0xb00
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0xc00
_except_c00:
.global PortCC
.global vPortSystemCall
l.nop
l.sfeqi r11, 0x0FCC
l.bnf 1f
l.j vPortSystemCall
l.nop
l.j PortCC
l.nop
 
1:
l.addi r1, r1, 4 //FIXME
l.addi r1,r1,-116 //free 29 words of stack (stack is r1), FIXME comment
l.sw -0x8(r1), r11
l.lwz r11, 112(r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.lwz r3, -0x8(r1)
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j syscall_except
l.nop
 
.org 0xd00
_except_d00:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j res1_except
l.sw -4(r1), r3
l.addi r3, r0, 0xd00
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0xe00
_except_e00:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j trap_except
l.sw -4(r1), r3
l.addi r3, r0, 0xe00
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
 
.org 0xf00
_except_f00:
l.nop
l.addi r1,r1,-116 //free 29 words of stack (stack is r1)
l.sw 0x18(r1),r9 //save register r9(return addr) to stack
l.jal store_regs //save registers r3-r31 (except r9) to stack (r9 is changed here)
l.nop
 
l.movhi r9,hi(end_except) //set return addr to end_except instruction
l.ori r9,r9,lo(end_except) //set return addr to end_except instruction
l.j res2_except
l.sw -4(r1), r3
l.addi r3, r0, 0xf00
l.sw -132(r1), r3
l.lwz r3, -4(r1)
l.j vPortMiscIntHandler
l.nop
 
store_regs: //save registers r3-r31 (except r9) to stack
l.sw 0x00(r1),r3
l.sw 0x04(r1),r4
l.sw 0x08(r1),r5
l.sw 0x0c(r1),r6
l.sw 0x10(r1),r7
l.sw 0x14(r1),r8
l.sw 0x1c(r1),r10
l.sw 0x20(r1),r11
l.sw 0x24(r1),r12
l.sw 0x28(r1),r13
l.sw 0x2c(r1),r14
l.sw 0x30(r1),r15
l.sw 0x34(r1),r16
l.sw 0x38(r1),r17
l.sw 0x3c(r1),r18
l.sw 0x40(r1),r19
l.sw 0x44(r1),r20
l.sw 0x48(r1),r21
l.sw 0x4c(r1),r22
l.sw 0x50(r1),r23
l.sw 0x54(r1),r24
l.sw 0x58(r1),r25
l.sw 0x5c(r1),r26
l.sw 0x60(r1),r27
l.sw 0x64(r1),r28
l.sw 0x68(r1),r29
l.sw 0x6c(r1),r30
l.sw 0x70(r1),r31
l.jr r9
l.nop
 
end_except: //load back registers from stack r3-r31
l.lwz r3,0x00(r1)
l.lwz r4,0x04(r1)
l.lwz r5,0x08(r1)
l.lwz r6,0x0c(r1)
l.lwz r7,0x10(r1)
l.lwz r8,0x14(r1)
l.lwz r9,0x18(r1)
l.lwz r10,0x1c(r1)
l.lwz r11,0x20(r1)
l.lwz r12,0x24(r1)
l.lwz r13,0x28(r1)
l.lwz r14,0x2c(r1)
l.lwz r15,0x30(r1)
l.lwz r16,0x34(r1)
l.lwz r17,0x38(r1)
l.lwz r18,0x3c(r1)
l.lwz r19,0x40(r1)
l.lwz r20,0x44(r1)
l.lwz r21,0x48(r1)
l.lwz r22,0x4c(r1)
l.lwz r23,0x50(r1)
l.lwz r24,0x54(r1)
l.lwz r25,0x58(r1)
l.lwz r26,0x5c(r1)
l.lwz r27,0x60(r1)
l.lwz r28,0x64(r1)
l.lwz r29,0x68(r1)
l.lwz r30,0x6c(r1)
l.lwz r31,0x70(r1)
l.addi r1,r1,116 //free stack places
l.rfe //recover SR register and prior PC (jumps back to program)
l.nop
 
 
.section .text
 
_start:
372,7 → 247,7
1:
l.sfeq r2, r3
l.bf __main
l.noP
l.nop
 
l.sw 0x0(r2), r0
l.addi r2, r2, 0x4
381,7 → 256,7
 
/* Jump to main */
__main:
l.movhi r2,hi(_main)
l.ori r2,r2,lo(_main)
l.movhi r2, hi(_main)
l.ori r2, r2, lo(_main)
l.jr r2
l.nop
/Demo/OpenRISC_SIM_GCC/arch/interrupts.h
0,0 → 1,14
/* Number of interrupt handlers */
#define MAX_INT_HANDLERS 32
 
/* Handler entry */
struct ihnd {
void (*handler)(void *);
void *arg;
};
 
/* Add interrupt handler */
int int_add(unsigned long vect, void (*handler)(void *), void *arg);
 
/* Initialize routine */
int int_init(void);
/Demo/OpenRISC_SIM_GCC/arch/Makefile
1,8 → 1,8
include ../Makefile.inc
 
CFLAGS += -DIC=0 -DDC=0
CFLAGS += -DIC=0 -DDC=0 -g
 
SRC_C = support.c int.c interrupts.c
SRC_C = support.c interrupts.c
SRC_S = reset.S
 
OBJ_C = $(SRC_C:.c=.o)
/Demo/OpenRISC_SIM_GCC/arch/support.c
1,14 → 1,7
/* Support */
#include "spr_defs.h"
#include "support.h"
#include "int.h"
 
void int_main();
 
void ext_except(void) {
int_main();
}
 
/* Start function, called by reset exception handler. */
static char *main_argv[2] = {"NULL", " "};
 
/Demo/OpenRISC_SIM_GCC/drivers/uart.h
122,6 → 122,6
void uart_putc(char);
char uart_getc(void);
void uart_print_str(char *p);
void uart_put_int(int n);
void uart_print_int(int n);
 
#endif
/Demo/OpenRISC_SIM_GCC/drivers/uart.c
35,9 → 35,6
/* Set RX interrupt for each byte */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
 
/* Enable RX interrupt */
REG8(UART_BASE + UART_IER) = UART_IER_RDI | UART_IER_THRI;
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
80,7 → 77,7
}
}
 
void uart_put_int(int n) {
void uart_print_int(int n) {
int a;
char c;
if (n<0) {
89,7 → 86,7
}
 
a = n/10;
if(a) uart_put_int(a);
if(a) uart_print_int(a);
 
c = '0' + (n % 10);
uart_putc(c);
/Demo/OpenRISC_SIM_GCC/drivers/Makefile
1,7 → 1,7
include ../Makefile.inc
 
INCDIR = -I../arch
CFLAGS += $(INCDIR)
CFLAGS += $(INCDIR) -g
 
SRC_C = uart.c
SRC_S =

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