OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc/trunk/rtos/freertos-6.1.1
    from Rev 668 to Rev 669
    Reverse comparison

Rev 668 → Rev 669

/Source/portable/GCC/OpenRISC/port.c
88,14 → 88,11
inline void vPortDisableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt stop
// mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_IEE)); // interrupt stop
// mtspr(SPR_SR, mfspr(SPR_SR) & ~(SPR_SR_TEE)); // interrupt stop
}
 
inline void vPortEnableInterrupts( void )
{
mtspr(SPR_SR, mfspr(SPR_SR) | (SPR_SR_TEE|SPR_SR_IEE)); // Tick, interrupt start
//mtspr(SPR_SR, mfspr(SPR_SR) | (SPR_SR_IEE)); // interrupt start
}
 
 
/Source/portable/GCC/OpenRISC/portasm.S
3,74 → 3,6
.file "portasm.S"
.section .text
 
.macro portSAVE_REGISTER
l.addi r1, r1, -116
l.sw 0x00(r1), r3
l.sw 0x04(r1), r4
l.sw 0x08(r1), r5
l.sw 0x0c(r1), r6
l.sw 0x10(r1), r7
l.sw 0x14(r1), r8
l.sw 0x18(r1), r9
l.sw 0x1c(r1), r10
l.sw 0x20(r1), r11
l.sw 0x24(r1), r12
l.sw 0x28(r1), r13
l.sw 0x2c(r1), r14
l.sw 0x30(r1), r15
l.sw 0x34(r1), r16
l.sw 0x38(r1), r17
l.sw 0x3c(r1), r18
l.sw 0x40(r1), r19
l.sw 0x44(r1), r20
l.sw 0x48(r1), r21
l.sw 0x4c(r1), r22
l.sw 0x50(r1), r23
l.sw 0x54(r1), r24
l.sw 0x58(r1), r25
l.sw 0x5c(r1), r26
l.sw 0x60(r1), r27
l.sw 0x64(r1), r28
l.sw 0x68(r1), r29
l.sw 0x6c(r1), r30
l.sw 0x70(r1), r31
.endm
 
 
.macro portRESTORE_REGISTER
l.lwz r3 , 0x00(r1)
l.lwz r4 , 0x04(r1)
l.lwz r5 , 0x08(r1)
l.lwz r6 , 0x0c(r1)
l.lwz r7 , 0x10(r1)
l.lwz r8 , 0x14(r1)
l.lwz r9 , 0x18(r1)
l.lwz r10, 0x1c(r1)
l.lwz r11, 0x20(r1)
l.lwz r12, 0x24(r1)
l.lwz r13, 0x28(r1)
l.lwz r14, 0x2c(r1)
l.lwz r15, 0x30(r1)
l.lwz r16, 0x34(r1)
l.lwz r17, 0x38(r1)
l.lwz r18, 0x3c(r1)
l.lwz r19, 0x40(r1)
l.lwz r20, 0x44(r1)
l.lwz r21, 0x48(r1)
l.lwz r22, 0x4c(r1)
l.lwz r23, 0x50(r1)
l.lwz r24, 0x54(r1)
l.lwz r25, 0x58(r1)
l.lwz r26, 0x5c(r1)
l.lwz r27, 0x60(r1)
l.lwz r28, 0x64(r1)
l.lwz r29, 0x68(r1)
l.lwz r30, 0x6c(r1)
l.lwz r31, 0x70(r1)
l.addi r1, r1, 116
.endm
 
 
.macro portSAVE_CONTEXT
.global pxCurrentTCB
# make rooms in stack

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.