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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/rtems/c/src/lib/libbsp/mips64orion
    from Rev 30 to Rev 173
    ↔ Reverse comparison
  •

Rev 30 → Rev 173

/p4000/bsp_specs
0,0 → 1,23
%rename cpp old_cpp
%rename lib old_lib
%rename endfile old_endfile
%rename startfile old_startfile
%rename link old_link
 
*cpp:
%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded)
 
*lib:
%{!qrtems: %(old_lib)} %{qrtems: --start-group \
%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
-lc -lgcc --end-group \
%{!qnolinkcmds: -T linkcmds%s}}
 
*startfile:
%{!qrtems: %(old_startfile)} %{qrtems: \
%{!qrtems_debug: start.o%s} \
%{qrtems_debug: start_g.o%s}}
 
*link:
%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start}
 
/p4000/times
0,0 → 1,200
#
# Timing Test Suite Results for the NO_BSP
#
# NOTE: This is just a template. The times are irrelevant since this BSP
# can only be compiled -- not executed.
#
# $Id: times,v 1.2 2001-09-27 12:00:24 chris Exp $
#
# @(#)times 08/01/96 1.4
 
NOTE: To obtain the execution time in microseconds, divide the number of
cycles by the clock speed. For example, if rtems_semaphore create
is reported to be 1164 cycles, then at 66 Mhz it takes 17.64
microseconds or 8.75 microseconds at 133 Mhz.
 
Board: Algorithmics P4000i
CPU: IDT 4650
Clock Speed: 100MHz
Memory Configuration: SRAM, DRAM, cache, etc
Wait States:
 
Times Reported in: cycles
Timer Source: on-CPU cycle counter
 
Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types
Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types
 
# DESCRIPTION A B
== ================================================================= ==== ====
1 rtems_semaphore_create 788 759
rtems_semaphore_delete 903 945
rtems_semaphore_obtain: available 119 119
rtems_semaphore_obtain: not available -- NO_WAIT 118 118
rtems_semaphore_release: no waiting tasks 127 127
 
2 rtems_semaphore_obtain: not available -- caller blocks 842 840
 
3 rtems_semaphore_release: task readied -- preempts caller 777 751
 
4 rtems_task_restart: blocked task -- preempts caller 1611 1595
rtems_task_restart: ready task -- preempts caller 1253 1395
rtems_semaphore_release: task readied -- returns to caller 365 345
rtems_task_create 798 797
rtems_task_start 464 460
rtems_task_restart: suspended task -- returns to caller 517 517
rtems_task_delete: suspended task 529 595
rtems_task_restart: ready task -- returns to caller 527 525
rtems_task_restart: blocked task -- returns to caller 707 684
rtems_task_delete: blocked task 609 675
 
5 rtems_task_suspend: calling task 549 549
rtems_task_resume: task readied -- preempts caller 702 699
 
6 rtems_task_restart: calling task 291 291
rtems_task_suspend: returns to caller 195 194
rtems_task_resume: task readied -- returns to caller 198 198
rtems_task_delete: ready task 734 736
 
7 rtems_task_restart: suspended task -- preempts caller 1049 990
 
8 rtems_task_set_priority: obtain current priority 94 94
rtems_task_set_priority: returns to caller 418 355
rtems_task_mode: obtain current mode 44 43
rtems_task_mode: no reschedule 0 49
rtems_task_mode: reschedule -- returns to caller 0 232
rtems_task_mode: reschedule -- preempts caller 0 687
rtems_task_set_note 0 101
rtems_task_get_note 0 103
rtems_clock_set 0 237
rtems_clock_get 0 16
 
9 rtems_message_queue_create 3583 3432
rtems_message_queue_send: no waiting tasks 252 252
rtems_message_queue_urgent: no waiting tasks 252 252
rtems_message_queue_receive: available 207 207
rtems_message_queue_flush: no messages flushed 95 96
rtems_message_queue_flush: messages flushed 110 110
rtems_message_queue_delete 1044 1111
 
10 rtems_message_queue_receive: not available -- NO_WAIT 132 131
rtems_message_queue_receive: not available -- caller blocks 884 892
 
11 rtems_message_queue_send: task readied -- preempts caller 397 817
 
12 rtems_message_queue_send: task readied -- returns to caller 397 397
 
13 rtems_message_queue_urgent: task readied -- preempts caller 816 817
 
14 rtems_message_queue_urgent: task readied -- returns to caller 397 398
 
15 rtems_event_receive: obtain current events 5 5
rtems_event_receive: not available -- NO_WAIT 99 99
rtems_event_receive: not available -- caller blocks 689 689
rtems_event_send: no task readied 123 123
rtems_event_receive: available 326 349
rtems_event_send: task readied -- returns to caller 333 429
 
16 rtems_event_send: task readied -- preempts caller 843 838
 
17 rtems_task_set_priority: preempts caller 1002 991
 
18 rtems_task_delete: calling task 1171 1157
 
19 rtems_signal_catch 0 1306
rtems_signal_send: returns to caller 0 1019
rtems_signal_send: signal to self 0 496
exit ASR overhead: returns to calling task 0 120
exit ASR overhead: returns to preempting task 0 73
 
20 rtems_partition_create 1293 1306
rtems_region_create 1010 1019
rtems_partition_get_buffer: available 481 496
rtems_partition_get_buffer: not available 120 120
rtems_partition_return_buffer 587 460
rtems_partition_delete 379 320
rtems_region_get_segment: available 179 179
rtems_region_get_segment: not available -- NO_WAIT 349 293
rtems_region_return_segment: no waiting tasks 335 322
rtems_region_get_segment: not available -- caller blocks 1603 1496
rtems_region_return_segment: task readied -- preempts caller 1616 1533
rtems_region_return_segment: task readied -- returns to caller 940 939
rtems_region_delete 301 348
rtems_io_initialize 9 10
rtems_io_open 6 6
rtems_io_close 6 6
rtems_io_read 6 6
rtems_io_write 6 5
rtems_io_control 6 6
 
21 rtems_task_ident 1057 1058
rtems_message_queue_ident 963 963
rtems_semaphore_ident 1137 1136
rtems_partition_ident 962 961
rtems_region_ident 923 924
rtems_port_ident 918 917
rtems_timer_ident 942 941
rtems_rate_monotonic_ident 924 925
 
22 rtems_message_queue_broadcast: task readied -- returns to caller 1084 1095
rtems_message_queue_broadcast: no waiting tasks 147 148
rtems_message_queue_broadcast: task readied -- preempts caller 1305 1268
 
23 rtems_timer_create 202 201
rtems_timer_fire_after: inactive 261 261
rtems_timer_fire_after: active 271 269
rtems_timer_cancel: active 142 141
rtems_timer_cancel: inactive 122 124
rtems_timer_reset: inactive 222 222
rtems_timer_reset: active 246 245
rtems_timer_fire_when: inactive 312 311
rtems_timer_fire_when: active 358 358
rtems_timer_delete: active 263 263
rtems_timer_delete: inactive 247 247
rtems_task_wake_when 833 831
 
24 rtems_task_wake_after: yield -- returns to caller 99 98
rtems_task_wake_after: yields -- preempts caller 479 478
 
25 rtems_clock_tick 313 318
 
26 _ISR_Disable 64 57
_ISR_Flash 51 36
_ISR_Enable 31 18
_Thread_Disable_dispatch 53 37
_Thread_Enable_dispatch 260 233
_Thread_Set_state 446 463
_Thread_Disptach (NO FP) 839 801
context switch: no floating point contexts 673 653
context switch: self 156 162
context switch: to another task 84 70
context switch: restore 1st FP task 1030 1013
fp context switch: save idle, restore idle 969 948
fp context switch: save idle, restore initialized 275 267
fp context switch: save initialized, restore initialized 319 292
_Thread_Resume 512 480
_Thread_Unblock 121 139
_Thread_Ready 199 203
_Thread_Get 27 27
_Semaphore_Get 20 21
_Thread_Get: invalid id 5 5
 
27 interrupt entry overhead: returns to interrupted task 0 0
interrupt exit overhead: returns to interrupted task 27 41
interrupt entry overhead: returns to nested interrupt 0 0
interrupt exit overhead: returns to nested interrupt 0 0
interrupt entry overhead: returns to preempting task 0 0
interrupt exit overhead: returns to preempting task 0 0
 
28 rtems_port_create 574 560
rtems_port_external_to_internal 87 87
rtems_port_internal_to_external 86 86
rtems_port_delete 395 353
 
29 rtems_rate_monotonic_create 621 633
rtems_rate_monotonic_period: initiate period -- returns to caller 773 694
rtems_rate_monotonic_period: obtain status 295 284
rtems_rate_monotonic_cancel 408 451
rtems_rate_monotonic_delete: inactive 453 471
rtems_rate_monotonic_delete: active 332 336
rtems_rate_monotonic_period: conclude periods -- caller blocks 664 686
/p4000/console/console.c
0,0 → 1,274
/*
* This file contains the IDT 4650 console IO package.
*
* Author: Craig Lebakken <craigl@transition.com>
*
* COPYRIGHT (c) 1996 by Transition Networks Inc.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of Transition Networks not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* Transition Networks makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c:
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: console.c,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
 
 
/*
* Rather than deleting this, it is commented out to (hopefully) help
* the submitter send updates.
*
* static char _sccsid[] = "@(#)console.c 08/20/96 1.6\n";
*/
 
 
 
#include <bsp.h>
#include <rtems/libio.h>
#include <ctype.h>
 
char idtsim_getchar( void );
void idtsim_putchar( char c );
void mips_leddisplay( char a, char b, char c, char d );
 
 
/* console_initialize
*
* This routine initializes the console IO driver.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values:
*/
 
rtems_device_driver console_initialize(
rtems_device_major_number major,
rtems_device_minor_number minor,
void *arg
)
{
rtems_status_code status;
status = rtems_io_register_name(
"/dev/console",
major,
(rtems_device_minor_number) 0
);
if (status != RTEMS_SUCCESSFUL)
rtems_fatal_error_occurred(status);
return RTEMS_SUCCESSFUL;
}
 
 
/* is_character_ready
*
* This routine returns TRUE if a character is available.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values:
*/
 
rtems_boolean is_character_ready(
char *ch
)
{
*ch = '\0'; /* return NULL for no particular reason */
return(TRUE);
}
 
/* inbyte
*
* This routine reads a character from the SOURCE.
*
* Input parameters: NONE
*
* Output parameters: NONE
*
* Return values:
* character read from SOURCE
*/
 
char inbyte( void )
{
/*
* If polling, wait until a character is available.
*/
 
return idtsim_getchar();
}
 
/* outbyte
*
* This routine transmits a character out the SOURCE. It may support
* XON/XOFF flow control.
*
* Input parameters:
* ch - character to be transmitted
*
* Output parameters: NONE
*/
 
void outbyte(
char ch
)
{
#define NUM_LEDS 4
static unsigned int cur_led = 0;
static unsigned char led_chars[NUM_LEDS];
 
/*
* If polling, wait for the transmitter to be ready.
* Check for flow control requests and process.
* Then output the character.
*/
 
idtsim_putchar( ch );
 
/* print out first four alpha numeric characters in a line */
if ( ch == '\n' )
{
mips_leddisplay( led_chars[0], led_chars[1], led_chars[2], led_chars[3] );
cur_led = 0;
}
else if ( isalnum( (unsigned char) ch ) && cur_led < NUM_LEDS )
{
led_chars[cur_led++] = ch;
}
 
}
 
 
#if 0
static int console_fd = -1;
#endif
 
/*
* Open entry point
*/
 
rtems_device_driver console_open(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
#if 0
int console_fd = open("tty0", 2); /* open for read/write */
#endif
return RTEMS_SUCCESSFUL;
}
/*
* Close entry point
*/
 
rtems_device_driver console_close(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
#if 0
if ( console_fd )
close( console_fd );
#endif
return RTEMS_SUCCESSFUL;
}
 
/*
* read bytes from the serial port. We only have stdin.
*/
 
rtems_device_driver console_read(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
rtems_libio_rw_args_t *rw_args;
char *buffer;
int maximum;
int count = 0;
rw_args = (rtems_libio_rw_args_t *) arg;
 
buffer = rw_args->buffer;
maximum = rw_args->count;
 
for (count = 0; count < maximum; count++) {
buffer[ count ] = inbyte();
if (buffer[ count ] == '\n' || buffer[ count ] == '\r') {
buffer[ count++ ] = '\n';
break;
}
}
 
rw_args->bytes_moved = count;
return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED;
}
 
/*
* write bytes to the serial port. Stdout and stderr are the same.
*/
 
rtems_device_driver console_write(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
int count;
int maximum;
rtems_libio_rw_args_t *rw_args;
char *buffer;
 
rw_args = (rtems_libio_rw_args_t *) arg;
 
buffer = rw_args->buffer;
maximum = rw_args->count;
 
for (count = 0; count < maximum; count++) {
if ( buffer[ count ] == '\n') {
outbyte('\r');
}
outbyte( buffer[ count ] );
}
 
rw_args->bytes_moved = maximum;
return 0;
}
 
/*
* IO Control entry point
*/
 
rtems_device_driver console_control(
rtems_device_major_number major,
rtems_device_minor_number minor,
void * arg
)
{
return RTEMS_SUCCESSFUL;
}
/p4000/console/led.S
0,0 → 1,23
/*
* $Id: led.S,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
 
#include <iregdef.h>
#include <idtmon.h>
#include <idtcpu.h>
 
 
FRAME(mips_leddisplay,sp,0,ra)
j ra
nop
ENDFRAME(mips_leddisplay)
 
FRAME(sbddisplay,sp,0,ra)
j ra
ENDFRAME(sbddisplay)
 
 
FRAME(sbdblank,sp,0,ra)
j ra
ENDFRAME(sbdblank)
 
/p4000/console/Makefile.am
0,0 → 1,35
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
PGM = $(ARCH)/console.rel
 
C_FILES = console.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
S_FILES = led.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
 
OBJS = $(C_O_FILES) $(S_O_FILES)
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(PGM): $(OBJS)
$(make-rel)
 
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
 
all-local: $(ARCH) $(OBJS) $(PGM)
 
.PRECIOUS: $(PGM)
 
EXTRA_DIST = console.c led.S
 
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/startup/idtmem.S
0,0 → 1,938
/*
 
Based upon IDT provided code with the following release:
 
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
 
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
 
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
 
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
$Id: idtmem.S,v 1.2 2001-09-27 12:00:25 chris Exp $
 
*/
 
/************************************************************************
**
** idtmem.s - memory and cache functions
**
** Copyright 1991 Integrated Device Technology, Inc.
** All Rights Reserved
**
**************************************************************************/
 
/*
* 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack
* to set mem_size.
*/
 
#include <iregdef.h>
#include <idtcpu.h>
#include <idtmon.h>
 
.data
mem_size:
.word 0
dcache_size:
.word 0
icache_size:
#if defined(CPU_R3000)
.word MINCACHE
#endif
#if defined(CPU_R4000)
.word 0
#endif
 
#if defined(CPU_R4000)
.data
scache_size:
.word 0
icache_linesize:
.word 0
dcache_linesize:
.word 0
scache_linesize:
.word 0
#endif
 
 
.text
 
#if defined (CPU_R3000)
#define CONFIGFRM ((2*4)+4)
 
/*************************************************************************
**
** Config_Dcache() -- determine size of Data cache
**
**************************************************************************/
 
FRAME(config_Dcache,sp, CONFIGFRM, ra)
.set noreorder
subu sp,CONFIGFRM
sw ra,CONFIGFRM-4(sp) /* save return address */
sw s0,4*4(sp) /* save s0 in first regsave slot */
mfc0 s0,C0_SR /* save SR */
nop
mtc0 zero,C0_SR /* disable interrupts */
.set reorder
jal _size_cache /* returns Data cache size in v0 */
sw v0, dcache_size /* save it */
and s0, ~SR_PE /* do not clear PE */
.set noreorder
mtc0 s0,C0_SR /* restore SR */
nop
.set reorder
lw s0, 4*4(sp) /* restore s0 */
lw ra,CONFIGFRM-4(sp) /* restore ra */
addu sp,CONFIGFRM /* pop stack */
j ra
ENDFRAME(config_Dcache)
 
/*************************************************************************
**
** Config_Icache() -- determine size of Instruction cache
** MUST be run in uncached mode/handled in idt_csu.s
**
**************************************************************************/
 
FRAME(config_Icache,sp, CONFIGFRM, ra)
.set noreorder
subu sp,CONFIGFRM
sw ra,CONFIGFRM-4(sp) /* save return address */
sw s0,4*4(sp) /* save s0 in first regsave slot */
mfc0 s0,C0_SR /* save SR */
nop
mtc0 zero, C0_SR /* disable interrupts */
li v0,SR_SWC /* swap caches/disable ints */
mtc0 v0,C0_SR
nop
.set reorder
jal _size_cache /* returns instruction cache size */
.set noreorder
mtc0 zero,C0_SR /* swap back caches */
nop
and s0,~SR_PE /* do not inadvertantly clear PE */
mtc0 s0,C0_SR /* restore SR */
nop
.set reorder
sw v0, icache_size /* save it AFTER caches back */
lw s0,4*4(sp) /* restore s0 */
lw ra,CONFIGFRM-4(sp) /* restore ra */
addu sp,CONFIGFRM /* pop stack */
j ra
ENDFRAME(config_Icache)
 
/************************************************************************
**
** _size_cache()
** returns cache size in v0
**
************************************************************************/
 
FRAME(_size_cache,sp,0,ra)
.set noreorder
mfc0 t0,C0_SR /* save current sr */
nop
and t0,~SR_PE /* do not inadvertently clear PE */
or v0,t0,SR_ISC /* isolate cache */
mtc0 v0,C0_SR
/*
* First check if there is a cache there at all
*/
move v0,zero
li v1,0xa5a5a5a5 /* distinctive pattern */
sw v1,K0BASE /* try to write into cache */
lw t1,K0BASE /* try to read from cache */
nop
mfc0 t2,C0_SR
nop
.set reorder
and t2,SR_CM
bne t2,zero,3f /* cache miss, must be no cache */
bne v1,t1,3f /* data not equal -> no cache */
/*
* Clear cache size boundries to known state.
*/
li v0,MINCACHE
1:
sw zero,K0BASE(v0)
sll v0,1
ble v0,MAXCACHE,1b
 
li v0,-1
sw v0,K0BASE(zero) /* store marker in cache */
li v0,MINCACHE /* MIN cache size */
 
2: lw v1,K0BASE(v0) /* Look for marker */
bne v1,zero,3f /* found marker */
sll v0,1 /* cache size * 2 */
ble v0,MAXCACHE,2b /* keep looking */
move v0,zero /* must be no cache */
.set noreorder
3: mtc0 t0,C0_SR /* restore sr */
j ra
nop
ENDFRAME(_size_cache)
.set reorder
 
 
#define FLUSHFRM (2*4)
 
/***************************************************************************
**
** flush_Dcache() - flush entire Data cache
**
****************************************************************************/
FRAME(flush_Dcache,sp,FLUSHFRM,ra)
lw t2, dcache_size
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
and t3,~SR_PE /* dont inadvertently clear PE */
beq t2,zero,_Dflush_done /* no D cache, get out! */
nop
li v0, SR_ISC /* isolate cache */
mtc0 v0, C0_SR
nop
.set reorder
li t0,K0BASE /* set loop registers */
or t1,t0,t2
 
2: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bne t0,t1,2b
 
.set noreorder
_Dflush_done:
mtc0 t3,C0_SR /* restore Status Register */
.set reorder
j ra
ENDFRAME(flush_Dcache)
 
 
/***************************************************************************
**
** flush_Icache() - flush entire Instruction cache
**
** NOTE: Icache can only be flushed/cleared when uncached
** Code forces into uncached memory regardless of calling mode
**
****************************************************************************/
FRAME(flush_Icache,sp,FLUSHFRM,ra)
lw t1,icache_size
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
la v0,1f
li v1,K1BASE
or v0,v1
j v0 /* force into non-cached space */
nop
1:
and t3,~SR_PE /* dont inadvertently clear PE */
beq t1,zero,_Iflush_done /* no i-cache get out */
nop
li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
mtc0 v0,C0_SR
li t0,K0BASE
.set reorder
or t1,t0,t1
 
1: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bne t0,t1,1b
.set noreorder
_Iflush_done:
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
.set reorder
j ra
ENDFRAME(flush_Icache)
 
/**************************************************************************
**
** clear_Dcache(base_addr, byte_count) - flush portion of Data cache
**
** a0 = base address of portion to be cleared
** a1 = byte count of length
**
***************************************************************************/
FRAME(clear_Dcache,sp,0,ra)
 
lw t2, dcache_size /* Data cache size */
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
and t3,~SR_PE /* dont inadvertently clear PE */
nop
nop
.set reorder
/*
* flush data cache
*/
 
.set noreorder
nop
li v0,SR_ISC /* isolate data cache */
mtc0 v0,C0_SR
.set reorder
bltu t2,a1,1f /* cache is smaller than region */
move t2,a1
1: addu t2,a0 /* ending address + 1 */
move t0,a0
 
1: sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bltu t0,t2,1b
 
.set noreorder
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
nop
.set reorder
j ra
ENDFRAME(clear_Dcache)
 
 
/**************************************************************************
**
** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache
**
** a0 = base address of portion to be cleared
** a1 = byte count of length
**
** NOTE: Icache can only be flushed/cleared when uncached
** Code forces into uncached memory regardless of calling mode
**
***************************************************************************/
FRAME(clear_Icache,sp,0,ra)
 
lw t1, icache_size /* Instruction cache size */
/*
* flush text cache
*/
.set noreorder
mfc0 t3,C0_SR /* save SR */
nop
la v0,1f
li v1,K1BASE
or v0,v1
j v0 /* force into non-cached space */
nop
1:
and t3,~SR_PE /* dont inadvertently clear PE */
nop
nop
li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */
mtc0 v0,C0_SR
.set reorder
bltu t1,a1,1f /* cache is smaller than region */
move t1,a1
1: addu t1,a0 /* ending address + 1 */
move t0,a0
 
sb zero,0(t0)
sb zero,4(t0)
sb zero,8(t0)
sb zero,12(t0)
sb zero,16(t0)
sb zero,20(t0)
sb zero,24(t0)
addu t0,32
sb zero,-4(t0)
bltu t0,t1,1b
.set noreorder
mtc0 t3,C0_SR /* un-isolate, enable interrupts */
nop
nop
nop /* allow time for caches to swap */
.set reorder
j ra
ENDFRAME(clear_Icache)
 
 
/**************************************************************************
**
** get_mem_conf - get memory configuration
**
***************************************************************************/
 
 
FRAME(get_mem_conf,sp,0,ra)
 
lw t6, mem_size
sw t6, 0(a0)
lw t7, icache_size
sw t7, 4(a0)
lw t8, dcache_size
sw t8, 8(a0)
j ra
 
ENDFRAME(get_mem_conf)
#endif /* defined CPU_R3000 */
 
#if defined(CPU_R4000)
#define LEAF(label) FRAME(label,sp,0,ra)
#define XLEAF(label) \
.globl label ; \
label:
#define END(label) ENDFRAME(label)
 
/*
* cacheop macro to automate cache operations
* first some helpers...
*/
#define _mincache(size, maxsize) \
bltu size,maxsize,8f ; \
move size,maxsize ; \
8:
 
#define _align(tmp, minaddr, maxaddr, linesize) \
subu tmp,linesize,1 ; \
not tmp ; \
and minaddr,tmp ; \
addu maxaddr,-1 ; \
and maxaddr,tmp
 
/* This is a bit of a hack really because it relies on minaddr=a0 */
#define _doop1(op1) \
cache op1,0(a0)
 
#define _doop2(op1, op2) \
cache op1,0(a0) ; \
cache op2,0(a0)
 
/* specials for cache initialisation */
#define _doop1lw1(op1) \
cache op1,0(a0) ; \
lw zero,0(a0) ; \
cache op1,0(a0)
 
#define _doop121(op1,op2) \
cache op1,0(a0) ; \
nop; \
cache op2,0(a0) ; \
nop; \
cache op1,0(a0)
 
#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \
.set noreorder ; \
7: _doop##tag##ops ; \
bne minaddr,maxaddr,7b ; \
addu minaddr,linesize ; \
.set reorder
 
/* finally the cache operation macros */
#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
_mincache(n, cache_size); \
blez n,9f ; \
addu n,kva ; \
_align(t1, kva, n, cache_linesize) ; \
_oploopn(kva, n, cache_linesize, tag, ops) ; \
9:
 
#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \
blez n,9f ; \
addu n,kva ; \
_align(t1, kva, n, cache_linesize) ; \
_oploopn(kva, n, cache_linesize, tag, ops) ; \
9:
 
#define icacheop(kva, n, cache_size, cache_linesize, op) \
icacheopn(kva, n, cache_size, cache_linesize, 1, (op))
 
#define vcacheop(kva, n, cache_size, cache_linesize, op) \
vcacheopn(kva, n, cache_size, cache_linesize, 1, (op))
 
.text
 
/*
* static void _size_cache() R4000
*
* Internal routine to determine cache sizes by looking at R4000 config
* register. Sizes are returned in registers, as follows:
* t2 icache size
* t3 dcache size
* t6 scache size
* t4 icache line size
* t5 dcache line size
* t7 scache line size
*/
LEAF(_size_cache)
mfc0 t0,C0_CONFIG
 
and t1,t0,CFG_ICMASK
srl t1,CFG_ICSHIFT
li t2,0x1000
sll t2,t1
 
and t1,t0,CFG_DCMASK
srl t1,CFG_DCSHIFT
li t3,0x1000
sll t3,t1
 
li t4,32
and t1,t0,CFG_IB
bnez t1,1f
li t4,16
1:
 
li t5,32
and t1,t0,CFG_DB
bnez t1,1f
li t5,16
1:
 
move t6,zero # default to no scache
move t7,zero #
 
and t1,t0,CFG_C_UNCACHED # test config register
bnez t1,1f # no scache if uncached/non-coherent
li t6,0x100000 # assume 1Mb scache <<-NOTE
and t1,t0,CFG_SBMASK
srl t1,CFG_SBSHIFT
li t7,16
sll t7,t1
1: j ra
END(_size_cache)
 
 
/*
* void config_cache() R4000
*
* Work out size of I, D & S caches, assuming they are already initialised.
*/
LEAF(config_cache)
lw t0,icache_size
bgtz t0,8f # already known?
move v0,ra
bal _size_cache
move ra,v0
 
sw t2,icache_size
sw t3,dcache_size
sw t6,scache_size
sw t4,icache_linesize
sw t5,dcache_linesize
sw t7,scache_linesize
8: j ra
END(config_cache)
 
 
/*
* void _init_cache() R4000
*/
LEAF(_init_cache)
/*
* First work out the sizes
*/
move v0,ra
bal _size_cache
move ra,v0
/*
* The caches may be in an indeterminate state,
* so we force good parity into them by doing an
* invalidate, load/fill, invalidate for each line.
*/
 
/* disable all i/u and cache exceptions */
mfc0 v0,C0_SR
and v1,v0,~SR_IE
or v1,SR_DE
mtc0 v1,C0_SR
 
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
 
/* assume bottom of RAM will generate good parity for the cache */
li a0,PHYS_TO_K0(0)
move a2,t2 # icache_size
move a3,t4 # icache_linesize
move a1,a2
icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I))
 
li a0,PHYS_TO_K0(0)
move a2,t3 # dcache_size
move a3,t5 # dcache_linesize
move a1,a2
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D))
 
/* assume unified I & D in scache <<-NOTE */
blez t6,1f
li a0,PHYS_TO_K0(0)
move a2,t6
move a3,t7
move a1,a2
icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD))
 
1: mtc0 v0,C0_SR
j ra
END(_init_cache)
 
/*
* void flush_cache (void) R4000
*
* Flush and invalidate all caches
*/
LEAF(flush_cache)
/* secondary cacheops do all the work if present */
lw a2,scache_size
blez a2,1f
lw a3,scache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
b 2f
 
1:
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
 
lw a2,dcache_size
lw a3,dcache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
 
2: j ra
END(flush_cache)
/*
* void flush_cache_nowrite (void) R4000
*
* Invalidate all caches
*/
LEAF(flush_cache_nowrite)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
 
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
 
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
 
lw a2,dcache_size
lw a3,dcache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
 
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
li a0,PHYS_TO_K0(0)
move a1,a2
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
 
2: mtc0 v0,C0_SR
j ra
END(flush_cache_nowrite)
/*
* void clean_cache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in all caches
*/
LEAF(clean_cache)
XLEAF(clear_cache)
 
/* secondary cacheops do all the work (if fitted) */
lw a2,scache_size
blez a2,1f
lw a3,scache_linesize
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
b 2f
 
1: lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
/* save kva & n for subsequent loop */
move t8,a0
move t9,a1
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
 
lw a2,dcache_size
lw a3,dcache_linesize
/* restore kva & n */
move a0,t8
move a1,t9
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
 
2: j ra
END(clean_cache)
/*
* void clean_dcache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in primary data cache
*/
LEAF(clean_dcache)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
 
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D)
 
2: j ra
END(clean_dcache)
/*
* void clean_dcache_indexed (unsigned kva, size_t n) R4000
*
* Writeback and invalidate indexed range in primary data cache
*/
LEAF(clean_dcache_indexed)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
 
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
 
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D)
 
2: j ra
END(clean_dcache_indexed)
/*
* void clean_dcache_nowrite (unsigned kva, size_t n) R4000
*
* Invalidate an address range in primary data cache
*/
LEAF(clean_dcache_nowrite)
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
 
vcacheop(a0,a1,a2,a3,Hit_Invalidate_D)
 
2: j ra
END(clean_dcache_nowrite)
/*
* void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in primary data cache
*/
LEAF(clean_dcache_nowrite_indexed)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
 
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
 
lw a2,dcache_size
blez a2,2f
lw a3,dcache_linesize
 
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
 
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Store_Tag_D)
 
2: mtc0 v0,C0_SR
j ra
END(clean_dcache_nowrite_indexed)
/*
* void clean_icache (unsigned kva, size_t n) R4000
*
* Invalidate address range in primary instruction cache
*/
LEAF(clean_icache)
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
 
vcacheop(a0,a1,a2,a3,Hit_Invalidate_I)
 
2: j ra
END(clean_icache)
/*
* void clean_icache_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in primary instruction cache
*/
LEAF(clean_icache_indexed)
lw a2,icache_size
blez a2,2f
lw a3,icache_linesize
 
#ifdef CPU_ORION
srl a2,1 # do one set (half cache) at a time
move t8,a0 # save kva & n
move t9,a1
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
 
addu a0,t8,a2 # do next set
move a1,t9 # restore n
#endif
icacheop(a0,a1,a2,a3,Index_Invalidate_I)
 
2: j ra
END(clean_icache_indexed)
 
 
/*
* void clean_scache (unsigned kva, size_t n) R4000
*
* Writeback and invalidate address range in secondary cache
*/
LEAF(clean_scache)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD)
 
2: j ra
END(clean_scache)
/*
* void clean_scache_indexed (unsigned kva, size_t n) R4000
*
* Writeback and invalidate indexed range in secondary cache
*/
LEAF(clean_scache_indexed)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
 
icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD)
 
2: j ra
END(clean_scache_indexed)
/*
* void clean_scache_nowrite (unsigned kva, size_t n) R4000
*
* Invalidate an address range in secondary cache
*/
LEAF(clean_scache_nowrite)
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
 
vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD)
 
2: j ra
END(clean_scache_nowrite)
/*
* void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000
*
* Invalidate indexed range in secondary cache
*/
LEAF(clean_scache_nowrite_indexed)
mfc0 v0,C0_SR
and v1,v0,~SR_IE
mtc0 v1,C0_SR
 
mtc0 zero,C0_TAGLO
mtc0 zero,C0_TAGHI
 
lw a2,scache_size
blez a2,2f
lw a3,scache_linesize
 
icacheop(a0,a1,a2,a3,Index_Store_Tag_SD)
 
2: mtc0 v0,C0_SR
j ra
END(clean_scache_nowrite_indexed)
/**************************************************************************
**
** get_mem_conf - get memory configuration R4000
**
***************************************************************************/
 
 
FRAME(get_mem_conf,sp,0,ra)
 
lw t6, mem_size
sw t6, 0(a0)
lw t7, icache_size
sw t7, 4(a0)
lw t8, dcache_size
sw t8, 8(a0)
lw t7, scache_size
sw t7, 12(a0)
j ra
 
ENDFRAME(get_mem_conf)
 
#endif /* defined(CPU_R4000) */
 
/*
* void set_mem_size (mem_size)
*
* config_memory()'s memory size gets written into mem_size here.
* Now we don't need to call config_cache() with memory size - New to IDTC6.0
*/
FRAME(set_memory_size,sp,0,ra)
sw a0, mem_size
j ra
ENDFRAME(set_memory_size)
 
 
/p4000/startup/bspstart.c
0,0 → 1,119
/*
* This routine starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before this routine is invoked.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: bspstart.c,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
/*
* Rather than deleting this, it is commented out to (hopefully) help
* the submitter send updates.
*
* static char _sccsid[] = "@(#)bspstart.c 06/11/96 1.2\n";
*/
 
 
#include <bsp.h>
#include <rtems/libio.h>
#include <libcsupport.h>
#include <string.h>
/*
* The original table from the application and our copy of it with
* some changes.
*/
 
extern rtems_configuration_table Configuration;
 
rtems_configuration_table BSP_Configuration;
 
rtems_cpu_table Cpu_table;
 
char *rtems_progname;
 
/*
* Use the shared implementations of the following routines
*/
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, unsigned32, int );
 
/*
* Function: bsp_pretasking_hook
* Created: 95/03/10
*
* Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*
* NOTES:
* Must not use libc (to do io) from here, since drivers are
* not yet initialized.
*
*/
#define LIBC_HEAP_SIZE (64 * 1024)
 
void bsp_pretasking_hook(void)
{
extern int end;
rtems_unsigned32 heap_start;
 
heap_start = (rtems_unsigned32) &end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
 
bsp_libc_init((void *) heap_start, LIBC_HEAP_SIZE, 0);
 
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
extern int end; /* defined by linker */
 
/*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
 
void bsp_start( void )
{
/*
* Allocate the memory for the RTEMS Work Space. This can come from
* a variety of places: hard coded address, malloc'ed from outside
* RTEMS world (e.g. simulator or primitive memory manager), or (as
* typically done by stock BSPs) by subtracting the required amount
* of work space from the last physical address on the CPU board.
*/
 
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
 
BSP_Configuration.work_space_start =
(void *)((unsigned64)((&end) + LIBC_HEAP_SIZE + 0x2000) & ~0x7);
 
/*
* initialize the CPU table for this BSP
*/
 
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.postdriver_hook = bsp_postdriver_hook;
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
Cpu_table.clicks_per_microsecond = CPU_CLOCK_RATE_MHZ;
}
/p4000/startup/ghlinkcmds
0,0 → 1,19
#
# $Id: ghlinkcmds,v 1.2 2001-09-27 12:00:25 chris Exp $
#
 
-map
-sec
{
.text 0x80010000 :
.data align(16) :
.rodata :
.fini :
# .sdata :
.symtab :
.strtab :
.debug :
# .sbss :
.bss align(8) :
.init 0xbfc00000 :
}
/p4000/startup/idttlb.S
0,0 → 1,390
/*
 
Based upon IDT provided code with the following release:
 
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
 
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
 
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
 
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
$Id: idttlb.S,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
 
/*
** idttlb.s - fetch the registers associated with and the contents
** of the tlb.
**
*/
/* 950308: Ketan patched a few tlb functions that would not have worked.*/
#include <iregdef.h>
#include <idtcpu.h>
#include <idtmon.h>
 
 
.text
 
#if defined(CPU_R3000)
/*
** ret_tlblo -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo,sp,0,ra)
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # write to index register
nop
tlbr # put tlb entry in entrylo and hi
nop
mfc0 v0,C0_TLBLO # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
nop
.set reorder
ENDFRAME(ret_tlblo)
#endif
#if defined(CPU_R4000)
/*
** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB
** 'c' callable - as ret_tlblo(index) - where index is the
** tlb entry to return the lo value for - if called from assembly
** language then index should be in register a0.
*/
FRAME(ret_tlblo0,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO0 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo0)
 
FRAME(ret_tlblo1,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # clear interrupts
mfc0 t1,C0_TLBHI # save pid
mtc0 a0,C0_INX # write to index register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # put tlb entry in entrylo and hi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBLO1 # get the requested entry lo
mtc0 t1,C0_TLBHI # restore pid
mtc0 t0,C0_SR # restore status register
j ra
ENDFRAME(ret_tlblo1)
 
/*
** ret_pagemask(index) -- return pagemask contents of tlb entry "index"
*/
FRAME(ret_pagemask,sp,0,ra)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_PAGEMASK # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
ENDFRAME(ret_pagemask)
 
/*
** ret_tlbwired(void) -- return wired register
*/
FRAME(ret_tlbwired,sp,0,ra)
mfc0 v0,C0_WIRED
j ra
ENDFRAME(ret_tlbwired)
#endif
 
/*
** ret_tlbhi -- return the tlb entry high content for tlb entry
** index
*/
FRAME(ret_tlbhi,sp,0,ra)
#if defined(CPU_R3000)
.set noreorder
mfc0 t0,C0_SR # save sr
nop
and t0,~SR_PE
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
sll a0,TLBINX_INXSHIFT # position index
mtc0 a0,C0_INX # drop it in C0 register
nop
tlbr # read entry to entry hi/lo
nop
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
nop
.set reorder
#endif
#if defined(CPU_R4000)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
mtc0 a0,C0_INX # drop it in C0 register
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbr # read entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v0,C0_TLBHI # to return value
mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(ret_tlbhi)
 
/*
** ret_tlbpid() -- return tlb pid contained in the current entry hi
*/
FRAME(ret_tlbpid,sp,0,ra)
#if defined(CPU_R3000)
.set noreorder
mfc0 v0,C0_TLBHI # fetch tlb high
nop
and v0,TLBHI_PIDMASK # isolate and position
srl v0,TLBHI_PIDSHIFT
j ra
nop
.set reorder
#endif
#if defined(CPU_R4000)
mfc0 v0,C0_TLBHI # to return value
nop
and v0,TLBHI_PIDMASK
j ra
#endif
ENDFRAME(ret_tlbpid)
 
/*
** tlbprobe(address, pid) -- probe the tlb to see if address is currently
** mapped
** a0 = vpn - virtual page numbers are 0=0 1=0x1000, 2=0x2000...
** virtual page numbers for the r3000 are in
** entry hi bits 31-12
** a1 = pid - this is a process id ranging from 0 to 63
** this process id is shifted left 6 bits and or'ed into
** the entry hi register
** returns an index value (0-63) if successful -1 -f not
*/
FRAME(tlbprobe,sp,0,ra)
#if defined(CPU_R3000)
.set noreorder
mfc0 t0,C0_SR /* fetch status reg */
and a0,TLBHI_VPNMASK /* isolate just the vpn */
and t0,~SR_PE /* don't inadvertantly clear pe */
mtc0 zero,C0_SR
mfc0 t1,C0_TLBHI
sll a1,TLBHI_PIDSHIFT /* possition the pid */
and a1,TLBHI_PIDMASK
or a0,a1 /* build entry hi value */
mtc0 a0,C0_TLBHI
nop
tlbp /* do the probe */
nop
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
nop
sra v0,v1,TLBINX_INXSHIFT /* get index positioned for return */
1:
mtc0 t1,C0_TLBHI /* restore tlb hi */
mtc0 t0,C0_SR /* restore the status reg */
j ra
nop
.set reorder
#endif
#if defined(CPU_R4000)
mfc0 t0,C0_SR # save sr
mtc0 zero,C0_SR # disable interrupts
mfc0 t1,C0_TLBHI # save current pid
and a0,TLBHI_VPN2MASK # construct tlbhi for probe
and a1,TLBHI_PIDMASK
or a0,a1
mtc0 a0,C0_TLBHI
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbp # probe entry to entry hi/lo0/lo1/mask
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mfc0 v1,C0_INX
li v0,-1
bltz v1,1f
move v0,v1
1: mtc0 t1,C0_TLBHI # restore current pid
mtc0 t0,C0_SR # restore sr
j ra
#endif
ENDFRAME(tlbprobe)
 
/*
** resettlb(index) Invalidate the TLB entry specified by index
*/
FRAME(resettlb,sp,0,ra)
#if defined(CPU_R3000)
.set noreorder
mfc0 t0,C0_TLBHI # fetch the current hi
mfc0 v0,C0_SR # fetch the status reg.
li t2,K0BASE&TLBHI_VPNMASK
and v0,~SR_PE # dont inadvertantly clear PE
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # set up tlbhi
mtc0 zero,C0_TLBLO
sll a0,TLBINX_INXSHIFT
mtc0 a0,C0_INX
nop
tlbwi # do actual invalidate
nop
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
nop
.set reorder
#endif
#if defined(CPU_R4000)
li t2,K0BASE&TLBHI_VPN2MASK
mfc0 t0,C0_TLBHI # save current TLBHI
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_TLBHI # invalidate entry
mtc0 zero,C0_TLBLO0
mtc0 zero,C0_TLBLO1
mtc0 a0,C0_INX
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t0,C0_TLBHI
mtc0 v0,C0_SR
j ra
#endif
ENDFRAME(resettlb)
 
#if defined(CPU_R3000)
/*
** Setup TLB entry
**
** map_tlb(index, tlbhi, phypage)
** a0 = TLB entry index
** a1 = virtual page number and PID
** a2 = physical page
*/
FRAME(map_tlb,sp,0,ra)
.set noreorder
sll a0,TLBINX_INXSHIFT
mfc0 v0,C0_SR # fetch the current status
mfc0 a3,C0_TLBHI # save the current hi
and v0,~SR_PE # dont inadvertantly clear parity
 
mtc0 zero,C0_SR
mtc0 a1,C0_TLBHI # set the hi entry
mtc0 a2,C0_TLBLO # set the lo entry
mtc0 a0,C0_INX # load the index
nop
tlbwi # put the hi/lo in tlb entry indexed
nop
mtc0 a3,C0_TLBHI # put back the tlb hi reg
mtc0 v0,C0_SR # restore the status register
j ra
nop
.set reorder
ENDFRAME(map_tlb)
#endif
#if defined(CPU_R4000)
/*
** Setup R4000 TLB entry
**
** map_tlb4000(mask_index, tlbhi, pte_even, pte_odd)
** a0 = TLB entry index and page mask
** a1 = virtual page number and PID
** a2 = pte -- contents of even pte
** a3 = pte -- contents of odd pte
*/
FRAME(map_tlb4000,sp,0,ra)
and t2,a0,TLBPGMASK_MASK
and a0,TLBINX_INXMASK
mfc0 t1,C0_TLBHI # save current TLBPID
mfc0 v0,C0_SR # save SR and disable interrupts
mtc0 zero,C0_SR
mtc0 t2,C0_PAGEMASK # set
mtc0 a1,C0_TLBHI # set VPN and TLBPID
mtc0 a2,C0_TLBLO0 # set PPN and access bits
mtc0 a3,C0_TLBLO1 # set PPN and access bits
mtc0 a0,C0_INX # set INDEX to wired entry
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
tlbwi # drop it in
.set noreorder
nop; nop; nop; nop; nop; nop; nop; nop
.set reorder
mtc0 t1,C0_TLBHI # restore TLBPID
mtc0 v0,C0_SR # restore SR
j ra
ENDFRAME(map_tlb4000)
#endif
 
 
/*
** Set current TLBPID. This assumes PID is positioned correctly in reg.
** a0.
*/
FRAME(set_tlbpid,sp,0,ra)
.set noreorder
mtc0 a0,C0_TLBHI
j ra
nop
.set reorder
ENDFRAME(set_tlbpid)
 
/p4000/startup/linkcmds
0,0 → 1,113
/*
* $Id: linkcmds,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
OUTPUT_FORMAT("elf32-bigmips")
OUTPUT_ARCH(mips)
/* Do we need any of these for elf?
__DYNAMIC = 0; */
_DYNAMIC_LINK = 0;
 
SECTIONS
{
/* Read-only sections, merged into text segment: */
.text 0x80030000 : /* */
/* .text 0xa0020000 : /* */
/* .text 0x00020000 : /* */
{
_ftext = . ;
*(.init)
eprol = .;
*(.text)
*(.text.*)
*(.gnu.linkonce.t*)
*(.mips16.fn.*)
*(.mips16.call.*)
PROVIDE (__runtime_reloc_start = .);
*(.rel.sdata)
PROVIDE (__runtime_reloc_stop = .);
*(.fini)
/* CREATE_OBJECT_SYMBOLS */
etext = .;
_etext = .;
}
.ctors :
{
___ctors = .;
/*
* This version is preferable but requires a very late
* model binutils (post 2.9.1).
KEEP(*crtbegin.o(.ctors));
KEEP(*(SORT(.ctors.*)));
KEEP(*(.ctors));
*/
*crtbegin.o(.ctors);
*(.ctors.*);
*(.ctors);
___ctors_end = .;
}
.dtors :
{
___dtors = .;
/*
* This version is preferable but requires a very late
* model binutils (post 2.9.1).
KEEP(*crtbegin.o(.dtors));
KEEP(*(SORT(.dtors.*)));
KEEP(*(.dtors));
*/
*crtbegin.o(.dtors);
*(.dtors.*);
*(.dtors);
___dtors_end = .;
}
. = .;
 
 
.rodata ALIGN(8) : { *(.rodata) *(.gnu.linkonce.r*) }
.rodata1 ALIGN(8) :
{
*(.rodata1)
. = ALIGN(8);
}
.reginfo . : { *(.reginfo) }
/* also: .hash .dynsym .dynstr .plt(if r/o) .rel.got */
/* Read-write section, merged into data segment: */
.data ALIGN(16) :
{
_fdata = . ;
*(.data)
CONSTRUCTORS
}
.data1 ALIGN(8) : { *(.data1) }
_gp = . + 0x8000;
.lit8 . : { *(.lit8) }
.lit4 . : { *(.lit4) }
/* also (before uninitialized portion): .dynamic .got .plt(if r/w)
(or does .dynamic go into its own segment?) */
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
.sdata ALIGN(8) : { *(.sdata) }
_edata = .;
__bss_start = ALIGN(8);
_fbss = .;
.sbss ALIGN(8) : { *(.sbss) *(.scommon) }
.bss ALIGN(8) :
{
*(.bss)
*(COMMON)
_end = . ;
end = . ;
}
/* Debug sections. These should never be loadable, but they must have
zero addresses for the debuggers to work correctly. */
.line 0 : { *(.line) }
.debug 0 : { *(.debug) }
.debug_sfnames 0 : { *(.debug_sfnames) }
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_macinfo 0 : { *(.debug_macinfo) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
}
 
/p4000/startup/inittlb.c
0,0 → 1,16
/*
* $Id: inittlb.c,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
#include <idtcpu.h>
 
extern void resettlb( int i );
 
void init_tlb(void)
{
int i;
 
for (i = 0; i < N_TLB_ENTRIES; i++ )
resettlb(i);
}
 
/p4000/startup/bspclean.c
0,0 → 1,37
/* bsp_cleanup()
*
* This routine normally is part of start.s and usually returns
* control to a monitor.
*
* INPUT: NONE
*
* OUTPUT: NONE
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: bspclean.c,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
/*
* Rather than deleting this, it is commented out to (hopefully) help
* the submitter send updates.
*
* static char _sccsid[] = "@(#)bspclean.c 03/15/96 1.1\n";
*/
 
 
 
#include <rtems.h>
#include <bsp.h>
 
void idtsim__exit();
 
void bsp_cleanup( void )
{
idtsim__exit();
}
/p4000/startup/Makefile.am
0,0 → 1,47
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:25 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
VPATH = @srcdir@:@srcdir@/../../../shared
 
PGM = $(ARCH)/startup.rel
 
C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
setvec.c inittlb.c gnatinstallhandler.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
S_FILES = idtmem.S idttlb.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
 
OBJS = $(C_O_FILES) $(S_O_FILES)
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(PGM): $(OBJS)
$(make-rel)
 
$(PROJECT_RELEASE)/lib/ghlinkcmds: ghlinkcmds
$(INSTALL_DATA) $< $@
 
$(PROJECT_RELEASE)/lib/linkcmds: linkcmds
$(INSTALL_DATA) $< $@
 
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/ghlinkcmds \
$(PROJECT_RELEASE)/lib/linkcmds
 
all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
 
.PRECIOUS: $(PGM)
 
EXTRA_DIST = bspclean.c bspstart.c ghlinkcmds idtmem.S idttlb.S inittlb.c \
linkcmds setvec.c
 
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/startup/setvec.c
0,0 → 1,52
/* set_vector
*
* This routine installs an interrupt vector on the target Board/CPU.
* This routine is allowed to be as board dependent as necessary.
*
* INPUT:
* handler - interrupt handler entry point
* vector - vector number
* type - 0 indicates raw hardware connect
* 1 indicates RTEMS interrupt connect
*
* RETURNS:
* address of previous interrupt handler
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: setvec.c,v 1.2 2001-09-27 12:00:25 chris Exp $
*/
 
/*
* Rather than deleting this, it is commented out to (hopefully) help
* the submitter send updates.
*
* static char _sccsid[] = "@(#)setvec.c 04/25/96 1.2\n";
*/
 
 
#include <rtems.h>
#include <bsp.h>
 
mips_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
mips_isr_entry previous_isr;
 
if ( type )
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
else {
/* XXX: install non-RTEMS ISR as "raw" interupt */
rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr );
}
return previous_isr;
}
 
/p4000/include/coverhd.h
0,0 → 1,115
/* coverhd.h
*
* This include file has defines to represent the overhead associated
* with calling a particular directive from C. These are used in the
* Timing Test Suite to ignore the overhead required to pass arguments
* to directives. On some CPUs and/or target boards, this overhead
* is significant and makes it difficult to distinguish internal
* RTEMS execution time from that used to call the directive.
* This file should be updated after running the C overhead timing
* test. Once this update has been performed, the RTEMS Time Test
* Suite should be rebuilt to account for these overhead times in the
* timing results.
*
* NOTE: If these are all zero, then the times reported include
* all calling overhead including passing of arguments.
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: coverhd.h,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
/* @(#)coverhd.h 04/08/96 1.3 */
 
#ifndef __COVERHD_h
#define __COVERHD_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 5
#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4
#define CALLING_OVERHEAD_TASK_CREATE 6
#define CALLING_OVERHEAD_TASK_IDENT 4
#define CALLING_OVERHEAD_TASK_START 5
#define CALLING_OVERHEAD_TASK_RESTART 4
#define CALLING_OVERHEAD_TASK_DELETE 4
#define CALLING_OVERHEAD_TASK_SUSPEND 4
#define CALLING_OVERHEAD_TASK_RESUME 4
#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5
#define CALLING_OVERHEAD_TASK_MODE 4
#define CALLING_OVERHEAD_TASK_GET_NOTE 5
#define CALLING_OVERHEAD_TASK_SET_NOTE 5
#define CALLING_OVERHEAD_TASK_WAKE_WHEN 9
#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4
#define CALLING_OVERHEAD_INTERRUPT_CATCH 5
#define CALLING_OVERHEAD_CLOCK_GET 9
#define CALLING_OVERHEAD_CLOCK_SET 8
#define CALLING_OVERHEAD_CLOCK_TICK 3
 
#define CALLING_OVERHEAD_TIMER_CREATE 4
#define CALLING_OVERHEAD_TIMER_IDENT 4
#define CALLING_OVERHEAD_TIMER_DELETE 4
#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6
#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 10
#define CALLING_OVERHEAD_TIMER_RESET 4
#define CALLING_OVERHEAD_TIMER_CANCEL 4
#define CALLING_OVERHEAD_SEMAPHORE_CREATE 5
#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4
#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4
#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5
#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4
#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5
#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4
 
#define CALLING_OVERHEAD_EVENT_SEND 4
#define CALLING_OVERHEAD_EVENT_RECEIVE 5
#define CALLING_OVERHEAD_SIGNAL_CATCH 5
#define CALLING_OVERHEAD_SIGNAL_SEND 4
#define CALLING_OVERHEAD_PARTITION_CREATE 6
#define CALLING_OVERHEAD_PARTITION_IDENT 4
#define CALLING_OVERHEAD_PARTITION_DELETE 4
#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 4
#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 4
#define CALLING_OVERHEAD_REGION_CREATE 6
#define CALLING_OVERHEAD_REGION_IDENT 4
#define CALLING_OVERHEAD_REGION_DELETE 4
#define CALLING_OVERHEAD_REGION_GET_SEGMENT 5
#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 4
#define CALLING_OVERHEAD_PORT_CREATE 6
#define CALLING_OVERHEAD_PORT_IDENT 4
#define CALLING_OVERHEAD_PORT_DELETE 4
#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4
#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4
 
#define CALLING_OVERHEAD_IO_INITIALIZE 5
#define CALLING_OVERHEAD_IO_OPEN 5
#define CALLING_OVERHEAD_IO_CLOSE 5
#define CALLING_OVERHEAD_IO_READ 5
#define CALLING_OVERHEAD_IO_WRITE 5
#define CALLING_OVERHEAD_IO_CONTROL 5
#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4
#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4
#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3
 
#ifdef __cplusplus
}
#endif
 
#endif
/* end of include file */
/p4000/include/Makefile.am
0,0 → 1,21
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
H_FILES = bsp.h coverhd.h
 
$(PROJECT_INCLUDE):
$(mkinstalldirs) $@
 
$(PROJECT_INCLUDE)/%.h: %.h
$(INSTALL_DATA) $< $@
 
TMPINSTALL_FILES += $(PROJECT_INCLUDE) $(H_FILES:%.h=$(PROJECT_INCLUDE)/%.h)
 
all-local: $(TMPINSTALL_FILES)
 
EXTRA_DIST = bsp.h coverhd.h
 
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/include/bsp.h
0,0 → 1,126
/* bsp.h
*
* This include file contains all board IO definitions.
*
* XXX : put yours in here
*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: bsp.h,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
/* @(#)bsp.h 03/15/96 1.1 */
 
#ifndef __P4000_BSP_h
#define __P4000_BSP_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <rtems.h>
#include <console.h>
#include <clockdrv.h>
 
/*
* confdefs.h overrides for this BSP:
* - number of termios serial ports (defaults to 1)
* - Interrupt stack space is not minimum if defined.
*/
 
/* #define CONFIGURE_NUMBER_OF_TERMIOS_PORTS 2 */
#define CONFIGURE_INTERRUPT_STACK_MEMORY (4 * 1024)
 
extern void WriteDisplay( char * string );
 
/*
* Define the time limits for RTEMS Test Suite test durations.
* Long test and short test duration limits are provided. These
* values are in seconds and need to be converted to ticks for the
* application.
*
*/
 
#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */
#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */
 
/*
* Stuff for Time Test 27
*/
 
#define MUST_WAIT_FOR_INTERRUPT 0
 
#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 )
 
#define Cause_tm27_intr()
 
#define Clear_tm27_intr()
 
#define Lower_tm27_intr()
 
extern unsigned32 mips_get_timer( void );
 
#define CPU_CLOCK_RATE_MHZ (50)
#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */
 
/*
* Simple spin delay in microsecond units for device drivers.
* This is very dependent on the clock speed of the target.
*
* NOTE: This macro generates a warning like "integer constant out
* of range" which is safe to ignore. In 64 bit mode, unsigned32
* types are actually 64 bits long so that comparisons between
* unsigned32 types and pointers are valid. The warning is caused
* by code in the delay macro that is necessary for 64 bit mode.
*/
 
#define delay( microseconds ) \
{ \
unsigned32 _end_clock = mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \
_end_clock %= 0x100000000; /* make sure result is 32 bits */ \
\
/* handle timer overflow, if necessary */ \
while ( _end_clock < mips_get_timer() ); \
\
while ( _end_clock > mips_get_timer() ); \
}
 
/* Constants */
 
#define RAM_START 0
#define RAM_END 0x100000
 
/* miscellaneous stuff assumed to exist */
 
extern rtems_configuration_table BSP_Configuration;
 
/*
* Device Driver Table Entries
*/
 
/*
* NOTE: Use the standard Console driver entry
*/
/*
* NOTE: Use the standard Clock driver entry
*/
 
/* miscellaneous stuff assumed to exist */
 
mips_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
);
 
#ifdef __cplusplus
}
#endif
 
#endif
/* end of include file */
/p4000/configure.in
0,0 → 1,32
dnl Process this file with autoconf to produce a configure script.
dnl
dnl $Id: configure.in,v 1.2 2001-09-27 12:00:24 chris Exp $
 
AC_PREREQ(2.13)
AC_INIT(bsp_specs)
RTEMS_TOP(../../../../../..)
AC_CONFIG_AUX_DIR(../../../../../..)
 
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE(rtems-c-src-lib-libbsp-mips64orion-p4000,$RTEMS_VERSION,no)
AM_MAINTAINER_MODE
 
RTEMS_PROG_CC_FOR_TARGET
RTEMS_CANONICALIZE_TOOLS
 
RTEMS_ENV_RTEMSBSP
RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
RTEMS_CANONICAL_HOST
 
RTEMS_PROJECT_ROOT
 
# Explicitly list all Makefiles here
AC_OUTPUT(
Makefile
console/Makefile
include/Makefile
liblnk/Makefile
start/Makefile
startup/Makefile
wrapup/Makefile)
/p4000/Makefile.am
0,0 → 1,17
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
 
# wrapup is the one that actually builds and installs the library
# from the individual .rel files built in other directories
SUBDIRS = include start startup console liblnk wrapup
 
include $(top_srcdir)/../../bsp.am
 
EXTRA_DIST = bsp_specs times
 
include $(top_srcdir)/../../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/liblnk/Makefile.am
0,0 → 1,32
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
PGM = $(ARCH)/liblnk.rel
 
S_FILES = lnklib.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
 
OBJS = $(S_O_FILES)
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(PGM): $(OBJS)
$(make-rel)
 
# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile
 
all-local: $(ARCH) $(OBJS) $(PGM)
 
.PRECIOUS: $(PGM)
 
EXTRA_DIST = lnklib.S
 
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/liblnk/lnklib.S
0,0 → 1,62
/*
* $Id: lnklib.S,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
 
#include <iregdef.h>
#include <idtcpu.h>
 
#define FRAME(name,frm_reg,offset,ret_reg) \
.globl name; \
.ent name; \
name:; \
.frame frm_reg,offset,ret_reg
 
#define ENDFRAME(name) \
.end name
 
#define PROM_LINK(name,entry) \
.globl name; \
.ent name; \
name: la $2,+entry; \
j $2; \
.end name
 
#define PROM_ENTRY(x) (0xbfc00000+((x)*8))
 
#define PROM_RESET PROM_ENTRY(0)
#define PROM_NOT_IMP PROM_ENTRY(1)
#define PROM_RESTART PROM_ENTRY(2)
#define PROM_REINIT PROM_ENTRY(3)
#define PROM_GETCHAR PROM_ENTRY(11)
#define PROM_PUTCHAR PROM_ENTRY(12)
#define PROM_SHOWCHAR PROM_ENTRY(13)
#define PROM_PRINTF PROM_ENTRY(16)
#define PROM_RETURN PROM_ENTRY(17)
 
#define PROM_RGETS PROM_ENTRY(25)
#define PROM_FLUSHCACHE PROM_ENTRY(28)
#define PROM_CLEARCACHE PROM_ENTRY(29)
#define PROM_SETJMP PROM_ENTRY(30)
#define PROM_LONGJMP PROM_ENTRY(31)
 
.text
 
PROM_LINK(idtsim_putchar, PROM_PUTCHAR)
PROM_LINK(idtsim_getchar, PROM_GETCHAR)
PROM_LINK(idtsim_showchar, PROM_SHOWCHAR)
PROM_LINK(idtsim__exit, PROM_RETURN)
PROM_LINK(idtsim_reinit, PROM_REINIT)
PROM_LINK(idtsim_restart, PROM_RESTART)
PROM_LINK(idtsim_reset, PROM_RESET)
PROM_LINK(idtsim_promexit, PROM_RETURN)
PROM_LINK(idtsim_setjmp, PROM_SETJMP)
PROM_LINK(idtsim_longjmp, PROM_LONGJMP)
 
FRAME(idtsim_init_sbrk,sp,0,ra)
j ra
ENDFRAME(idtsim_init_sbrk)
 
FRAME(idtsim_init_file,sp,0,ra)
j ra
ENDFRAME(idtsim_init_file)
 
/p4000/README
0,0 → 1,47
#
# $Id: README,v 1.2 2001-09-27 12:00:24 chris Exp $
#
# @(#)README 08/20/96 1.2
#
 
BSP NAME: p4000
BOARD: Algorithmics P4000 SBC
BUS: N/A
CPU FAMILY: mips
CPU: IDT 4650
COPROCESSORS: N/A
MODE: 32 bit mode
 
DEBUG MONITOR: IDT/SIM
 
PERIPHERALS
===========
TIMERS: 4650 internal
RESOLUTION: half of internal clock frequency
SERIAL PORTS: IDT/SIM controlled
REAL-TIME CLOCK: none
DMA: none
VIDEO: none
SCSI: none
NETWORKING: none
 
DRIVER INFORMATION
==================
CLOCK DRIVER: 4650 internal
IOSUPP DRIVER: N/A
SHMSUPP: N/A
TIMER DRIVER: 4650 internal
TTY DRIVER: uses IDT/SIM
 
STDIO
=====
PORT: Console port 0
ELECTRICAL: RS-232
BAUD: 9600
BITS PER CHARACTER: 8
PARITY: None
STOP BITS: 1
 
NOTES
=====
 
/p4000/start/Makefile.am
0,0 → 1,32
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
PGM = $(ARCH)/start.o
 
S_FILES = start.S
S_O_FILES = $(S_FILES:%.S=$(ARCH)/%.o)
 
OBJS = $(S_O_FILES)
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o: $(PGM)
$(INSTALL_DATA) $< $@
 
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/start$(LIB_VARIANT).o
 
all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
 
.PRECIOUS: $(PGM)
 
EXTRA_DIST = start.S
 
include $(top_srcdir)/../../../../../../automake/local.am
/p4000/start/start.S
0,0 → 1,299
/*
 
Based upon IDT provided code with the following release:
 
This source code has been made available to you by IDT on an AS-IS
basis. Anyone receiving this source is licensed under IDT copyrights
to use it in any way he or she deems fit, including copying it,
modifying it, compiling it, and redistributing it either with or
without modifications. No license under IDT patents or patent
applications is to be implied by the copyright license.
 
Any user of this software should understand that IDT cannot provide
technical support for this software and will not be responsible for
any consequences resulting from the use of this software.
 
Any person who transfers this source code or any derivative work must
include the IDT copyright notice, this paragraph, and the preceeding
two paragraphs in the transferred software.
 
COPYRIGHT IDT CORPORATION 1996
LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 
$Id: start.S,v 1.2 2001-09-27 12:00:24 chris Exp $
*/
 
/*************************************************************************
**
** Copyright 1991-95 Integrated Device Technology, Inc.
** All Rights Reserved
**
** idt_csu.S -- IDT stand alone startup code
**
**************************************************************************/
#include <iregdef.h>
#include <idtcpu.h>
#include <idtmon.h>
 
 
.extern _fbss,4 /* this is defined by the linker */
.extern end,4 /* this is defined by the linker */
 
.lcomm sim_mem_cfg_struct,12
 
.text
 
 
#define TMP_STKSIZE 1024
 
/**************************************************************************
**
** start - Typicl standalone start up code required for R3000/R4000
**
**
** 1) Initialize the STATUS Register
** a) Clear parity error bit
** b) Set co_processor 1 usable bit ON
** c) Clear all IntMask Enables
** d) Set kernel/disabled mode
** 2) Initialize Cause Register
** a) clear software interrupt bits
** 3) Determine FPU installed or not
** if not, clear CoProcessor 1 usable bit
** 4) Clear bss area
** 5) MUST allocate temporary stack until memory size determined
** It MUST be uncached to prevent overwriting when caches are cleared
** 6) Install exception handlers
** 7) Determine memory and cache sizes
** 8) Establish permanent stack (cached or uncached as defined by bss)
** 9) Flush Instruction and Data caches
** 10) If there is a Translation Lookaside Buffer, Clear the TLB
** 11) Execute initialization code if the IDT/c library is to be used
**
** 12) Jump to user's "main()"
** 13) Jump to promexit
**
** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally.
** This is used to mark code specific to R3xxx or R4xxx processors.
** IDT/C 6.x defines __mips to be the ISA level for which we're
** generating code. This is used to make sure the stack etc. is
** double word aligned, when using -mips3 (default) or -mips2,
** when compiling with IDT/C6.x
**
***************************************************************************/
 
FRAME(start,sp,0,ra)
 
.set noreorder
#ifdef _R3000
li v0,SR_PE|SR_CU1 /* reset parity error and set */
/* cp1 usable */
#endif
#ifdef _R4000
#if __mips==3 || defined(R4650)
li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/
/* 4650: Need fr to be set anyway */
#else
li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/
#endif mips3
#endif
 
mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */
nop
mtc0 zero,C0_CAUSE /* clear software interrupts */
nop
 
#ifdef _R4000
li v0,CFG_C_NONCOHERENT # initialise default cache mode
mtc0 v0,C0_CONFIG
#endif
 
/*
** check to see if an fpu is really plugged in
*/
li t3,0xaaaa5555 /* put a's and 5's in t3 */
mtc1 t3,fp0 /* try to write them into fp0 */
mtc1 zero,fp1 /* try to write zero in fp */
mfc1 t0,fp0
mfc1 t1,fp1
nop
bne t0,t3,1f /* branch if no match */
nop
bne t1,zero,1f /* double check for positive id */
nop
/* We have a FPU. clear fcsr */
ctc1 zero, fcr31
j 2f /* status register already correct */
nop
1:
#ifdef _R3000
li v0, SR_PE /* reset parity error/NO cp1 usable */
#endif
 
#ifdef _R4000
li v0,SR_DE /* clear ERL and disable FPA */
#endif
 
mtc0 v0, C0_SR /* reset status register */
2:
la gp, _gp
 
la v0,_fbss /* clear bss before using it */
la v1,end /* end of bss */
3: sw zero,0(v0)
bltu v0,v1,3b
add v0,4
 
 
/************************************************************************
**
** Temporary Stack - needed to handle stack saves until
** memory size is determined and permanent stack set
**
** MUST be uncached to avoid confusion at cache
** switching during memory sizing
**
*************************************************************************/
#if __mips==3
/* For MIPS 3, we need to be sure that the stack is aligned on a
* double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 11f /* Last three bits Zero, already aligned */
nop
add v0, 4
11:
#endif
 
or v0, K1BASE /* switch to uncached */
add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */
sub v1, v1, (4*4) /* overhead */
move sp, v1 /* set sp to top of stack */
4: sw zero, 0(v0)
bltu v0, v1, 4b /* clear out temp stack */
add v0, 4
jal init_exc_vecs /* install exception handlers */
nop /* MUST do before memory probes */
 
la v0, 5f
li v1, K1BASE /* force into uncached space */
or v0, v1 /* during memory/cache probes */
j v0
nop
5:
la a0, sim_mem_cfg_struct
jal sim_mem_cfg /* Make SIM call to get mem size */
nop
la a0, sim_mem_cfg_struct
lw a0, 0(a0) /* Get memory size from struct */
#ifdef _R3000
jal config_Icache
nop
jal config_Dcache /* determine size of D & I caches */
nop
#endif
#ifdef _R4000
jal config_cache /* determine size of D & I caches */
nop
#endif
 
move v0, a0 /* mem_size */
 
#if __mips==3
/* For MIPS 3, we need to be sure that the stack (and hence v0
* here) is aligned on a double word boundary.
*/
andi t0, v0, 0x7
beqz t0, 12f /* Last three bits Zero, already aligned */
nop
subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/
12:
#endif
 
 
 
/**************************************************************************
**
** Permanent Stack - now know top of memory, put permanent stack there
**
***************************************************************************/
 
la t2, _fbss /* cache mode as linked */
and t2, 0xF0000000 /* isolate segment */
la t1, 6f
j t1 /* back to original cache mode */
nop
6:
or v0, t2 /* stack back to original cache mode */
addiu v0,v0,-16 /* overhead */
move sp, v0 /* now replace count w top of memory */
move v1, v0
subu v1, P_STACKSIZE /* clear requested stack size */
 
7: sw zero, 0(v1) /* clear P_STACKSIZE stack */
bltu v1,v0,7b
add v1, 4
.set reorder
 
#ifdef _R3000
jal flush_Icache
jal flush_Dcache /* flush Data & Instruction caches */
#endif
#ifdef _R4000
jal flush_cache_nowrite /* flush Data & Instruction caches */
#endif
 
 
 
/**************************************************************************
**
** If this chip supports a Translation Lookaside Buffer, clear it
**
***************************************************************************/
 
.set noreorder
mfc0 t1, C0_SR /* look at Status Register */
nop
.set reorder
#ifdef _R3000
li t2, SR_TS /* TLB Shutdown bit */
and t1,t2 /* TLB Shutdown if 1 */
bnez t1, 8f /* skip clearing if no TLB */
#endif
 
#ifndef R4650
jal init_tlb /* clear the tlb */
#endif
 
 
/************************************************************************
**
** Initialization required if using IDT/c or libc.a, standard C Lib
**
** can SKIP if not necessary for application
**
************************************************************************/
8:
 
jal idtsim_init_sbrk
jal idtsim_init_file
/*********************** END I/O initialization **********************/
 
 
jal main
 
jal idtsim_promexit
 
ENDFRAME(start)
 
 
.globl sim_mem_cfg
sim_mem_cfg:
.set noat
.set noreorder
li AT, (0xbfc00000+((55)*8))
jr AT
nop
.set at
.set reorder
/p4000/wrapup/Makefile.am
0,0 → 1,34
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:25 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
BSP_FILES = startup console liblnk
CPU_FILES = clock timer
 
# bummer; have to use $foreach since % pattern subst rules only replace 1x
OBJS = $(foreach piece, $(BSP_FILES), $(wildcard ../$(piece)/$(ARCH)/*.o)) \
$(foreach piece, $(CPU_FILES), ../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(piece).rel)
LIB = $(ARCH)/libbsp.a
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(LIB): $(OBJS)
$(make-library)
 
$(PROJECT_RELEASE)/lib/libbsp$(LIB_VARIANT).a: $(LIB)
$(INSTALL_DATA) $< $@
 
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/libbsp$(LIB_VARIANT).a
 
all-local: $(ARCH) $(OBJS) $(LIB) $(TMPINSTALL_FILES)
 
.PRECIOUS: $(LIB)
 
include $(top_srcdir)/../../../../../../automake/local.am
/configure.in
0,0 → 1,24
dnl Process this file with autoconf to produce a configure script.
dnl
dnl $Id: configure.in,v 1.2 2001-09-27 12:00:24 chris Exp $
 
AC_PREREQ(2.13)
AC_INIT(p4000)
RTEMS_TOP(../../../../..)
AC_CONFIG_AUX_DIR(../../../../..)
 
RTEMS_CANONICAL_TARGET_CPU
AM_INIT_AUTOMAKE(rtems-c-src-lib-libbsp-mips64orion,$RTEMS_VERSION,no)
AM_MAINTAINER_MODE
 
RTEMS_ENV_RTEMSBSP
RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
RTEMS_PROJECT_ROOT
 
RTEMS_BSP_ALIAS(${RTEMS_BSP},bspdir)
AC_CONFIG_SUBDIRS($bspdir)
 
# Explicitly list all Makefiles here
AC_OUTPUT(
Makefile)
/Makefile.am
0,0 → 1,12
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:00:24 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal
 
## Descend into the $(RTEMS_BSP_FAMILY) directory
SUBDIRS = $(RTEMS_BSP_FAMILY)
 
include $(top_srcdir)/../../../../../automake/subdirs.am
include $(top_srcdir)/../../../../../automake/local.am
/README
0,0 → 1,7
#
# $Id: README,v 1.2 2001-09-27 12:00:24 chris Exp $
#
 
The MIPS bsp are now called p4600 and p4650, referring to which cpu they use.
The same bsp sub-directory can be used, the cpu is selected by the bsp
specific makefiles (p4600.cfg and p4650.cfg).

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