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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk/rtos/rtems/c/src/lib/libbsp/powerpc/score603e/startup
    from Rev 30 to Rev 173
    ↔ Reverse comparison
  •

Rev 30 → Rev 173

/bspstart.c
0,0 → 1,296
/* bspstart.c
*
* This set of routines starts the application. It includes application,
* board, and monitor specific initialization and configuration.
* The generic CPU dependent initialization has been performed
* before any of these are invoked.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <bsp.h>
#include <rtems/libio.h>
 
#include <libcsupport.h>
 
#include <string.h>
 
/*
* The original table from the application and our copy of it with
* some changes.
*/
extern rtems_configuration_table Configuration;
rtems_configuration_table BSP_Configuration;
rtems_cpu_table Cpu_table;
rtems_unsigned32 bsp_isr_level;
 
/*
* Use the shared implementations of the following routines
*/
 
void bsp_postdriver_hook(void);
void bsp_libc_init( void *, unsigned32, int );
 
/*PAGE
*
* bsp_pretasking_hook
*
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
*/
 
void bsp_pretasking_hook(void)
{
extern int end;
rtems_unsigned32 heap_start;
rtems_unsigned32 heap_size;
 
heap_start = (rtems_unsigned32) &end;
if (heap_start & (CPU_ALIGNMENT-1))
heap_start = (heap_start + CPU_ALIGNMENT) & ~(CPU_ALIGNMENT-1);
 
heap_size = BSP_Configuration.work_space_start - (void *)&end;
heap_size &= 0xfffffff0; /* keep it as a multiple of 16 bytes */
 
bsp_libc_init((void *) heap_start, heap_size, 0);
 
#ifdef RTEMS_DEBUG
rtems_debug_enable( RTEMS_DEBUG_ALL_MASK );
#endif
}
 
/*PAGE
*
* bsp_predriver_hook
*
* Before drivers are setup initialize interupt vectors.
*/
 
void init_RTC();
void initialize_PMC();
 
void bsp_predriver_hook(void)
{
init_RTC();
 
init_PCI();
initialize_universe();
initialize_PCI_bridge ();
 
#if (HAS_PMC_PSC8)
initialize_PMC();
#endif
 
/*
* Initialize Bsp General purpose vector table.
*/
initialize_external_exception_vector();
 
#if (0)
/*
* XXX - Modify this to write a 48000000 (loop to self) command
* to each interrupt location. This is better for debug.
*/
bsp_spurious_initialize();
#endif
 
}
 
/*PAGE
*
* initialize_PMC
*/
 
void initialize_PMC() {
volatile rtems_unsigned32 *PMC_addr;
rtems_unsigned8 data;
 
#if (0) /* First Values sent */
/*
* set PMC base address.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
 
/*
* Clear status, enable SERR and memory space only.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x0201ff37;
 
/*
* Bit 0 and 1 HI cause Medium Loopback to occur.
*/
PMC_addr = (volatile rtems_unsigned32 *)
SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
/* *PMC_addr = data | 0x3; */
*PMC_addr = data & 0xfc;
 
#endif
 
 
#if (1)
 
/*
* Clear status, enable SERR and memory space only.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x4 );
*PMC_addr = 0x020080cc;
 
/*
* set PMC base address.
*/
PMC_addr = SCORE603E_PCI_DEVICE_ADDRESS( 0x14 );
*PMC_addr = (SCORE603E_PCI_REGISTER_BASE >> 24) & 0x3f;
 
PMC_addr = (volatile rtems_unsigned32 *)
SCORE603E_PMC_SERIAL_ADDRESS( 0x100000 );
data = *PMC_addr;
*PMC_addr = data & 0xfc;
 
#endif
}
 
 
 
/*PAGE
*
* SCORE603e_bsp_postdriver_hook
*
* Standard post driver hook plus some BSP specific stuff.
*/
void SCORE603e_bsp_postdriver_hook(void)
{
extern void Init_EE_mask_init(void);
 
bsp_postdriver_hook();
 
Init_EE_mask_init();
}
 
void bsp_set_trap_vectors( void );
 
/*PAGE
*
* bsp_start
*
* This routine does the bulk of the system initialization.
*/
 
void bsp_start( void )
{
unsigned char *work_space_start;
unsigned int msr_value = 0x0000;
volatile rtems_unsigned32 *ptr;
 
delay( 1000 );
 
/*
* Zero out lots of memory
*/
 
memset(
&end,
0,
(unsigned char *)&RAM_END - (unsigned char *) &end
);
 
/*
* There are multiple ROM monitors available for this board.
*/
#if (SCORE603E_USE_SDS)
 
/*
* Write instruction for Unconditional Branch to ROM vector.
*/
Code = 0x4bf00002;
for (Address = 0x100; Address <= 0xe00; Address += 0x100) {
A_Vector = (unsigned32 *)Address;
Code = 0x4bf00002 + Address;
*A_Vector = Code;
}
for (Address = 0x1000; Address <= 0x1400; Address += 0x100) {
A_Vector = (unsigned32 *)Address;
Code = 0x4bf00002 + Address;
*A_Vector = Code;
}
Cpu_table.exceptions_in_RAM = TRUE;
msr_value = 0x2030;
 
#elif (SCORE603E_USE_OPEN_FIRMWARE)
Cpu_table.exceptions_in_RAM = TRUE;
msr_value = 0x2030;
 
#elif (SCORE603E_USE_NONE)
Cpu_table.exceptions_in_RAM = TRUE;
msr_value = 0x2030;
_CPU_MSR_SET( msr_value );
bsp_set_trap_vectors();
 
#elif (SCORE603E_USE_DINK)
Cpu_table.exceptions_in_RAM = TRUE;
msr_value = 0x2030;
_CPU_MSR_SET( msr_value );
 
/*
* Override the DINK error on a Decrementor interrupt.
*/
/* org dec_vector - rfi */
ptr = (rtems_unsigned32 *)0x900;
*ptr = 0x4c000064;
 
#else
#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
#endif
 
_CPU_MSR_SET( msr_value );
 
/*
* Need to "allocate" the memory for the RTEMS Workspace and
* tell the RTEMS configuration where it is. This memory is
* not malloc'ed. It is just "pulled from the air".
*/
 
work_space_start =
(unsigned char *)&RAM_END - BSP_Configuration.work_space_size;
 
if ( work_space_start <= (unsigned char *)&end ) {
DEBUG_puts( "bspstart: Not enough RAM!!!\n" );
bsp_cleanup();
}
 
BSP_Configuration.work_space_start = work_space_start;
 
/*
* initialize the CPU table for this BSP
*/
 
/* Cpu_table.exceptions_in_RAM was set above */
Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */
Cpu_table.predriver_hook = bsp_predriver_hook; /* Init vectors */
Cpu_table.postdriver_hook = SCORE603e_bsp_postdriver_hook;
Cpu_table.clicks_per_usec = 66 / 4; /* XXX get from linkcmds */
Cpu_table.do_zero_of_workspace = TRUE;
Cpu_table.interrupt_stack_size = CONFIGURE_INTERRUPT_STACK_MEMORY;
Cpu_table.idle_task_stack_size = (3 * STACK_MINIMUM_SIZE);
 
#if ( PPC_USE_DATA_CACHE )
instruction_cache_enable ();
data_cache_enable ();
#endif
}
 
/Hwr_init.c
0,0 → 1,213
/* Hwr_init.c
*
* $Id:
*/
 
#include <bsp.h>
 
#define PPC603e_SPR_HID0 1008
#define PPC603e_SPR_HID1 1009
#define PPC603e_SPR_IBAT0U 528
#define PPC603e_SPR_IBAT0L 529
#define PPC603e_SPR_DBAT0U 536
#define PPC603e_SPR_DBAT0L 537
#define PPC603e_SPR_IBAT1U 530
#define PPC603e_SPR_IBAT1L 531
#define PPC603e_SPR_DBAT1U 538
#define PPC603e_SPR_DBAT1L 539
#define PPC603e_SPR_IBAT2U 532
#define PPC603e_SPR_IBAT2L 533
#define PPC603e_SPR_DBAT2U 540
#define PPC603e_SPR_DBAT2L 541
#define PPC603e_SPR_IBAT3U 534
#define PPC603e_SPR_IBAT3L 535
#define PPC603e_SPR_DBAT3U 542
#define PPC603e_SPR_DBAT3L 543
#define PPC603e_SPR_DMISS 976
#define PPC603e_SPR_DCMP 977
#define PPC603e_SPR_HASH1 978
#define PPC603e_SPR_HASH2 979
#define PPC603e_SPR_IMISS 980
#define PPC603e_SPR_ICMP 981
#define PPC603e_SPR_RPA 982
#define PPC603e_SPR_SDR1 25
#define PPC603e_SPR_PVR 287
#define PPC603e_SPR_DAR 19
#define PPC603e_SPR_SPRG0 272
#define PPC603e_SPR_SPRG1 273
#define PPC603e_SPR_SPRG2 274
#define PPC603e_SPR_SPRG3 275
#define PPC603e_SPR_DSISR 18
#define PPC603e_SPR_SRR0 26
#define PPC603e_SPR_SRR1 27
#define PPC603e_SPR_TBL_WRITE 284
#define PPC603e_SPR_TBU_WRITE 285
#define PPC603e_SPR_DEC 22
#define PPC603e_SPR_IABR 1010
#define PPC603e_SPR_EAR 282
 
 
 
#define PCI_MEM_CMD (SCORE603E_PCI_MEM_BASE >> 16)
 
 
typedef struct {
rtems_unsigned32 counter_1_100;
rtems_unsigned32 counter_hours;
rtems_unsigned32 counter_min;
rtems_unsigned32 counter_sec;
rtems_unsigned32 counter_month;
rtems_unsigned32 counter_date;
rtems_unsigned32 counter_year;
rtems_unsigned32 counter_day_of_week;
 
rtems_unsigned32 RAM_1_100;
rtems_unsigned32 RAM_hours;
rtems_unsigned32 RAM_month;
rtems_unsigned32 RAM_date;
rtems_unsigned32 RAM_year;
rtems_unsigned32 RAM_day_of_week;
 
rtems_unsigned32 interupt_status_mask;
rtems_unsigned32 command_register;
}Harris_RTC;
 
void init_RTC()
{
volatile Harris_RTC *the_RTC;
the_RTC = (volatile Harris_RTC *)SCORE603E_RTC_ADDRESS;
 
the_RTC->command_register = 0x0;
}
 
void init_PCI()
{
#if (SCORE603E_USE_SDS) | (SCORE603E_USE_OPEN_FIRMWARE) | (SCORE603E_USE_NONE)
rtems_unsigned32 value;
 
/*
* NOTE: Accessing any memory location not mapped by the BAT
* registers will cause a TLB miss exception.
* Set the DBAT1 to be configured for 256M of PCI MEM
* at 0xC0000000 with Write-through and Guarded Attributed and
* read/write access allowed
*/
 
/* load DBAT1U (spr538) - 256Mbytes, User, Super */
value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
asm volatile(
"isync;"
"mtspr 538, %0"
: "=r" (value)
: "0" (value)
);
 
/* load DBAT1L (spr539) - Write-through, Guarded and Read/Write */
value = SCORE603E_PCI_MEM_BASE | 0x0002;
asm volatile (
"mtspr 539, %0;"
"isync"
: "=r" (value)
: "0" (value)
);
 
#elif (SCORE603E_USE_DINK)
/* DINK Monitor setsup and uses all 4 BAT registers. */
/* The fourth BAT register can be modified to access this area */
 
#if (0)
/*
* NOTE: Accessing any memory location not mapped by the BAT
* registers will cause a TLB miss exception.
* Set the DBAT3 to be configured for 256M of PCI MEM
* at 0xC0000000 with Write-through and Guarded Attributed and
* read/write access allowed
*/
 
/* load DBAT3U (spr542) - 256Mbytes, User, Super */
value = SCORE603E_PCI_MEM_BASE | 0x1FFF;
asm volatile(
"isync;"
"mtspr 542, %0"
: "=r" (value)
: "0" (value)
);
 
/* load DBAT3L (spr543) - Write-through, Guarded and Read/Write */
value = SCORE603E_PCI_MEM_BASE | 0x0002;
asm volatile (
"mtspr 543, %0;"
"isync"
: "=r" (value)
: "0" (value)
);
#endif
 
#else
#error "SCORE603E BSPSTART.C -- what ROM monitor are you using"
#endif
}
 
#define PPC_Get_HID0( _value ) \
do { \
_value = 0; /* to avoid warnings */ \
asm volatile( \
"mfspr %0, 0x3f0;" /* get HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
 
#define PPC_Set_HID0( _value ) \
do { \
asm volatile( \
"isync;" \
"mtspr 0x3f0, %0;" /* load HID0 */ \
"isync" \
: "=r" (_value) \
: "0" (_value) \
); \
} while (0)
 
 
void instruction_cache_enable ()
{
rtems_unsigned32 value;
 
/*
* Enable the instruction cache
*/
 
PPC_Get_HID0( value );
 
value |= 0x00008000; /* Set ICE bit */
 
PPC_Set_HID0( value );
}
 
void data_cache_enable ()
{
rtems_unsigned32 value;
 
/*
* enable data cache
*/
 
PPC_Get_HID0( value );
 
value |= 0x00004000; /* set DCE bit */
 
PPC_Set_HID0( value );
}
 
 
 
 
 
 
 
 
 
 
/linkcmds
0,0 → 1,191
OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc",
"elf32-powerpc")
 
OUTPUT_ARCH(powerpc)
ENTRY(_start)
 
/*
* Number of Decrementer countdowns per millisecond
*
* Calculated by: (66 Mhz * 1000) / 4 cycles per click
*/
 
PROVIDE(CPU_PPC_CLICKS_PER_MS = 16500);
 
/*
MEMORY
{
VECTORS : ORIGIN = 0, LENGTH = 64K
RAM : ORIGIN = 1M, LENGTH = 31M
EPROM : ORIGIN = 0xFFF00000, LENGTH = 0x80000
}
*/
 
SECTIONS
{
.vectors 0x00100 :
{
*(.vectors)
}
 
/* Read-only sections, merged into text segment: */
/* SDS ROM worked at 0x30000 */
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rela.text : { *(.rela.text) }
.rela.data : { *(.rela.data) }
.rela.rodata : { *(.rela.rodata) }
.rela.got : { *(.rela.got) }
.rela.got1 : { *(.rela.got1) }
.rela.got2 : { *(.rela.got2) }
.rela.ctors : { *(.rela.ctors) }
.rela.dtors : { *(.rela.dtors) }
.rela.init : { *(.rela.init) }
.rela.fini : { *(.rela.fini) }
.rela.bss : { *(.rela.bss) }
.rela.plt : { *(.rela.plt) }
.rela.sdata : { *(.rela.sdata2) }
.rela.sbss : { *(.rela.sbss2) }
.rela.sdata2 : { *(.rela.sdata2) }
.rela.sbss2 : { *(.rela.sbss2) }
.plt : { *(.plt) }
.text 0x100000:
{
*(.text)
*(.gnu.linkonce.t.*)
*(.descriptors)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
}
.init : { *(.init) }
.fini : { *(.fini) }
.rodata : { *(.rodata) *(.gnu.linkonce.r*) }
.rodata1 : {
*(.rodata1)
_etext = .;
PROVIDE (_etext = .);
}
PROVIDE (__SDATA2_START__ = .);
.sdata2 : { *(.sdata2) }
.sbss2 : { *(.sbss2) }
PROVIDE (__SBSS2_END__ = .);
/* Adjust the address for the data segment. We want to adjust up to
the same address within the page on the next page up. It would
be more correct to do this:
. = ALIGN(0x40000) + (ALIGN(8) & (0x40000 - 1));
The current expression does not correctly handle the case of a
text segment ending precisely at the end of a page; it causes the
data segment to skip a page. The above expression does not have
this problem, but it will currently (2/95) cause BFD to allocate
a single segment, combining both text and data, for this case.
This will prevent the text segment from being shared among
multiple executions of the program; I think that is more
important than losing a page of the virtual address space (note
that no actual memory is lost; the page which is skipped can not
be referenced). */
. = ALIGN(8) + 0x40000;
PROVIDE (sdata = .);
.data :
{
*(.data)
*(.gnu.linkonce.d.*)
CONSTRUCTORS
}
PROVIDE (__EXCEPT_START__ = .);
.gcc_except_table : { *(.gcc_except_table) }
PROVIDE (__EXCEPT_END__ = .);
 
.data1 : { *(.data1) }
.got1 : { *(.got1) }
.dynamic : { *(.dynamic) }
/* Put .ctors and .dtors next to the .got2 section, so that the pointers
get relocated with -mrelocatable. Also put in the .fixup pointers.
The current compiler no longer needs this, but keep it around for 2.7.2 */
PROVIDE (_GOT2_START_ = .);
.got2 : { *(.got2) }
PROVIDE (__GOT2_END__ = .);
PROVIDE (__CTOR_LIST__ = .);
.ctors : { *(.ctors) }
PROVIDE (__CTOR_END__ = .);
PROVIDE (__DTOR_LIST__ = .);
.dtors : { *(.dtors) }
PROVIDE (__DTOR_END__ = .);
PROVIDE (_FIXUP_START_ = .);
.fixup : { *(.fixup) }
PROVIDE (_FIXUP_END_ = .);
PROVIDE (__FIXUP_END__ = .);
PROVIDE (_GOT2_END_ = .);
.got : {
PROVIDE (_GOT_START_ = .);
s.got = .;
*(.got)
}
.got.plt : { *(.got.plt) }
PROVIDE (_GOT_END_ = .);
PROVIDE (__GOT_END__ = .);
/* We want the small data sections together, so single-instruction offsets
can access them all, and initialized data all before uninitialized, so
we can shorten the on-disk segment size. */
PROVIDE (__SDATA_START__ = .);
.sdata : {
*(.sdata)
_edata = .;
}
PROVIDE (_edata = .);
PROVIDE (RAM_END = ADDR(.text) + 10M);
. = ALIGN(8) + 0x1000;
PROVIDE (__SBSS_START__ = .);
.sbss :
{
PROVIDE (__sbss_start = .);
*(.sbss)
*(.scommon)
PROVIDE (__sbss_end = .);
}
PROVIDE (__SBSS_END__ = .);
.bss :
{
PROVIDE (__bss_start = .);
*(.dynbss)
*(.bss)
*(COMMON)
. = ALIGN(8) + 0x8000;
PROVIDE (__stack = .);
_end = . ;
PROVIDE (end = .);
}
 
/* These are needed for ELF backends which have not yet been
converted to the new style linker. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
/* These must appear regardless of . */
}
/vmeintr.c
0,0 → 1,70
/* vmeintr.c
*
* VMEbus support routines for the Generation I board.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <rtems.h>
#include <bsp.h>
#include <vmeintr.h>
 
/*PAGE
*
* VME_interrupt_Disable
*
*/
 
void VME_interrupt_Disable (
VME_interrupt_Mask mask /* IN */
)
{
volatile rtems_unsigned8 *VME_interrupt_enable;
rtems_unsigned8 value;
 
#if 0
VME_interrupt_enable = ACC_VIE;
#else
VME_interrupt_enable = 0;
#endif
value = *VME_interrupt_enable;
 
value &= ~mask; /* turn off interrupts for all levels in mask */
 
*VME_interrupt_enable = value;
}
 
/*PAGE
*
* VME_interrupt_Enable
*
*/
 
void VME_interrupt_Enable (
VME_interrupt_Mask mask /* IN */
)
{
volatile rtems_unsigned8 *VME_interrupt_enable;
rtems_unsigned8 value;
 
#if 0
VME_interrupt_enable = ACC_VIE;
#else
VME_interrupt_enable = 0;
#endif
value = *VME_interrupt_enable;
 
value |= mask; /* turn on interrupts for all levels in mask */
 
*VME_interrupt_enable = value;
}
 
 
/82378zb.c
0,0 → 1,161
/* 82378zb.c
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <bsp.h>
#if (SCORE603E_GENERATION == 1)
#include <rtems/libio.h>
 
#include <libcsupport.h>
 
#include <string.h>
#include <fcntl.h>
#include <assert.h>
/*
* initialize 82378zb
*/
void initialize_PCI_bridge ()
{
 
/*
* INT CNTRL-1 ICW1
* LTIM and ICW4
*/
Write_82378ZB( 0x20, 0x19);
/*
* INT CNTRL-1 ICW 2
* Sets 5 msbs of the base address in the interrupt vector table
* for the vector routines to 0100 0 ??
*/
Write_82378ZB( 0x21, 0x40 );
/*
* INT CNTRL-1 ICW 3
* Cascade CNTRL-2 INT output to IRQ[2] input of CNTRL-1
*/
Write_82378ZB( 0x21, 0x04 );
/*
* INT CNTRL-1 ICW 4
* Set Microprocessor mode for 80x86 system.
*/
Write_82378ZB( 0x21, 0x01 );
/*
* INT CNTRL-1 OCW 2
* Set Non-specific EOI command
*/
Write_82378ZB( 0x20, 0x20 );
/*
* INT CNTRL-1 OCW 3
* Interrupt controller in normal mask mode.
* Disable Poll mode command
* Read IRQ register.
*/
Write_82378ZB( 0x20, 0x2a );
/*
* INT CNTRL-1 OCW 1
* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
* a masked IRQ will not set the interrupt request register (IRR) bit for
* that channel.
*
* XXXX - Was 0xfd Only allowing Timer interrupt through changed to
* 0xe1.
*/
Write_82378ZB( 0x21, 0xe1 );
/*
* INT CNTRL-2 ICW 1
* LTIM and ICW4
*/
Write_82378ZB( 0xa0, 0x19 );
/*
* INT CNTRL-2 ICW 2
* Sets 5 msbs of the base address in the interrupt vector table
* for the vector routines to 0100 1 ??
*/
Write_82378ZB( 0xa1, 0x48 );
/*
* INT CNTRL-1 ICW 3
* Slave Identification Code (Must be intialized to 2).
*/
Write_82378ZB( 0xa1, 0x02 );
/*
* INT CNTRL-1 ICW 4
* Set Microprocessor mode for 80x86 system.
*/
Write_82378ZB( 0xa1, 0x01 );
/*
* INT CNTRL-1 OCW 2
* Set Non-specific EOI command
*/
Write_82378ZB( 0xa0, 0x20 );
/*
* INT CNTRL-1 OCW 3
* Interrupt controller in normal mask mode.
* Disable Poll mode command
* Read IRQ register.
*/
Write_82378ZB( 0xa0, 0x2a );
/*
* INT CNTRL-1 OCW 1
* Write Interrupt Request mask for IRQ[7:0]. An interrupt request for
* a masked IRQ will not set the interrupt request register (IRR) bit for
* that channel.
*
* XXXX - All interrupts masked.
*/
Write_82378ZB( 0xa1, 0xff );
}
 
 
rtems_unsigned16 read_and_clear_irq ()
{
rtems_unsigned16 irq;
 
/*
* XXX - Fix this for all interrupts later
*/
 
Write_82378ZB( 0x20, 0x0c);
Read_82378ZB( 0x20, irq );
irq &= 0x7;
Write_82378ZB( 0x20, 0x20 );
return irq;
}
 
void init_irq_data_register()
{
assert (0);
}
rtems_unsigned16 get_irq_mask()
{
assert (0);
return 0;
}
void set_irq_mask(
rtems_unsigned16 value
)
{
assert (0);
}
#endif /* end of generation 1 */
/bspclean.c
0,0 → 1,16
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id: bspclean.c,v 1.2 2001-09-27 12:01:04 chris Exp $
*/
 
void bsp_cleanup( void )
{
asm volatile( "li 10,99" ); /* 0x63 */
asm volatile( "sc" );
}
/genpvec.c
0,0 → 1,206
/* genpvec.c
*
* These routines handle the external exception. Multiple ISRs occur off
* of this one interrupt.
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <bsp.h>
#include "chain.h"
#include <assert.h>
 
#include <stdio.h> /* for sprintf */
 
 
/*
* Proto types for this file
*/
 
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
);
 
#define NUM_LIRQ_HANDLERS 20
#define NUM_LIRQ ( MAX_BOARD_IRQS - PPC_IRQ_LAST )
 
/*
* Structure to for one of possible multiple interrupt handlers for
* a given interrupt.
*/
typedef struct
{
Chain_Node Node;
rtems_isr_entry handler; /* isr routine */
rtems_vector_number vector; /* vector number */
} EE_ISR_Type;
 
 
/* Note: The following will not work if we add a method to remove
* handlers at a later time.
*/
EE_ISR_Type ISR_Nodes [NUM_LIRQ_HANDLERS];
rtems_unsigned16 Nodes_Used;
Chain_Control ISR_Array [NUM_LIRQ];
 
/* XXX */
void init_irq_data_register();
 
void initialize_external_exception_vector ()
{
int i;
rtems_isr_entry previous_isr;
rtems_status_code status;
 
Nodes_Used = 0;
 
/*
* Mask out all interupts until they have a handler installed.
*/
 
for (i=0; i <NUM_LIRQ; i++)
Chain_Initialize_empty( &ISR_Array[i] );
init_irq_data_register();
/*
* Install external_exception_ISR () as the handler for
* the General Purpose Interrupt.
*/
status = rtems_interrupt_catch( external_exception_ISR,
PPC_IRQ_EXTERNAL, (rtems_isr_entry *) &previous_isr );
}
 
void Init_EE_mask_init() {
;
}
 
/*
* This routine installs one of multiple ISRs for the general purpose
* inerrupt.
*/
rtems_isr_entry set_EE_vector(
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector /* vector number */
)
{
rtems_unsigned16 vec_idx = vector - Score_IRQ_First;
rtems_unsigned32 index;
assert (Nodes_Used < NUM_LIRQ_HANDLERS);
/*
* If we have already installed this handler for this vector, then
* just reset it.
*/
 
for ( index=0 ; index <= Nodes_Used ; index++ ) {
if ( ISR_Nodes[index].vector == vector &&
ISR_Nodes[index].handler == handler )
return NULL;
}
 
/*
* Doing things in this order makes them more atomic
*/
Nodes_Used++;
 
index = Nodes_Used - 1;
 
ISR_Nodes[index].handler = handler;
ISR_Nodes[index].vector = vector;
 
/* printf( "Vector Index: %04x, Vector: %d (%x)\n",
vec_idx, vector, vector); */
 
Chain_Append( &ISR_Array[vec_idx], &ISR_Nodes[index].Node );
 
/*
* Unmask the interrupt.
*/
unmask_irq( vec_idx );
 
return NULL;
}
 
/*
* This interrupt service routine is called for an External Exception.
*/
rtems_isr external_exception_ISR (
rtems_vector_number vector /* IN */
)
{
rtems_unsigned16 index;
EE_ISR_Type *node;
rtems_unsigned16 value;
char err_msg[100];
#if (HAS_PMC_PSC8)
rtems_unsigned16 PMC_irq;
rtems_unsigned16 check_irq;
rtems_unsigned16 status_word;
#endif
 
index = read_and_clear_irq();
if ( index >= NUM_LIRQ ) {
sprintf( err_msg, "ERROR:: Invalid interrupt number (%02x)\n", index );
DEBUG_puts( err_msg );
return;
}
 
#if (HAS_PMC_PSC8)
PMC_irq = SCORE603E_PCI_IRQ_0 - SCORE603E_IRQ00;
 
if (index == PMC_irq) {
status_word = read_and_clear_PMC_irq( index );
 
for (check_irq=SCORE603E_IRQ16; check_irq<=SCORE603E_IRQ19; check_irq++) {
if ( Is_PMC_IRQ( check_irq, status_word )) {
index = check_irq - SCORE603E_IRQ00;
node = (EE_ISR_Type *)(ISR_Array[ index ].first);
 
if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
sprintf(err_msg,"ERROR:: check %d interrupt %02d has no isr\n",
check_irq, index);
DEBUG_puts( err_msg);
value = get_irq_mask();
sprintf(err_msg," Mask = %02x\n", value);
DEBUG_puts( err_msg);
}
while ( !_Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
(*node->handler)( node->vector );
node = (EE_ISR_Type *) node->Node.next;
}
}
}
}
else
#endif
{
node = (EE_ISR_Type *)(ISR_Array[ index ].first);
if ( _Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
sprintf(err_msg,"ERROR:: interrupt %02x has no isr\n", index);
DEBUG_puts( err_msg);
value = get_irq_mask();
sprintf(err_msg," Mask = %02x\n", value);
DEBUG_puts( err_msg);
return;
}
while ( !_Chain_Is_tail( &ISR_Array[ index ], (void *)node ) ) {
(*node->handler)( node->vector );
node = (EE_ISR_Type *) node->Node.next;
}
}
 
}
 
 
 
/Makefile.am
0,0 → 1,46
##
## $Id: Makefile.am,v 1.2 2001-09-27 12:01:04 chris Exp $
##
 
AUTOMAKE_OPTIONS = foreign 1.4
 
VPATH = @srcdir@:@srcdir@/../../../shared
 
PGM = $(ARCH)/startup.rel
 
#
# First and second generation use different Bridge chips :(
# Generation 1 --> 82378zb
# Generation 2 --> FPGA
STARTUP_C_FILES = 82378zb.c FPGA.c
 
C_FILES = bspclean.c bsplibc.c bsppost.c bspstart.c bootcard.c main.c sbrk.c \
setvec.c Hwr_init.c spurious.c genpvec.c $(STARTUP_C_FILES) \
gnatinstallhandler.c
C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
 
OBJS = $(C_O_FILES)
 
include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
include $(top_srcdir)/../../../../../../automake/lib.am
 
#
# (OPTIONAL) Add local stuff here using +=
#
 
$(PGM): $(OBJS)
$(make-rel)
 
$(PROJECT_RELEASE)/lib/linkcmds: linkcmds
$(INSTALL_DATA) $< $@
 
TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/linkcmds
 
all-local: $(ARCH) $(OBJS) $(PGM) $(TMPINSTALL_FILES)
 
.PRECIOUS: $(PGM)
 
EXTRA_DIST = 82378zb.c FPGA.c Hwr_init.c bspclean.c bspstart.c genpvec.c \
linkcmds setvec.c spurious.c vmeintr.c
 
include $(top_srcdir)/../../../../../../automake/local.am
/setvec.c
0,0 → 1,73
/* set_vector
*
* This routine installs an interrupt vector on the target Board/CPU.
* This routine is allowed to be as board dependent as necessary.
*
* INPUT:
* handler - interrupt handler entry point
* vector - vector number
* type - 0 indicates raw hardware connect
* 1 indicates RTEMS interrupt connect
*
* RETURNS:
* address of previous interrupt handler
*
* Author: Andrew Bray <andy@i-cubed.co.uk>
*
* COPYRIGHT (c) 1995 by i-cubed ltd.
*
* To anyone who acknowledges that this file is provided "AS IS"
* without any express or implied warranty:
* permission to use, copy, modify, and distribute this file
* for any purpose is hereby granted without fee, provided that
* the above copyright notice and this notice appears in all
* copies, and that the name of i-cubed limited not be used in
* advertising or publicity pertaining to distribution of the
* software without specific, written prior permission.
* i-cubed limited makes no representations about the suitability
* of this software for any purpose.
*
* Derived from c/src/lib/libbsp/no_cpu/no_bsp/startup/setvec.c:
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <rtems.h>
#include <bsp.h>
 
 
/*
* This routine installs vector number vector.
*
*/
rtems_isr_entry set_vector( /* returns old vector */
rtems_isr_entry handler, /* isr routine */
rtems_vector_number vector, /* vector number */
int type /* RTEMS or RAW intr */
)
{
rtems_isr_entry previous_isr;
rtems_status_code status;
 
 
/*
* vectors greater than PPC603e_IRQ_LAST are handled by the General purpose
* interupt handler.
*/
if ( vector > PPC_IRQ_LAST ) {
set_EE_vector( handler, vector );
}
else {
status = rtems_interrupt_catch(
handler, vector, (rtems_isr_entry *) &previous_isr );
}
return previous_isr;
}
/spurious.c
0,0 → 1,259
/*
* Score603e Spurious Trap Handler
*
* This is just enough of a trap handler to let us know what
* the likely source of the trap was.
*
* Developed as part of the port of RTEMS to the ERC32 implementation
* of the SPARC by On-Line Applications Research Corporation (OAR)
* under contract to the European Space Agency (ESA).
*
* COPYRIGHT (c) 1995. European Space Agency.
*
* This terms of the RTEMS license apply to this file.
*
* $Id: spurious.c,v 1.2 2001-09-27 12:01:04 chris Exp $
*/
 
#include <bsp.h>
 
#include <string.h>
 
static const char digits[16] = "0123456789abcdef";
 
rtems_isr bsp_stub_handler(
rtems_vector_number trap
)
{
}
 
/*
* bsp_spurious_handler
*
* Print a message on the debug console and then die
*/
rtems_isr bsp_spurious_handler(
rtems_vector_number trap
)
{
 
switch ( trap ) {
case PPC_IRQ_SYSTEM_RESET:
DEBUG_puts( "\nTrap: System reset" );
break;
case PPC_IRQ_MCHECK:
DEBUG_puts( "\nTrap: Machine check" );
break;
case PPC_IRQ_PROTECT:
DEBUG_puts( "\nTrap: DSI" );
break;
case PPC_IRQ_ISI:
DEBUG_puts( "ISI" );
break;
case PPC_IRQ_EXTERNAL:
DEBUG_puts( "\nTrap: External interupt" );
break;
case PPC_IRQ_ALIGNMENT:
DEBUG_puts( "\nTrap: Alignment Exception" );
break;
case PPC_IRQ_PROGRAM:
DEBUG_puts( "\nTrap: Program" );
break;
case PPC_IRQ_NOFP:
DEBUG_puts( "\nTrap: Floating point unavailable" );
break;
case PPC_IRQ_DECREMENTER:
DEBUG_puts( "\nTrap: Decrementer" );
break;
case PPC_IRQ_RESERVED_A:
DEBUG_puts( "\nTrap: Reserved 0x00a00" );
break;
case PPC_IRQ_RESERVED_B:
DEBUG_puts( "\nTrap: Reserved 0x00b00" );
break;
case PPC_IRQ_SCALL:
DEBUG_puts( "\nTrap: System call" );
break;
case PPC_IRQ_TRACE:
DEBUG_puts( "\nTrap: Trace" );
break;
case PPC_IRQ_FP_ASST:
DEBUG_puts( "\nTrap: Floating point Assist" );
break;
 
#if defined(ppc403)
#error "Please fill in names. "
case PPC_IRQ_CRIT :
DEBUG_puts( "\nTrap: Critical Error ");
break;
case PPC_IRQ_PIT:
DEBUG_puts( "\nTrap: 0x01000" );
break;
case PPC_IRQ_FIT:
DEBUG_puts( "\nTrap: 0x01010" );
break;
case PPC_IRQ_WATCHDOG :
DEBUG_puts( "\nTrap: 0x01020" );
break;
case PPC_IRQ_DEBUG :
DEBUG_puts( "\nTrap: 0x02000" );
break;
 
#elif defined(ppc601)
#error "Please fill in names. "
case PPC_IRQ_TRACE :
DEBUG_puts( "\nTrap: 0x02000" );
break;
 
#elif defined(ppc603)
#error "Please fill in names. "
case PPC_IRQ_TRANS_MISS :
DEBUG_puts( "\nTrap: 0x1000" );
break;
case PPC_IRQ_DATA_LOAD:
DEBUG_puts( "\nTrap: 0x1100" );
break;
case PPC_IRQ_DATA_STORE:
DEBUG_puts( "\nTrap: 0x1200" );
break;
case PPC_IRQ_ADDR_BRK:
DEBUG_puts( "\nTrap: 0x1300" );
break;
case PPC_IRQ_SYS_MGT:
DEBUG_puts( "\nTrap: 0x1400" );
break;
 
#elif defined(ppc603e)
case PPC_TLB_INST_MISS:
DEBUG_puts( "\nTrap: Instruction Translation Miss" );
break;
case PPC_TLB_LOAD_MISS:
DEBUG_puts( "\nTrap: Data Load Translation Miss" );
break;
case PPC_TLB_STORE_MISS :
DEBUG_puts( "\nTrap: Data store Translation Miss");
break;
case PPC_IRQ_ADDRBRK:
DEBUG_puts( "\nTrap: Instruction address break point" );
break;
case PPC_IRQ_SYS_MGT:
DEBUG_puts( "\nTrap: System management interrupt" );
break;
 
#elif defined(ppc604)
#error "Please fill in names. "
case PPC_IRQ_ADDR_BRK:
DEBUG_puts( "0x1300" );
break;
case PPC_IRQ_SYS_MGT:
DEBUG_puts( "0x1400" );
break;
#endif
 
default:
DEBUG_puts( "\nTrap: Undefined exception " );
break;
}
 
/*
* What else can we do but stop ...
*/
/*
asm volatile( "" );
*/
while (1);
}
 
/*
* bsp_spurious_initialize
*
* Install the spurious handler for most traps.
*/
 
void bsp_spurious_initialize()
{
rtems_unsigned32 trap;
 
for ( trap=0 ; trap < PPC_IRQ_LAST ; trap++ ) {
if (trap == PPC_IRQ_DECREMENTER)
;
/* set_vector( bsp_stub_handler, trap, 1 ); */
else
set_vector( bsp_spurious_handler, trap, 1 );
}
}
 
void bsp_set_trap_vectors( void )
{
volatile rtems_unsigned32 *ptr;
 
/* reset_vector */
ptr = (rtems_unsigned32 *)0x00100 ;
*ptr = 0x48000000;
 
/* org mach_vector */
ptr = (rtems_unsigned32 *)0x00200;
*ptr = 0x48000000;
 
/* org prot_vector */
ptr = (rtems_unsigned32 *)0x00300;
*ptr = 0x48000000;
 
/* org isi_vector */
ptr = (rtems_unsigned32 *)0x00400;
*ptr = 0x48000000;
 
/* org ext_vector */
ptr = (rtems_unsigned32 *)0x0500 ;
*ptr = 0x48000000;
 
/* org align_vector */
ptr = (rtems_unsigned32 *)0x00600 ;
*ptr = 0x48000000;
 
/* org prog_vector */
ptr = (rtems_unsigned32 *)0x00700 ;
*ptr = 0x48000000;
 
/* org float_vector */
ptr = (rtems_unsigned32 *)0x00800;
*ptr = 0x48000000;
 
/* org dec_vector - rfi */
ptr = (rtems_unsigned32 *)0x900;
*ptr = 0x4c000064;
 
/* org sys_vector */
ptr = (rtems_unsigned32 *)0x0c00 ;
*ptr = 0x48000000;
 
/* org trace_vector */
ptr = (rtems_unsigned32 *)0x0d00 ;
*ptr = 0x48000000;
 
/* org itm_vector */
ptr = (rtems_unsigned32 *)0x01000 ;
*ptr = 0x48000000;
 
/* org dltm_vector */
ptr = (rtems_unsigned32 *)0x01100 ;
*ptr = 0x48000000;
 
/* org dstm_vector */
ptr = (rtems_unsigned32 *)0x1200 ;
*ptr = 0x48000000;
 
/* org addr_vector */
ptr = (rtems_unsigned32 *)0x1300 ;
*ptr = 0x48000000;
 
/* org sysmgmt_vector */
ptr = (rtems_unsigned32 *)0x1400 ;
*ptr = 0x48000000;
 
}
 
 
 
 
 
/FPGA.c
0,0 → 1,171
/* FPGA.c
*
* COPYRIGHT (c) 1989-1997.
* On-Line Applications Research Corporation (OAR).
* Copyright assigned to U.S. Government, 1994.
*
* The license and distribution terms for this file may in
* the file LICENSE in this distribution or at
* http://www.OARcorp.com/rtems/license.html.
*
* $Id:
*/
 
#include <bsp.h>
#if (SCORE603E_GENERATION == 2)
#include <rtems/libio.h>
 
#include <libcsupport.h>
 
#include <string.h>
#include <fcntl.h>
#include <assert.h>
 
/*
* initialize FPGA
*/
void initialize_PCI_bridge ()
{
#if (!SCORE603E_USE_DINK)
rtems_unsigned16 mask, shift, data;
 
shift = SCORE603E_85C30_0_IRQ - Score_IRQ_First;
mask = 1 << shift;
 
shift = SCORE603E_85C30_1_IRQ - Score_IRQ_First;
mask = mask & (1 << shift);
 
data = *SCORE603E_FPGA_MASK_DATA;
data = ~mask;
 
*SCORE603E_FPGA_MASK_DATA = data;
#endif
 
}
 
void set_irq_mask(
rtems_unsigned16 value
)
{
rtems_unsigned16 *loc;
 
loc = (rtems_unsigned16 *)SCORE603E_FPGA_MASK_DATA;
 
*loc = value;
}
 
rtems_unsigned16 get_irq_mask()
{
rtems_unsigned16 *loc;
rtems_unsigned16 value;
 
loc = (rtems_unsigned16 *)SCORE603E_FPGA_MASK_DATA;
 
value = *loc;
 
return value;
}
 
void unmask_irq(
rtems_unsigned16 irq_idx
)
{
rtems_unsigned16 value;
rtems_unsigned32 mask_idx = irq_idx;
 
value = get_irq_mask();
 
#if (HAS_PMC_PSC8)
switch (irq_idx + Score_IRQ_First ) {
case SCORE603E_85C30_4_IRQ:
case SCORE603E_85C30_2_IRQ:
case SCORE603E_85C30_5_IRQ:
case SCORE603E_85C30_3_IRQ:
mask_idx = SCORE603E_PCI_IRQ_0 - Score_IRQ_First;
break;
default:
break;
}
#endif
 
value &= (~(0x1 << mask_idx));
set_irq_mask( value );
}
 
 
void init_irq_data_register()
{
rtems_unsigned32 index;
rtems_unsigned32 i;
 
#if (SCORE603E_USE_DINK)
set_irq_mask( 0xffff );
#endif
 
/*
* Clear any existing interupts from the vector data register.
*/
for (i=0; i<20; i++) {
index = (*SCORE603E_FPGA_VECT_DATA);
if ( (index&0x10) != 0x10 )
break;
}
}
 
rtems_unsigned16 read_and_clear_PMC_irq(
rtems_unsigned16 irq
)
{
rtems_unsigned16 status_word = irq;
 
status_word = (*SCORE603E_PMC_STATUS_ADDRESS);
 
return status_word;
}
 
rtems_boolean Is_PMC_IRQ(
rtems_unsigned32 pmc_irq,
rtems_unsigned16 status_word
)
{
rtems_boolean result= FALSE;
 
switch(pmc_irq) {
case SCORE603E_85C30_4_IRQ:
result = Is_PMC_85C30_4_IRQ( status_word );
break;
case SCORE603E_85C30_2_IRQ:
result = Is_PMC_85C30_2_IRQ( status_word );
break;
case SCORE603E_85C30_5_IRQ:
result = Is_PMC_85C30_5_IRQ( status_word );
break;
case SCORE603E_85C30_3_IRQ:
result = Is_PMC_85C30_3_IRQ( status_word );
break;
default:
assert( 0 );
break;
}
 
return result;
}
 
rtems_unsigned16 read_and_clear_irq()
{
rtems_unsigned16 irq;
 
irq = (*SCORE603E_FPGA_VECT_DATA);
 
if ((irq & 0xffff0) != 0x10) {
DEBUG_puts( "ERROR:: no irq data\n");
return (irq | 0x80);
}
 
irq &=0xf;
 
return irq;
}
 
#endif /* end of generation 2 */
 

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