OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk
    from Rev 123 to Rev 124
    ↔ Reverse comparison
  •

Rev 123 → Rev 124

/or1ksim/cpu/or32/execute.c
787,15 → 787,6
decode_execute (current);
#endif
 
#if SET_OV_FLAG
/* Check for range exception */
if ((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) &&
(cpu_state.sprs[SPR_SR] & SPR_SR_OV))
{
except_handle (EXCEPT_RANGE, cpu_state.sprs[SPR_EEAR_BASE]);
}
#endif
 
if (breakpoint)
{
except_handle (EXCEPT_TRAP, cpu_state.sprs[SPR_EEAR_BASE]);
/or1ksim/cpu/or32/insnset.c
34,7 → 34,7
temp2 = (orreg_t)PARAM2;
temp3 = (orreg_t)PARAM1;
temp1 = temp2 + temp3;
SET_PARAM0(temp1);
SET_PARAM0 (temp1);
 
/* Set overflow if two negative values gave a positive sum, or if two
positive values gave a negative sum. Otherwise clear it */
227,32 → 227,61
INSTRUCTION (l_and) {
uorreg_t temp1;
temp1 = PARAM1 & PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
if (ARITH_SET_FLAG) {
if(!temp1)
cpu_state.sprs[SPR_SR] |= SPR_SR_F;
else
cpu_state.sprs[SPR_SR] &= ~SPR_SR_F;
}
}
INSTRUCTION (l_or) {
uorreg_t temp1;
temp1 = PARAM1 | PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
}
INSTRUCTION (l_xor) {
uorreg_t temp1;
temp1 = PARAM1 ^ PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
}
INSTRUCTION (l_sub) {
orreg_t temp1;
temp1 = (orreg_t)PARAM1 - (orreg_t)PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
orreg_t temp1, temp2, temp3;
 
temp3 = (orreg_t)PARAM2;
temp2 = (orreg_t)PARAM1;
temp1 = temp2 - temp3;
SET_PARAM0 (temp1);
 
/* Set overflow if a negative value minus a positive value gave a positive
sum, or if a positive value minus a negative value gave a negative
sum. Otherwise clear it */
if ((((long int) temp2 < 0) &&
((long int) temp3 >= 0) &&
((long int) temp1 >= 0)) ||
(((long int) temp2 >= 0) &&
((long int) temp3 < 0) &&
((long int) temp1 < 0)))
{
cpu_state.sprs[SPR_SR] |= SPR_SR_OV;
}
else
{
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV;
}
 
/* Set the carry flag if (as unsigned values) the second operand is greater
than the first. */
if ((uorreg_t) temp3 > (uorreg_t) temp2)
{
cpu_state.sprs[SPR_SR] |= SPR_SR_CY;
}
else
{
cpu_state.sprs[SPR_SR] &= ~SPR_SR_CY;
}
 
/* Trigger a range exception if the overflow flag is set and the SR[OVE] bit
is set. */
if (((cpu_state.sprs[SPR_SR] & SPR_SR_OVE) == SPR_SR_OVE) &&
((cpu_state.sprs[SPR_SR] & SPR_SR_OV) == SPR_SR_OV))
{
except_handle (EXCEPT_RANGE, cpu_state.pc);
}
}
/*int mcount = 0;*/
INSTRUCTION (l_mul) {
398,7 → 427,6
uorreg_t temp1;
 
temp1 = PARAM1 << PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
}
406,7 → 434,6
orreg_t temp1;
temp1 = (orreg_t)PARAM1 >> PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
}
413,7 → 440,6
INSTRUCTION (l_srl) {
uorreg_t temp1;
temp1 = PARAM1 >> PARAM2;
SET_OV_FLAG_FN (temp1);
SET_PARAM0(temp1);
/* runtime.sim.cycles += 2; */
}
/or1ksim/cpu/common/execute.h
39,13 → 39,6
 
#define CURINSN(INSN) (strcmp(cur->insn, (INSN)) == 0)
 
/*! Sets a new SPR_SR_OV value, based on a three register operation. */
#define SET_OV_FLAG_FN(value) \
if((value) & 0x80000000) \
cpu_state.sprs[SPR_SR] |= SPR_SR_OV; \
else \
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OV
 
/*!The main structure holding the current execution state of the CPU
 
Not to be confused with @c runtime, which holds the state of the
/or1ksim/configure.ac
234,7 → 234,7
AC_MSG_RESULT(dynamic)
;;
*)
AC_MSG_ERROR("excecution must one of simple/complex/dynamic")
AC_MSG_ERROR("execution must one of simple/complex/dynamic")
;;
esac
],
265,17 → 265,6
])
AC_MSG_RESULT(${enable_range_stats-no})
 
set_arith_flag="0"
AC_MSG_CHECKING(whether arithmethic instructions set flag)
AC_ARG_ENABLE(arith_flag,
[ --enable-arith-flag Whether arithmethic instructions setflag.], [
case "$enableval" in
no) set_arith_flag="0" ;;
yes) set_arith_flag="1" ;;
esac
])
AC_MSG_RESULT(${enable_arith_flag-no})
 
# check for --enable-debug argument (for argtable2)
AC_ARG_ENABLE(
[debug],
292,7 → 281,6
AC_SUBST(DEBUGFLAGS)
 
AC_DEFINE_UNQUOTED(RAW_RANGE_STATS, $raw_range_stats, [ Specifies, whether we should do register accesses over time analysis. Simple execution must be enabled!])
AC_DEFINE_UNQUOTED(ARITH_SET_FLAG, $set_arith_flag, [Whether arithmethic instructions set flag on zero])
AC_DEFINE_UNQUOTED(HAVE_ETH_PHY, $eth_phy, [Whether we have ethernet PHY support])
AC_DEFINE_UNQUOTED(SIMPLE_EXECUTION, $execution == 0, [Whether we are building with simple execution module])
AC_DEFINE_UNQUOTED(COMPLEX_EXECUTION, $execution == 1, [Whether we are building with complex execution module])
/or1ksim/doc/or1ksim.info
141,34 → 141,6
analyse register access over time. The default is for this to be
disabled.
 
`--enable-arith-flag'
`--disable-arith-flag'
If enabled, this option causes instructions to set the flag (`F'
bit) in the supervision register. The instructions affected by
this are `l.add', `l.addc', `l.addi', `l.and' and `l.andi'.
 
The default is for this to be disabled.
 
Caution: As with `--enable-ov-flag', this appears another
very dangerous option, to the extent of arguably being a bug.
It also appears to be only partially implemented--why only
the instructions early in the alphabet?
 
Whether or not flags are set is part of the OpenRISC 1000
architectural specification. The only flags which should set
this are the "set flag" instructions: `l.sfeq', `l.sfeqi',
`l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui', `l.sfgts',
`l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles', `l.sflesi',
`l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi', `l.sfltu',
`l.sfltui', `l.sfne' and `l.sfnei'.
 
The flags are correctly set (irrespective of
`--enable-arith_flag').
 
Correct behavior is thus achieved if this flag is not set.
`--enable-arith-flag' should never be used.
 
 
`--enable-debug'
`--disable-debug'
This is a feature of the Argtable2 package used to process
187,16 → 159,31
 
 
A number of configuration flags have been removed since version 0.3.0,
because they led to invalid behavior of Or1ksim. Those removed include
because they led to invalid behavior of Or1ksim. Those removed are:
 
`--enable-arith-flag'
`--disable-arith-flag'
If enabled, this option caused certain instructions to set the flag
(`F' bit) in the supervision register if the result were zero.
The instructions affected by this were `l.add', `l.addc',
`l.addi', `l.and' and `l.andi'.
 
If set, this caused incorrect behavior. Whether or not flags are
set is part of the OpenRISC 1000 architectural specification. The
only flags which should set this are the "set flag" instructions:
`l.sfeq', `l.sfeqi', `l.sfges', `l.sfgesi', `l.sfgeu', `l.sfgeui',
`l.sfgts', `l.sfgtsi', `l.sfgtu', `l.sfgtui', `l.sfles',
`l.sflesi', `l.sfleu', `l.sfleui', `l.sflts', `l.sfltsi',
`l.sfltu', `l.sfltui', `l.sfne' and `l.sfnei'.
 
`--enable-ov-flag'
`--disable-ov-flag'
This flag used to cause certain instructions to set the overflow
flag. If not, those instructions would not set the overflow flat.
The instructions affected by this were `l.add', `l.addc',
`l.addi', `l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli',
`l.or', `l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra',
`l.srai', `l.sub', `l.xor' and `l.xori'.
This flag caused certain instructions to set the overflow flag.
If not, those instructions would not set the overflow flat. The
instructions affected by this were `l.add', `l.addc', `l.addi',
`l.and', `l.andi', `l.div', `l.divu', `l.mul', `l.muli', `l.or',
`l.ori', `l.sll', `l.slli', `l.srl', `l.srli', `l.sra', `l.srai',
`l.sub', `l.xor' and `l.xori'.
 
This guaranteed incorrect behavior. The OpenRISC 1000 architecture
specification defines which flags are set by which instructions.
3426,25 → 3413,25
* --debug-config: Standalone Simulator.
(line 48)
* --disable-all-tests: Configuring the Build.
(line 110)
(line 82)
* --disable-arith-flag: Configuring the Build.
(line 95)
* --disable-debug: Configuring the Build.
(line 75)
* --disable-debug: Configuring the Build.
(line 103)
* --disable-ethphy: Configuring the Build.
(line 59)
* --disable-ov-flag: Configuring the Build.
(line 123)
(line 110)
* --disable-profiling: Configuring the Build.
(line 30)
* --disable-range-stats: Configuring the Build.
(line 69)
* --enable-all-tests: Configuring the Build.
(line 109)
(line 81)
* --enable-arith-flag: Configuring the Build.
(line 94)
* --enable-debug: Configuring the Build.
(line 74)
* --enable-debug: Configuring the Build.
(line 102)
* --enable-ethphy: Configuring the Build.
(line 58)
* --enable-execution: Configuring the Build.
3452,7 → 3439,7
* --enable-mprofile: Standalone Simulator.
(line 77)
* --enable-ov-flag: Configuring the Build.
(line 122)
(line 109)
* --enable-profile: Standalone Simulator.
(line 74)
* --enable-profiling: Configuring the Build.
3524,9 → 3511,9
(line 66)
* 16550 (UART configuration): UART Configuration. (line 73)
* all tests enabled: Configuring the Build.
(line 110)
(line 82)
* Argtable2 debugging: Configuring the Build.
(line 103)
(line 75)
* ATA/ATAPI configuration: Disc Interface Configuration.
(line 6)
* ATA/ATAPI device configuration: Disc Interface Configuration.
3679,7 → 3666,7
(line 6)
* Debug Unit verification (VAPI): Verification API. (line 34)
* debugging enabled (Argtable2): Configuring the Build.
(line 103)
(line 75)
* DejaGnu board configurations: Regression Testing. (line 35)
* DejaGnu configuration: Regression Testing. (line 21)
* DejaGNU tests directories: Regression Testing. (line 50)
3806,7 → 3793,7
* firmware (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 117)
* flag setting by instructions: Configuring the Build.
(line 75)
(line 95)
* floating point multiply and add: Known Issues. (line 56)
* floating point support: Known Issues. (line 42)
* frame buffer configuration: Frame Buffer Configuration.
3962,7 → 3949,7
* or1ksim_set_time_point: Simulator Library. (line 73)
* output rediretion: Concepts. (line 7)
* overflow flag setting by instructions: Configuring the Build.
(line 123)
(line 110)
* packet (ATA/ATAPI device configuration): Disc Interface Configuration.
(line 113)
* pagesize (MMU configuration): Memory Management Configuration.
4216,7 → 4203,7
* test README: Regression Testing. (line 32)
* testing: Regression Testing. (line 6)
* tests, all enabled.: Configuring the Build.
(line 110)
(line 82)
* timings_file (CUC configuration): CUC Configuration. (line 46)
* timings_fn (CUC configuration - deprecated): CUC Configuration.
(line 46)
4298,51 → 4285,51
Node: Installation1224
Node: Preparation1471
Node: Configuring the Build1766
Node: Build and Install7464
Node: Known Issues8310
Node: Usage11372
Node: Standalone Simulator11586
Node: Profiling Utility14489
Node: Memory Profiling Utility15399
Node: Simulator Library16764
Node: Configuration24542
Node: Configuration File Format25151
Node: Configuration File Preprocessing25443
Node: Configuration File Syntax25814
Node: Simulator Configuration28599
Node: Simulator Behavior28890
Node: Verification API Configuration32934
Node: CUC Configuration34874
Node: Core OpenRISC Configuration36791
Node: CPU Configuration37293
Node: Memory Configuration41411
Node: Memory Management Configuration47869
Node: Cache Configuration50246
Node: Interrupt Configuration52632
Node: Power Management Configuration53368
Node: Branch Prediction Configuration54645
Node: Debug Interface Configuration56005
Node: Peripheral Configuration60225
Node: Memory Controller Configuration60851
Node: UART Configuration64265
Node: DMA Configuration67784
Node: Ethernet Configuration69651
Node: GPIO Configuration73627
Node: Display Interface Configuration75260
Node: Frame Buffer Configuration77569
Node: Keyboard Configuration79433
Node: Disc Interface Configuration81671
Node: Generic Peripheral Configuration86614
Node: Interactive Command Line88909
Node: Verification API95883
Node: Code Internals100313
Node: Coding Conventions100896
Node: Global Data Structures105323
Node: Concepts107980
Ref: Output Redirection108125
Node: Internal Debugging108664
Node: Regression Testing109188
Node: GNU Free Documentation License112983
Node: Index135390
Node: Build and Install6975
Node: Known Issues7821
Node: Usage10883
Node: Standalone Simulator11097
Node: Profiling Utility14000
Node: Memory Profiling Utility14910
Node: Simulator Library16275
Node: Configuration24053
Node: Configuration File Format24662
Node: Configuration File Preprocessing24954
Node: Configuration File Syntax25325
Node: Simulator Configuration28110
Node: Simulator Behavior28401
Node: Verification API Configuration32445
Node: CUC Configuration34385
Node: Core OpenRISC Configuration36302
Node: CPU Configuration36804
Node: Memory Configuration40922
Node: Memory Management Configuration47380
Node: Cache Configuration49757
Node: Interrupt Configuration52143
Node: Power Management Configuration52879
Node: Branch Prediction Configuration54156
Node: Debug Interface Configuration55516
Node: Peripheral Configuration59736
Node: Memory Controller Configuration60362
Node: UART Configuration63776
Node: DMA Configuration67295
Node: Ethernet Configuration69162
Node: GPIO Configuration73138
Node: Display Interface Configuration74771
Node: Frame Buffer Configuration77080
Node: Keyboard Configuration78944
Node: Disc Interface Configuration81182
Node: Generic Peripheral Configuration86125
Node: Interactive Command Line88420
Node: Verification API95394
Node: Code Internals99824
Node: Coding Conventions100407
Node: Global Data Structures104834
Node: Concepts107491
Ref: Output Redirection107636
Node: Internal Debugging108175
Node: Regression Testing108699
Node: GNU Free Documentation License112494
Node: Index134901

End Tag Table
/or1ksim/doc/or1ksim.texi
178,37 → 178,6
If enabled, this option allows statistics to be collected to analyse
register access over time. The default is for this to be disabled.
 
@item --enable-arith-flag
@cindex @code{--enable-arith-flag}
@itemx --disable-arith-flag
@cindex @code{--disable-arith-flag}
@cindex flag setting by instructions
If enabled, this option causes instructions to set the flag (@code{F} bit) in
the supervision register. The instructions affected by this are @code{l.add},
@code{l.addc}, @code{l.addi}, @code{l.and} and @code{l.andi}.
 
The default is for this to be disabled.
 
@quotation Caution
As with @code{--enable-ov-flag}, this appears another very dangerous option,
to the extent of arguably being a bug. It also appears to be only partially
implemented---why only the instructions early in the alphabet?
 
Whether or not flags are set is part of the OpenRISC 1000 architectural
specification. The only flags which should set this are the ``set flag''
instructions: @code{l.sfeq}, @code{l.sfeqi}, @code{l.sfges}, @code{l.sfgesi},
@code{l.sfgeu}, @code{l.sfgeui}, @code{l.sfgts}, @code{l.sfgtsi},
@code{l.sfgtu}, @code{l.sfgtui}, @code{l.sfles}, @code{l.sflesi},
@code{l.sfleu}, @code{l.sfleui}, @code{l.sflts}, @code{l.sfltsi},
@code{l.sfltu}, @code{l.sfltui}, @code{l.sfne} and @code{l.sfnei}.
 
The flags are correctly set (irrespective of @code{--enable-arith_flag}).
 
Correct behavior is thus achieved if this flag is not set.
@code{--enable-arith-flag} should never be used.
 
@end quotation
 
@item --enable-debug
@cindex @code{--enable-debug}
@itemx --disable-debug
236,22 → 205,41
@end table
 
A number of configuration flags have been removed since version 0.3.0,
because they led to invalid behavior of Or1ksim. Those removed include
because they led to invalid behavior of Or1ksim. Those removed are:
 
@table @code
 
@item --enable-arith-flag
@cindex @code{--enable-arith-flag}
@itemx --disable-arith-flag
@cindex @code{--disable-arith-flag}
@cindex flag setting by instructions
If enabled, this option caused certain instructions to set the flag
(@code{F} bit) in the supervision register if the result were zero.
The instructions affected by this were @code{l.add}, @code{l.addc},
@code{l.addi}, @code{l.and} and @code{l.andi}.
 
If set, this caused incorrect behavior. Whether or not flags are set is part
of the OpenRISC 1000 architectural specification. The only flags which
should set this are the ``set flag'' instructions: @code{l.sfeq},
@code{l.sfeqi}, @code{l.sfges}, @code{l.sfgesi}, @code{l.sfgeu},
@code{l.sfgeui}, @code{l.sfgts}, @code{l.sfgtsi}, @code{l.sfgtu},
@code{l.sfgtui}, @code{l.sfles}, @code{l.sflesi}, @code{l.sfleu},
@code{l.sfleui}, @code{l.sflts}, @code{l.sfltsi}, @code{l.sfltu},
@code{l.sfltui}, @code{l.sfne} and @code{l.sfnei}.
 
@item --enable-ov-flag
@cindex @code{--enable-ov-flag}
@itemx --disable-ov-flag
@cindex @code{--disable-ov-flag}
@cindex overflow flag setting by instructions
This flag used to cause certain instructions to set the overflow flag.
If not, those instructions would not set the overflow flat. The
instructions affected by this were @code{l.add}, @code{l.addc},
@code{l.addi}, @code{l.and}, @code{l.andi}, @code{l.div}, @code{l.divu},
@code{l.mul}, @code{l.muli}, @code{l.or}, @code{l.ori}, @code{l.sll},
@code{l.slli}, @code{l.srl}, @code{l.srli}, @code{l.sra}, @code{l.srai},
@code{l.sub}, @code{l.xor} and @code{l.xori}.
This flag caused certain instructions to set the overflow flag. If not,
those instructions would not set the overflow flat. The instructions
affected by this were @code{l.add}, @code{l.addc}, @code{l.addi},
@code{l.and}, @code{l.andi}, @code{l.div}, @code{l.divu}, @code{l.mul},
@code{l.muli}, @code{l.or}, @code{l.ori}, @code{l.sll}, @code{l.slli},
@code{l.srl}, @code{l.srli}, @code{l.sra}, @code{l.srai}, @code{l.sub},
@code{l.xor} and @code{l.xori}.
 
This guaranteed incorrect behavior. The OpenRISC 1000 architecture
specification defines which flags are set by which instructions.
/or1ksim/doc/version.texi
1,4 → 1,4
@set UPDATED 9 June 2010
@set UPDATED 15 June 2010
@set UPDATED-MONTH June 2010
@set EDITION 2010-06-15
@set VERSION 2010-06-15
/or1ksim/NEWS
7,6 → 7,9
 
No new features are provided, pending full release of 0.4.0.
 
The configuration options --enable-arith-flag and --enable-ov-flag have been
removed, since they were the source of bugs, notably Bugs 1782, 1783 and 1784.
 
The following bugs are fixed.
* Bug 1770: l.div does not set carry or give correct exception.
* Bug 1771: l.add* do not correctly set the overflow flag.
18,6 → 21,9
* Bug 1777: l.macrc not correctly implemented.
* Bug 1778: l.ror and l.rori are not implemented.
* Bug 1779: l.mtspr implementation is incorrect.
* Bug 1782: Or1ksim setting of overflow flag is wrong.
* Bug 1783: Or1ksim definition of overflow is wrong.
* Bug 1784: Or1ksim does not trigger overflow exceptions.
 
The following bugs are either cannot be reproduced or will not be fixed.
 
/or1ksim/ChangeLog
1,8 → 1,13
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* configure: Regenerated.
* configure.ac: Version changed to current date.
* configure.ac: Version changed to current date. enable-arith-flag
and enable-ov-flag config options removed.
* cpu/or32/insnset.c <l_mfspr, l_mtspr>: Use bitwise OR, not
addition to calculate SPR address.
<l_and, l_or, l_sll, l_sra, l_srl, l_xor>: Do not now affect CY and OV
flags.
<l_sub>: Sets OV and CY flags correctly, and triggers Range
Exception if required.
* NEWS: Updated with new bugs fixed.
 
2010-06-14 Jeremy Bennett <jeremy.bennett@embecosm.com>
/or1ksim/testsuite/test-code-or1k/inst-set-test/is-sub-test.S
0,0 → 1,241
/* is-sub-test.S. l.sub instruction test of Or1ksim
*
* Copyright (C) 1999-2006 OpenCores
* Copyright (C) 2010 Embecosm Limited
*
* Contributors various OpenCores participants
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of OpenRISC 1000 Architectural Simulator.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http: www.gnu.org/licenses/>.
*/
 
/* ----------------------------------------------------------------------------
* Coding conventions are described in inst-set-test.S
* ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
* Test coverage
*
* The l.sub instruction should set the carry and overflow flags.
*
* Problems in this area were reported in Bugs 1782, 1783 and 1784. Having
* fixed the problem, this is (in good software engineering style), a
* regression test to go with the fix.
*
* This is not a comprehensive test of any instruction (yet).
*
* Of course what is really needed is a comprehensive instruction test...
* ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of subtraction in registers
*
*
* Arguments
* set_flags: Flags to set in the SR
* clr_flags: Flags to clear in the SR
* op1: First operand value
* op2: Second operand value
* res: Expected result
* cy: Expected carry flag
* ov: Expected overflow flag
* ------------------------------------------------------------------------- */
#define TEST_SUB(set_flags, clr_flags, op1, op2, res, cy, ov) \
l.mfspr r3,r0,SPR_SR ;\
LOAD_CONST (r2, set_flags) /* Set flags */ ;\
l.or r3,r3,r2 ;\
LOAD_CONST (r2, ~clr_flags) /* Clear flags */ ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load numbers to subtract */ ;\
LOAD_CONST (r6,op2) ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
50: l.sub r4,r5,r6 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" - 0x") ;\
PUTH (op2) ;\
PUTS (" = 0x") ;\
PUTH (res) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, res) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", cy) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", ov) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 53f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 54f ;\
l.nop ;\
;\
53: PUTS (" - exception triggered: FALSE\n") ;\
54:
 
 
/* ----------------------------------------------------------------------------
* Start of code
* ------------------------------------------------------------------------- */
.section .text
.global _start
_start:
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* Test of subtract signed, l.sub
* ------------------------------------------------------------------------- */
_sub:
LOAD_STR (r3, "l.sub\n")
l.jal _puts
l.nop
 
/* Subtract two small positive numbers. Sets the carry, but never the
overflow if the result is negative. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x00000003, 0x00000002, 0x00000001,
FALSE, FALSE)
 
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x00000001, 0x00000002, 0xffffffff,
TRUE, FALSE)
 
/* Check carry in is ignored. */
TEST_SUB (SPR_SR_CY, SPR_SR_OV,
0x00000003, 0x00000002, 0x00000001,
FALSE, FALSE)
 
/* Subtract two small negative numbers. Sets the carry flag if the
result is negative, but never the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0xfffffffd, 0xfffffffe, 0xffffffff,
TRUE, FALSE)
 
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0xffffffff, 0xfffffffe, 0x00000001,
FALSE, FALSE)
 
/* Subtract two quite large positive numbers. Should set neither the
overflow nor the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x3fffffff, 0x40000000,
FALSE, FALSE)
 
/* Subtract two quite large negative numbers. Should set neither the
overflow nor the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x40000000, 0x40000000, 0x00000000,
FALSE, FALSE)
 
/* Subtract two large positive numbers with a negative result. Should
set the carry, but not the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x3fffffff, 0x40000000, 0xffffffff,
TRUE, FALSE)
 
/* Subtract two large negative numbers with a positive result. Should
set niether the carry nor the overflow flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x40000000, 0x3fffffff, 0x00000001,
FALSE, FALSE)
 
/* Subtract a large positive from a large negative number. Should set
overflow but not the carry flag. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x80000000, 0x7fffffff, 0x00000001,
FALSE, TRUE)
 
/* Subtract a large negative from a large positive number. Should set
both the overflow and carry flags. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x80000000, 0xffffffff,
TRUE, TRUE)
 
/* Check that range exceptions are triggered */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
/* Check that an overflow alone causes a RANGE Exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x80000000, 0x7fffffff, 0x00000001,
FALSE, TRUE)
 
/* Check that a carry alone does not cause a RANGE Exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x3fffffff, 0x40000000, 0xffffffff,
TRUE, FALSE)
 
/* Check that carry and overflow together cause an exception. */
TEST_SUB (0, SPR_SR_CY | SPR_SR_OV,
0x7fffffff, 0x80000000, 0xffffffff,
TRUE, TRUE)
 
/* Finished checking range exceptions */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, ~SPR_SR_OVE) /* Clear OVE */
l.and r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag cleared **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* All done
* ------------------------------------------------------------------------- */
_exit:
LOAD_STR (r3, "Test completed\n")
l.jal _puts
l.nop
 
TEST_EXIT
or1ksim/testsuite/test-code-or1k/inst-set-test/is-sub-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in =================================================================== --- or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in (revision 123) +++ or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.in (revision 124) @@ -58,10 +58,13 @@ POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ -check_PROGRAMS = is-add-test$(EXEEXT) is-div-test$(EXEEXT) \ - is-find-test$(EXEEXT) is-jump-test$(EXEEXT) \ - is-lws-test$(EXEEXT) is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) \ - is-ror-test$(EXEEXT) is-spr-test$(EXEEXT) $(am__EXEEXT_1) +check_PROGRAMS = is-add-test$(EXEEXT) is-and-test$(EXEEXT) \ + is-div-test$(EXEEXT) is-find-test$(EXEEXT) \ + is-jump-test$(EXEEXT) is-lws-test$(EXEEXT) \ + is-mac-test$(EXEEXT) is-mul-test$(EXEEXT) is-or-test$(EXEEXT) \ + is-ror-test$(EXEEXT) is-shift-test$(EXEEXT) \ + is-spr-test$(EXEEXT) is-sub-test$(EXEEXT) is-xor-test$(EXEEXT) \ + $(am__EXEEXT_1) subdir = inst-set-test DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 @@ -92,6 +95,12 @@ is_add_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_add_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_and_test_OBJECTS = is-and-test.$(OBJEXT) +is_and_test_OBJECTS = $(am_is_and_test_OBJECTS) +is_and_test_DEPENDENCIES = inst-set-test.lo +is_and_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_and_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_div_test_OBJECTS = is-div-test.$(OBJEXT) is_div_test_OBJECTS = $(am_is_div_test_OBJECTS) is_div_test_DEPENDENCIES = inst-set-test.lo @@ -128,6 +137,12 @@ is_mul_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_mul_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_or_test_OBJECTS = is-or-test.$(OBJEXT) +is_or_test_OBJECTS = $(am_is_or_test_OBJECTS) +is_or_test_DEPENDENCIES = inst-set-test.lo +is_or_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_or_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_ror_test_OBJECTS = is-ror-test.$(OBJEXT) is_ror_test_OBJECTS = $(am_is_ror_test_OBJECTS) is_ror_test_DEPENDENCIES = inst-set-test.lo @@ -134,6 +149,12 @@ is_ror_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_ror_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_shift_test_OBJECTS = is-shift-test.$(OBJEXT) +is_shift_test_OBJECTS = $(am_is_shift_test_OBJECTS) +is_shift_test_DEPENDENCIES = inst-set-test.lo +is_shift_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_shift_test_LDFLAGS) $(LDFLAGS) -o $@ am_is_spr_test_OBJECTS = is-spr-test.$(OBJEXT) is_spr_test_OBJECTS = $(am_is_spr_test_OBJECTS) is_spr_test_DEPENDENCIES = inst-set-test.lo @@ -140,6 +161,18 @@ is_spr_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ $(is_spr_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_sub_test_OBJECTS = is-sub-test.$(OBJEXT) +is_sub_test_OBJECTS = $(am_is_sub_test_OBJECTS) +is_sub_test_DEPENDENCIES = inst-set-test.lo +is_sub_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_sub_test_LDFLAGS) $(LDFLAGS) -o $@ +am_is_xor_test_OBJECTS = is-xor-test.$(OBJEXT) +is_xor_test_OBJECTS = $(am_is_xor_test_OBJECTS) +is_xor_test_DEPENDENCIES = inst-set-test.lo +is_xor_test_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ + $(LIBTOOLFLAGS) --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) \ + $(is_xor_test_LDFLAGS) $(LDFLAGS) -o $@ DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) depcomp = $(SHELL) $(top_srcdir)/../../depcomp am__depfiles_maybe = depfiles @@ -159,17 +192,22 @@ --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ $(LDFLAGS) -o $@ SOURCES = $(libinst_set_test_la_SOURCES) $(inst_set_test_old_SOURCES) \ - $(is_add_test_SOURCES) $(is_div_test_SOURCES) \ - $(is_find_test_SOURCES) $(is_jump_test_SOURCES) \ - $(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \ - $(is_mul_test_SOURCES) $(is_ror_test_SOURCES) \ - $(is_spr_test_SOURCES) -DIST_SOURCES = $(libinst_set_test_la_SOURCES) \ - $(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \ + $(is_add_test_SOURCES) $(is_and_test_SOURCES) \ $(is_div_test_SOURCES) $(is_find_test_SOURCES) \ $(is_jump_test_SOURCES) $(is_lws_test_SOURCES) \ $(is_mac_test_SOURCES) $(is_mul_test_SOURCES) \ - $(is_ror_test_SOURCES) $(is_spr_test_SOURCES) + $(is_or_test_SOURCES) $(is_ror_test_SOURCES) \ + $(is_shift_test_SOURCES) $(is_spr_test_SOURCES) \ + $(is_sub_test_SOURCES) $(is_xor_test_SOURCES) +DIST_SOURCES = $(libinst_set_test_la_SOURCES) \ + $(inst_set_test_old_SOURCES) $(is_add_test_SOURCES) \ + $(is_and_test_SOURCES) $(is_div_test_SOURCES) \ + $(is_find_test_SOURCES) $(is_jump_test_SOURCES) \ + $(is_lws_test_SOURCES) $(is_mac_test_SOURCES) \ + $(is_mul_test_SOURCES) $(is_or_test_SOURCES) \ + $(is_ror_test_SOURCES) $(is_shift_test_SOURCES) \ + $(is_spr_test_SOURCES) $(is_sub_test_SOURCES) \ + $(is_xor_test_SOURCES) ETAGS = etags CTAGS = ctags DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) @@ -301,51 +339,76 @@ # The new instruction set tests. is_add_test_SOURCES = inst-set-test.h \ - is-add-test.S + is-add-test.S is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_add_test_LDADD = inst-set-test.lo +is_and_test_SOURCES = inst-set-test.h \ + is-and-test.S + +is_and_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_and_test_LDADD = inst-set-test.lo is_div_test_SOURCES = inst-set-test.h \ - is-div-test.S + is-div-test.S is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_div_test_LDADD = inst-set-test.lo is_find_test_SOURCES = inst-set-test.h \ - is-find-test.S + is-find-test.S is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_find_test_LDADD = inst-set-test.lo is_jump_test_SOURCES = inst-set-test.h \ - is-jump-test.S + is-jump-test.S is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_jump_test_LDADD = inst-set-test.lo is_lws_test_SOURCES = inst-set-test.h \ - is-lws-test.S + is-lws-test.S is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_lws_test_LDADD = inst-set-test.lo is_mac_test_SOURCES = inst-set-test.h \ - is-mac-test.S + is-mac-test.S is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_mac_test_LDADD = inst-set-test.lo is_mul_test_SOURCES = inst-set-test.h \ - is-mul-test.S + is-mul-test.S is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_mul_test_LDADD = inst-set-test.lo +is_or_test_SOURCES = inst-set-test.h \ + is-or-test.S + +is_or_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_or_test_LDADD = inst-set-test.lo is_ror_test_SOURCES = inst-set-test.h \ - is-ror-test.S + is-ror-test.S is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_ror_test_LDADD = inst-set-test.lo +is_shift_test_SOURCES = inst-set-test.h \ + is-shift-test.S + +is_shift_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_shift_test_LDADD = inst-set-test.lo is_spr_test_SOURCES = inst-set-test.h \ - is-spr-test.S + is-spr-test.S is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld is_spr_test_LDADD = inst-set-test.lo +is_sub_test_SOURCES = inst-set-test.h \ + is-sub-test.S +is_sub_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_sub_test_LDADD = inst-set-test.lo +is_xor_test_SOURCES = inst-set-test.h \ + is-xor-test.S + +is_xor_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_xor_test_LDADD = inst-set-test.lo + # The old test which builds with warnings and runs with errors inst_set_test_old_SOURCES = inst-set-test-old.c inst_set_test_old_LDFLAGS = -T$(srcdir)/../default.ld @@ -412,6 +475,9 @@ is-add-test$(EXEEXT): $(is_add_test_OBJECTS) $(is_add_test_DEPENDENCIES) @rm -f is-add-test$(EXEEXT) $(is_add_test_LINK) $(is_add_test_OBJECTS) $(is_add_test_LDADD) $(LIBS) +is-and-test$(EXEEXT): $(is_and_test_OBJECTS) $(is_and_test_DEPENDENCIES) + @rm -f is-and-test$(EXEEXT) + $(is_and_test_LINK) $(is_and_test_OBJECTS) $(is_and_test_LDADD) $(LIBS) is-div-test$(EXEEXT): $(is_div_test_OBJECTS) $(is_div_test_DEPENDENCIES) @rm -f is-div-test$(EXEEXT) $(is_div_test_LINK) $(is_div_test_OBJECTS) $(is_div_test_LDADD) $(LIBS) @@ -430,12 +496,24 @@ is-mul-test$(EXEEXT): $(is_mul_test_OBJECTS) $(is_mul_test_DEPENDENCIES) @rm -f is-mul-test$(EXEEXT) $(is_mul_test_LINK) $(is_mul_test_OBJECTS) $(is_mul_test_LDADD) $(LIBS) +is-or-test$(EXEEXT): $(is_or_test_OBJECTS) $(is_or_test_DEPENDENCIES) + @rm -f is-or-test$(EXEEXT) + $(is_or_test_LINK) $(is_or_test_OBJECTS) $(is_or_test_LDADD) $(LIBS) is-ror-test$(EXEEXT): $(is_ror_test_OBJECTS) $(is_ror_test_DEPENDENCIES) @rm -f is-ror-test$(EXEEXT) $(is_ror_test_LINK) $(is_ror_test_OBJECTS) $(is_ror_test_LDADD) $(LIBS) +is-shift-test$(EXEEXT): $(is_shift_test_OBJECTS) $(is_shift_test_DEPENDENCIES) + @rm -f is-shift-test$(EXEEXT) + $(is_shift_test_LINK) $(is_shift_test_OBJECTS) $(is_shift_test_LDADD) $(LIBS) is-spr-test$(EXEEXT): $(is_spr_test_OBJECTS) $(is_spr_test_DEPENDENCIES) @rm -f is-spr-test$(EXEEXT) $(is_spr_test_LINK) $(is_spr_test_OBJECTS) $(is_spr_test_LDADD) $(LIBS) +is-sub-test$(EXEEXT): $(is_sub_test_OBJECTS) $(is_sub_test_DEPENDENCIES) + @rm -f is-sub-test$(EXEEXT) + $(is_sub_test_LINK) $(is_sub_test_OBJECTS) $(is_sub_test_LDADD) $(LIBS) +is-xor-test$(EXEEXT): $(is_xor_test_OBJECTS) $(is_xor_test_DEPENDENCIES) + @rm -f is-xor-test$(EXEEXT) + $(is_xor_test_LINK) $(is_xor_test_OBJECTS) $(is_xor_test_LDADD) $(LIBS) mostlyclean-compile: -rm -f *.$(OBJEXT) @@ -446,6 +524,7 @@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inst-set-test-old.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/inst-set-test.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-add-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-and-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-div-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-find-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-jump-test.Po@am__quote@ @@ -452,8 +531,12 @@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-lws-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mac-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-mul-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-or-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-ror-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-shift-test.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-spr-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-sub-test.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/is-xor-test.Po@am__quote@ .S.o: @am__fastdepCCAS_TRUE@ $(CPPASCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $<
/or1ksim/testsuite/test-code-or1k/inst-set-test/is-and-test.S
0,0 → 1,237
/* is-and-test.S. l.and and l.andi instruction test of Or1ksim
*
* Copyright (C) 1999-2006 OpenCores
* Copyright (C) 2010 Embecosm Limited
*
* Contributors various OpenCores participants
* Contributor Jeremy Bennett <jeremy.bennett@embecosm.com>
*
* This file is part of OpenRISC 1000 Architectural Simulator.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 3 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http: www.gnu.org/licenses/>.
*/
 
/* ----------------------------------------------------------------------------
* Coding conventions are described in inst-set-test.S
* ------------------------------------------------------------------------- */
 
/* ----------------------------------------------------------------------------
* Test coverage
*
* The l.and and l.andi instructions should never set the carry and overflow
* flags.
*
* Problems in this area were reported in Bugs 1782, 1783 and 1784. Having
* fixed the problem, this is (in good software engineering style), a
* regression test to go with the fix.
*
* This is not a comprehensive test of any instruction (yet).
*
* Of course what is really needed is a comprehensive instruction test...
* ------------------------------------------------------------------------- */
 
 
#include "inst-set-test.h"
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of bitwise AND in registers
*
* This opcode should never set the flags. Result is compared with the native
* computed value.
*
* Arguments
* op1: First operand value
* op2: Second operand value
* ------------------------------------------------------------------------- */
#define TEST_AND(op1, op2) \
l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load operands */ ;\
LOAD_CONST (r6,op2) ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
50: l.and r4,r5,r6 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) /* Save SR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" & 0x") ;\
PUTH (op2) ;\
PUTS (" = 0x") ;\
PUTH (op1 & op2) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, op1 & op2) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", FALSE) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", FALSE) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 51f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 52f ;\
l.nop ;\
;\
51: PUTS (" - exception triggered: FALSE\n") ;\
52:
 
 
/* ----------------------------------------------------------------------------
* A macro to carry out a test of bitwise AND with an immediate operand
*
* This opcode should never set the flags. Result is compared with the native
* computed value.
*
* Arguments
* op1: First operand value
* op2: Second operand value
* ------------------------------------------------------------------------- */
#define TEST_ANDI(op1, op2) \
l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\
LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\
l.and r3,r3,r2 ;\
l.mtspr r0,r3,SPR_SR ;\
;\
LOAD_CONST (r5,op1) /* Load operands */ ;\
l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\
53: l.andi r4,r5,op2 ;\
l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\
l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\
PUSH (r5) /* Save EPCR for later */ ;\
PUSH (r2) /* Save SR for later */ ;\
PUSH (r4) /* Save result for later */ ;\
;\
PUTS (" 0x") ;\
PUTH (op1) ;\
PUTS (" & 0x") ;\
PUTHH (op2) ;\
PUTS (" = 0x") ;\
PUTH (op1 & op2) ;\
PUTS (": ") ;\
POP (r4) ;\
CHECK_RES1 (r4, op1 & op2) ;\
;\
POP(r2) /* Retrieve SR */ ;\
PUSH(r2) ;\
LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- carry flag set: ", FALSE) ;\
;\
POP(r2) /* Retrieve SR */ ;\
LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
CHECK_FLAG ("- overflow flag set: ", FALSE) ;\
;\
POP (r2) /* Retrieve EPCR */ ;\
LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\
l.and r2,r2,r4 ;\
l.sfeq r2,r4 ;\
l.bnf 54f ;\
;\
PUTS (" - exception triggered: TRUE\n") ;\
l.j 55f ;\
l.nop ;\
;\
54: PUTS (" - exception triggered: FALSE\n") ;\
55:
 
 
/* ----------------------------------------------------------------------------
* Start of code
* ------------------------------------------------------------------------- */
.section .text
.global _start
_start:
/* Always set OVE. We should never trigger an exception, even if this
bit is set. */
l.mfspr r3,r0,SPR_SR
LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */
l.or r3,r3,r2
l.mtspr r0,r3,SPR_SR
LOAD_STR (r3, " ** OVE flag set **\n")
l.jal _puts
l.nop
 
/* ----------------------------------------------------------------------------
* Test of and, l.and
* ------------------------------------------------------------------------- */
_and:
LOAD_STR (r3, "l.and\n")
l.jal _puts
l.nop
 
/* Test a range of operands */
TEST_AND (0x00000000, 0x00000000)
TEST_AND (0xffffffff, 0xffffffff)
TEST_AND (0xaaaaaaaa, 0x00000000)
TEST_AND (0xaaaaaaaa, 0xaaaaaaaa)
TEST_AND (0x55555555, 0x00000000)
TEST_AND (0x55555555, 0x55555555)
TEST_AND (0xaaaaaaaa, 0x55555555)
TEST_AND (0x4c70f07c, 0xb38f0f83)
TEST_AND (0x4c70f07c, 0xc4c70f07)
TEST_AND (0xb38f0f83, 0x38f0f83b)
 
/* ----------------------------------------------------------------------------
* Test of and with immediate half word, l.andi
* ------------------------------------------------------------------------- */
_andi:
LOAD_STR (r3, "l.andi\n")
l.jal _puts
l.nop
 
/* Test a range of operands */
TEST_ANDI (0x00000000, 0x0000)
TEST_ANDI (0xffffffff, 0xffff)
TEST_ANDI (0xaaaaaaaa, 0x0000)
TEST_ANDI (0xaaaaaaaa, 0xaaaa)
TEST_ANDI (0x55555555, 0x0000)
TEST_ANDI (0x55555555, 0x5555)
TEST_ANDI (0xaaaaaaaa, 0x5555)
TEST_ANDI (0x4c70f07c, 0x0f83)
TEST_ANDI (0x4c70f07c, 0x0f07)
TEST_ANDI (0xb38f0f83, 0xf83b)
 
/* ----------------------------------------------------------------------------
* All done
* ------------------------------------------------------------------------- */
_exit:
LOAD_STR (r3, "Test completed\n")
l.jal _puts
l.nop
 
TEST_EXIT
or1ksim/testsuite/test-code-or1k/inst-set-test/is-and-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: or1ksim/testsuite/test-code-or1k/inst-set-test/is-xor-test.S =================================================================== --- or1ksim/testsuite/test-code-or1k/inst-set-test/is-xor-test.S (nonexistent) +++ or1ksim/testsuite/test-code-or1k/inst-set-test/is-xor-test.S (revision 124) @@ -0,0 +1,256 @@ +/* is-xor-test.S. l.xor and l.xori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.xor and l.xori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* A macro to sign extend a 16-bit value */ +#define SE(v) (v | ((v & 0x8000) << 1) | \ + ((v & 0x8000) << 2) | \ + ((v & 0x8000) << 3) | \ + ((v & 0x8000) << 4) | \ + ((v & 0x8000) << 5) | \ + ((v & 0x8000) << 6) | \ + ((v & 0x8000) << 7) | \ + ((v & 0x8000) << 8) | \ + ((v & 0x8000) << 9) | \ + ((v & 0x8000) << 10) | \ + ((v & 0x8000) << 11) | \ + ((v & 0x8000) << 12) | \ + ((v & 0x8000) << 13) | \ + ((v & 0x8000) << 14) | \ + ((v & 0x8000) << 15) | \ + ((v & 0x8000) << 16) ) + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XOR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.xor r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise XOR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. Note that the OR1K architecture specfies that the immediate + * operand is sign-extended, not zero-extended. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_XORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.xori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" ^ 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 ^ SE (op2)) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 ^ SE (op2)) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of xor, l.xor + * ------------------------------------------------------------------------- */ +_xor: + LOAD_STR (r3, "l.xor\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XOR (0x00000000, 0x00000000) + TEST_XOR (0xffffffff, 0xffffffff) + TEST_XOR (0xaaaaaaaa, 0x00000000) + TEST_XOR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_XOR (0x55555555, 0x00000000) + TEST_XOR (0x55555555, 0x55555555) + TEST_XOR (0xaaaaaaaa, 0x55555555) + TEST_XOR (0x4c70f07c, 0xb38f0f83) + TEST_XOR (0x4c70f07c, 0xc4c70f07) + TEST_XOR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of xor with immediate half word, l.xori + * ------------------------------------------------------------------------- */ +_xori: + LOAD_STR (r3, "l.xori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_XORI (0x00000000, 0x0000) + TEST_XORI (0xffffffff, 0xffff) + TEST_XORI (0xaaaaaaaa, 0x0000) + TEST_XORI (0xaaaaaaaa, 0xaaaa) + TEST_XORI (0x55555555, 0x0000) + TEST_XORI (0x55555555, 0x5555) + TEST_XORI (0xaaaaaaaa, 0x5555) + TEST_XORI (0x4c70f07c, 0x0f83) + TEST_XORI (0x4c70f07c, 0x0f07) + TEST_XORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
or1ksim/testsuite/test-code-or1k/inst-set-test/is-xor-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: or1ksim/testsuite/test-code-or1k/inst-set-test/is-shift-test.S =================================================================== --- or1ksim/testsuite/test-code-or1k/inst-set-test/is-shift-test.S (nonexistent) +++ or1ksim/testsuite/test-code-or1k/inst-set-test/is-shift-test.S (revision 124) @@ -0,0 +1,378 @@ +/* is-shift-test.S. shift instructions test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The shift instructions should never set the carry and overflow flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift in registers + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFT(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: opc r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of shift with an immediate operand + * + * This opcode should never set the flags. + * + * Arguments + * opc: The operand + * op1: First operand value + * op2: Second operand value + * res: The expected result + * ------------------------------------------------------------------------- */ +#define TEST_SHIFTI(opc, op1, op2, res) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: opc r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" shifted by 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (res) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, res) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of shift left logical, l.sll + * ------------------------------------------------------------------------- */ +_sll: + LOAD_STR (r3, "l.sll\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000001, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000004, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000010, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x0000001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00000021, 0x671e1f06) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00002224, 0x38f0f830) + TEST_SHIFT (l.sll, 0xb38f0f83, 0x00f789f0, 0x0f830000) + TEST_SHIFT (l.sll, 0xb38f0f83, 0xffffffff, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift left logical with immediate, l.slli + * ------------------------------------------------------------------------- */ +_slli: + LOAD_STR (r3, "l.slli\n") + l.jal _puts + l.nop + + /* Shift left by zero. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift left by amounts in the 1-31 range */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0001, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0004, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0010, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x001f, 0x80000000) + + /* Shift left by larger amounts - should be masked. */ + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0021, 0x671e1f06) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0024, 0x38f0f830) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x0030, 0x0f830000) + TEST_SHIFTI (l.slli, 0xb38f0f83, 0x003f, 0x80000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic, l.sra + * ------------------------------------------------------------------------- */ +_sra: + LOAD_STR (r3, "l.sra\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000001, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000004, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000010, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x0000001f, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00000021, 0xd9c787c1) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00002224, 0xfb38f0f8) + TEST_SHIFT (l.sra, 0xb38f0f83, 0x00f789f0, 0xffffb38f) + TEST_SHIFT (l.sra, 0xb38f0f83, 0xffffffff, 0xffffffff) + + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.sra, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.sra, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right arithmetic with immediate, l.srai + * ------------------------------------------------------------------------- */ +_srai: + LOAD_STR (r3, "l.srai\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0001, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0004, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0010, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x001f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0021, 0xd9c787c1) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0024, 0xfb38f0f8) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x0030, 0xffffb38f) + TEST_SHIFTI (l.srai, 0xb38f0f83, 0x003f, 0xffffffff) + + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srai, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * Test of shift right logical, l.srl + * ------------------------------------------------------------------------- */ +_srl: + LOAD_STR (r3, "l.srl\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000001, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000004, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000010, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x0000001f, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000001, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000004, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000010, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x0000001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00000021, 0x59c787c1) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00002224, 0x0b38f0f8) + TEST_SHIFT (l.srl, 0xb38f0f83, 0x00f789f0, 0x0000b38f) + TEST_SHIFT (l.srl, 0xb38f0f83, 0xffffffff, 0x00000001) + + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00000021, 0x2638783e) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00002224, 0x04c70f07) + TEST_SHIFT (l.srl, 0x4c70f07c, 0x00f789f0, 0x00004c70) + TEST_SHIFT (l.srl, 0x4c70f07c, 0xffffffff, 0x00000000) + + +/* ---------------------------------------------------------------------------- + * Test of shift right logical with immediate, l.srli + * ------------------------------------------------------------------------- */ +_srli: + LOAD_STR (r3, "l.srli\n") + l.jal _puts + l.nop + + /* Shift right by zero. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0000, 0xb38f0f83) + + /* Shift right by amounts in the 1-31 range */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0001, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0004, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0010, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x001f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0001, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0004, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0010, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x001f, 0x00000000) + + /* Shift right by larger amounts - should be masked. */ + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0021, 0x59c787c1) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0024, 0x0b38f0f8) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x0030, 0x0000b38f) + TEST_SHIFTI (l.srli, 0xb38f0f83, 0x003f, 0x00000001) + + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0021, 0x2638783e) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0024, 0x04c70f07) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x0030, 0x00004c70) + TEST_SHIFTI (l.srli, 0x4c70f07c, 0x003f, 0x00000000) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
or1ksim/testsuite/test-code-or1k/inst-set-test/is-shift-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: or1ksim/testsuite/test-code-or1k/inst-set-test/is-or-test.S =================================================================== --- or1ksim/testsuite/test-code-or1k/inst-set-test/is-or-test.S (nonexistent) +++ or1ksim/testsuite/test-code-or1k/inst-set-test/is-or-test.S (revision 124) @@ -0,0 +1,237 @@ +/* is-or-test.S. l.or and l.ori instruction test of Or1ksim + * + * Copyright (C) 1999-2006 OpenCores + * Copyright (C) 2010 Embecosm Limited + * + * Contributors various OpenCores participants + * Contributor Jeremy Bennett + * + * This file is part of OpenRISC 1000 Architectural Simulator. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 3 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program. If not, see . + */ + +/* ---------------------------------------------------------------------------- + * Coding conventions are described in inst-set-test.S + * ------------------------------------------------------------------------- */ + +/* ---------------------------------------------------------------------------- + * Test coverage + * + * The l.or and l.ori instructions should never set the carry and overflow + * flags. + * + * Problems in this area were reported in Bugs 1782, 1783 and 1784. Having + * fixed the problem, this is (in good software engineering style), a + * regression test to go with the fix. + * + * This is not a comprehensive test of any instruction (yet). + * + * Of course what is really needed is a comprehensive instruction test... + * ------------------------------------------------------------------------- */ + + +#include "inst-set-test.h" + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR in registers + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_OR(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + LOAD_CONST (r6,op2) ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +50: l.or r4,r5,r6 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 50b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 51f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 52f ;\ + l.nop ;\ + ;\ +51: PUTS (" - exception triggered: FALSE\n") ;\ +52: + + +/* ---------------------------------------------------------------------------- + * A macro to carry out a test of bitwise OR with an immediate operand + * + * This opcode should never set the flags. Result is compared with the native + * computed value. + * + * Arguments + * op1: First operand value + * op2: Second operand value + * ------------------------------------------------------------------------- */ +#define TEST_ORI(op1, op2) \ + l.mfspr r3,r0,SPR_SR /* Clear flags */ ;\ + LOAD_CONST (r2, ~(SPR_SR_CY | SPR_SR_OV)) ;\ + l.and r3,r3,r2 ;\ + l.mtspr r0,r3,SPR_SR ;\ + ;\ + LOAD_CONST (r5,op1) /* Load operands */ ;\ + l.mtspr r0,r0,SPR_EPCR_BASE /* Clear record */ ;\ +53: l.ori r4,r5,op2 ;\ + l.mfspr r2,r0,SPR_SR /* So we can examine flags */ ;\ + l.mfspr r5,r0,SPR_EPCR_BASE /* What triggered exception */ ;\ + PUSH (r5) /* Save EPCR for later */ ;\ + PUSH (r2) /* Save SR for later */ ;\ + PUSH (r4) /* Save result for later */ ;\ + ;\ + PUTS (" 0x") ;\ + PUTH (op1) ;\ + PUTS (" | 0x") ;\ + PUTHH (op2) ;\ + PUTS (" = 0x") ;\ + PUTH (op1 | op2) ;\ + PUTS (": ") ;\ + POP (r4) ;\ + CHECK_RES1 (r4, op1 | op2) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + PUSH(r2) ;\ + LOAD_CONST (r4, SPR_SR_CY) /* The carry bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- carry flag set: ", FALSE) ;\ + ;\ + POP(r2) /* Retrieve SR */ ;\ + LOAD_CONST (r4, SPR_SR_OV) /* The overflow bit */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + CHECK_FLAG ("- overflow flag set: ", FALSE) ;\ + ;\ + POP (r2) /* Retrieve EPCR */ ;\ + LOAD_CONST (r4, 53b) /* The opcode of interest */ ;\ + l.and r2,r2,r4 ;\ + l.sfeq r2,r4 ;\ + l.bnf 54f ;\ + ;\ + PUTS (" - exception triggered: TRUE\n") ;\ + l.j 55f ;\ + l.nop ;\ + ;\ +54: PUTS (" - exception triggered: FALSE\n") ;\ +55: + + +/* ---------------------------------------------------------------------------- + * Start of code + * ------------------------------------------------------------------------- */ + .section .text + .global _start +_start: + /* Always set OVE. We should never trigger an exception, even if this + bit is set. */ + l.mfspr r3,r0,SPR_SR + LOAD_CONST (r2, SPR_SR_OVE) /* Set OVE */ + l.or r3,r3,r2 + l.mtspr r0,r3,SPR_SR + + LOAD_STR (r3, " ** OVE flag set **\n") + l.jal _puts + l.nop + +/* ---------------------------------------------------------------------------- + * Test of or, l.or + * ------------------------------------------------------------------------- */ +_or: + LOAD_STR (r3, "l.or\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_OR (0x00000000, 0x00000000) + TEST_OR (0xffffffff, 0xffffffff) + TEST_OR (0xaaaaaaaa, 0x00000000) + TEST_OR (0xaaaaaaaa, 0xaaaaaaaa) + TEST_OR (0x55555555, 0x00000000) + TEST_OR (0x55555555, 0x55555555) + TEST_OR (0xaaaaaaaa, 0x55555555) + TEST_OR (0x4c70f07c, 0xb38f0f83) + TEST_OR (0x4c70f07c, 0xc4c70f07) + TEST_OR (0xb38f0f83, 0x38f0f83b) + +/* ---------------------------------------------------------------------------- + * Test of or with immediate half word, l.ori + * ------------------------------------------------------------------------- */ +_ori: + LOAD_STR (r3, "l.ori\n") + l.jal _puts + l.nop + + /* Test a range of operands */ + TEST_ORI (0x00000000, 0x0000) + TEST_ORI (0xffffffff, 0xffff) + TEST_ORI (0xaaaaaaaa, 0x0000) + TEST_ORI (0xaaaaaaaa, 0xaaaa) + TEST_ORI (0x55555555, 0x0000) + TEST_ORI (0x55555555, 0x5555) + TEST_ORI (0xaaaaaaaa, 0x5555) + TEST_ORI (0x4c70f07c, 0x0f83) + TEST_ORI (0x4c70f07c, 0x0f07) + TEST_ORI (0xb38f0f83, 0xf83b) + +/* ---------------------------------------------------------------------------- + * All done + * ------------------------------------------------------------------------- */ +_exit: + LOAD_STR (r3, "Test completed\n") + l.jal _puts + l.nop + + TEST_EXIT
or1ksim/testsuite/test-code-or1k/inst-set-test/is-or-test.S Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am =================================================================== --- or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am (revision 123) +++ or1ksim/testsuite/test-code-or1k/inst-set-test/Makefile.am (revision 124) @@ -42,6 +42,7 @@ # The test programs check_PROGRAMS = is-add-test \ + is-and-test \ is-div-test \ is-find-test \ is-jump-test \ @@ -48,56 +49,85 @@ is-lws-test \ is-mac-test \ is-mul-test \ + is-or-test \ is-ror-test \ + is-shift-test \ is-spr-test \ + is-sub-test \ + is-xor-test \ $(INST_SET_TEST_OLD) # The new instruction set tests. -is_add_test_SOURCES = inst-set-test.h \ - is-add-test.S -is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_add_test_LDADD = inst-set-test.lo +is_add_test_SOURCES = inst-set-test.h \ + is-add-test.S +is_add_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_add_test_LDADD = inst-set-test.lo -is_div_test_SOURCES = inst-set-test.h \ - is-div-test.S -is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_div_test_LDADD = inst-set-test.lo +is_and_test_SOURCES = inst-set-test.h \ + is-and-test.S +is_and_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_and_test_LDADD = inst-set-test.lo -is_find_test_SOURCES = inst-set-test.h \ - is-find-test.S -is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_find_test_LDADD = inst-set-test.lo +is_div_test_SOURCES = inst-set-test.h \ + is-div-test.S +is_div_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_div_test_LDADD = inst-set-test.lo -is_jump_test_SOURCES = inst-set-test.h \ - is-jump-test.S -is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_jump_test_LDADD = inst-set-test.lo +is_find_test_SOURCES = inst-set-test.h \ + is-find-test.S +is_find_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_find_test_LDADD = inst-set-test.lo -is_lws_test_SOURCES = inst-set-test.h \ - is-lws-test.S -is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_lws_test_LDADD = inst-set-test.lo +is_jump_test_SOURCES = inst-set-test.h \ + is-jump-test.S +is_jump_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_jump_test_LDADD = inst-set-test.lo -is_mac_test_SOURCES = inst-set-test.h \ - is-mac-test.S -is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_mac_test_LDADD = inst-set-test.lo +is_lws_test_SOURCES = inst-set-test.h \ + is-lws-test.S +is_lws_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_lws_test_LDADD = inst-set-test.lo -is_mul_test_SOURCES = inst-set-test.h \ - is-mul-test.S -is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_mul_test_LDADD = inst-set-test.lo +is_mac_test_SOURCES = inst-set-test.h \ + is-mac-test.S +is_mac_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mac_test_LDADD = inst-set-test.lo -is_ror_test_SOURCES = inst-set-test.h \ - is-ror-test.S -is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_ror_test_LDADD = inst-set-test.lo +is_mul_test_SOURCES = inst-set-test.h \ + is-mul-test.S +is_mul_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_mul_test_LDADD = inst-set-test.lo -is_spr_test_SOURCES = inst-set-test.h \ - is-spr-test.S -is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld -is_spr_test_LDADD = inst-set-test.lo +is_or_test_SOURCES = inst-set-test.h \ + is-or-test.S +is_or_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_or_test_LDADD = inst-set-test.lo +is_ror_test_SOURCES = inst-set-test.h \ + is-ror-test.S +is_ror_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_ror_test_LDADD = inst-set-test.lo + +is_shift_test_SOURCES = inst-set-test.h \ + is-shift-test.S +is_shift_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_shift_test_LDADD = inst-set-test.lo + +is_spr_test_SOURCES = inst-set-test.h \ + is-spr-test.S +is_spr_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_spr_test_LDADD = inst-set-test.lo + +is_sub_test_SOURCES = inst-set-test.h \ + is-sub-test.S +is_sub_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_sub_test_LDADD = inst-set-test.lo + +is_xor_test_SOURCES = inst-set-test.h \ + is-xor-test.S +is_xor_test_LDFLAGS = -T$(srcdir)/inst-set-test.ld +is_xor_test_LDADD = inst-set-test.lo + # The old test which builds with warnings and runs with errors inst_set_test_old_SOURCES = inst-set-test-old.c
/or1ksim/testsuite/test-code-or1k/ChangeLog
1,5 → 1,10
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* inst-set-test/is-and-test.S: Created.
* inst-set-test/is-or-test.S: Created.
* inst-set-test/is-shift-test.S: Created.
* inst-set-test/is-spr-test.S: Created.
* inst-set-test/is-sub-test.S: Created.
* inst-set-test/is-xor-test.S: Created.
* inst-set-test/Makefile.am: Updated for new tests
* inst-set-test/Makefile.in: Regenerated.
 
/or1ksim/testsuite/or1ksim.tests/inst-set-test.exp
254,6 → 254,96
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-add-test"
 
# Run the l.and, and l.andi tests
run_or1ksim "and-test" \
[list "! ** OVE flag set **" \
"!l.and" \
" 0x00000000 & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff & 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0xaaaaaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x55555555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x55555555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0xb38f0f83 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0xc4c70f07 = 0x44400004: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 & 0x38f0f83b = 0x30800803: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.andi" \
" 0x00000000 & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff & 0xffff = 0x0000ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0xaaaa = 0x0000aaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 & 0x5555 = 0x00005555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa & 0x5555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0x0f83 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c & 0x0f07 = 0x00000004: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 & 0xf83b = 0x00000803: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-and-test"
 
# Run the l.div and l.divu test
run_or1ksim "div-test" \
[list "!l.div" \
865,6 → 955,96
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-mul-test"
 
# Run the l.or, and l.ori tests
run_or1ksim "or-test" \
[list "! ** OVE flag set **" \
"!l.or" \
" 0x00000000 | 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff | 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x00000000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0xaaaaaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x00000000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x55555555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x55555555 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0xb38f0f83 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0xc4c70f07 = 0xccf7ff7f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 | 0x38f0f83b = 0xbbffffbb: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.ori" \
" 0x00000000 | 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff | 0xffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x0000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0xaaaa = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x0000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 | 0x5555 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa | 0x5555 = 0xaaaaffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0x0f83 = 0x4c70ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c | 0x0f07 = 0x4c70ff7f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 | 0xf83b = 0xb38fffbb: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-or-test"
 
# Run the l.ror test
run_or1ksim "ror-test" \
[list "!l.ror" \
946,3 → 1126,520
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-spr-test"
 
# Run the shift tests
run_or1ksim "shift-test" \
[list "! ** OVE flag set **" \
"!l.sll" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.slli" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0x671e1f06: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0x38f0f830: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0x0f830000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0x80000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.sra" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0000001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00002224 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00f789f0 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srai" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0xd9c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0xfb38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0xffffb38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0024 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0030 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x003f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srl" \
" 0xb38f0f83 shifted by 0x00000000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000001 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000004 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000010 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0000001f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0000001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00000021 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00002224 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x00f789f0 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0xffffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00000021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00002224 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x00f789f0 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.srli" \
" 0xb38f0f83 shifted by 0x0000 = 0xb38f0f83: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0001 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0004 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0010 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x001f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0001 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0004 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0010 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x001f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0021 = 0x59c787c1: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0024 = 0x0b38f0f8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x0030 = 0x0000b38f: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 shifted by 0x003f = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0021 = 0x2638783e: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0024 = 0x04c70f07: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x0030 = 0x00004c70: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c shifted by 0x003f = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-shift-test"
 
# Run the l.sub test
run_or1ksim "sub-test" \
[list "! ** OVE flag cleared **" \
"!l.sub" \
" 0x00000003 - 0x00000002 = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x00000001 - 0x00000002 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x00000003 - 0x00000002 = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xfffffffd - 0xfffffffe = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff - 0xfffffffe = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x7fffffff - 0x3fffffff = 0x40000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x40000000 - 0x40000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x3fffffff - 0x40000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x40000000 - 0x3fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x80000000 - 0x7fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" - exception triggered: FALSE" \
" 0x7fffffff - 0x80000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
" - exception triggered: FALSE" \
"! ** OVE flag set **" \
" RANGE exception" \
" 0x80000000 - 0x7fffffff = 0x00000001: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: TRUE" \
" - exception triggered: TRUE" \
" 0x3fffffff - 0x40000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" RANGE exception" \
" 0x7fffffff - 0x80000000 = 0xffffffff: OK" \
" - carry flag set: TRUE" \
" - overflow flag set: TRUE" \
" - exception triggered: TRUE" \
"! ** OVE flag cleared **" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-sub-test"
 
# Run the l.xor test
run_or1ksim "xor-test" \
[list "! ** OVE flag set **" \
"!l.xor" \
" 0x00000000 ^ 0x00000000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff ^ 0xffffffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x00000000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0xaaaaaaaa = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x00000000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x55555555 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x55555555 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0xb38f0f83 = 0xffffffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0xc4c70f07 = 0x88b7ff7b: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ^ 0x38f0f83b = 0x8b7ff7b8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!l.xori" \
" 0x00000000 ^ 0x0000 = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xffffffff ^ 0xffff = 0x00000000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x0000 = 0xaaaaaaaa: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0xaaaa = 0x55550000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x0000 = 0x55555555: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x55555555 ^ 0x5555 = 0x55550000: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xaaaaaaaa ^ 0x5555 = 0xaaaaffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0x0f83 = 0x4c70ffff: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0x4c70f07c ^ 0x0f07 = 0x4c70ff7b: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
" 0xb38f0f83 ^ 0xf83b = 0x4c70f7b8: OK" \
" - carry flag set: FALSE" \
" - overflow flag set: FALSE" \
" - exception triggered: FALSE" \
"!Test completed" \
"!report(0xdeaddead);" \
"!exit(0)"] \
"inst-set-test.cfg" "inst-set-test/is-xor-test"
/or1ksim/testsuite/ChangeLog
1,6 → 1,6
2010-06-15 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Added tests for l.mfspr and
l.mtspr instructions.
l.mtspr, l.sub, logical and shift instructions.
 
2010-06-14 Jeremy Bennett <jeremy.bennett@embecosm.com>
* or1ksim.tests/inst-set-test.exp: Modified output from RANGE
/or1ksim/testsuite/README
12,8 → 12,8
Tests are provided for the standalone simulator (or1ksim) and for the library
(libsim.a).
 
At the time of writing a total of 1,857 tests compile, run and pass. That
figure is broken down into 1,593 tests of the standalone simulator and 264
At the time of writing a total of 2,499 tests compile, run and pass. That
figure is broken down into 2,235 tests of the standalone simulator and 264
tests of the library
 
Configuration and make files are provided for further test programs. These
46,7 → 46,7
Working tests
=============
 
A total of 1,593 tests of standalone Or1ksim:
A total of 2,235 tests of standalone Or1ksim:
 
basic: 8 tests of a wide range of instructions and registers.
cache: 5 tests of the Or1ksim cache modeling
67,6 → 67,7
local-global: 1 test of C local and global variables.
inst-set-test: A collection of tests of individual instructions
is-add-test 213 tests of the l.add* instructions (Bugs 1771, 1776)
is-and-test 80 tests of the l.and* instructions (Bugs 1782-1784)
is-div-test: 101 tests of the l.div and l.divu instructions (Bug 1770).
is-find-test: 14 tests of the l.ff1 and l.fl1 instructions (Bug 1772).
is-jump-test: 27 tests of the jump instructions (Bug 1775).
73,8 → 74,12
is-lws-test: 13 tests of the l.lws instruction (Bug 1767).
is-mac-test: 189 tests of the MAC instructions (Bugs 1773, 1777).
is-mul-test: 186 tests of the l.mul* instructions (Bug 1774).
is-or-test 80 tests of the l.or* instructions (Bugs 1782-1784)
is-ror-test: 36 tests of the l.ror and l.rori instructions (Bug 1778).
is-shift-test: 344 tests of the shift instructions (Bug 1782-1784).
is-spr-test: 28 tests of the l.mfspr and l.mtspr instructions (Bug 1779).
is-sub-test 58 tests of the l.sub instruction (Bugs 1782-1784)
is-xor-test 80 tests of the l.xor* instructions (Bugs 1782-1784)
mem-test: 16 tests of simple memory access.
mmu: 110 tests of the MMU.
mul: 5 tests of the multiply functionality.
/or1ksim/config.h.in
3,9 → 3,6
/* Define if building universal (internal helper macro) */
#undef AC_APPLE_UNIVERSAL_BUILD
 
/* Whether arithmethic instructions set flag on zero */
#undef ARITH_SET_FLAG
 
/* "Whether the compiler supports 'long long'." */
#undef CC_HAS_LONG_LONG
 
/or1ksim/configure
963,7 → 963,6
enable_execution
enable_ethphy
enable_range_stats
enable_arith_flag
enable_debug
'
ac_precious_vars='build_alias
1619,7 → 1618,6
--enable-execution Execution style to use (simple/complex/dynamic)
--enable-ethphy compiles sim with ethernet phy support
--enable-range-stats Specifies, whether we should do register accesses over time analysis.
--enable-arith-flag Whether arithmethic instructions setflag.
--enable-debug enable library debugging symbols
 
Optional Packages:
4554,13 → 4552,13
else
lt_cv_nm_interface="BSD nm"
echo "int some_variable = 0;" > conftest.$ac_ext
(eval echo "\"\$as_me:4557: $ac_compile\"" >&5)
(eval echo "\"\$as_me:4555: $ac_compile\"" >&5)
(eval "$ac_compile" 2>conftest.err)
cat conftest.err >&5
(eval echo "\"\$as_me:4560: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
(eval echo "\"\$as_me:4558: $NM \\\"conftest.$ac_objext\\\"\"" >&5)
(eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out)
cat conftest.err >&5
(eval echo "\"\$as_me:4563: output\"" >&5)
(eval echo "\"\$as_me:4561: output\"" >&5)
cat conftest.out >&5
if $GREP 'External.*some_variable' conftest.out > /dev/null; then
lt_cv_nm_interface="MS dumpbin"
5765,7 → 5763,7
;;
*-*-irix6*)
# Find out which ABI we are using.
echo '#line 5768 "configure"' > conftest.$ac_ext
echo '#line 5766 "configure"' > conftest.$ac_ext
if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
(eval $ac_compile) 2>&5
ac_status=$?
7134,11 → 7132,11
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7137: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7135: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:7141: \$? = $ac_status" >&5
echo "$as_me:7139: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
7473,11 → 7471,11
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7476: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7474: $lt_compile\"" >&5)
(eval "$lt_compile" 2>conftest.err)
ac_status=$?
cat conftest.err >&5
echo "$as_me:7480: \$? = $ac_status" >&5
echo "$as_me:7478: \$? = $ac_status" >&5
if (exit $ac_status) && test -s "$ac_outfile"; then
# The compiler can only warn and ignore the option if not recognized
# So say no if there are warnings other than the usual output.
7578,11 → 7576,11
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7581: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7579: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:7585: \$? = $ac_status" >&5
echo "$as_me:7583: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
7633,11 → 7631,11
-e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \
-e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \
-e 's:$: $lt_compiler_flag:'`
(eval echo "\"\$as_me:7636: $lt_compile\"" >&5)
(eval echo "\"\$as_me:7634: $lt_compile\"" >&5)
(eval "$lt_compile" 2>out/conftest.err)
ac_status=$?
cat out/conftest.err >&5
echo "$as_me:7640: \$? = $ac_status" >&5
echo "$as_me:7638: \$? = $ac_status" >&5
if (exit $ac_status) && test -s out/conftest2.$ac_objext
then
# The compiler can only warn and ignore the option if not recognized
10449,7 → 10447,7
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 10452 "configure"
#line 10450 "configure"
#include "confdefs.h"
 
#if HAVE_DLFCN_H
10545,7 → 10543,7
lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2
lt_status=$lt_dlunknown
cat > conftest.$ac_ext <<_LT_EOF
#line 10548 "configure"
#line 10546 "configure"
#include "confdefs.h"
 
#if HAVE_DLFCN_H
17586,8 → 17584,8
$as_echo "dynamic" >&6; }
;;
*)
{ { $as_echo "$as_me:$LINENO: error: \"excecution must one of simple/complex/dynamic\"" >&5
$as_echo "$as_me: error: \"excecution must one of simple/complex/dynamic\"" >&2;}
{ { $as_echo "$as_me:$LINENO: error: \"execution must one of simple/complex/dynamic\"" >&5
$as_echo "$as_me: error: \"execution must one of simple/complex/dynamic\"" >&2;}
{ (exit 1); exit 1; }; }
;;
esac
17633,22 → 17631,6
{ $as_echo "$as_me:$LINENO: result: ${enable_range_stats-no}" >&5
$as_echo "${enable_range_stats-no}" >&6; }
 
set_arith_flag="0"
{ $as_echo "$as_me:$LINENO: checking whether arithmethic instructions set flag" >&5
$as_echo_n "checking whether arithmethic instructions set flag... " >&6; }
# Check whether --enable-arith_flag was given.
if test "${enable_arith_flag+set}" = set; then
enableval=$enable_arith_flag;
case "$enableval" in
no) set_arith_flag="0" ;;
yes) set_arith_flag="1" ;;
esac
 
fi
 
{ $as_echo "$as_me:$LINENO: result: ${enable_arith_flag-no}" >&5
$as_echo "${enable_arith_flag-no}" >&6; }
 
# check for --enable-debug argument (for argtable2)
# Check whether --enable-debug was given.
if test "${enable_debug+set}" = set; then
17673,11 → 17655,6
 
 
cat >>confdefs.h <<_ACEOF
#define ARITH_SET_FLAG $set_arith_flag
_ACEOF
 
 
cat >>confdefs.h <<_ACEOF
#define HAVE_ETH_PHY $eth_phy
_ACEOF
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.