Subversion Repositories openrisc

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-2.c (revision 322) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "popcntw" } } */ + +int foo(int x) +{ + return __builtin_popcount(x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/parity-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/parity-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/parity-1.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power5" } */ +/* { dg-final { scan-assembler "popcntb" } } */ +/* { dg-final { scan-assembler-not "mullw" } } */ + +int foo(int x) +{ + return __builtin_parity(x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/parity-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/warn-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/warn-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/warn-2.c (revision 322) @@ -0,0 +1,18 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O -mcpu=power7 -mno-altivec" } */ + +/* { dg-warning "-mno-altivec disables vsx" "" { target *-*-* } 1 } */ + +double +foo (double *x, double *y) +{ + double z[2]; + int i; + + for (i = 0; i < 2; i++) + z[i] = x[i] + y[i]; + return z[0] * z[1]; +} + +/* { dg-final { scan-assembler-not "xsadddp" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/warn-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c (revision 322) @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-darwin* powerpc*-*-linux* } } */ +/* { dg-options "-mno-powerpc-gfxopt -mpowerpc64" } */ +extern void bar (void *); +extern double x; +void +foo (void) +{ + char buf2 [32][1024]; + bar (buf2 [(int) x]); +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/e500-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/e500-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/e500-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test functioning of command option -mno-isel */ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-O2 -mno-isel" } */ + +/* { dg-final { scan-assembler-not "isel" } } */ + +int +foo (int x, int y) +{ + if (x < y) + return x; + else + return y; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/e500-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c (revision 322) @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* rs6000-*-* } } */ +/* { dg-options "-mno-powerpc-gfxopt" } */ +/* { dg-final { scan-assembler-not "stfiwx" } } */ + +/* A basic test of the old-style (not stfiwx) fp -> int conversion. */ +int f(double a, double b) +{ + int a1 = a; + int b1 = b; + return a1+b1; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-fpint.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-33.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-33.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-33.c (revision 322) @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +/* We should only produce one vspltw as we already splatted the value. */ +/* { dg-final { scan-assembler-times "vspltw" 1 } } */ + +#include + +vector float f(vector float a) +{ + vector float b = vec_splat (a, 2); + return vec_splat (b, 0); +} + +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-33.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-16.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-16.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-16.c (revision 322) @@ -0,0 +1,22 @@ +/* This is a compile-only test for interaction of "-maltivec" and "-save-temps". */ +/* Author: Ziemowit Laski . */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-save-temps -maltivec" } */ + +#include + +#define vector_float vector float +#define vector_float_foo vector float foo +#define vector_float_bar_eq vector float bar = + +/* NB: Keep the following split across three lines. */ +vector +int +a1 = { 100, 200, 300, 400 }; + +vector_float f1 = { 1.0, 2.0, 3.0, 4.0 }; +vector_float_foo = { 3.0, 4.0, 5.0, 6.0 }; +vector_float_bar_eq { 8.0, 7.0, 6.0, 5.0 }; + +/* { dg-final { cleanup-saved-temps } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-16.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap32.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap32.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap32.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "lwbrx" } } */ +/* { dg-final { scan-assembler "stwbrx" } } */ + +unsigned int ui; +unsigned int load_bswap32 (unsigned int *p) { return __builtin_bswap32 (*p); } +void store_bswap32 (unsigned int a) { ui = __builtin_bswap32 (a); }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap32.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c (revision 322) @@ -0,0 +1,17 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ + +struct c +{ + double d; + int i; +}; + +struct j +{ + int tt; + struct c d; + int t; +}; + +int f[sizeof(struct j)!=24?-1:1];

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-3.c (revision 322) @@ -0,0 +1,80 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +extern void exit (int); +extern void abort (void); + +typedef int int4 __attribute__ ((vector_size (16))); +typedef float float4 __attribute__ ((vector_size (16))); + +int4 a1 = (int4) { 100, 200, 300, 400 }; +int4 a2 = (int4) { 500, 600, 700, 800 }; + +float4 f1 = (float4) { 1.0, 2.0, 3.0, 4.0 }; +float4 f2 = (float4) { 5.0, 6.0, 7.0, 8.0 }; + +int i3[4] __attribute__((aligned(16))); +int j3[4] __attribute__((aligned(16))); +float h3[4] __attribute__((aligned(16))); +float g3[4] __attribute__((aligned(16))); + +#define vec_store(dst, src) \ + __builtin_vec_st (src, 0, (__typeof__ (src) *) dst) + +#define vec_add_int4(x, y) \ + __builtin_altivec_vaddsws (x, y) + +#define vec_add_float4(x, y) \ + __builtin_altivec_vaddfp (x, y) + +#define my_abs(x) (x > 0.0F ? x : -x) + +void +compare_int4 (int *a, int *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (a[i] != b[i]) + abort (); +} + +void +compare_float4 (float *a, float *b) +{ + int i; + + for (i = 0; i < 4; ++i) + if (my_abs(a[i] - b[i]) >= 1.0e-6) + abort (); +} + +void +main1 () +{ + int loc1 = 600, loc2 = 800; + int4 a3 = (int4) { loc1, loc2, 1000, 1200 }; + int4 itmp; + double locf = 12.0; + float4 f3 = (float4) { 6.0, 8.0, 10.0, 12.0 }; + float4 ftmp; + + vec_store (i3, a3); + itmp = vec_add_int4 (a1, a2); + vec_store (j3, itmp); + compare_int4 (i3, j3); + + vec_store (g3, f3); + ftmp = vec_add_float4 (f1, f2); + vec_store (h3, ftmp); + compare_float4 (g3, h3); +} + +int +main () +{ + main1 (); + exit (0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr42747.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr42747.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr42747.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7 -ffast-math" } */ + +double foo (double x) { return __builtin_sqrt (x); } + +/* { dg-final { scan-assembler "xssqrtdp" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr42747.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/doloop-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/doloop-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/doloop-1.c (revision 322) @@ -0,0 +1,17 @@ +/* Make sure both loops are recognized as doloops. + If so, "bdnz" will be generated on ppc; if not, + you will get "ble" or "blt" or "bge". */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +void foo (int count, char* pca, char* pcb) { + int i; + if (count > 10) + for (i = 0; i < count; ++i) + pcb += i; + else + for (i = 0; i < count; ++i) + pca += i; + *pca = *pcb; +} +/* { dg-final { scan-assembler "bdnz" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/doloop-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of macchwu. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of mulhhwu. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulhhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulhhwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050830-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050830-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050830-1.c (revision 322) @@ -0,0 +1,13 @@ +/* Make sure the doloop optimization is done for this loop. */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "bdn" } } */ +extern int a[]; +int foo(int w) { + int n = w; + while (n >= 512) + { + a[n] = 42; + n -= 256; + } + }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050830-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of mulchw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mulchw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mulchw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c (revision 322) @@ -0,0 +1,10 @@ +/* PR rtl-optimization/10588 */ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int foo(int x) +{ + return x == 0; +} + +/* { dg-final { scan-assembler "cntlzw|isel" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-eq0-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of macchw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "macchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-macchw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-6.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-6.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-6.c (revision 322) @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include +#include + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 3.0, 5.0 }; +vector float c = { 2.0, 6.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu1_lt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 11.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-macros.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-macros.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-macros.c (revision 322) @@ -0,0 +1,64 @@ +/* Copyright (C) 2007 Free Software Foundation, Inc. */ + +/* { dg-do preprocess } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Conditional macros should not be expanded by pragmas. */ +#pragma __vector +_Pragma ("__vector") + +/* Redefinition of conditional macros. */ +/* No warning should be generated. */ + +#define __vector __new_vector +#define __pixel __new_pixel +#define __bool __new_bool +#define vector new_vector +#define pixel new_pixel +#define bool new_bool + +/* Definition of conditional macros. */ +/* No warning should be generated. */ + +#undef __vector +#define __vector __new_vector + +#undef __pixel +#define __pixel __new_pixel + +#undef __bool +#define __bool __new_bool + +#undef vector +#define vector new_vector + +#undef pixel +#define pixel new_pixel + +#undef bool +#define bool new_bool + +/* Re-definition of "unconditional" macros. */ +/* Warnings should be generated as usual. */ + +#define __vector __newer_vector +#define __pixel __newer_pixel +#define __bool __newer_bool +#define vector newer_vector +#define pixel newer_pixel +#define bool newer_bool + +/* { dg-warning "redefined" "__vector redefined" { target *-*-* } 45 } */ +/* { dg-warning "redefined" "__pixel redefined" { target *-*-* } 46 } */ +/* { dg-warning "redefined" "__bool redefined" { target *-*-* } 47 } */ +/* { dg-warning "redefined" "vector redefined" { target *-*-* } 48 } */ +/* { dg-warning "redefined" "pixel redefined" { target *-*-* } 49 } */ +/* { dg-warning "redefined" "bool redefined" { target *-*-* } 50 } */ + +/* { dg-message "location of the previous" "prev __vector defn" { target *-*-* } 25 } */ +/* { dg-message "location of the previous" "prev __pixel defn" { target *-*-* } 28 } */ +/* { dg-message "location of the previous" "prev __bool defn" { target *-*-* } 31 } */ +/* { dg-message "location of the previous" "prev vector defn" { target *-*-* } 34 } */ +/* { dg-message "location of the previous" "prev pixel defn" { target *-*-* } 37 } */ +/* { dg-message "location of the previous" "prev bool defn" { target *-*-* } 40 } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-macros.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec" } */ +/* { dg-final { scan-assembler "lvx" } } */ + +void foo(void) +{ + int x[8] __attribute__((aligned(128))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memcpy.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-25.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-25.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-25.c (revision 322) @@ -0,0 +1,20 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2 -Wall" } */ + + +#define vector __attribute__((__vector_size__(16) )) +vector int f() +{ + int t = 4; + return (vector int){t,t,t,t}; +} +vector int f1() +{ + return (vector int){4,4,4,4}; +} + +/* We should be able to materialize the constant vector without + any lvewx instructions as it is constant. */ +/* { dg-final { scan-assembler-not "lvewx" } } */ +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-25.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c (revision 322) @@ -0,0 +1,52 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "fmr \[0-9\]+,\[0-9\]+" } } + +/* Origin:Pete Steinmetz */ + +/* PR 16796: Extraneous move. */ + +static const double huge = 1.0e300; +typedef int int64_t __attribute__ ((__mode__ (__DI__))); +typedef unsigned int u_int64_t __attribute__ ((__mode__ (__DI__))); + +double __floor(double x) +{ + union { + double dbl_val; + long int long_val; + } temp; + + int64_t i0,j0; + u_int64_t i; + temp.dbl_val = x; + i0 = temp.long_val; + + j0 = ((i0>>52)&0x7ff)-0x3ff; + if(j0<52) { + if(j0<0) { + if(huge+x>0.0) { + if(i0>=0) {i0=0;} + else if((i0&0x7fffffffffffffff)!=0) + { i0=0xbff0000000000000;} + } + } else { + i = (0x000fffffffffffff)>>j0; + if((i0&i)==0) return x; + if(huge+x>0.0) { + if(i0<0) i0 += (0x0010000000000000)>>j0; + i0 &= (~i); + } + } + } else { + if (j0==0x400) + return x+x; + else + return x; + } + temp.long_val = i0; + x = temp.dbl_val; + return x; +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-mov-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c (revision 322) @@ -0,0 +1,67 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ + +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,1,31" } } */ +/* { dg-final { scan-assembler-not "rlwinm \[0-9\]+,\[0-9\]+,\[0-9\]+,0xffffffff" } } */ + +/* Origin:Pete Steinmetz */ + +/* PR 17104 many sign extends added. */ + +struct { + int f1 : 1; + int f2 : 1; + int f3 : 1; + int f4 : 1; + int f5 : 1; + int f6 : 1; + int f7 : 1; + int f8 : 1; + int f9 : 1; + int f10 : 1; + int f11 : 1; + int f12 : 1; + int f13 : 1; + int f14 : 1; + int f15 : 1; + int f16 : 1; + int f17 : 2; + int f18 : 2; + int f19 : 2; + int f20 : 2; + int f21 : 2; + int f22 : 2; + int f23 : 2; + int f24 : 2; + } s; + +void foo () +{ + + s.f1 = 0; + s.f2 = 0; + s.f3 = 0; + s.f4 = 0; + s.f5 = 0; + s.f6 = 0; + s.f7 = 0; + s.f8 = 0; + s.f9 = 0; + s.f10 = 0; + s.f11 = 0; + s.f12 = 0; + s.f13 = 0; + s.f14 = 0; + s.f15 = 0; + s.f16 = 0; + s.f17 = 0; + s.f18 = 0; + s.f19 = 0; + s.f20 = 0; + s.f21 = 0; + s.f22 = 0; + s.f23 = 0; + s.f24 = 0; + +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-bitfield1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c (revision 322) @@ -0,0 +1,38 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvnmadd" } } */ +/* { dg-final { scan-assembler "xvnmsub" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmaxsp" } } */ +/* { dg-final { scan-assembler "xvminsp" } } */ +/* { dg-final { scan-assembler "xvsqrtsp" } } */ +/* { dg-final { scan-assembler "xvabssp" } } */ +/* { dg-final { scan-assembler "xvnabssp" } } */ +/* { dg-final { scan-assembler "xvresp" } } */ +/* { dg-final { scan-assembler "xvrsqrtesp" } } */ + +void use_builtins (__vector float *p, __vector float *q, __vector float *r, __vector float *s) +{ + p[0] = __builtin_vsx_xvaddsp (q[0], r[0]); + p[1] = __builtin_vsx_xvsubsp (q[1], r[1]); + p[2] = __builtin_vsx_xvmulsp (q[2], r[2]); + p[3] = __builtin_vsx_xvdivsp (q[3], r[3]); + p[4] = __builtin_vsx_xvmaxsp (q[4], r[4]); + p[5] = __builtin_vsx_xvminsp (q[5], r[5]); + p[6] = __builtin_vsx_xvabssp (q[6]); + p[7] = __builtin_vsx_xvnabssp (q[7]); + p[8] = __builtin_vsx_xvsqrtsp (q[8]); + p[9] = __builtin_vsx_xvmaddsp (q[9], r[9], s[9]); + p[10] = __builtin_vsx_xvmsubsp (q[10], r[10], s[10]); + p[11] = __builtin_vsx_xvnmaddsp (q[11], r[11], s[11]); + p[12] = __builtin_vsx_xvnmsubsp (q[12], r[12], s[12]); + p[13] = __builtin_vsx_xvresp (q[13]); + p[14] = __builtin_vsx_xvrsqrtesp (q[14]); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c (revision 322) @@ -0,0 +1,116 @@ +/* Verify that unwinding can find SPE registers in signal frames. */ +/* Origin: Joseph Myers */ +/* { dg-do run { target { powerpc*-*-linux* && powerpc_spe } } } */ +/* { dg-options "-fexceptions -fnon-call-exceptions -O2" } */ + +#include +#include +#include +#include + +int count; +char *null; +int found_reg; + +typedef int v2si __attribute__((__vector_size__(8))); + +v2si v1 = { 123, 234 }; +v2si v2 = { 345, 456 }; + +static _Unwind_Reason_Code +force_unwind_stop (int version, _Unwind_Action actions, + _Unwind_Exception_Class exc_class, + struct _Unwind_Exception *exc_obj, + struct _Unwind_Context *context, + void *stop_parameter) +{ + unsigned int reg; + if (actions & _UA_END_OF_STACK) + abort (); + if (_Unwind_GetGR (context, 1215) == 123) + found_reg = 1; + return _URC_NO_REASON; +} + +static void force_unwind () +{ + struct _Unwind_Exception *exc = malloc (sizeof (*exc)); + memset (&exc->exception_class, 0, sizeof (exc->exception_class)); + exc->exception_cleanup = 0; + +#ifndef __USING_SJLJ_EXCEPTIONS__ + _Unwind_ForcedUnwind (exc, force_unwind_stop, 0); +#else + _Unwind_SjLj_ForcedUnwind (exc, force_unwind_stop, 0); +#endif + + abort (); +} + +static void counter (void *p __attribute__((unused))) +{ + ++count; +} + +static void handler (void *p __attribute__((unused))) +{ + if (count != 2) + abort (); + if (!found_reg) + abort (); + exit (0); +} + +static int __attribute__((noinline)) fn5 () +{ + char dummy __attribute__((cleanup (counter))); + force_unwind (); + return 0; +} + +static void fn4 (int sig) +{ + char dummy __attribute__((cleanup (counter))); + /* Clobber high part without compiler's knowledge so the only saved + copy is from the signal frame. */ + asm volatile ("evmergelo 15,15,15"); + fn5 (); + null = NULL; +} + +static void fn3 () +{ + abort (); +} + +static int __attribute__((noinline)) fn2 () +{ + register v2si r15 asm("r15"); + r15 = v1; + asm volatile ("" : "+r" (r15)); + *null = 0; + fn3 (); + return 0; +} + +static int __attribute__((noinline)) fn1 () +{ + signal (SIGSEGV, fn4); + signal (SIGBUS, fn4); + fn2 (); + return 0; +} + +static int __attribute__((noinline)) fn0 () +{ + char dummy __attribute__((cleanup (handler))); + fn1 (); + null = 0; + return 0; +} + +int main() +{ + fn0 (); + abort (); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-unwind-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test generation of nmachhw on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmachhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c (revision 322) @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include +#include + +#define N 256 + +__attribute__ ((noinline)) +void bar (double *pa, double *pb, double *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + } + + bar (pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,a,b,c); + main1 (N-2,a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 3 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c (revision 322) @@ -0,0 +1,31 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct A +{ + long long a; + unsigned char b; +}; + +struct D +{ + unsigned char y; + struct A x; + unsigned char z; +}; + +struct E +{ + long long d; + unsigned char e; +}; + +struct y +{ + struct A b2; + struct D b3; + struct E b4; +}; + +int f[sizeof(struct y)!=56?-1:1];

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-11.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-1.c (revision 322) @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-options "-O2" } */ +#include +#include +register int *testreg asm ("r29"); + +int x; +int y; +int *ext_func (int *p) { return p; } + +void test_reg_save_restore (int*) __attribute__((noinline)); +void +test_reg_save_restore (int *p) +{ + setlocale (LC_ALL, "C"); + testreg = ext_func(p); +} +main() { + testreg = &x; + test_reg_save_restore (&y); + if (testreg != &y) + abort (); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of nmaclhw on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmaclhw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c (revision 322) @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +long foo(long x) +{ + return -(x == 0); +} + +long bar(long x) +{ + long t = __builtin_clzl(x); + return -(t>>(sizeof(long) == 8 ? 6 : 5)); +} + +/* { dg-final { scan-assembler-not "cntlz" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-negeq0-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test generation of machhwu on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c (revision 322) @@ -0,0 +1,12 @@ +// { dg-do compile } +/* { dg-skip-if "" { powerpc*-*-aix* } { "*" } { "" } } */ +// { dg-options "-O2 -mpowerpc64" } +// { dg-final { scan-assembler-not "stfd" } } + +// The register allocator should have allocated the temporary long long value in a floating point register. + +double +d2ll2d (double d) +{ + return (double)(long long)d; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-double-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c (revision 322) @@ -0,0 +1,25 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Basic test for the new VMX intrinsics and error messages. */ +#include + +int main(int argc, char **argv) +{ +vector float t; + vec_promote(); /* { dg-error "vec_promote only accepts 2" } */ + vec_promote(1.0f); /* { dg-error "vec_promote only accepts 2" } */ + vec_promote(1.0f, 2, 3); /* { dg-error "vec_promote only accepts 2" } */ + vec_extract (); /* { dg-error "vec_extract only accepts 2" } */ + vec_extract (t); /* { dg-error "vec_extract only accepts 2" } */ + vec_extract (t, 2); + vec_extract (t, 2, 5, 6); /* { dg-error "vec_extract only accepts 2" } */ + vec_splats (); /* { dg-error "vec_splats only accepts 1" } */ + vec_splats (t, 3); /* { dg-error "vec_splats only accepts 1" } */ + vec_insert (); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t, 3); /* { dg-error "vec_insert only accepts 3" } */ + vec_insert (t, 3, 2, 4, 6, 6); /* { dg-error "vec_insert only accepts 3" } */ + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-3.c (revision 322) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "popcntd" } } */ + +long foo(int x) +{ + return __builtin_popcountl(x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/popcount-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c (revision 322) @@ -0,0 +1,12 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-options "-O" } */ +/* { dg-final { scan-assembler "li r3,12345\n\t(bl|jbsr) " } } */ + +/* Check that zero-size structures don't affect parameter passing. */ + +struct empty { }; +extern void foo (struct empty e, int a); +void bar (void) { + struct empty e; + foo (e, 12345); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-17.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-17.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-17.c (revision 322) @@ -0,0 +1,11 @@ +/* Verify a statement in the GCC Manual that GCC allows the use of a + typedef name as a vector type specifier. */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec" } */ + +typedef unsigned int ui; +typedef signed char sc; +__vector ui vui; +__vector sc vsc;

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-17.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c (revision 322) @@ -0,0 +1,152 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xvadddp" } } */ +/* { dg-final { scan-assembler "xvsubdp" } } */ +/* { dg-final { scan-assembler "xvmuldp" } } */ +/* { dg-final { scan-assembler "xvdivdp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvsqrtdp" } } */ +/* { dg-final { scan-assembler "xvcpsgndp" } } */ +/* { dg-final { scan-assembler "xvrdpim" } } */ +/* { dg-final { scan-assembler "xvrdpip" } } */ +/* { dg-final { scan-assembler "xvrdpiz" } } */ +/* { dg-final { scan-assembler "xvrdpic" } } */ +/* { dg-final { scan-assembler "xvrdpi " } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +double a[SIZE] __attribute__((__aligned__(32))); +double b[SIZE] __attribute__((__aligned__(32))); +double c[SIZE] __attribute__((__aligned__(32))); +double d[SIZE] __attribute__((__aligned__(32))); +double e[SIZE] __attribute__((__aligned__(32))); + +void +vector_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +void +vector_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + +void +vector_multiply (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] * c[i]; +} + +void +vector_multiply_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) + d[i]; +} + +void +vector_multiply_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) - d[i]; +} + +void +vector_divide (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] / c[i]; +} + +extern double sqrt (double); +extern double floor (double); +extern double ceil (double); +extern double trunc (double); +extern double nearbyint (double); +extern double rint (double); +extern double copysign (double, double); + +void +vector_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = sqrt (b[i]); +} + +void +vector_floor (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = floor (b[i]); +} + +void +vector_ceil (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = ceil (b[i]); +} + +void +vector_trunc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = trunc (b[i]); +} + +void +vector_nearbyint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = nearbyint (b[i]); +} + +void +vector_rint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = rint (b[i]); +} + +void +vector_copysign (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = copysign (b[i], c[i]); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c (revision 322) @@ -0,0 +1,22 @@ +/* { dg-do link } */ +/* { dg-options "-mminimal-toc" { target { powerpc*-*-* && lp64 } } } */ + +char *strchr (const char *, int); + +int +foo (int a) +{ + int b; + + b = 0; + if ("/"[1] != '\0') + if (strchr ("/", a)) + b = 1; + return b; +} + +int +main (void) +{ + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-toc.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap16.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap16.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap16.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler "lhbrx" } } */ +/* { dg-final { scan-assembler "sthbrx" } } */ + +unsigned short us; +unsigned int load_bswap16 (unsigned short *p) { return __builtin_bswap16 (*p); } +void store_bswap16 (unsigned int a) { us = __builtin_bswap16 (a); }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap16.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c (revision 322) @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ + +struct b +{ + long long t; + int i; +}; + +struct l +{ + int i; + double d; +}; +struct k +{ + int tt; + struct l d; + struct b h; + int t; +}; + +int f[sizeof(struct k)!=36?-1:1];

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-9.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c (revision 322) @@ -0,0 +1,363 @@ +/* { dg-do run { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2" } */ +#include +#include +#include + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. + Parameter passing of integral and floating point is tested. */ + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Testcase could break on future gcc's, if parameter regs + are changed before this asm. */ + +#ifndef __MACH__ +#define save_parms(lparms) \ + asm volatile ("ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ + "std 5,16(11)\n\t" \ + "std 6,24(11)\n\t" \ + "std 7,32(11)\n\t" \ + "std 8,40(11)\n\t" \ + "std 9,48(11)\n\t" \ + "std 10,56(11)\n\t" \ + "stfd 1,64(11)\n\t" \ + "stfd 2,72(11)\n\t" \ + "stfd 3,80(11)\n\t" \ + "stfd 4,88(11)\n\t" \ + "stfd 5,96(11)\n\t" \ + "stfd 6,104(11)\n\t" \ + "stfd 7,112(11)\n\t" \ + "stfd 8,120(11)\n\t" \ + "stfd 9,128(11)\n\t" \ + "stfd 10,136(11)\n\t" \ + "stfd 11,144(11)\n\t" \ + "stfd 12,152(11)\n\t" \ + "stfd 13,160(11)\n\t":::"11", "memory"); \ + lparms = gparms; +#else +#define save_parms(lparms) \ + asm volatile ("ld r11,gparms@got(r2)\n\t" \ + "std r3,0(r11)\n\t" \ + "std r4,8(r11)\n\t" \ + "std r5,16(r11)\n\t" \ + "std r6,24(r11)\n\t" \ + "std r7,32(r11)\n\t" \ + "std r8,40(r11)\n\t" \ + "std r9,48(r11)\n\t" \ + "std r10,56(r11)\n\t" \ + "stfd f1,64(r11)\n\t" \ + "stfd f2,72(r11)\n\t" \ + "stfd f3,80(r11)\n\t" \ + "stfd f4,88(r11)\n\t" \ + "stfd f5,96(r11)\n\t" \ + "stfd f6,104(r11)\n\t" \ + "stfd f7,112(r11)\n\t" \ + "stfd f8,120(r11)\n\t" \ + "stfd f9,128(r11)\n\t" \ + "stfd f10,136(r11)\n\t" \ + "stfd f11,144(r11)\n\t" \ + "stfd f12,152(r11)\n\t" \ + "stfd f13,160(r11)\n\t":::"r11", "memory"); \ + lparms = gparms; +#endif + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 1 +*/ +void __attribute__ ((noinline)) fcld (char *s, long l, double d) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldi (char *s, long l, double d, signed int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if (d != lparms.fprs[0]) + abort (); + + if ((signed long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : gpr 4 + d : fpr 2 + i : gpr 5 +*/ +void __attribute__ ((noinline)) +fcldu (char *s, long l, float d, unsigned int i) +{ + reg_parms_t lparms; + save_parms (lparms); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if (l != lparms.gprs[1]) + abort (); + + if ((double) d != lparms.fprs[0]) + abort (); + + if ((unsigned long) i != lparms.gprs[3]) + abort (); +} + +/* Paramter passing. + s : gpr 3 + l : slot 1 + d : slot 2 +*/ + +void __attribute__ ((noinline)) fceld (char *s, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort (); + + l = va_arg (arg, long); + d = va_arg (arg, double); + + /* Go back one frame. */ + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[1].l != l) + abort (); + + if (sp->slot[2].d != d) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + d : slot 3 + l : slot 4 +*/ +void __attribute__ ((noinline)) fciiedl (char *s, int i, int j, ...) +{ + stack_frame_t *sp; + reg_parms_t lparms; + va_list arg; + double d; + long l; + save_parms (lparms); + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort (); + + if ((long) i != lparms.gprs[1]) + abort (); + + if ((long) j != lparms.gprs[2]) + abort (); + + d = va_arg (arg, double); + l = va_arg (arg, long); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (sp->slot[3].d != d) + abort (); + + if (sp->slot[4].l != l) + abort (); +} + +/* +Parameter Register Offset in parameter save area +c r3 0-7 (not stored in parameter save area) +ff f1 8-15 (not stored) +d r5 16-23 (not stored) +ld f2 24-31 (not stored) +f r7 32-39 (not stored) +s r8,r9 40-55 (not stored) +gg f3 56-63 (not stored) +t (none) 64-79 (stored in parameter save area) +e (none) 80-87 (stored) +hh f4 88-95 (stored) + +*/ + +typedef struct +{ + int a; + double dd; +} sparm; + +typedef union +{ + int i[2]; + long l; + double d; +} double_t; + +/* Example from ABI documentation with slight changes. + Paramter passing. + c : gpr 3 + ff : fpr 1 + d : gpr 5 + ld : fpr 2 + f : gpr 7 + s : gpr 8 - 9 + gg : fpr 3 + t : save area offset 64 - 79 + e : save area offset 80 - 88 + hh : fpr 4 +*/ + +void __attribute__ ((noinline)) +fididisdsid (int c, double ff, int d, double ld, int f, + sparm s, double gg, sparm t, int e, double hh) +{ + stack_frame_t *sp; + reg_parms_t lparms; + double_t dx, dy; + + save_parms (lparms); + + /* Parm 0: int. */ + if ((long) c != lparms.gprs[0]) + abort (); + + /* Parm 1: double. */ + if (ff != lparms.fprs[0]) + abort (); + + /* Parm 2: int. */ + if ((long) d != lparms.gprs[2]) + abort (); + + /* Parm 3: double. */ + if (ld != lparms.fprs[1]) + abort (); + + /* Parm 4: int. */ + if ((long) f != lparms.gprs[4]) + abort (); + + /* Parm 5: struct sparm. */ + dx.l = lparms.gprs[5]; + dy.l = lparms.gprs[6]; + + if (s.a != dx.i[0]) + abort (); + if (s.dd != dy.d) + abort (); + + /* Parm 6: double. */ + if (gg != lparms.fprs[2]) + abort (); + + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* Parm 7: struct sparm. */ + dx.l = sp->slot[8].l; + dy.l = sp->slot[9].l; + if (t.a != dx.i[0]) + abort (); + if (t.dd != dy.d) + abort (); + + /* Parm 8: int. */ + if (e != sp->slot[10].l) + abort (); + + /* Parm 9: double. */ + + if (hh != lparms.fprs[3]) + abort (); +} + +int +main () +{ + char *s = "ii"; + + fcld (s, 1, 1.0); + fcldi (s, 1, 1.0, -2); + fcldu (s, 1, 1.0, 2); + fceld (s, 1, 1.0); + fciiedl (s, 1, 2, 1.0, 3); + fididisdsid (1, 1.0, 2, 2.0, -1, (sparm) + { + 3, 3.0}, 4.0, (sparm) + { + 5, 5.0}, 6, 7.0); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c (revision 322) @@ -0,0 +1,36 @@ +/* { dg-require-effective-target stdint_types } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=power5" } */ + +/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores + to test whether lwbrx/stwbrx is generated for normal power systems. */ + +#include +#define __const_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + + +/* This byte swap implementation is used by the Linux kernel and the + GNU C library. */ + +uint64_t +swap64_load (uint64_t *in) +{ + return __const_swab64 (*in); +} + +void +swap64_store (uint64_t *out, uint64_t in) +{ + *out = __const_swab64 (in); +} + +/* { dg-final { scan-assembler-times "lwbrx" 2 } } */ +/* { dg-final { scan-assembler-times "stwbrx" 2 } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-4.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-4.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-4.c (revision 322) @@ -0,0 +1,65 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#define vector __attribute__((vector_size(16))) + +static int vector x, y, z; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + z = __builtin_altivec_vadduwm (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = __builtin_altivec_vcmpbfp_p (0, f, g); + int1 = __builtin_altivec_vcmpeqfp_p (0, f, g); + int1 = __builtin_altivec_vcmpequb_p (0, c, d); + int1 = __builtin_altivec_vcmpequh_p (0, s, t); + int1 = __builtin_altivec_vcmpequw_p (0, i, j); + int1 = __builtin_altivec_vcmpgefp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtfp_p (0, f, g); + int1 = __builtin_altivec_vcmpgtsb_p (0, c, d); + int1 = __builtin_altivec_vcmpgtsh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtsw_p (0, i, j); + int1 = __builtin_altivec_vcmpgtub_p (0, c, d); + int1 = __builtin_altivec_vcmpgtuh_p (0, s, t); + int1 = __builtin_altivec_vcmpgtuw_p (0, i, j); + + __builtin_altivec_mtvscr (i); + __builtin_altivec_dssall (); + s = __builtin_altivec_mfvscr (); + __builtin_altivec_dss (3); + + __builtin_altivec_dst (pi, int1 + int2, 3); + __builtin_altivec_dstst (pi, int1 + int2, 3); + __builtin_altivec_dststt (pi, int1 + int2, 3); + __builtin_altivec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) __builtin_altivec_lvsl (int1 + 69, pi); + uc = (vector unsigned char) __builtin_altivec_lvsr (int1 + 69, pi); + + c = __builtin_altivec_lvebx (int1, pi); + s = __builtin_altivec_lvehx (int1, pi); + i = __builtin_altivec_lvewx (int1, pi); + i = __builtin_altivec_lvxl (int1, pi); + i = __builtin_altivec_lvx (int1, pi); + + __builtin_altivec_stvx (i, int2, pi); + __builtin_altivec_stvebx (c, int2, pi); + __builtin_altivec_stvehx (s, int2, pi); + __builtin_altivec_stvewx (i, int2, pi); + __builtin_altivec_stvxl (i, int2, pi); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/powerpc.exp =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/powerpc.exp (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/powerpc.exp (revision 322) @@ -0,0 +1,41 @@ +# Copyright (C) 2005, 2007 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the 'dg.exp' driver. + +# Exit immediately if this isn't a PowerPC target. +if { ![istarget powerpc*-*-*] && ![istarget rs6000-*-*] } then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize 'dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20030218-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20030218-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20030218-1.c (revision 322) @@ -0,0 +1,26 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* Test vectors that can interconvert without a cast. */ + +__ev64_opaque__ opp; +int vint __attribute__((vector_size (8))); +short vshort __attribute__((vector_size (8))); +float vfloat __attribute__((vector_size (8))); + +int +main (void) +{ + __ev64_opaque__ george = { 1, 2 }; /* { dg-error "opaque vector types cannot be initialized" } */ + + opp = vfloat; + vshort = opp; + vfloat = vshort; /* { dg-error "incompatible types when assigning" } */ + + /* Just because this is a V2SI, it doesn't make it an opaque. */ + vint = vshort; /* { dg-message "note: use -flax-vector-conversions to permit conversions between vectors with differing element types or numbers of subparts" } */ + /* { dg-error "incompatible types when assigning" "" { target *-*-* } 22 } */ + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20030218-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/regnames-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/regnames-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/regnames-1.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-options "-mregnames" } */ + +register double f17 asm ("f17"); +double foo (void) +{ + return f17; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/regnames-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of mullhwu on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-mpowerpc-gfxopt" } */ +/* { dg-final { scan-assembler "stfiwx" } } */ + +int foo (double x) +{ + return x; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stfiwx.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-7.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-7.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-7.c (revision 322) @@ -0,0 +1,34 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only" } */ + +/* Test PowerPC PAIRED extensions. */ + +#include +#include + +static float out[2] __attribute__ ((aligned (8))); + +vector float b = { 2.0, 8.0 }; +vector float c = { 3.0, 6.0 }; + +vector float a = { 0.0, 0.0 }; +void +test_api () +{ + + if (paired_cmpu1_gt (b, c)) + { + a = paired_add (b, c); + paired_stx (a, 0, out); + } + if ((out[0] != 5.0) || (out[1] != 14.0)) + abort (); +} + +int +main () +{ + test_api (); + return (0); +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-26.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-26.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-26.c (revision 322) @@ -0,0 +1,11 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* A compiler implementing context-sensitive keywords must define this + preprocessor macro so that altivec.h does not provide the vector, + pixel, etc. macros. */ + +#ifndef __APPLE_ALTIVEC__ +#error __APPLE_ALTIVEC__ not pre-defined +#endif

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-26.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test generation of nmacchw on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmacchw " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c (revision 322) @@ -0,0 +1,212 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxsel" } } */ +/* { dg-final { scan-assembler "vperm" } } */ +/* { dg-final { scan-assembler "xvrdpi" } } */ +/* { dg-final { scan-assembler "xvrdpic" } } */ +/* { dg-final { scan-assembler "xvrdpim" } } */ +/* { dg-final { scan-assembler "xvrdpip" } } */ +/* { dg-final { scan-assembler "xvrdpiz" } } */ +/* { dg-final { scan-assembler "xvrspi" } } */ +/* { dg-final { scan-assembler "xvrspic" } } */ +/* { dg-final { scan-assembler "xvrspim" } } */ +/* { dg-final { scan-assembler "xvrspip" } } */ +/* { dg-final { scan-assembler "xvrspiz" } } */ +/* { dg-final { scan-assembler "xsrdpi" } } */ +/* { dg-final { scan-assembler "xsrdpic" } } */ +/* { dg-final { scan-assembler "xsrdpim" } } */ +/* { dg-final { scan-assembler "xsrdpip" } } */ +/* { dg-final { scan-assembler "xsrdpiz" } } */ +/* { dg-final { scan-assembler "xsmaxdp" } } */ +/* { dg-final { scan-assembler "xsmindp" } } */ +/* { dg-final { scan-assembler "xxland" } } */ +/* { dg-final { scan-assembler "xxlandc" } } */ +/* { dg-final { scan-assembler "xxlnor" } } */ +/* { dg-final { scan-assembler "xxlor" } } */ +/* { dg-final { scan-assembler "xxlxor" } } */ +/* { dg-final { scan-assembler "xvcmpeqdp" } } */ +/* { dg-final { scan-assembler "xvcmpgtdp" } } */ +/* { dg-final { scan-assembler "xvcmpgedp" } } */ +/* { dg-final { scan-assembler "xvcmpeqsp" } } */ +/* { dg-final { scan-assembler "xvcmpgtsp" } } */ +/* { dg-final { scan-assembler "xvcmpgesp" } } */ +/* { dg-final { scan-assembler "xxsldwi" } } */ +/* { dg-final { scan-assembler-not "call" } } */ + +extern __vector int si[][4]; +extern __vector short ss[][4]; +extern __vector signed char sc[][4]; +extern __vector float f[][4]; +extern __vector unsigned int ui[][4]; +extern __vector unsigned short us[][4]; +extern __vector unsigned char uc[][4]; +extern __vector __bool int bi[][4]; +extern __vector __bool short bs[][4]; +extern __vector __bool char bc[][4]; +extern __vector __pixel p[][4]; +#ifdef __VSX__ +extern __vector double d[][4]; +extern __vector long sl[][4]; +extern __vector unsigned long ul[][4]; +extern __vector __bool long bl[][4]; +#endif + +int do_sel(void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxsel_4si (si[i][1], si[i][2], si[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel_8hi (ss[i][1], ss[i][2], ss[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel_16qi (sc[i][1], sc[i][2], sc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel_4sf (f[i][1], f[i][2], f[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel_2df (d[i][1], d[i][2], d[i][3]); i++; + + si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], bi[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], bs[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], bc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], bi[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], bl[i][3]); i++; + + si[i][0] = __builtin_vsx_xxsel (si[i][1], si[i][2], ui[i][3]); i++; + ss[i][0] = __builtin_vsx_xxsel (ss[i][1], ss[i][2], us[i][3]); i++; + sc[i][0] = __builtin_vsx_xxsel (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_xxsel (f[i][1], f[i][2], ui[i][3]); i++; + d[i][0] = __builtin_vsx_xxsel (d[i][1], d[i][2], ul[i][3]); i++; + + return i; +} + +int do_perm(void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_vperm_4si (si[i][1], si[i][2], uc[i][3]); i++; + ss[i][0] = __builtin_vsx_vperm_8hi (ss[i][1], ss[i][2], uc[i][3]); i++; + sc[i][0] = __builtin_vsx_vperm_16qi (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_vperm_4sf (f[i][1], f[i][2], uc[i][3]); i++; + d[i][0] = __builtin_vsx_vperm_2df (d[i][1], d[i][2], uc[i][3]); i++; + + si[i][0] = __builtin_vsx_vperm (si[i][1], si[i][2], uc[i][3]); i++; + ss[i][0] = __builtin_vsx_vperm (ss[i][1], ss[i][2], uc[i][3]); i++; + sc[i][0] = __builtin_vsx_vperm (sc[i][1], sc[i][2], uc[i][3]); i++; + f[i][0] = __builtin_vsx_vperm (f[i][1], f[i][2], uc[i][3]); i++; + d[i][0] = __builtin_vsx_vperm (d[i][1], d[i][2], uc[i][3]); i++; + + return i; +} + +int do_xxperm (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xxpermdi_2df (d[i][1], d[i][2], 0); i++; + d[i][0] = __builtin_vsx_xxpermdi (d[i][1], d[i][2], 1); i++; + return i; +} + +double x, y; +void do_concat (void) +{ + d[0][0] = __builtin_vsx_concat_2df (x, y); +} + +void do_set (void) +{ + d[0][0] = __builtin_vsx_set_2df (d[0][1], x, 0); + d[1][0] = __builtin_vsx_set_2df (d[1][1], y, 1); +} + +extern double z[][4]; + +int do_math (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xvrdpi (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpic (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpim (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpip (d[i][1]); i++; + d[i][0] = __builtin_vsx_xvrdpiz (d[i][1]); i++; + + f[i][0] = __builtin_vsx_xvrspi (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspic (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspim (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspip (f[i][1]); i++; + f[i][0] = __builtin_vsx_xvrspiz (f[i][1]); i++; + + z[i][0] = __builtin_vsx_xsrdpi (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpic (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpim (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpip (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsrdpiz (z[i][1]); i++; + z[i][0] = __builtin_vsx_xsmaxdp (z[i][1], z[i][0]); i++; + z[i][0] = __builtin_vsx_xsmindp (z[i][1], z[i][0]); i++; + return i; +} + +int do_cmp (void) +{ + int i = 0; + + d[i][0] = __builtin_vsx_xvcmpeqdp (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xvcmpgtdp (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xvcmpgedp (d[i][1], d[i][2]); i++; + + f[i][0] = __builtin_vsx_xvcmpeqsp (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xvcmpgtsp (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xvcmpgesp (f[i][1], f[i][2]); i++; + return i; +} + +int do_logical (void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxland (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlandc (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlnor (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlor (si[i][1], si[i][2]); i++; + si[i][0] = __builtin_vsx_xxlxor (si[i][1], si[i][2]); i++; + + ss[i][0] = __builtin_vsx_xxland (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlandc (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlnor (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlor (ss[i][1], ss[i][2]); i++; + ss[i][0] = __builtin_vsx_xxlxor (ss[i][1], ss[i][2]); i++; + + sc[i][0] = __builtin_vsx_xxland (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlandc (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlnor (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlor (sc[i][1], sc[i][2]); i++; + sc[i][0] = __builtin_vsx_xxlxor (sc[i][1], sc[i][2]); i++; + + d[i][0] = __builtin_vsx_xxland (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlandc (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlnor (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlor (d[i][1], d[i][2]); i++; + d[i][0] = __builtin_vsx_xxlxor (d[i][1], d[i][2]); i++; + + f[i][0] = __builtin_vsx_xxland (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlandc (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlnor (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlor (f[i][1], f[i][2]); i++; + f[i][0] = __builtin_vsx_xxlxor (f[i][1], f[i][2]); i++; + return i; +} + +int do_xxsldwi (void) +{ + int i = 0; + + si[i][0] = __builtin_vsx_xxsldwi (si[i][1], si[i][2], 0); i++; + ss[i][0] = __builtin_vsx_xxsldwi (ss[i][1], ss[i][2], 1); i++; + sc[i][0] = __builtin_vsx_xxsldwi (sc[i][1], sc[i][2], 2); i++; + ui[i][0] = __builtin_vsx_xxsldwi (ui[i][1], ui[i][2], 3); i++; + us[i][0] = __builtin_vsx_xxsldwi (us[i][1], us[i][2], 0); i++; + uc[i][0] = __builtin_vsx_xxsldwi (uc[i][1], uc[i][2], 1); i++; + f[i][0] = __builtin_vsx_xxsldwi (f[i][1], f[i][2], 2); i++; + d[i][0] = __builtin_vsx_xxsldwi (d[i][1], d[i][2], 3); i++; + return i; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr25960.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr25960.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr25960.c (revision 322) @@ -0,0 +1,17 @@ +/* { dg-do run { target { powerpc*-*-darwin* powerpc*-*-aix* rs6000-*-* powerpc*-*-linux* } } } */ +/* { dg-options "-O2 -mlong-double-128" } */ + +extern void abort (void); + +volatile long double l, m, n; + +int +main (void) +{ + l = __builtin_copysignl (0.0L, -1.0L); + m = __builtin_copysignl (0.0L, -1.0L); + n = l + m; + if (__builtin_copysignl (1.0L, n) >= 0.0L) + abort (); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr25960.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of mulchwu on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchwu " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of nmachhw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmachhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmachhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c (revision 322) @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include +#include + +#define N 256 + +__attribute__ ((noinline)) +void bar (char *pa, char *pb, char *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] + pc[i])) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, char * __restrict__ pa, char * __restrict__ pb, char * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] + pc[i]; + } + + bar (pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + char a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + char b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + char c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,a,b,c); + main1 (N-2,a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 2 "vect" } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr37168.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr37168.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr37168.c (revision 322) @@ -0,0 +1,14 @@ +/* PR target/37168 */ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +#define C 3.68249351546114573519399405666776E-44f +#define vector __attribute__ ((altivec (vector__))) + +vector float +foo (vector float a) +{ + vector float b = __builtin_vec_madd (b, a, (vector float) { C, C, C, C }); + return b; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr37168.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c (revision 322) @@ -0,0 +1,14 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-final { scan-assembler ".comm _x,12,2" } } */ +/* { dg-final { scan-assembler-not ".space 7" } } */ +/* PR 23071 */ + +struct Test { + double D __attribute__((packed,aligned(4))); + short X; +} x; + +struct { + char x; + struct Test t; +} b = { 1, { 2, 3 } };

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-12.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of nmaclhw. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "nmaclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (short)c; + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-nmaclhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of machhwu. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "machhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-machhwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-10.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-10.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-10.c (revision 322) @@ -0,0 +1,79 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec -fno-inline" } */ + +#include + +extern void exit (int); +extern void abort (void); + +typedef union +{ + float f[4]; + unsigned int i[4]; + vector float v; +} vec_float_t; + +void +check_vec_all_num () +{ + vec_float_t a, b, c; + + a.i[0] = 0xfffa5a5a; + a.f[1] = 1.0; + a.f[2] = 1.0; + a.f[3] = 1.0; + + b.f[0] = 1.0; + b.f[1] = 1.0; + b.f[2] = 1.0; + b.f[3] = 1.0; + + c.i[0] = 0xfffa5a5a; + c.i[1] = 0xfffa5a5a; + c.i[2] = 0xfffa5a5a; + c.i[3] = 0xfffa5a5a; + + if (vec_all_numeric (a.v)) + abort (); + + if (vec_all_nan (a.v)) + abort (); + + if (!vec_all_numeric (b.v)) + abort (); + + if (vec_all_nan (b.v)) + abort (); + + if (vec_all_numeric (c.v)) + abort (); + + if (!vec_all_nan (c.v)) + abort (); + +} + +void +check_cmple() +{ + vector float a = {1.0, 2.0, 3.0, 4.0}; + vector float b = {1.0, 3.0, 2.0, 5.0}; + vector bool int aux; + vector signed int le = {-1, -1, 0, -1}; + + aux = vec_cmple (a, b); + + if (!vec_all_eq (aux, le)) + abort (); +} + + +int +main() +{ + check_cmple (); + check_vec_all_num (); + exit (0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-10.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c (revision 322) @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +#include + +/* This used to ICE with reloading of a constant address. */ + +vector float f(void) +{ + vector float * a = (void*)16; + return vec_lvlx (0, a); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of mulhhw on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhw " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of machhw on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhw " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c (revision 322) @@ -0,0 +1,24 @@ +/* { dg-do run { target powerpc*-*-darwin* } } */ + +/* You might think you'd need -maltivec for this, but actually you + don't; GCC will happily do everything in GPRs, and it still + tests that the ABI is correct. */ + +#include +#include + +#define vector __attribute__((vector_size(16))) + +int main(void) +{ + vector unsigned int v = { 100, 200, 300, 400 }; + vector unsigned int w = { 4, 5, 6, 7 }; + char x[64]; + sprintf (x, "%lvu,%d,%lvu", v, 1, w); + if (strcmp (x, "100 200 300 400,1,4 5 6 7") != 0) + { + puts (x); + abort (); + } + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-18.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-18.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-18.c (revision 322) @@ -0,0 +1,24 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -mabi=altivec" } */ +/* { dg-final { scan-assembler "vcmpgtub" { target *-*-linux* } } } */ +/* { dg-final { scan-assembler "vcmpgtsb" { target *-*-darwin* } } } */ +/* { dg-final { scan-assembler "vcmpgtsh" } } */ +/* { dg-final { scan-assembler "vcmpgtsw" } } */ + +/* Verify a statement in the GCC Manual that vector type specifiers can + omit "signed" or "unsigned". The default is the default signedness + of the base type, which differs depending on the ABI. */ + +#include + +extern vector char vc1, vc2; +extern vector short vs1, vs2; +extern vector int vi1, vi2; + +int signedness (void) +{ + return vec_all_le (vc1, vc2) + && vec_all_le (vs1, vs2) + && vec_all_le (vi1, vi2); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-18.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c (revision 322) @@ -0,0 +1,152 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7 -ffast-math" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ +/* { dg-final { scan-assembler "xvsqrtsp" } } */ +/* { dg-final { scan-assembler "xvcpsgnsp" } } */ +/* { dg-final { scan-assembler "xvrspim" } } */ +/* { dg-final { scan-assembler "xvrspip" } } */ +/* { dg-final { scan-assembler "xvrspiz" } } */ +/* { dg-final { scan-assembler "xvrspic" } } */ +/* { dg-final { scan-assembler "xvrspi " } } */ + +#ifndef SIZE +#define SIZE 1024 +#endif + +float a[SIZE] __attribute__((__aligned__(32))); +float b[SIZE] __attribute__((__aligned__(32))); +float c[SIZE] __attribute__((__aligned__(32))); +float d[SIZE] __attribute__((__aligned__(32))); +float e[SIZE] __attribute__((__aligned__(32))); + +void +vector_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] + c[i]; +} + +void +vector_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] - c[i]; +} + +void +vector_multiply (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] * c[i]; +} + +void +vector_multiply_add (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) + d[i]; +} + +void +vector_multiply_subtract (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = (b[i] * c[i]) - d[i]; +} + +void +vector_divide (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = b[i] / c[i]; +} + +extern float sqrtf (float); +extern float floorf (float); +extern float ceilf (float); +extern float truncf (float); +extern float nearbyintf (float); +extern float rintf (float); +extern float copysignf (float, float); + +void +vector_sqrt (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = sqrtf (b[i]); +} + +void +vector_floor (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = floorf (b[i]); +} + +void +vector_ceil (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = ceilf (b[i]); +} + +void +vector_trunc (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = truncf (b[i]); +} + +void +vector_nearbyint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = nearbyintf (b[i]); +} + +void +vector_rint (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = rintf (b[i]); +} + +void +vector_copysign (void) +{ + int i; + + for (i = 0; i < SIZE; i++) + a[i] = copysignf (b[i], c[i]); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c (revision 322) @@ -0,0 +1,18 @@ +/* Test generation of dlmzb for strlen on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "dlmzb\\. " } } */ + +typedef __SIZE_TYPE__ size_t; + +size_t strlen(const char *); + +size_t +strlen8(const long long *s) +{ + return strlen((const char *)s); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-dlmzb-strlen-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c (revision 322) @@ -0,0 +1,403 @@ +/* { dg-do run { target { { powerpc*-*-linux* && lp64 } && powerpc_altivec_ok } } } */ +/* { dg-options "-O2 -fprofile -mprofile-kernel -maltivec -mabi=altivec" } */ +#include +#include +#include +#include + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +void __attribute__((no_instrument_function)) +sig_ill_handler (int sig) +{ + exit(0); +} + +extern void abort (void); + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; + long pad; + vector int vrs[12]; +} reg_parms_t; + +reg_parms_t gparms; + +/* _mcount call is done on Linux ppc64 early in the prologue. + my_mcount will provide a entry point _mcount, + which will save all register to gparms. + Note that _mcount need to restore lr to original value, + therefor use ctr to return. +*/ + +void __attribute__((no_instrument_function)) +my_mcount() +{ + asm volatile (".type _mcount,@function\n\t" + ".globl _mcount\n\t" + "_mcount:\n\t" + "mflr 0\n\t" + "mtctr 0\n\t" + "ld 0,16(1)\n\t" + "mtlr 0\n\t" + "ld 11,gparms@got(2)\n\t" + "std 3,0(11)\n\t" + "std 4,8(11)\n\t" + "std 5,16(11)\n\t" + "std 6,24(11)\n\t" + "std 7,32(11)\n\t" + "std 8,40(11)\n\t" + "std 9,48(11)\n\t" + "std 10,56(11)\n\t" + "stfd 1,64(11)\n\t" + "stfd 2,72(11)\n\t" + "stfd 3,80(11)\n\t" + "stfd 4,88(11)\n\t" + "stfd 5,96(11)\n\t" + "stfd 6,104(11)\n\t" + "stfd 7,112(11)\n\t" + "stfd 8,120(11)\n\t" + "stfd 9,128(11)\n\t" + "stfd 10,136(11)\n\t" + "stfd 11,144(11)\n\t" + "stfd 12,152(11)\n\t" + "stfd 13,160(11)\n\t" + "li 3,176\n\t" + "stvx 2,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 3,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 4,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 5,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 6,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 7,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 8,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 9,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 10,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 11,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 12,3,11\n\t" + "addi 3,3,16\n\t" + "stvx 13,3,11\n\t" + "ld 3,0(11)\n\t" + "bctr"); +} + +/* Stackframe structure relevant for parameter passing. */ +typedef union +{ + double d; + unsigned long l; + unsigned int i[2]; +} parm_t; + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + parm_t slot[100]; +} stack_frame_t; + +typedef union +{ + unsigned int i[4]; + unsigned long l[2]; + vector int v; +} vector_int_t; + +/* Paramter passing. + s : gpr 3 + v : vpr 2 + i : gpr 7 +*/ +void __attribute__ ((noinline)) +fcvi (char *s, vector int v, int i) +{ + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if ((long) i != lparms.gprs[4]) + abort(); +} +/* Paramter passing. + s : gpr 3 + v : vpr 2 + w : vpr 3 +*/ + +void __attribute__ ((noinline)) +fcvv (char *s, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + v : vpr 2 + w : vpr 3 +*/ +void __attribute__ ((noinline)) +fcivv (char *s, int i, vector int v, vector int w) +{ + vector int a, c = {6, 8, 10, 12}; + reg_parms_t lparms = gparms; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); +} + +/* Paramter passing. + s : gpr 3 + v : slot 2-3 + w : slot 4-5 +*/ + +void __attribute__ ((noinline)) +fcevv (char *s, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, s); + + if (s != (char *) lparms.gprs[0]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + /* Go back one frame. */ + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[2].l != 0x100000002ULL + || sp->slot[4].l != 0x500000006ULL) + abort(); +} + +/* Paramter passing. + s : gpr 3 + i : gpr 4 + j : gpr 5 + v : slot 4-5 + w : slot 6-7 +*/ +void __attribute__ ((noinline)) +fciievv (char *s, int i, int j, ...) +{ + vector int a, c = {6, 8, 10, 12}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, j); + + if (s != (char *) lparms.gprs[0]) + abort(); + + if ((long) i != lparms.gprs[1]) + abort(); + + if ((long) j != lparms.gprs[2]) + abort(); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + a = vec_add (v,w); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +void __attribute__ ((noinline)) +fcvevv (char *s, vector int x, ...) +{ + vector int a, c = {7, 10, 13, 16}; + vector int v,w; + stack_frame_t *sp; + reg_parms_t lparms = gparms; + va_list arg; + + va_start (arg, x); + + v = va_arg(arg, vector int); + w = va_arg(arg, vector int); + + a = vec_add (v,w); + a = vec_add (a, x); + + if (!vec_all_eq (a, c)) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[4].l != 0x100000002ULL + || sp->slot[6].l != 0x500000006ULL) + abort(); +} + +int __attribute__((no_instrument_function, noinline)) +main1() +{ + char *s = "vv"; + vector int v = {1, 2, 3, 4}; + vector int w = {5, 6, 7, 8}; + + fcvi (s, v, 2); + fcvv (s, v, w); + fcivv (s, 1, v, w); + fcevv (s, v, w); + fciievv (s, 1, 2, v, w); + fcvevv (s, v, v, w); + return 0; +} + +int __attribute__((no_instrument_function)) +main() +{ + /* Exit on systems without altivec. */ + signal (SIGILL, sig_ill_handler); + /* Altivec instruction, 'vor %v0,%v0,%v0'. */ + asm volatile (".long 0x10000484"); + signal (SIGILL, SIG_DFL); + + return main1 (); +} + +/* Paramter passing. + Function called with no prototype. + s : gpr 3 + v : vpr 2 gpr 5-6 + w : vpr 3 gpr 7-8 + x : vpr 4 gpr 9-10 + y : vpr 5 slot 8-9 +*/ +void +fnp_cvvvv (char *s, vector int v, vector int w, + vector int x, vector int y) +{ + vector int a, c = {12, 16, 20, 24}; + reg_parms_t lparms = gparms; + stack_frame_t *sp; + vector_int_t v0, v1, v2, v3; + + if (s != (char *) lparms.gprs[0]) + abort(); + + if (!vec_all_eq (v, lparms.vrs[0])) + abort (); + + if (!vec_all_eq (w, lparms.vrs[1])) + abort (); + + if (!vec_all_eq (x, lparms.vrs[2])) + abort (); + + if (!vec_all_eq (y, lparms.vrs[3])) + abort (); + + a = vec_add (v,w); + a = vec_add (a,x); + a = vec_add (a,y); + + if (!vec_all_eq (a, c)) + abort (); + + v0.v = lparms.vrs[0]; + v1.v = lparms.vrs[1]; + v2.v = lparms.vrs[2]; + v3.v = lparms.vrs[3]; + + if (v0.l[0] != lparms.gprs[2]) + abort (); + + if (v0.l[1] != lparms.gprs[3]) + abort (); + + if (v1.l[0] != lparms.gprs[4]) + abort (); + + if (v1.l[1] != lparms.gprs[5]) + abort (); + + if (v2.l[0] != lparms.gprs[6]) + abort (); + + if (v2.l[1] != lparms.gprs[7]) + abort (); + + sp = __builtin_frame_address(0); + sp = sp->backchain; + + if (sp->slot[8].l != v3.l[0]) + abort (); + + if (sp->slot[9].l != v3.l[1]) + abort (); +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c (revision 322) @@ -0,0 +1,36 @@ +/* { dg-require-effective-target stdint_types } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-options "-O2 -mcpu=power7" } */ + +/* This is a clone of gcc-dg/optimize-bswapdi-1.c, redone to use load and stores + to test whether ldbrx/stdbrx is generated for power7. */ + +#include +#define __const_swab64(x) ((uint64_t)( \ + (((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \ + (((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \ + (((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \ + (((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) << 8) | \ + (((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >> 8) | \ + (((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \ + (((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \ + (((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56))) + + +/* This byte swap implementation is used by the Linux kernel and the + GNU C library. */ + +uint64_t +swap64_load (uint64_t *in) +{ + return __const_swab64 (*in); +} + +void +swap64_store (uint64_t *out, uint64_t in) +{ + *out = __const_swab64 (in); +} + +/* { dg-final { scan-assembler "ldbrx" } } */ +/* { dg-final { scan-assembler "stdbrx" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/optimize-bswapdi-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-5.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-5.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-5.c (revision 322) @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#define vector __attribute__((vector_size(16))) + +void foo (const unsigned long x, + vector signed int a, vector signed int b) +{ + unsigned char d[64]; + + __builtin_altivec_stvewx (b, 0, d); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20020118-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20020118-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20020118-1.c (revision 322) @@ -0,0 +1,19 @@ +/* { dg-do run { target powerpc*-*-* } }*/ +/* VxWorks only guarantees 64 bits of alignment (STACK_BOUNDARY == 64). */ +/* { dg-skip-if "" { "powerpc*-*-vxworks*" } { "*" } { "" } } */ + +/* Test local alignment. Test new target macro STARTING_FRAME_PHASE. */ +/* Origin: Aldy Hernandez . */ + +extern void abort(void); + +int main () +{ + int darisa[4] __attribute__((aligned(16))) ; + int *stephanie = (int *) darisa; + + if ((unsigned long) stephanie % 16 != 0) + abort (); + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20020118-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr39457.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr39457.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr39457.c (revision 322) @@ -0,0 +1,56 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-options "-O2 -mminimal-toc" } */ + +/* PR 39457 -- fix breakage because the compiler ran out of registers and + wanted to stash a floating point value to the LR/CTR register. */ + +/* -O2 -m64 -mminimal-toc */ +typedef struct { void *s; } S; +typedef void (*T1) (void); +typedef void (*T2) (void *, void *, int, void *); +char *fn1 (const char *, ...); +void *fn2 (void); +int fn3 (char *, int); +int fn4 (const void *); +int fn5 (const void *); +long fn6 (void) __attribute__ ((__const__)); +int fn7 (void *, void *, void *); +void *fn8 (void *, long); +void *fn9 (void *, long, const char *, ...); +void *fn10 (void *); +long fn11 (void) __attribute__ ((__const__)); +long fn12 (void *, const char *, T1, T2, void *); +void *fn13 (void *); +long fn14 (void) __attribute__ ((__const__)); +extern void *v1; +extern char *v2; +extern int v3; + +void +foo (void *x, char *z) +{ + void *i1, *i2; + int y; + if (v1) + return; + v1 = fn9 (fn10 (fn2 ()), fn6 (), "x", 0., "y", 0., 0); + y = 520 - (520 - fn4 (x)) / 2; + fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", fn8 (v1, fn14 ()), "x", 18.0, + "y", 16.0, "wid", 80.0, "hi", 500.0, 0); + fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 80.0, "y2", + 500.0, "f", fn3 ("fff", 0x0D0DFA00), 0); + fn13 (((S *) fn8 (v1, fn6 ()))->s); + fn12 (fn8 (v1, fn11 ()), "ev", (T1) fn7, 0, fn8 (v1, fn6 ())); + fn9 (fn8 (v1, fn6 ()), fn6 (), "wig", + fn8 (v1, fn14 ()), "x", 111.0, "y", 14.0, "wid", 774.0, "hi", + 500.0, 0); + v1 = fn9 (fn10 (v1), fn6 (), "x1", 0., "y1", 0., "x2", 774.0, "y2", + 500.0, "f", fn3 ("gc", 0x0D0DFA00), 0); + fn1 (z, 0); + i1 = fn9 (fn8 (v1, fn6 ()), fn6 (), "pixbuf", x, "x", + 800 - fn5 (x) / 2, "y", y - fn4 (x), 0); + fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, "/ok/"); + fn12 (fn8 (i1, fn11 ()), "ev", (T1) fn7, 0, 0); + i2 = fn9 (fn8 (v1, fn6 ()), fn6 (), "txt", "OK", "fnt", v2, "x", + 800, "y", y - fn4 (x) + 15, "ar", 0, "f", v3, 0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr39457.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-dd.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-dd.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-dd.c (revision 322) @@ -0,0 +1,33 @@ +/* Test generation of DFP instructions for POWER6. */ +/* Origin: Janis Johnson */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -mcpu=power6" } */ + +/* { dg-final { scan-assembler "dadd" } } */ +/* { dg-final { scan-assembler "ddiv" } } */ +/* { dg-final { scan-assembler "dmul" } } */ +/* { dg-final { scan-assembler "dsub" } } */ +/* { dg-final { scan-assembler-times "dcmpu" 6 } } */ +/* { dg-final { scan-assembler-times "dctfix" 2 } } */ +/* { dg-final { scan-assembler-times "drintn" 2 } } */ +/* { dg-final { scan-assembler-times "dcffixq" 2 } } */ + +extern _Decimal64 a, b, c; +extern int result; +extern int si; +extern long long di; + +void add (void) { a = b + c; } +void div (void) { a = b / c; } +void mul (void) { a = b * c; } +void sub (void) { a = b - c; } +void eq (void) { result = a == b; } +void ne (void) { result = a != b; } +void lt (void) { result = a < b; } +void le (void) { result = a <= b; } +void gt (void) { result = a > b; } +void ge (void) { result = a >= b; } +void ddsi (void) { si = a; } +void dddi (void) { di = a; } +void sidd (void) { a = si; } +void didd (void) { a = di; }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-dd.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of mullhwu. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mullhwu\\. " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mullhwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c (revision 322) @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Check that "volatile" type qualifier is propagated to vector type. */ + +#include + +vector float *f (volatile vector float *a) +{ + return a; /* { dg-warning "discards qualifiers" } */ +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-volatile.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c (revision 322) @@ -0,0 +1,21 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w -mhard-float" } */ +/* This used to ICE as the peephole was not checking to see + if the register is a floating point one (I think this cannot + happen in real life except in this example). */ + +register volatile double t1 __asm__("r14"); +register volatile double t2 __asm__("r15"); +register volatile double t3 __asm__("r16"), t4 __asm__("r17"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-8.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-8.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-8.c (revision 322) @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include + +static float out[2] __attribute__ ((aligned (8))); +void +test_api (float x) +{ + vector float c = {x, x}; + vector float b = {60.0, 88.0}; + vector float a; + + a = paired_sub (b, c); + paired_stx (a, 0, out); +} + + +int main () +{ + test_api (6); + return (0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test generation of mullhw on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-27.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-27.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-27.c (revision 322) @@ -0,0 +1,32 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#define f0() void x0 (vector float x) { } +f0 () + +#define f1(type) void x1##type (vector type x) { } +f1 (float) + +#define f2(v, type) void x2##type (v type x) { } +f2 (vector, float) + +#define f3(type) void x3##type (vector bool type x) { } +f3 (int) + +#define f4(v, type) void x4##type (v bool type x) { } +f4 (vector, int) + +#define f5(b, type) void x5##type (vector b type x) { } +f5 (bool, int) + +#define f6(v, b, type) void x6##type (v b type x) { } +f6 (vector, bool, int) + +#define f7(v, b, type) void x7##type (v type b x) { } +f7 (vector, bool, int) + +int vector = 6; + +#define v1(v) int x8 (int v) { return v; } +v1(vector)

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-27.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c (revision 322) @@ -0,0 +1,14 @@ +/* Test generation of maclhw on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-td.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-td.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-td.c (revision 322) @@ -0,0 +1,33 @@ +/* Test generation of DFP instructions for POWER6. */ +/* Origin: Janis Johnson */ +/* { dg-do compile { target { powerpc*-*-linux* && powerpc_fprs } } } */ +/* { dg-options "-std=gnu99 -mcpu=power6" } */ + +/* { dg-final { scan-assembler "daddq" } } */ +/* { dg-final { scan-assembler "ddivq" } } */ +/* { dg-final { scan-assembler "dmulq" } } */ +/* { dg-final { scan-assembler "dsubq" } } */ +/* { dg-final { scan-assembler-times "dcmpuq" 6 } } */ +/* { dg-final { scan-assembler-times "dctfixq" 2 } } */ +/* { dg-final { scan-assembler-times "drintnq" 2 } } */ +/* { dg-final { scan-assembler-times "dcffixq" 2 } } */ + +extern _Decimal128 a, b, c; +extern int result; +extern int si; +extern long long di; + +void add (void) { a = b + c; } +void div (void) { a = b / c; } +void mul (void) { a = b * c; } +void sub (void) { a = b - c; } +void eq (void) { result = a == b; } +void ne (void) { result = a != b; } +void lt (void) { result = a < b; } +void le (void) { result = a <= b; } +void gt (void) { result = a > b; } +void ge (void) { result = a >= b; } +void tdsi (void) { si = a; } +void tddi (void) { di = a; } +void sitd (void) { a = si; } +void ditd (void) { a = di; }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/dfp-td.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of nmacchw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "nmacchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a -= (short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-nmacchw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c (revision 322) @@ -0,0 +1,142 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvcmpeqdp." } } */ +/* { dg-final { scan-assembler "xvcmpgtdp." } } */ +/* { dg-final { scan-assembler "xvcmpgedp." } } */ +/* { dg-final { scan-assembler "xvcmpeqsp." } } */ +/* { dg-final { scan-assembler "xvcmpgtsp." } } */ +/* { dg-final { scan-assembler "xvcmpgesp." } } */ +/* { dg-final { scan-assembler "vcmpbfp." } } */ +/* { dg-final { scan-assembler "vcmpequb." } } */ +/* { dg-final { scan-assembler "vcmpequh." } } */ +/* { dg-final { scan-assembler "vcmpequw." } } */ +/* { dg-final { scan-assembler "vcmpgtub." } } */ +/* { dg-final { scan-assembler "vcmpgtuh." } } */ +/* { dg-final { scan-assembler "vcmpgtuw." } } */ +/* { dg-final { scan-assembler "vcmpgtsb." } } */ +/* { dg-final { scan-assembler "vcmpgtsh." } } */ +/* { dg-final { scan-assembler "vcmpgtsw." } } */ +/* { dg-final { scan-assembler-not "vcmpeqfp" } } */ +/* { dg-final { scan-assembler-not "vcmpgtfp" } } */ +/* { dg-final { scan-assembler-not "vcmpgefp" } } */ + +/* check that Altivec builtins generate VSX if -mvsx. */ + +#include + +int *v16qi_s (vector signed char *a, vector signed char *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v16qi_u (vector unsigned char *a, vector unsigned char *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v8hi_s (vector short *a, vector short *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v8hi_u (vector unsigned short *a, vector unsigned short *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4si_s (vector int *a, vector int *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4si_u (vector unsigned int *a, vector unsigned int *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 2; + + return p; +} + +int *v4sf (vector float *a, vector float *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 3; + + if (vec_all_in (*a, *b)) /* veccmpbfp. */ + *p++ = 4; + + return p; +} + +int *v2df (vector double *a, vector double *b, int *p) +{ + if (vec_all_eq (*a, *b)) + *p++ = 1; + + if (vec_all_gt (*a, *b)) + *p++ = 2; + + if (vec_all_ge (*a, *b)) + *p++ = 3; + + return p; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c (revision 322) @@ -0,0 +1,6 @@ +/* { dg-do compile { target powerpc_fprs } } */ +/* { dg-options "-O2 -fpic" } */ +double foo (double x) { + return x + 1.75; +} +/* { dg-final { scan-assembler "lfs" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/compress-float-ppc-pic.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c (revision 322) @@ -0,0 +1,40 @@ +/* { dg-do compile { target powerpc*-apple-darwin* } } */ +/* { dg-options "-S" } */ + +typedef void PF (void); + +static void f(void) { +} + +void f1(void) { +} + +extern void f2(void) { +} + +static void f3(void); + +void pe(void) +{ +} + +PF* g (void) { f(); return f; } +PF* x (void) { return f1; } +PF* y (void) { f2(); return f2; } +PF* z (void) { return f3; } +PF* w (void) { pe(); return pe; } + +int main() +{ + (*g())(); + (*x())(); + (*y())(); + (*z())(); + (*w())(); + return 0; +} + +void f3(void) { +} + +/* { dg-final { scan-assembler-not "non_lazy_ptr" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/non-lazy-ptr-test.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of mulchwu. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchwu\\. " } } */ + +int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr35907.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr35907.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr35907.c (revision 322) @@ -0,0 +1,57 @@ +/* PR target/35907 */ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +#define vector __attribute__((vector_size (16))) +union +{ + vector int k; + int c[16]; +} u, v, w; +vector int m; + +void __attribute__((noinline)) +bar (void *i, vector int j) +{ + asm volatile ("" : : "r" (i), "r" (&j) : "memory"); +} + +int __attribute__((noinline)) +foo (int i, vector int j) +{ + char *p = __builtin_alloca (64 + i); + m += u.k; + v.k = m; + w.k = j; + if (__builtin_memcmp (&v.c, &w.c, 16) != 0) + __builtin_abort (); + j += u.k; + bar (p, j); + j += u.k; + bar (p, j); + return 0; +} + +void +test (void) +{ + vector int l; + int i; + for (i = 0; i < 4; i++) + u.c[i] = i; + l = u.k; + if (foo (64, l)) + __builtin_abort (); + l += u.k; + if (foo (64, l)) + __builtin_abort (); +} + +int +main () +{ + test (); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr35907.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c (revision 322) @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include +#include + +#define N 256 + +__attribute__ ((noinline)) +void bar (double *pd, double *pa, double *pb, double *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, double * __restrict__ pd, double * __restrict__ pa, double * __restrict__ pb, double * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + double a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + double b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + double c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rotate.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rotate.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rotate.c (revision 322) @@ -0,0 +1,6 @@ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "slwi" } } */ +unsigned int foo (unsigned int x) +{ + return ((x >> 16) & 0xffff) | ((x & 0xffff) << 16); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rotate.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-3.c (revision 322) @@ -0,0 +1,15 @@ +/* { dg-do compile { target { ilp32 } } } */ +/* { dg-options "-O2" } */ +struct Q +{ + long x:20; + long y:4; + long z:8; +}b; +/* This should generate a single rl[w]imi. */ +void rotins (unsigned int x) +{ + b.y = (x<<12) | (x>>20); +} + +/* { dg-final { scan-assembler-not "inm" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/20050603-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of mulchw on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchw " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of maclhwu on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-11.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-11.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-11.c (revision 322) @@ -0,0 +1,59 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec" } */ +/* { dg-final { scan-assembler-not "lvx" } } */ +#include + +void foo (vector int); +void foo_s (vector short); +void foo_c (vector char); + +/* All constants should be loaded into vector register without + load from memory. */ +void +bar (void) +{ + foo ((vector int) {0, 0, 0, 0}); + foo ((vector int) {1, 1, 1, 1}); + foo ((vector int) {15, 15, 15, 15}); + foo ((vector int) {-16, -16, -16, -16}); + foo ((vector int) {0x10001, 0x10001, 0x10001, 0x10001}); + foo ((vector int) {0xf000f, 0xf000f, 0xf000f, 0xf000f}); + foo ((vector int) {0xfff0fff0, 0xfff0fff0, 0xfff0fff0, 0xfff0fff0}); + foo ((vector int) {0x1010101, 0x1010101, 0x1010101, 0x1010101}); + foo ((vector int) {0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f, 0xf0f0f0f}); + foo ((vector int) {0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0, 0xf0f0f0f0}); + foo ((vector int) {0x10101010, 0x10101010, 0x10101010, 0x10101010}); + foo ((vector int) {0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e, 0x1e1e1e1e}); + foo ((vector int) {0x100010, 0x100010, 0x100010, 0x100010}); + foo ((vector int) {0x1e001e, 0x1e001e, 0x1e001e, 0x1e001e}); + foo ((vector int) {0x10, 0x10, 0x10, 0x10}); + foo ((vector int) {0x1e, 0x1e, 0x1e, 0x1e}); + + foo_s ((vector short int) {0, 0, 0, 0, 0, 0, 0, 0}); + foo_s ((vector short int) {1, 1, 1, 1, 1, 1, 1, 1}); + foo_s ((vector short int) {15, 15, 15, 15, 15, 15, 15, 15}); + foo_s ((vector short int) {-16, -16, -16, -16, -16, -16, -16, -16}); + foo_s ((vector short int) {0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0, + 0xf0f0, 0xf0f0, 0xf0f0, 0xf0f0}); + foo_s ((vector short int) {0xf0f, 0xf0f, 0xf0f, 0xf0f, + 0xf0f, 0xf0f, 0xf0f, 0xf0f}); + foo_s ((vector short int) {0x1010, 0x1010, 0x1010, 0x1010, + 0x1010, 0x1010, 0x1010, 0x1010}); + foo_s ((vector short int) {0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e, + 0x1e1e, 0x1e1e, 0x1e1e, 0x1e1e}); + + foo_c ((vector char) {0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0}); + foo_c ((vector char) {1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 1}); + foo_c ((vector char) {15, 15, 15, 15, 15, 15, 15, 15, + 15, 15, 15, 15, 15, 15, 15, 15}); + foo_c ((vector char) {-16, -16, -16, -16, -16, -16, -16, -16, + -16, -16, -16, -16, -16, -16, -16, -16}); + foo_c ((vector char) {16, 16, 16, 16, 16, 16, 16, 16, + 16, 16, 16, 16, 16, 16, 16, 16}); + foo_c ((vector char) {30, 30, 30, 30, 30, 30, 30, 30, + 30, 30, 30, 30, 30, 30, 30, 30}); + +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-11.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of macchw on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchw " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c (revision 322) @@ -0,0 +1,28 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +/* { dg-final { scan-assembler-times "vor" 2 } } */ +#include + +/* Make sure that lvlx and lvrx are not combined into one insn and + we still get a vor. */ + +vector unsigned char +lvx_float (long off, float *p) +{ + vector unsigned char l, r; + + l = (vector unsigned char) vec_lvlx (off, p); + r = (vector unsigned char) vec_lvrx (off, p); + return vec_or(l, r); +} + +vector unsigned char +lvxl_float (long off, float *p) +{ + vector unsigned char l, r; + + l = (vector unsigned char) vec_lvlxl (off, p); + r = (vector unsigned char) vec_lvrxl (off, p); + return vec_or(l, r); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of mulhhw. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c (revision 322) @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O -maltivec" } */ +/* { dg-final { scan-assembler "stvx" } } */ + +#include + +void foo(void) +{ + int x[8] __attribute__((aligned(128))); + memset (x, 0, sizeof (x)); + bar (x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-vector-memset.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of machhw. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "machhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (b >> 16) * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-machhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ +struct f +{ + int i; + long long ll; +}; + +int f[sizeof(struct f)!=12?-1:1];

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-19.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-19.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-19.c (revision 322) @@ -0,0 +1,13 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ +/* { dg-final { scan-assembler "dst" } } */ + +void foo ( char* image ) +{ + while ( 1 ) + { + __builtin_altivec_dst( (void *)( (long)image & ~0x0f ), 0, 0 ); + image += 48; + } +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-19.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c (revision 322) @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvadddp" } } */ +/* { dg-final { scan-assembler "xvsubdp" } } */ +/* { dg-final { scan-assembler "xvmuldp" } } */ +/* { dg-final { scan-assembler "xvdivdp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ + +__vector double a, b, c, d; + +void +vector_add (void) +{ + a = b + c; +} + +void +vector_subtract (void) +{ + a = b - c; +} + +void +vector_multiply (void) +{ + a = b * c; +} + +void +vector_multiply_add (void) +{ + a = (b * c) + d; +} + +void +vector_multiply_subtract (void) +{ + a = (b * c) - d; +} + +void +vector_divide (void) +{ + a = b / c; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c (revision 322) @@ -0,0 +1,29 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-options "-Wall" } */ +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ABI. */ + +typedef int __attribute__((vector_size(16))) v4si; +typedef int __attribute__((vector_size(8))) v2si; + +v4si +f(v4si v) +{ /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + return v; +} + +v2si +g(v2si v) +{ + return v; +} + +int +main() +{ + v4si v = { 1, 2, 3, 4 }; + v2si w = { 5, 6 }; + v = f (v); /* { dg-error "altivec instructions are disabled" "PR18631" { xfail *-*-* } } */ + w = g (w); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-3.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-6.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-6.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-6.c (revision 322) @@ -0,0 +1,66 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O0 -Wall" } */ + +#include + +/* These denote "generic" GCC vectors. */ +static int __attribute__((vector_size(16))) x, y, z; + +static vector signed int i,j; +static vector signed short s,t; +static vector signed char c,d; +static vector float f,g; + +static vector unsigned char uc; + +static vector signed int *pi; + +static int int1, int2; + +void +b() +{ + z = vec_add (x, y); + + /* Make sure the predicates accept correct argument types. */ + + int1 = vec_all_in (f, g); + int1 = vec_all_ge (f, g); + int1 = vec_all_eq (c, d); + int1 = vec_all_ne (s, t); + int1 = vec_any_eq (i, j); + int1 = vec_any_ge (f, g); + int1 = vec_all_ngt (f, g); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + int1 = vec_any_ge (c, d); + int1 = vec_any_ge (s, t); + int1 = vec_any_ge (i, j); + + vec_mtvscr (i); + vec_dssall (); + s = (vector signed short) vec_mfvscr (); + vec_dss (3); + + vec_dst (pi, int1 + int2, 3); + vec_dstst (pi, int1 + int2, 3); + vec_dststt (pi, int1 + int2, 3); + vec_dstt (pi, int1 + int2, 3); + + uc = (vector unsigned char) vec_lvsl (int1 + 69, (signed int *) pi); + uc = (vector unsigned char) vec_lvsr (int1 + 69, (signed int *) pi); + + c = vec_lde (int1, (signed char *) pi); + s = vec_lde (int1, (signed short *) pi); + i = vec_lde (int1, (signed int *) pi); + i = vec_ldl (int1, pi); + i = vec_ld (int1, pi); + + vec_st (i, int2, pi); + vec_ste (c, int2, (signed char *) pi); + vec_ste (s, int2, (signed short *) pi); + vec_ste (i, int2, (signed int *) pi); + vec_stl (i, int2, pi); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-6.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c (revision 322) @@ -0,0 +1,318 @@ +/* { dg-do run { target { powerpc64-*-* && { lp64 && dfprt } } } } */ +/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC64 ELF ABI for decimal float values. */ + +extern void abort (void); +int failcnt = 0; + +/* Support compiling the test to report individual failures; default is + to abort as soon as a check fails. */ +#ifdef DBG +#include +#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; } +#else +#define FAILURE abort (); +#endif + +typedef struct +{ + int pad; + _Decimal32 d; +} d32parm_t; + +typedef struct +{ + unsigned long gprs[8]; + double fprs[13]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Testcase could break on future gcc's, if parameter regs + are changed before this asm. */ + +#ifndef __MACH__ +#define save_parms(lparms) \ + asm volatile ("ld 11,gparms@got(2)\n\t" \ + "std 3,0(11)\n\t" \ + "std 4,8(11)\n\t" \ + "std 5,16(11)\n\t" \ + "std 6,24(11)\n\t" \ + "std 7,32(11)\n\t" \ + "std 8,40(11)\n\t" \ + "std 9,48(11)\n\t" \ + "std 10,56(11)\n\t" \ + "stfd 1,64(11)\n\t" \ + "stfd 2,72(11)\n\t" \ + "stfd 3,80(11)\n\t" \ + "stfd 4,88(11)\n\t" \ + "stfd 5,96(11)\n\t" \ + "stfd 6,104(11)\n\t" \ + "stfd 7,112(11)\n\t" \ + "stfd 8,120(11)\n\t" \ + "stfd 9,128(11)\n\t" \ + "stfd 10,136(11)\n\t" \ + "stfd 11,144(11)\n\t" \ + "stfd 12,152(11)\n\t" \ + "stfd 13,160(11)\n\t":::"11", "memory"); \ + lparms = gparms; +#else +#define save_parms(lparms) \ + asm volatile ("ld r11,gparms@got(r2)\n\t" \ + "std r3,0(r11)\n\t" \ + "std r4,8(r11)\n\t" \ + "std r5,16(r11)\n\t" \ + "std r6,24(r11)\n\t" \ + "std r7,32(r11)\n\t" \ + "std r8,40(r11)\n\t" \ + "std r9,48(r11)\n\t" \ + "std r10,56(r11)\n\t" \ + "stfd f1,64(r11)\n\t" \ + "stfd f2,72(r11)\n\t" \ + "stfd f3,80(r11)\n\t" \ + "stfd f4,88(r11)\n\t" \ + "stfd f5,96(r11)\n\t" \ + "stfd f6,104(r11)\n\t" \ + "stfd f7,112(r11)\n\t" \ + "stfd f8,120(r11)\n\t" \ + "stfd f9,128(r11)\n\t" \ + "stfd f10,136(r11)\n\t" \ + "stfd f11,144(r11)\n\t" \ + "stfd f12,152(r11)\n\t" \ + "stfd f13,160(r11)\n\t":::"r11", "memory"); \ + lparms = gparms; +#endif + +typedef struct sf +{ + struct sf *backchain; + long a1; + long a2; + long a3; + long a4; + long a5; + unsigned long slot[100]; +} stack_frame_t; + +/* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ +void __attribute__ ((noinline)) +func0 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + double a13, double a14, + _Decimal64 a15, _Decimal128 a16, _Decimal64 a17) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != lparms.fprs[0]) FAILURE + if (a2 != lparms.fprs[1]) FAILURE + if (a3 != lparms.fprs[2]) FAILURE + if (a4 != lparms.fprs[3]) FAILURE + if (a5 != lparms.fprs[4]) FAILURE + if (a6 != lparms.fprs[5]) FAILURE + if (a7 != lparms.fprs[6]) FAILURE + if (a8 != lparms.fprs[7]) FAILURE + if (a9 != lparms.fprs[8]) FAILURE + if (a10 != lparms.fprs[9]) FAILURE + if (a11 != lparms.fprs[10]) FAILURE + if (a12 != lparms.fprs[11]) FAILURE + if (a13 != lparms.fprs[12]) FAILURE + if (a14 != *(double *)&sp->slot[13]) FAILURE + if (a15 != *(_Decimal64 *)&sp->slot[14]) FAILURE + if (a16 != *(_Decimal128 *)&sp->slot[15]) FAILURE + if (a17 != *(_Decimal64 *)&sp->slot[17]) FAILURE +} + +void __attribute__ ((noinline)) +func1 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + double a13, _Decimal128 a14) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != lparms.fprs[0]) FAILURE + if (a2 != lparms.fprs[1]) FAILURE + if (a3 != lparms.fprs[2]) FAILURE + if (a4 != lparms.fprs[3]) FAILURE + if (a5 != lparms.fprs[4]) FAILURE + if (a6 != lparms.fprs[5]) FAILURE + if (a7 != lparms.fprs[6]) FAILURE + if (a8 != lparms.fprs[7]) FAILURE + if (a9 != lparms.fprs[8]) FAILURE + if (a10 != lparms.fprs[9]) FAILURE + if (a11 != lparms.fprs[10]) FAILURE + if (a12 != lparms.fprs[11]) FAILURE + if (a13 != lparms.fprs[12]) FAILURE + if (a14 != *(_Decimal128 *)&sp->slot[13]) FAILURE +} + +void __attribute__ ((noinline)) +func2 (double a1, double a2, double a3, double a4, double a5, double a6, + double a7, double a8, double a9, double a10, double a11, double a12, + _Decimal128 a13) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != lparms.fprs[0]) FAILURE + if (a2 != lparms.fprs[1]) FAILURE + if (a3 != lparms.fprs[2]) FAILURE + if (a4 != lparms.fprs[3]) FAILURE + if (a5 != lparms.fprs[4]) FAILURE + if (a6 != lparms.fprs[5]) FAILURE + if (a7 != lparms.fprs[6]) FAILURE + if (a8 != lparms.fprs[7]) FAILURE + if (a9 != lparms.fprs[8]) FAILURE + if (a10 != lparms.fprs[9]) FAILURE + if (a11 != lparms.fprs[10]) FAILURE + if (a12 != lparms.fprs[11]) FAILURE + if (a13 != *(_Decimal128 *)&sp->slot[12]) FAILURE +} + +void __attribute__ ((noinline)) +func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8, + _Decimal64 a9, _Decimal128 a10) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ + if (a6 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */ + if (a7 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */ + if (a8 != *(_Decimal128 *)&sp->slot[10]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[12]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[13]) FAILURE +} + +void __attribute__ ((noinline)) +func4 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ + if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ + if (a5 != *(_Decimal128 *)&lparms.fprs[9]) FAILURE /* f10 & f11 */ + if (a6 != *(_Decimal64 *)&lparms.fprs[11]) FAILURE /* f12 */ + if (a7 != *(_Decimal128 *)&sp->slot[9]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[11]) FAILURE +} + +void __attribute__ ((noinline)) +func5 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR or parameter slot. */ + if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */ + if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */ + if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */ + if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */ + if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ + if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */ + if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */ + if (a9 != ((d32parm_t *)&lparms.fprs[8])->d) FAILURE /* f9 */ + if (a10 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */ + if (a11 != ((d32parm_t *)&lparms.fprs[10])->d) FAILURE /* f11 */ + if (a12 != ((d32parm_t *)&lparms.fprs[11])->d) FAILURE /* f12 */ + if (a13 != ((d32parm_t *)&lparms.fprs[12])->d) FAILURE /* f13 */ + if (a14 != ((d32parm_t *)&sp->slot[13])->d) FAILURE + if (a15 != ((d32parm_t *)&sp->slot[14])->d) FAILURE + if (a16 != ((d32parm_t *)&sp->slot[15])->d) FAILURE +} + +void __attribute__ ((noinline)) +func6 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */ + if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */ + if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ + if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */ + if (a6 != *(_Decimal128 *)&lparms.fprs[7]) FAILURE /* f8 & f9 */ + if (a7 != ((d32parm_t *)&lparms.fprs[9])->d) FAILURE /* f10 */ + if (a8 != *(_Decimal64 *)&lparms.fprs[10]) FAILURE /* f11 */ + if (a9 != *(_Decimal128 *)&lparms.fprs[11]) FAILURE /* f12 & f13 */ + if (a10 != ((d32parm_t *)&sp->slot[12])->d) FAILURE + if (a11 != *(_Decimal64 *)&sp->slot[13]) FAILURE +} + +int +main (void) +{ + func0 (1.5, 2.5, 3.5, 4.5, 5.5, 6.5, 7.5, 8.5, 9.5, 10.5, 11.5, 12.5, 13.5, + 14.5, 15.2dd, 16.2dl, 17.2dd); + func1 (101.5, 102.5, 103.5, 104.5, 105.5, 106.5, 107.5, 108.5, 109.5, + 110.5, 111.5, 112.5, 113.5, 114.2dd); + func2 (201.5, 202.5, 203.5, 204.5, 205.5, 206.5, 207.5, 208.5, 209.5, + 210.5, 211.5, 212.5, 213.2dd); + func3 (301.2dd, 302.2dl, 303.2dd, 304.2dl, 305.2dd, 306.2dl, 307.2dd, + 308.2dl, 309.2dd, 310.2dl); + func4 (401.2dl, 402.2dd, 403.2dl, 404.2dd, 405.2dl, 406.2dd, 407.2dl, + 408.2dd); +#if 0 + /* _Decimal32 doesn't yet follow the ABI; enable this when it does. */ + func5 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, + 515.2df, 516.2df); + func6 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); +#endif + + if (failcnt != 0) + abort (); + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc64-abi-dfp-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of macchwu on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchwu " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c (revision 322) @@ -0,0 +1,15 @@ +/* Test generation of mulhhwu on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulhhwu " } } */ + +unsigned int +f(unsigned int b, unsigned int c) +{ + unsigned int a = (b >> 16) * (c >> 16); + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulhhwu-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c (revision 322) @@ -0,0 +1,35 @@ +/* { dg-do run { target powerpc*-*-linux* powerpc*-*-eabi* } } */ +/* { dg-options {} } */ + +/* Test stack pointer alignment against variable alloca. */ +/* Inspired by PR libgcj/10610. */ +/* Origin: Franz Sirl . */ + +extern void abort (void); +extern void exit (int); + +register unsigned long sp __asm__ ("r1"); + +void g (int * val __attribute__ ((unused))) +{ + if (sp & 0xf) + abort (); +} + +void f (int val) +{ + int *val1 = __builtin_alloca (val); + + g (val1); + return; +} + +int main (void) +{ + int i; + + for (i = 1; i < 32; i++) + f (i); + + exit (0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-stackalign-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c (revision 322) @@ -0,0 +1,605 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec -O2" } */ + +#include + +int printf(const char * , ...); +extern void abort(); + +void foo(char *bS, char *bS_edge, int field_MBAFF, int top){ + char intra[16] __attribute__ ((aligned(16))); + signed short mv_const[8] __attribute__((aligned(16))); + + vector signed short v_three, v_ref_mask00, v_ref_mask01, v_vec_maskv, v_vec_maskh; + vector unsigned char v_permv, v_permh, v_bS, v_bSh, v_bSv, v_cbp_maskv, v_cbp_maskvn, v_cbp_maskh, v_cbp_maskhn, v_intra_maskh, v_intra_maskv, v_intra_maskhn, v_intra_maskvn; + vector unsigned char tmp7, tmp8, tmp9, tmp10, v_c1, v_cbp1, v_cbp2, v_pocl, v_poch; + vector signed short v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, v10, v11, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6; + vector signed short idx0; + vector signed short tmp00, tmp01, tmp02, tmp03; + vector unsigned char v_zero = (vector unsigned char) {'a','b','c','d','e','f','g','h','i','j','k','l','m','n','o','p'}; + v_three = (vector signed short) vec_ld (0, (vector signed short *) mv_const); + + vector unsigned char v_coef_mask = vec_ld(0, (vector unsigned char *)mv_const); + vector unsigned char v_coef_mask_hi = vec_splat(v_coef_mask, 0); + vector unsigned char v_coef_mask_lo = vec_splat(v_coef_mask, 1); + v_coef_mask = vec_sld(v_coef_mask_hi, v_coef_mask_lo, 8); + vector unsigned char v_bit_mask = vec_sub(vec_splat_u8(7), vec_lvsl(0, (unsigned char *)0)); + v_bit_mask = vec_sld(vec_sld(v_bit_mask, v_bit_mask, 8), v_bit_mask, 8); + v_bit_mask = vec_sl(vec_splat_u8(1), v_bit_mask); + tmp5 = (vector signed short) vec_and(v_coef_mask, v_bit_mask); + + intra[0] = 1; + tmp8 = vec_ld (0, (vector unsigned char *) intra); + tmp9 = vec_ld (0, (vector unsigned char *) mv_const); + tmp10 = vec_ld (0, (vector unsigned char *) mv_const); + v_permv = vec_ld (0, (vector unsigned char *) mv_const); + v_permh = vec_ld (0, (vector unsigned char *) mv_const); + tmp6 = vec_ld (0, (vector signed short *) mv_const); + + tmp8 = vec_splat((vector unsigned char) tmp8, 0); + tmp9 = vec_splat((vector unsigned char) tmp9, 12); + tmp10 = vec_splat((vector unsigned char) tmp10, 12); + tmp9 = vec_sld ((vector unsigned char) tmp9,(vector unsigned char) tmp8, 12); + tmp10 = vec_sld ((vector unsigned char) tmp10, (vector unsigned char) tmp8, 12); + v_intra_maskv = vec_or (tmp9, tmp8); + v_intra_maskh = vec_or (tmp10, tmp8); + v_intra_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskv, (vector unsigned char) v_zero); + v_intra_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_intra_maskh, (vector unsigned char) v_zero); + + tmp9 = vec_lvsl (4 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permv); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskv = vec_or (v_cbp1, v_cbp2); + + tmp9 = vec_lvsl (12 + (top<<2), (unsigned char *) 0x0); + v_cbp1 = vec_perm ((vector unsigned char) tmp6, (vector unsigned char) tmp6, tmp9); + v_cbp2 = (vector unsigned char) vec_perm ((vector unsigned char) tmp5, (vector unsigned char) tmp5, (vector unsigned char) v_permh); + v_cbp1 = (vector unsigned char) vec_sld ((vector unsigned char) v_cbp1,(vector unsigned char) v_cbp2, 12); + v_cbp_maskh = vec_or (v_cbp1, v_cbp2); + + v_cbp_maskv = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskh = (vector unsigned char) vec_cmpgt ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + intra[0] =0; + intra[1] =1; + intra[2] =2; + intra[3] =3; + intra[4] =4; + intra[5] = 5; + intra[6] =6; + intra[7] =7; + intra[8] =8; + intra[9] =9; + intra[10] =9; + intra[11] =9; + intra[12] = 0xff; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v0 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v1 = vec_sld (v0, v0, 15); + v1 = (vector signed short) vec_pack (v1, v0); + + v2 = vec_sld (v1, v1, 2); + v3 = vec_sld (v1, v1, 10); + + v4 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v2); + v5 = (vector signed short) vec_cmpeq ((vector signed char) v1, (vector signed char) v3); + v6 = (vector signed short) vec_cmpeq ((vector signed char) v2, (vector signed char) v3); + } + else { + v4 = v5 = v6 = (vector signed short) vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (0, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v4); + tmp4 = vec_and (tmp4, v5); + tmp1 = vec_and (tmp1, v6); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + v0 = vec_ld (0, (vector signed short *) mv_const); + v1 = vec_ld (16, (vector signed short *) mv_const); + v4 = vec_ld (64, (vector signed short *) mv_const); + v5 = vec_ld (80, (vector signed short *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v8, + (vector unsigned char) v8, (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp0 = (vector signed short) vec_perm ((vector unsigned char) v9, (vector unsigned char) v9, + (vector unsigned char) {0,1,2,3,8,9,10,11,4,5,6,7,12,13,14,15}); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + v2 = vec_ld (32, (vector signed short *) mv_const); + v3 = vec_ld (48, (vector signed short *) mv_const); + v6 = vec_ld (96, (vector signed short *) mv_const); + v7 = vec_ld (112,(vector signed short *) mv_const); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v0, (vector signed int) v1); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergel ((vector signed int) v4, (vector signed int) v5); + tmp1 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v2, (vector signed int) v3); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v2, (vector signed int) v3); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp3 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp4 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp0 = (vector signed short) vec_mergeh ((vector signed int) v6, (vector signed int) v7); + tmp1 = (vector signed short) vec_mergel ((vector signed int) v6, (vector signed int) v7); + tmp2 = vec_sld (tmp1, tmp1, 8); + tmp5 = vec_sub (vec_max (tmp0, tmp1), vec_min (tmp0, tmp1)); + tmp6 = vec_sub (vec_max (tmp0, tmp2), vec_min (tmp0, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 12); + tmp6 = vec_sld (tmp4, tmp4, 12); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned short) tmp3, (vector unsigned short) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned int) tmp00, (vector unsigned int) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned int) tmp02, (vector unsigned int) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskv = vec_or (tmp0, tmp2); + v_vec_maskv = vec_or (v_vec_maskv, tmp3); + + intra[0] = 1; + intra[1] = 1; + intra[2] = 2; + intra[3] = 3; + intra[4] = 2; + intra[5] = 2; + intra[6] = 2; + intra[7] = 1; + intra[8] = 1; + intra[9] = 5; + intra[10] = 5; + intra[11] = 5; + + intra[13] = 0; + intra[14] = 0; + intra[15] = 0; + + idx0 = vec_ld (0, (signed short *) intra); + + v_c1 = (vector unsigned char) {'1','2','3','4','5','6','7','8','1','2','3','4','5','6','7','8'}; + + if (field_MBAFF){ + v8 = (vector signed short) vec_and ((vector unsigned char) idx0, v_c1); + idx0 = (vector signed short) vec_sra ((vector unsigned char) idx0, v_c1); + + v9 = vec_sld (v8, v8, 15); + v9 = (vector signed short) vec_pack (v9, v8); + + v10 = vec_sld (v9, v9, 2); + v11 = vec_sld (v9, v9, 10); + + v8 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v10); + v9 = (vector signed short) vec_cmpeq ((vector signed char) v9, (vector signed char) v11); + v10 = (vector signed short) vec_cmpeq ((vector signed char) v10, (vector signed char) v11); + } + else { + v8 = v9 = v10 = (vector signed short) vec_nor (v_zero, v_zero); + } + + tmp1 = (vector signed short) vec_sl ((vector unsigned char) idx0, v_c1); + +if (1){ + int m; + unsigned char toto2[16] __attribute__((aligned(16))); + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + + printf("\nv_zero\n"); + + vec_st (v_zero, 0, (unsigned char *) toto2); + for (m=0; m< 16; m++) {printf("%c ", toto2[m]);} + printf("\n"); +} + + v_c1 = vec_mergeh ((vector unsigned char) v_zero, v_c1); + tmp1 = (vector signed short) vec_add (tmp1, (vector signed short) v_c1); + +if (1){ + vector unsigned char vres = + (vector unsigned char){'a','1','b','2','c','3','d','4','e','5','f','6','g','7','h','8'}; + unsigned char toto2[16] __attribute__((aligned(16))); + int m; + + printf("vc1\n"); + vec_st(v_c1, 0, (unsigned char *) toto2); + for (m=0; m<16;m++) {printf("%c ", toto2[m]);} + printf("\n"); + if (!vec_all_eq (vres, v_c1)) + abort(); +} + + v_pocl = vec_ld (32, (vector unsigned char *) mv_const); + v_poch = vec_ld (48, (vector unsigned char *) mv_const); + tmp2 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + v_pocl = vec_ld (0, (vector unsigned char *) mv_const); + v_poch = vec_ld (16, (vector unsigned char *) mv_const); + + tmp1 = (vector signed short) vec_perm (v_pocl, v_poch, (vector unsigned char) tmp1); + + tmp1 = vec_sel (tmp1, tmp2, (vector unsigned short) {0xffff,0xffff,0,0,0,0,0,0}); + + + tmp3 = (vector signed short) vec_splat ((vector unsigned char) idx0, 12); + v_c1 = (vector unsigned char) vec_nor (v_zero, v_zero); + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) idx0, (vector signed char) v_c1); + tmp1 = vec_sel (tmp1, (vector signed short) tmp3, (vector unsigned short) tmp0); + + tmp2 = vec_sld (tmp1, tmp1, 15); + tmp1 = (vector signed short) vec_pack (tmp2, tmp1); + + + tmp2 = vec_sld (tmp1, tmp1, 2); + tmp3 = vec_sld (tmp1, tmp1, 10); + + tmp0 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp2); + tmp4 = (vector signed short) vec_cmpeq ((vector signed char) tmp1, (vector signed char) tmp3); + tmp1 = (vector signed short) vec_cmpeq ((vector signed char) tmp2, (vector signed char) tmp3); + tmp0 = vec_and (tmp0, v8); + tmp4 = vec_and (tmp4, v9); + tmp1 = vec_and (tmp1, v10); + tmp2 = vec_sld ((vector signed short) tmp0, (vector signed short) tmp0, 8); + tmp3 = vec_sld ((vector signed short) tmp4, (vector signed short) tmp4, 8); + tmp5 = vec_sld ((vector signed short) tmp1, (vector signed short) tmp1, 8); + tmp0 = vec_and (tmp0, tmp2); + tmp4 = vec_and (tmp4, tmp3); + tmp1 = vec_and (tmp1, tmp5); + v_ref_mask00 = vec_mergeh ((vector signed short) tmp0, (vector signed short) v_c1); + v_ref_mask01 = vec_mergeh ((vector signed short) tmp4, (vector signed short) tmp1); + v_ref_mask00 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask00, (vector unsigned char) v_ref_mask00); + v_ref_mask01 = (vector signed short) vec_mergeh ((vector unsigned char) v_ref_mask01, (vector unsigned char) v_ref_mask01); + + + v_permv= vec_ld (0, (vector unsigned char *) mv_const); + v8 = vec_ld (0, (vector signed short *) mv_const); + v9 = vec_ld (16, (vector signed short *) mv_const); + tmp2 = vec_perm (v0, v0, v_permv); + tmp3 = vec_sub (vec_max (v8, v0), vec_min (v8, v0)); + tmp4 = vec_sub (vec_max (v8, tmp2), vec_min (v8, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v2, v2, v_permv); + tmp5 = vec_sub (vec_max (v9, v2), vec_min (v9, v2)); + tmp6 = vec_sub (vec_max (v9, tmp2), vec_min (v9, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp00 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v1, v1, v_permv); + tmp3 = vec_sub (vec_max (v0, v1), vec_min (v0, v1)); + tmp4 = vec_sub (vec_max (v0, tmp2), vec_min (v0, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v3, v3, v_permv); + tmp5 = vec_sub (vec_max (v2, v3), vec_min (v2, v3)); + tmp6 = vec_sub (vec_max (v2, tmp2), vec_min (v2, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp01 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp2 = vec_perm (v4, v4, v_permv); + tmp3 = vec_sub (vec_max (v1, v4), vec_min (v1, v4)); + tmp4 = vec_sub (vec_max (v1, tmp2), vec_min (v1, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v6, v6, v_permv); + tmp5 = vec_sub (vec_max (v3, v6), vec_min (v3, v6)); + tmp6 = vec_sub (vec_max (v3, tmp2), vec_min (v3, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp02 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + + tmp2 = vec_perm (v5, v5, v_permv); + tmp3 = vec_sub (vec_max (v4, v5), vec_min (v4, v5)); + tmp4 = vec_sub (vec_max (v4, tmp2), vec_min (v4, tmp2)); + tmp3 = (vector signed short) vec_cmpgt (tmp3, v_three); + tmp4 = (vector signed short) vec_cmpgt (tmp4, v_three); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + + tmp2 = vec_perm (v7, v7, v_permv); + tmp5 = vec_sub (vec_max (v6, v7), vec_min (v6, v7)); + tmp6 = vec_sub (vec_max (v6, tmp2), vec_min (v6, tmp2)); + tmp5 = (vector signed short) vec_cmpgt (tmp5, v_three); + tmp6 = (vector signed short) vec_cmpgt (tmp6, v_three); + tmp0 = vec_sld (tmp5, tmp5, 14); + tmp1 = vec_sld (tmp6, tmp6, 14); + tmp5 = vec_or (tmp0, tmp5); + tmp6 = vec_or (tmp1, tmp6); + + tmp3 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp5); + tmp4 = (vector signed short) vec_pack ((vector unsigned int) tmp4, (vector unsigned int) tmp6); + tmp5 = vec_sld (tmp3, tmp3, 14); + tmp6 = vec_sld (tmp4, tmp4, 14); + tmp3 = vec_or (tmp3, tmp5); + tmp4 = vec_or (tmp4, tmp6); + tmp03 = (vector signed short) vec_pack ((vector unsigned int) tmp3, (vector unsigned int) tmp4); + + tmp0 = (vector signed short) vec_pack ((vector unsigned short) tmp00, (vector unsigned short) tmp01); + tmp1 = (vector signed short) vec_pack ((vector unsigned short) tmp02, (vector unsigned short) tmp03); + tmp2 = (vector signed short) vec_mergeh ((vector signed int) tmp0, (vector signed int) tmp1); + tmp3 = (vector signed short) vec_mergel ((vector signed int) tmp0, (vector signed int) tmp1); + tmp4 = (vector signed short) vec_mergeh ((vector signed int) tmp2, (vector signed int) tmp3); + tmp5 = (vector signed short) vec_mergel ((vector signed int) tmp2, (vector signed int) tmp3); + tmp4 = vec_and (v_ref_mask00, tmp4); + tmp5 = vec_and (v_ref_mask01, tmp5); + + tmp0 = vec_nor (v_ref_mask00, v_ref_mask01); + tmp1 = vec_and (v_ref_mask00, v_ref_mask01); + tmp2 = vec_and (tmp4, tmp5); + tmp2 = vec_and (tmp2, tmp1); + tmp3 = vec_nor (tmp4, tmp5); + tmp3 = vec_nor (tmp3, tmp1); + v_vec_maskh = vec_or (tmp0, tmp2); + v_vec_maskh = vec_or (v_vec_maskh, tmp3); + + + v_intra_maskvn = vec_nor (v_intra_maskv, v_intra_maskv); + v_intra_maskhn = vec_nor (v_intra_maskh, v_intra_maskh); + v_cbp_maskvn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskv, (vector unsigned char) v_zero); + v_cbp_maskhn = (vector unsigned char) vec_cmpeq ((vector unsigned char) v_cbp_maskh, (vector unsigned char) v_zero); + + v_cbp_maskv = vec_and (v_cbp_maskv, v_intra_maskvn); + v_cbp_maskh = vec_and (v_cbp_maskh, v_intra_maskhn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_intra_maskvn); + v_vec_maskv = vec_and (v_vec_maskv, (vector signed short) v_cbp_maskvn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_intra_maskhn); + v_vec_maskh = vec_and (v_vec_maskh, (vector signed short) v_cbp_maskhn); + + tmp9 = vec_splat_u8(2); + tmp8 = vec_splat_u8(1); + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + + v_bSv = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskv); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskv); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskv); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSv = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSv); + + v_bS = vec_ld (0, (vector unsigned char *) mv_const); + v_bSh = vec_and ((vector unsigned char) v_bS, (vector unsigned char)v_intra_maskh); + tmp7 = vec_and ((vector unsigned char)tmp9, (vector unsigned char)v_cbp_maskh); + tmp6 = (vector signed short) vec_and ((vector unsigned char)tmp8, (vector unsigned char)v_vec_maskh); + tmp7 = vec_or ((vector unsigned char)tmp7, (vector unsigned char)tmp6); + v_bSh = vec_or ((vector unsigned char)tmp7, (vector unsigned char)v_bSh); + + v_permh = (vector unsigned char) vec_ld (0 , (vector unsigned char *) mv_const); + v_permv = (vector unsigned char) vec_ld (0, (vector unsigned char *) mv_const); + v_bSv = vec_and (v_bSv, v_permv); + v_bSh = vec_and (v_bSh, v_permh); + + vec_st (v_bSv, 0, (unsigned char *) mv_const); + vec_st (v_bSh, 0, (unsigned char *) mv_const); + + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSv = vec_mergeh (v_bSv, v_bSv); + v_bSh = vec_mergeh (v_bSh, v_bSh); + v_bSh = vec_mergeh (v_bSh, v_bSh); + + vec_st (v_bSv, 0, (vector unsigned char *) mv_const); + vec_st (v_bSh, 0,(vector unsigned char *) mv_const); +} + + +int main(int argc, char **argv) +{ + char toto[32] __attribute__((aligned(16))); + + foo(toto, toto, 0, 0); + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-vec-merge.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-1.c (revision 322) @@ -0,0 +1,33 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32} } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include + +static float in1[2] __attribute__ ((aligned (8))) = +{6.0, 7.0}; +static float in2[2] __attribute__ ((aligned (8))) = +{4.0, 3.0}; + +static float out[2] __attribute__ ((aligned (8))); + +vector float a, b, c, d; +void +test_api () +{ + b = paired_lx (0, in1); + c = paired_lx (0, in2); + + a = paired_sub (b, c); + + paired_stx (a, 0, out); +} + +int +main () +{ + test_api (); + return (0); +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c (revision 322) @@ -0,0 +1,22 @@ +/* { dg-do compile { target { powerpc_fprs && ilp32 } } } */ +/* { dg-options "-O3 -mcpu=power2 -fno-schedule-insns -w" } */ +/* { dg-final { scan-assembler-not "lfd" } } */ +/* { dg-final { scan-assembler-not "sfd" } } */ +/* { dg-final { scan-assembler "lfq" } } */ +/* { dg-final { scan-assembler "stfq" } } */ + +register volatile double t1 __asm__("fr0"); +register volatile double t2 __asm__("fr1"); +register volatile double t3 __asm__("fr2"), t4 __asm__("fr3"); +void t(double *a, double *b) +{ + t1 = a[-1]; + t2 = a[0]; + t3 = a[1]; + t4 = a[2]; + b[-1] = t1; + b[0] = t2; + b[1] = t3; + b[2] = t4; +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/rs6000-power2-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-20.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-20.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-20.c (revision 322) @@ -0,0 +1,23 @@ +/* { dg-do compile { target powerpc_altivec_ok } } */ +/* { dg-options "-maltivec -mcpu=G5 -O2" } */ + +#include + +void foo( float scalar) +{ + unsigned long width; + unsigned long x; + vector float vColor; + vector unsigned int selectMask; + vColor = vec_perm( vec_ld( 0, &scalar), vec_ld( 3, &scalar), vec_lvsl( 0, &scalar) ); + + float *destRow; + vector float store, load0; + + for( ; x < width; x++) + { + load0 = vec_sel( vColor, load0, selectMask ); + vec_st( store, 0, destRow ); + store = load0; + } +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-20.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/leaf.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/leaf.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/leaf.c (revision 322) @@ -0,0 +1,8 @@ +/* { dg-do compile { target rs6000-*-* } } */ +/* { dg-options "-O2" } */ +/* { dg-final { scan-assembler-not "\tstwu 1,-\[0-9\]*(1)\n" } } */ + +int Leaf (int i) +{ + return i + 1; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/leaf.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe1.c (revision 322) @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single -O0" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ + +/* (Test with -O0 so we don't optimize any of them away). */ + + +typedef float __attribute__((vector_size(8))) __ev64_fs__; + +__ev64_opaque__ Foo (void); + +void Bar () +{ + __ev64_fs__ fs = Foo (); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-9.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-9.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-9.c (revision 322) @@ -0,0 +1,25 @@ +/* { dg-do compile { target { powerpc-*-linux*paired* && ilp32 } } } */ +/* { dg-options "-mpaired -ffinite-math-only " } */ + +/* Test PowerPC PAIRED extensions. */ + +#include + +static float out[2] __attribute__ ((aligned (8))); +void +test_api (float y, float x) +{ + vector float c = {x, 7.0}; + vector float b = {0.0, 8.0}; + vector float a; + + a = paired_sub (b, c); + paired_stx (a, 0, out); +} + + +int main () +{ + test_api (6, 7); + return (0); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/paired-9.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c (revision 322) @@ -0,0 +1,11 @@ +/* Check that sizeof(bool) is 4 if we don't use special options. */ +/* Matt Austern */ +/* { dg-do run { target { powerpc*-*-darwin* && ilp32 } } } */ + +int dummy1[sizeof(_Bool) - 3]; +int dummy2[5 - sizeof(_Bool)]; + +int main() +{ + return sizeof(_Bool) == 4 ? 0 : 1; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-bool-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of mullhw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "mullhw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (short)c; + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-mullhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c (revision 322) @@ -0,0 +1,21 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-mcpu=G3 -funwind-tables" } */ +/* { dg-final { scan-assembler "bl save_world" } } */ +/* { dg-final { scan-assembler ".byte\t0x6b" } } */ + +/* Verify that on Darwin, even with -mcpu=G3, __builtin_eh_return + saves Altivec registers using save_world, and reports their + location in its EH information. */ + +long offset; +void *handler; + +extern void setup_offset(void); + +void foo(void) +{ + __builtin_unwind_init (); + setup_offset(); + __builtin_eh_return (offset, handler); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-ehreturn-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-28.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-28.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-28.c (revision 322) @@ -0,0 +1,16 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#define B bool +#define P pixel +#define I int +#define BI bool int +#define PI pixel int + +vector B int i; +vector P int j; +vector B I k; +vector P I l; +vector BI m; +vector PI n;

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-28.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c (revision 322) @@ -0,0 +1,16 @@ +/* Test generation of maclhw. on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "maclhw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (short)c; + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-maclhw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c (revision 322) @@ -0,0 +1,7 @@ +/* Test that SPE targets do not permit -m64. */ +/* Origin: Joseph Myers */ +/* { dg-do compile { target powerpc-*-*spe } } */ +/* { dg-options "-m64" } */ + +/* { dg-error "-m64 not supported in this configuration" "SPE not 64-bit" { target *-*-* } 0 } */ +/* { dg-error "64-bit E500 not supported" "64-bit E500" { target *-*-* } 0 } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-spe64-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O -mcpu=8540 -mspe -mabi=spe -mfloat-gprs=single" } */ +/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */ +/* { dg-final { scan-assembler "evstdd" } } */ + +void foo(void) +{ + int x[8] __attribute__((aligned(64))) = { 1, 1, 1, 1, 1, 1, 1, 1 }; + bar (x); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/spe-vector-memcpy.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of dlmzb for strlen on 440. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=440" } */ + +/* { dg-final { scan-assembler "dlmzb\\. " } } */ + +typedef __SIZE_TYPE__ size_t; + +size_t strlen(const char *); + +size_t +strlen8(const long long *s) +{ + return strlen((const char *)s); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/440-dlmzb-strlen-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c (revision 322) @@ -0,0 +1,9 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mno-popcntd -mcpu=power5" } */ +/* { dg-require-effective-target lp64 } */ +/* { dg-final { scan-assembler "lwbrx" } } */ +/* { dg-final { scan-assembler "stwbrx" } } */ + +unsigned long ul; +unsigned long load_bswap64 (unsigned long *p) { return __builtin_bswap64 (*p); } +void store_bswap64 (unsigned long a) { ul = __builtin_bswap64 (a); }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/bswap64-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c (revision 322) @@ -0,0 +1,229 @@ +/* { dg-do run { target { powerpc_fprs && { ilp32 && dfprt } } } } */ +/* { dg-options "-std=gnu99 -O2 -fno-strict-aliasing" } */ + +/* Testcase to check for ABI compliance of parameter passing + for the PowerPC ELF ABI for decimal float values. */ + +extern void abort (void); +int failcnt = 0; + +/* Support compiling the test to report individual failures; default is + to abort as soon as a check fails. */ +#ifdef DBG +#include +#define FAILURE { printf ("failed at line %d\n", __LINE__); failcnt++; } +#else +#define FAILURE abort (); +#endif + +typedef struct +{ + int pad; + _Decimal32 d; +} d32parm_t; + +typedef struct +{ + unsigned int gprs[8]; + double fprs[8]; +} reg_parms_t; + +reg_parms_t gparms; + + +/* Testcase could break on future gcc's, if parameter regs + are changed before this asm. */ + +#define save_parms(lparms) \ + asm volatile ("lis 11,gparms@ha\n\t" \ + "la 11,gparms@l(11)\n\t" \ + "st 3,0(11)\n\t" \ + "st 4,4(11)\n\t" \ + "st 5,8(11)\n\t" \ + "st 6,12(11)\n\t" \ + "st 7,16(11)\n\t" \ + "st 8,20(11)\n\t" \ + "st 9,24(11)\n\t" \ + "st 10,28(11)\n\t" \ + "stfd 1,32(11)\n\t" \ + "stfd 2,40(11)\n\t" \ + "stfd 3,48(11)\n\t" \ + "stfd 4,56(11)\n\t" \ + "stfd 5,64(11)\n\t" \ + "stfd 6,72(11)\n\t" \ + "stfd 7,80(11)\n\t" \ + "stfd 8,88(11)\n\t":::"11", "memory"); \ + lparms = gparms; + +typedef struct sf +{ + struct sf *backchain; + int a1; + unsigned int slot[200]; +} stack_frame_t; + +/* Fill up floating point registers with double arguments, forcing + decimal float arguments into the parameter save area. */ +void __attribute__ ((noinline)) +func0 (double a1, double a2, double a3, double a4, double a5, + double a6, double a7, double a8, _Decimal64 a9, _Decimal128 a10) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != lparms.fprs[0]) FAILURE + if (a2 != lparms.fprs[1]) FAILURE + if (a3 != lparms.fprs[2]) FAILURE + if (a4 != lparms.fprs[3]) FAILURE + if (a5 != lparms.fprs[4]) FAILURE + if (a6 != lparms.fprs[5]) FAILURE + if (a7 != lparms.fprs[6]) FAILURE + if (a8 != lparms.fprs[7]) FAILURE + if (a9 != *(_Decimal64 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal128 *)&sp->slot[2]) FAILURE +} + +/* Alternate 64-bit and 128-bit decimal float arguments, checking that + _Decimal128 is always passed in even/odd register pairs. */ +void __attribute__ ((noinline)) +func1 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5, _Decimal128 a6, _Decimal64 a7, _Decimal128 a8) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a8 != *(_Decimal128 *)&sp->slot[6]) FAILURE +} + +void __attribute__ ((noinline)) +func2 (_Decimal128 a1, _Decimal64 a2, _Decimal128 a3, _Decimal64 a4, + _Decimal128 a5, _Decimal64 a6, _Decimal128 a7, _Decimal64 a8) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a2 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ + if (a3 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a4 != *(_Decimal64 *)&lparms.fprs[7]) FAILURE /* f8 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a6 != *(_Decimal64 *)&sp->slot[4]) FAILURE + if (a7 != *(_Decimal128 *)&sp->slot[6]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[10]) FAILURE +} + +void __attribute__ ((noinline)) +func3 (_Decimal64 a1, _Decimal128 a2, _Decimal64 a3, _Decimal128 a4, + _Decimal64 a5) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != *(_Decimal64 *)&lparms.fprs[0]) FAILURE /* f1 */ + if (a2 != *(_Decimal128 *)&lparms.fprs[1]) FAILURE /* f2 & f3 */ + if (a3 != *(_Decimal64 *)&lparms.fprs[3]) FAILURE /* f4 */ + if (a4 != *(_Decimal128 *)&lparms.fprs[5]) FAILURE /* f6 & f7 */ + if (a5 != *(_Decimal128 *)&sp->slot[0]) FAILURE +} + +void __attribute__ ((noinline)) +func4 (_Decimal32 a1, _Decimal32 a2, _Decimal32 a3, _Decimal32 a4, + _Decimal32 a5, _Decimal32 a6, _Decimal32 a7, _Decimal32 a8, + _Decimal32 a9, _Decimal32 a10, _Decimal32 a11, _Decimal32 a12, + _Decimal32 a13, _Decimal32 a14, _Decimal32 a15, _Decimal32 a16) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + /* _Decimal32 is passed in the lower half of an FPR, or in parameter slot. */ + if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != ((d32parm_t *)&lparms.fprs[1])->d) FAILURE /* f2 */ + if (a3 != ((d32parm_t *)&lparms.fprs[2])->d) FAILURE /* f3 */ + if (a4 != ((d32parm_t *)&lparms.fprs[3])->d) FAILURE /* f4 */ + if (a5 != ((d32parm_t *)&lparms.fprs[4])->d) FAILURE /* f5 */ + if (a6 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ + if (a7 != ((d32parm_t *)&lparms.fprs[6])->d) FAILURE /* f7 */ + if (a8 != ((d32parm_t *)&lparms.fprs[7])->d) FAILURE /* f8 */ + if (a9 != *(_Decimal32 *)&sp->slot[0]) FAILURE + if (a10 != *(_Decimal32 *)&sp->slot[1]) FAILURE + if (a11 != *(_Decimal32 *)&sp->slot[2]) FAILURE + if (a12 != *(_Decimal32 *)&sp->slot[3]) FAILURE + if (a13 != *(_Decimal32 *)&sp->slot[4]) FAILURE + if (a14 != *(_Decimal32 *)&sp->slot[5]) FAILURE + if (a15 != *(_Decimal32 *)&sp->slot[6]) FAILURE + if (a16 != *(_Decimal32 *)&sp->slot[7]) FAILURE +} + +void __attribute__ ((noinline)) +func5 (_Decimal32 a1, _Decimal64 a2, _Decimal128 a3, + _Decimal32 a4, _Decimal64 a5, _Decimal128 a6, + _Decimal32 a7, _Decimal64 a8, _Decimal128 a9, + _Decimal32 a10, _Decimal64 a11, _Decimal128 a12) +{ + reg_parms_t lparms; + stack_frame_t *sp; + + save_parms (lparms); + sp = __builtin_frame_address (0); + sp = sp->backchain; + + if (a1 != ((d32parm_t *)&lparms.fprs[0])->d) FAILURE /* f1 */ + if (a2 != *(_Decimal64 *)&lparms.fprs[1]) FAILURE /* f2 */ + if (a3 != *(_Decimal128 *)&lparms.fprs[3]) FAILURE /* f4 & f5 */ + if (a4 != ((d32parm_t *)&lparms.fprs[5])->d) FAILURE /* f6 */ + if (a5 != *(_Decimal64 *)&lparms.fprs[6]) FAILURE /* f7 */ + + if (a6 != *(_Decimal128 *)&sp->slot[0]) FAILURE + if (a7 != *(_Decimal32 *)&sp->slot[4]) FAILURE + if (a8 != *(_Decimal64 *)&sp->slot[6]) FAILURE + if (a9 != *(_Decimal128 *)&sp->slot[8]) FAILURE + if (a10 != *(_Decimal32 *)&sp->slot[12]) FAILURE + if (a11 != *(_Decimal64 *)&sp->slot[14]) FAILURE + if (a12 != *(_Decimal128 *)&sp->slot[16]) FAILURE +} + +int +main () +{ + func0 (1., 2., 3., 4., 5., 6., 7., 8., 9.dd, 10.dl); + func1 (1.dd, 2.dl, 3.dd, 4.dl, 5.dd, 6.dl, 7.dd, 8.dl); + func2 (1.dl, 2.dd, 3.dl, 4.dd, 5.dl, 6.dd, 7.dl, 8.dd); + func3 (1.dd, 2.dl, 3.dd, 4.dl, 5.dl); + func4 (501.2df, 502.2df, 503.2df, 504.2df, 505.2df, 506.2df, 507.2df, + 508.2df, 509.2df, 510.2df, 511.2df, 512.2df, 513.2df, 514.2df, + 515.2df, 516.2df); + func5 (601.2df, 602.2dd, 603.2dl, 604.2df, 605.2dd, 606.2dl, + 607.2df, 608.2dd, 609.2dl, 610.2df, 611.2dd, 612.2dl); + + if (failcnt != 0) + abort (); + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc32-abi-dfp-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c (revision 322) @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -mcpu=power7" } */ +/* { dg-final { scan-assembler "xxpermdi" } } */ +/* { dg-final { scan-assembler-not "stxvd2x" } } */ + +/* Make sure double extract doesn't use a store instruction. */ + +double d0(__vector double v){ return __builtin_vec_extract (v, 0); } +double d1(__vector double v){ return __builtin_vec_extract (v, 1); } + +double e0(vector double v){ return __builtin_vec_ext_v2df (v, 0); } +double e1(vector double v){ return __builtin_vec_ext_v2df (v, 1); }

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-builtin-5.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c (revision 322) @@ -0,0 +1,64 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mcpu=power7 -O2 -ftree-vectorize -fno-vect-cost-model -fdump-tree-vect-details" } */ + +/* Taken from vect/vect-95.c. */ +#include +#include + +#define N 256 + +__attribute__ ((noinline)) +void bar (int *pd, int *pa, int *pb, int *pc) +{ + int i; + + /* check results: */ + for (i = 0; i < N; i++) + { + if (pa[i] != (pb[i] * pc[i])) + abort (); + if (pd[i] != 5.0) + abort (); + } + + return; +} + + +__attribute__ ((noinline)) int +main1 (int n, int * __restrict__ pd, int * __restrict__ pa, int * __restrict__ pb, int * __restrict__ pc) +{ + int i; + + for (i = 0; i < n; i++) + { + pa[i] = pb[i] * pc[i]; + pd[i] = 5.0; + } + + bar (pd,pa,pb,pc); + + return 0; +} + +int main (void) +{ + int i; + int a[N] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + int d[N+1] __attribute__ ((__aligned__(__BIGGEST_ALIGNMENT__))); + int b[N] = {0,3,6,9,12,15,18,21,24,27,30,33,36,39,42,45,48,51,54,57}; + int c[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19}; + + main1 (N,&d[1],a,b,c); + main1 (N-2,&d[1],a,b,c); + + return 0; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using peeling" 0 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { scan-tree-dump-times "Alignment of access forced using versioning" 0 "vect" } } */ +/* { dg-final { scan-tree-dump-times "Vectorizing an unaligned access" 4 "vect" {xfail {! vect_hw_misalign } } } } */ +/* { dg-final { cleanup-tree-dump "vect" } } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vectorize-7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c (revision 322) @@ -0,0 +1,19 @@ +/* { dg-do run { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-skip-if "need to be able to execute AltiVec" { ! { powerpc_altivec_ok && vmx_hw } } } */ +/* { dg-options "-maltivec" } */ + +/* With altivec turned on, Darwin wants to save the world but we did not mark lr as being saved any more + as saving the lr is not needed for saving altivec registers. */ + +int main (void) +{ + __label__ l1; + void __attribute__((used)) q(void) + { + goto l1; + } + + l1:; + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-save-world-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of mulchw. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "mulchw\\. " } } */ + +int +f(int b, int c) +{ + int a = (short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-mulchw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of maclhwu. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "maclhwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (unsigned short)c; + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-maclhwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-12.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-12.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-12.c (revision 322) @@ -0,0 +1,93 @@ +/* { dg-do run { target { powerpc*-*-* && vmx_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! vmx_hw } } } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Program to test PowerPC AltiVec instructions. */ + +#include + +extern void abort (void); +#define CHECK_IF(E) if(!(E)) abort() + +vector int a1 = (vector int){ 100, 200, 300, 400 }; +vector int a2 = (vector int){ 500, 600, 700, 800 }; +vector int addi = (vector int){ 600, 800, 1000, 1200 }; +vector int avgi = (vector int){ 300, 400, 500, 600 }; + +vector float f1 = (vector float){ 1.0, 2.0, 3.0, 4.0 }; +vector float f2 = (vector float){ 5.0, 6.0, 7.0, 8.0 }; +vector float f3; +vector float addf1 = (vector float){ 6.0, 8.0, 10.0, 12.0 }; +vector float addf2 = (vector float){ 6.1, 8.1, 10.1, 12.1 }; +vector float addf3 = (vector float){ 6.0, 8.0, 9.9, 12.1 }; +vector int k; +vector float f, g, h; + +int main () +{ + k = vec_add (a1, a2); + CHECK_IF (vec_all_eq (addi, k)); + CHECK_IF (vec_all_ge (addi, k)); + CHECK_IF (vec_all_le (addi, k)); + CHECK_IF (vec_any_eq (addi, k)); + CHECK_IF (vec_any_ge (addi, k)); + CHECK_IF (vec_any_le (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + CHECK_IF (!vec_any_ne (addi, k)); + CHECK_IF (!vec_any_lt (addi, k)); + CHECK_IF (!vec_any_gt (addi, k)); + + k = vec_avg (a1, a2); + CHECK_IF (vec_all_eq (k, avgi)); + + h = vec_add (f1, f2); + CHECK_IF (vec_all_eq (h, addf1)); + CHECK_IF (vec_all_ge (h, addf1)); + CHECK_IF (vec_all_le (h, addf1)); + CHECK_IF (vec_any_eq (h, addf1)); + CHECK_IF (vec_any_ge (h, addf1)); + CHECK_IF (vec_any_le (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + CHECK_IF (!vec_any_ne (h, addf1)); + CHECK_IF (!vec_any_lt (h, addf1)); + CHECK_IF (!vec_any_gt (h, addf1)); + + CHECK_IF (vec_all_gt (addf2, addf1)); + CHECK_IF (vec_any_gt (addf2, addf1)); + CHECK_IF (vec_all_ge (addf2, addf1)); + CHECK_IF (vec_any_ge (addf2, addf1)); + CHECK_IF (vec_all_ne (addf2, addf1)); + CHECK_IF (vec_any_ne (addf2, addf1)); + CHECK_IF (!vec_all_lt (addf2, addf1)); + CHECK_IF (!vec_any_lt (addf2, addf1)); + CHECK_IF (!vec_all_le (addf2, addf1)); + CHECK_IF (!vec_any_le (addf2, addf1)); + CHECK_IF (!vec_all_eq (addf2, addf1)); + CHECK_IF (!vec_any_eq (addf2, addf1)); + + CHECK_IF (vec_any_eq (addf3, addf1)); + CHECK_IF (vec_any_ne (addf3, addf1)); + CHECK_IF (vec_any_lt (addf3, addf1)); + CHECK_IF (vec_any_le (addf3, addf1)); + CHECK_IF (vec_any_gt (addf3, addf1)); + CHECK_IF (vec_any_ge (addf3, addf1)); + CHECK_IF (!vec_all_eq (addf3, addf1)); + CHECK_IF (!vec_all_ne (addf3, addf1)); + CHECK_IF (!vec_all_lt (addf3, addf1)); + CHECK_IF (!vec_all_le (addf3, addf1)); + CHECK_IF (!vec_all_gt (addf3, addf1)); + CHECK_IF (!vec_all_ge (addf3, addf1)); + + CHECK_IF (vec_all_numeric (addf3)); + CHECK_IF (vec_all_in (addf1, addf2)); + + CHECK_IF (vec_step (vector bool char) == 16); + CHECK_IF (vec_step (addf3) == 4); + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-12.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of macchw. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchw\\. " } } */ + +int +f(int a, int b, int c) +{ + a += (short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchw-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-options "-O -mpowerpc-gfxopt -fno-trapping-math" } */ +/* { dg-final { scan-assembler "fsel" } } */ + +/* If the user doesn't care about signals, fsel can be used in many cases. */ + +double foo(double a, double b, double c, double d) +{ + return a < b ? c : d; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-fsel-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c (revision 322) @@ -0,0 +1,57 @@ +/* { dg-do run { target { powerpc*-*-* && cell_hw } } } */ +/* { dg-do compile { target { powerpc*-*-* && { ! cell_hw } } } } */ +/* { dg-require-effective-target powerpc_ppu_ok } */ +/* { dg-options "-O2 -maltivec -mabi=altivec -mcpu=cell" } */ +#include +#include + +extern void abort (void); + +typedef short int sint16; +typedef signed char int8; + +int main1(void) __attribute__((noinline)); +int main1(void) +{ + sint16 test_vector[4] = { 1678, -2356, 19246, -17892 }; + int8 test_dst[128] __attribute__(( aligned( 16 ))); + float test_out[4] __attribute__(( aligned( 16 ))); + int p; + + for( p = 0; p < 24; ++p ) + { + memset( test_dst, 0, 128 ); + memcpy( &test_dst[p], test_vector, 8 ); + { + vector float VR, VL, V; + /* load the righthand section of the misaligned vector */ + VR = (vector float) vec_lvrx( 8, &test_dst[p] ); + VL = (vector float) vec_lvlx( 0, &test_dst[p] ); + /* Vector Shift Left Double by Octet Immediate, move the right hand section into the bytes */ + VR = vec_vsldoi( VR, VR, 2 << 2 ); + /* or those two together */ + V = vec_vor( VL, VR ); + /* sign extend */ + V = (vector float) vec_vupkhsh((vector bool short)V ); + /* fixed to float by S16_SHIFT_BITS bits */ + V = (vector float) vec_vcfsx ((vector signed int)V, 5 ); + + vec_stvx( V, 0, &test_out[0] ); + if (test_out[0] != 52.437500) + abort (); + if (test_out[1] != -73.625000) + abort (); + if (test_out[2] != 601.437500) + abort (); + if (test_out[3] != -559.125000) + abort (); + } + } +return 0; +} + + +int main(void) +{ + return main1(); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-cell-8.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c (revision 322) @@ -0,0 +1,16 @@ +/* { dg-do compile { target { { powerpc*-*-linux* && ilp32 } || { powerpc-*-eabi* } } } } */ +/* { dg-options "-O2 -fno-common -G 8 -meabi -msdata=eabi" } */ +/* { dg-require-effective-target nonpic } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata," } } */ +/* { dg-final { scan-assembler "\\.section\[ \t\]\\.sdata2," } } */ +/* { dg-final { scan-assembler "sdat@sda21\\((13|0)\\)" } } */ +/* { dg-final { scan-assembler "sdat2@sda21\\((2|0)\\)" } } */ + + +int sdat = 2; +const char sdat2[] = "1234"; + +const char * test (void) +{ + return sdat ? sdat2 : 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/ppc-sdata-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c (revision 322) @@ -0,0 +1,10 @@ +/* { dg-do compile { target powerpc*-*-darwin* } } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-Wno-long-long" } */ +struct f +{ + long long ll; + int i; +}; + +int f[sizeof(struct f)!=16?-1:1];

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/darwin-abi-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/980827-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/980827-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/980827-1.c (revision 322) @@ -0,0 +1,29 @@ +/* { dg-do run { target { { *-*-linux* && ilp32 } && powerpc_fprs } } } */ +/* { dg-options -O2 } */ + +extern void exit (int); +extern void abort (void); + +double dval = 0; + +void splat (double d); + +int main(void) +{ + splat(0); + if (dval == 0) + abort(); + exit (0); +} + +void splat (double d) +{ + union { + double f; + unsigned int l[2]; + } u; + + u.f = d + d; + u.l[1] |= 1; + asm volatile ("stfd %0,dval@sdarel(13)" : : "f" (u.f)); +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/980827-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c (revision 322) @@ -0,0 +1,48 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-O2 -ftree-vectorize -mcpu=power7" } */ +/* { dg-final { scan-assembler "xvaddsp" } } */ +/* { dg-final { scan-assembler "xvsubsp" } } */ +/* { dg-final { scan-assembler "xvmulsp" } } */ +/* { dg-final { scan-assembler "xvdivsp" } } */ +/* { dg-final { scan-assembler "xvmadd" } } */ +/* { dg-final { scan-assembler "xvmsub" } } */ + +__vector float a, b, c, d; + +void +vector_add (void) +{ + a = b + c; +} + +void +vector_subtract (void) +{ + a = b - c; +} + +void +vector_multiply (void) +{ + a = b * c; +} + +void +vector_multiply_add (void) +{ + a = (b * c) + d; +} + +void +vector_multiply_subtract (void) +{ + a = (b * c) - d; +} + +void +vector_divide (void) +{ + a = b / c; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/vsx-vector-4.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr41175.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr41175.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr41175.c (revision 322) @@ -0,0 +1,461 @@ +/* PR target/41175 */ +/* { dg-do run } */ +/* { dg-options "-Os" } */ + +#define X2(n) X1(n##0) X1(n##1) +#define X4(n) X2(n##0) X2(n##1) +#define X8(n) X4(n##0) X4(n##1) + +#ifndef __SPE__ +#define FLOAT_REG_CONSTRAINT "f" +#else +#define FLOAT_REG_CONSTRAINT "r" +#endif + +volatile int ll; + +__attribute__((noinline)) void +foo (void) +{ + asm volatile ("" : : : "memory"); +} + +__attribute__((noinline)) void +bar (char *p) +{ + asm volatile ("" : : "r" (p) : "memory"); +} + +__attribute__((noinline)) void +f1 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f2 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f3 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +} + +#ifndef __NO_FPRS__ +__attribute__((noinline)) void +f4 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f5 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f6 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X4(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X4(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X4(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f7 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f8 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f9 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X8(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X2(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X8(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X2(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X8(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X2(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f10 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f11 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f12 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X4(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X1(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X4(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X1(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X4(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X1(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f13 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); + foo (); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f14 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); + char *pp = __builtin_alloca (ll); + bar (pp); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} + +__attribute__((noinline)) void +f15 (void) +{ + int mem; +#undef X1 +#define X1(n) int gpr##n = 0; + X8(a) X8(b) X2(c) +#undef X1 +#define X1(n) double fpr##n = 0.0; + X8(d) +#undef X1 +#define X1(n) "+r" (gpr##n), + asm volatile ("" : X8(a) "=m" (mem) : : "memory"); + asm volatile ("" : X8(b) "=m" (mem) : : "memory"); + asm volatile ("" : X2(c) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "+" FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : X8(d) "=m" (mem) : : "memory"); +#undef X1 +#define X1(n) "r" (gpr##n), + asm volatile ("" : : X8(a) "m" (mem) : "memory"); + asm volatile ("" : : X8(b) "m" (mem) : "memory"); + asm volatile ("" : : X2(c) "m" (mem) : "memory"); +#undef X1 +#define X1(n) FLOAT_REG_CONSTRAINT (fpr##n), + asm volatile ("" : : X8(d) "m" (mem) : "memory"); +} +#endif + +int +main () +{ + ll = 60; + f1 (); + f2 (); + f3 (); +#ifndef __NO_FPRS__ + f4 (); + f5 (); + f6 (); + f7 (); + f8 (); + f9 (); + f10 (); + f11 (); + f12 (); + f13 (); + f14 (); + f15 (); +#endif + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr41175.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/asm-es-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/asm-es-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/asm-es-1.c (revision 322) @@ -0,0 +1,32 @@ +/* { dg-do run } */ +/* { dg-options "-O2" } */ + +static inline void __attribute__((always_inline)) +f1 (void) +{ + long unused; + asm volatile ("" : "=es" (unused) :: "memory"); +} + +static void __attribute__((noinline)) +f2 (long *val) +{ + *val = 0x1234; +} + +static long __attribute__((noinline)) +test (void) +{ + f1 (); + { + long val; + f2 (&val); + return val; + } +} + +int +main (void) +{ + return test () != 0x1234; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/asm-es-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c (revision 322) @@ -0,0 +1,91 @@ +/* { dg-do compile { target powerpc*-*-linux* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* Valid AltiVec vector types should be accepted with no warnings. */ + +__vector char vc; +__vector unsigned char vuc; +__vector signed char vsc; +__vector __bool char vbc; +__vector short vh; +__vector signed short vsh; +__vector unsigned short vuh; +__vector short int vhi; +__vector signed short int vshi; +__vector unsigned short int vuhi; +__vector __bool short vbh; +__vector __bool short int vbhi; +__vector int vi; +__vector unsigned int vui; +__vector signed int vsi; +__vector __bool int vbi; +__vector unsigned vuj; +__vector signed vsj; +__vector __bool vbj; +__vector float vf; +__vector _Bool vb; + +/* These should be rejected as invalid AltiVec types. */ + +__vector long long vll; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long vull; /* { dg-error "AltiVec types" "" } */ +__vector signed long long vsll; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long vbll; /* { dg-error "AltiVec types" "" } */ +__vector long long int vlli; /* { dg-error "AltiVec types" "" } */ +__vector unsigned long long int vulli; /* { dg-error "AltiVec types" "" } */ +__vector signed long long int vslli; /* { dg-error "AltiVec types" "" } */ +__vector __bool long long int vblli; /* { dg-error "AltiVec types" "" } */ +__vector double vd1; /* { dg-error "AltiVec types" "" } */ +__vector long double vld; /* { dg-error "AltiVec types" "" } */ +__vector _Complex float vcf; /* { dg-error "AltiVec types" "" } */ +__vector _Complex double vcd; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long double vcld; /* { dg-error "AltiVec types" "" } */ +__vector _Complex signed char vcsc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned char vcuc; /* { dg-error "AltiVec types" "" } */ +__vector _Complex short vcss; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned short vcus; /* { dg-error "AltiVec types" "" } */ +__vector _Complex int vcsi; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned int vcui; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long vcsl; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long vcul; /* { dg-error "AltiVec types" "" } */ +__vector _Complex long long vcsll; /* { dg-error "AltiVec types" "" } */ +__vector _Complex unsigned long long vcull; /* { dg-error "AltiVec types" "" } */ +__vector __complex float v_cf; /* { dg-error "AltiVec types" "" } */ +__vector __complex double v_cd; /* { dg-error "AltiVec types" "" } */ +__vector __complex long double v_cld; /* { dg-error "AltiVec types" "" } */ +__vector __complex signed char v_csc; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned char v_cuc; /* { dg-error "AltiVec types" "" } */ +__vector __complex short v_css; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned short v_cus; /* { dg-error "AltiVec types" "" } */ +__vector __complex int v_csi; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned int v_cui; /* { dg-error "AltiVec types" "" } */ +__vector __complex long v_csl; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long v_cul; /* { dg-error "AltiVec types" "" } */ +__vector __complex long long v_csll; /* { dg-error "AltiVec types" "" } */ +__vector __complex unsigned long long v_cull; /* { dg-error "AltiVec types" "" } */ + +/* These should be rejected because the component types are invalid. We + don't care about the actual error messages here. */ + +__vector __bool unsigned char vbuc; /* { dg-error "" "" } */ +__vector __bool signed char vbsc; /* { dg-error "" "" } */ +__vector __bool unsigned short vbuh; /* { dg-error "" "" } */ +__vector __bool signed short vbsh; /* { dg-error "" "" } */ +__vector __bool unsigned int vbui; /* { dg-error "" "" } */ +__vector __bool signed int vbsi; /* { dg-error "" "" } */ +__vector __bool unsigned vbuj; /* { dg-error "" "" } */ +__vector __bool signed vbsj; /* { dg-error "" "" } */ +__vector signed float vsf; /* { dg-error "" "" } */ +__vector unsigned float vuf; /* { dg-error "" "" } */ +__vector short float vsf; /* { dg-error "" "" } */ +__vector signed double vsd; /* { dg-error "" "" } */ +__vector unsigned double vud; /* { dg-error "" "" } */ +__vector short double vsd; /* { dg-error "" "" } */ +__vector __bool float vbf; /* { dg-error "" "" } */ +__vector __bool double vbd; /* { dg-error "" "" } */ +__vector __bool short float blf; /* { dg-error "" "" } */ +__vector __bool short double vlbd; /* { dg-error "" "" } */ + +/* { dg-message "note: previous" "prev vsf" { target *-*-* } 79 } */ +/* { dg-message "note: previous" "prev vsd" { target *-*-* } 82 } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-types-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr16286.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr16286.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr16286.c (revision 322) @@ -0,0 +1,27 @@ +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +/* PR 16286 + Compilation of a simple Altivec test program fails if vector, pixel + and/or bool are #undefined when compiling with -maltivec. This may be + done for building C++ programs that use the STL . */ + +#include +#undef vector +#undef pixel +#undef bool + +void test(void) +{ + __vector unsigned int a, b; + __vector __pixel v0; + __vector __bool v1; + + a = vec_and(a, b); + vec_step (b); +} + +/* { dg-bogus "(syntax|parse) error before \"vector\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"pixel\"" "-maltivec" { target powerpc*-*-* } 0 } */ +/* { dg-bogus "(syntax|parse) error before \"bool\"" "-maltivec" { target powerpc*-*-* } 0 } */

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/pr16286.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/longcall-1.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/longcall-1.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/longcall-1.c (revision 322) @@ -0,0 +1,13 @@ +/* PR target/35100 */ +/* { dg-do compile { target fpic } } */ +/* { dg-options "-fpic" } */ + +void foo (void) __attribute__((__longcall__)); +int baz (void) __attribute__((__longcall__)); + +int +bar (void) +{ + foo (); + return baz () + 1; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/longcall-1.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c (revision 322) @@ -0,0 +1,14 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-options "-O2 -mavoid-indexed-addresses" } */ + +/* { dg-final { scan-assembler-not "lbzx" } } + +/* Ensure that an indexed load is not generated with + -mavoid-indexed-addresses. */ + +char +do_one (char *base, unsigned long offset) +{ + return base[offset]; +} +

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/avoid-indexed-addresses.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-7.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-7.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-7.c (revision 322) @@ -0,0 +1,46 @@ +/* Origin: Aldy Hernandez */ + +/* { dg-do compile { target powerpc*-*-* } } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-maltivec" } */ + +#include + +int **intp; +int *var_int; +unsigned int **uintp; +vector pixel *varpixel; +vector signed char *vecchar; +vector signed int *vecint; +vector signed short *vecshort; +vector unsigned char *vecuchar; +vector unsigned int *vecuint; +vector unsigned short *vecushort; +vector float *vecfloat; + +int main () +{ + *vecfloat++ = vec_andc((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_andc(vecfloat[0], (vector bool int)vecint[1]); + *vecfloat++ = vec_vxor((vector bool int)vecint[0], vecfloat[1]); + *vecfloat++ = vec_vxor(vecfloat[0], (vector bool int)vecint[1]); + *varpixel++ = vec_packpx(vecuint[0], vecuint[1]); + *varpixel++ = vec_vpkpx(vecuint[0], vecuint[1]); + *vecshort++ = vec_vmulosb(vecchar[0], vecchar[1]); + *vecint++ = vec_ld(var_int[0], intp[1]); + *vecint++ = vec_lde(var_int[0], intp[1]); + *vecint++ = vec_ldl(var_int[0], intp[1]); + *vecint++ = vec_lvewx(var_int[0], intp[1]); + *vecint++ = vec_unpackh(vecshort[0]); + *vecint++ = vec_unpackl(vecshort[0]); + *vecushort++ = vec_andc((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_andc(vecushort[0], (vector bool short)vecshort[1]); + *vecushort++ = vec_vxor((vector bool short)vecshort[0], vecushort[1]); + *vecushort++ = vec_vxor(vecushort[0], (vector bool short)vecshort[1]); + *vecuint++ = vec_ld(var_int[0], uintp[1]); + *vecuint++ = vec_lvx(var_int[0], uintp[1]); + *vecuint++ = vec_vmsumubm(vecuchar[0], vecuchar[1], vecuint[2]); + *vecuchar++ = vec_xor(vecuchar[0], (vector unsigned char)vecchar[1]); + + return 0; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/altivec-7.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property Index: gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c =================================================================== --- gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c (nonexistent) +++ gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c (revision 322) @@ -0,0 +1,17 @@ +/* Test generation of macchwu. on 405. */ +/* Origin: Joseph Myers */ +/* { dg-do compile } */ +/* { dg-require-effective-target ilp32 } */ +/* { dg-options "-O2 -mcpu=405" } */ +/* { dg-skip-if "other options override -mcpu=405" { ! powerpc_405_nocache } { "*" } { "" } } */ + +/* { dg-final { scan-assembler "macchwu\\. " } } */ + +unsigned int +f(unsigned int a, unsigned int b, unsigned int c) +{ + a += (unsigned short)b * (c >> 16); + if (!a) + return 10; + return a; +}

gnu-src/gcc-4.5.1/gcc/testsuite/gcc.target/powerpc/405-macchwu-2.c Property changes : Added: svn:eol-style ## -0,0 +1 ## +native \ No newline at end of property Added: svn:keywords ## -0,0 +1 ## +Id \ No newline at end of property