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Rev 332 → Rev 333

/gnu-src/gcc-4.5.1/gcc/doc/invoke.texi
727,6 → 727,11
-mreturn-pointer-on-d0 @gol
-mno-crt0 -mrelax}
 
@emph{OpenRISC 1000 Options}
@gccoptlist{-mhard-float -msoft-float -mdouble-float -mhard-div @gol
-msoft-div -mhard-mul -msoft-mul -maj -msext -mcmov -mlogue @gol
-mror -msibcall -mor32-newlib -mor32-newlib-uart}
 
@emph{PDP-11 Options}
@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol
9609,6 → 9614,7
* MIPS Options::
* MMIX Options::
* MN10300 Options::
* OpenRISC 1000 Options::
* PDP-11 Options::
* picoChip Options::
* PowerPC Options::
14479,6 → 14485,110
This option makes symbolic debugging impossible.
@end table
 
@node OpenRISC 1000 Options
@subsection OpenRISC 1000 Options
@cindex OpenRISC 1000 options
 
These @samp{-m} options are defined for OpenRISC 1000 implementations:
 
@table @gcctabopt
 
@item -mhard-float
@opindex mhard-float
Generate code to use hardware (single precision) floating point
opcodes. The default is to use the software floating point library.
 
@item -msoft-float
@opindex msoft-float
Use the software library for floating point. This is enabled by default.
 
@item -mdouble-float
@opindex mdouble-float
Generate code to use double precision hardware floating point
opcodes. The default is not to enable this. Since no targets (hardware
or modelled) currently implement the double precision floating point
instruction set, this option is of little use, and also has not been
properly tested.
 
@item -mhard-div
@opindex mhard-div
Generate code to use hardware divide instructions. By default this is
not enabled.
 
@item -msoft-div
@opindex msoft-div
Generate code to use the software library for division. By default this
is enabled.
 
@item -mhard-mul
@opindex mhard-mul
Generate code to use hardware multiply instructions. By default this is
enabled.
 
@quotation Note
The standard Verilog RTL for OpenRISC includes a hardware multiply but
not divide instruction, so this will be the correct setting.
@end quotation
 
@item -msoft-mul
@opindex msoft-mul
Generate code to use the software library for multiplication. By
default this is not enabled.
 
@item -maj
@opindex maj
Align all branch and jump instructions on a double word boundary, padding with
@samp{l.nop} where necessary. It is not clear why this option exists, of
why it should ever be used. It is disabled by default and likely to be
removed in a future release of GCC.
 
@item -msext
@opindex msext
Use sign extending instructions. By default this is not enabled. It is
not clear why this has not been enabled by default, since the instructions
concerned are all mandatory on the OpenRISC 1000.
 
@item -mcmov
@opindex mcmov
Use the @samp{l.cmov} instruction in generated code. This is an optional
instruction on the OpenRISC 1000, so by default this option is not
enabled.
 
@item -mlogue
@opindex logue
Generate the prologue and epilogue using patterns in the machine
description, rather than fixed templates. This potentially allows
generation of more efficient code. However the functionality has not yet been
fully tested, and is disabled by default.
 
@item -mror
@opindex mror
Use rotate instructions in generated code. This is an optional
instruction on the OpenRISC 1000, so by default this option is not
enabled.
 
@item -msibcall
@opindex msibcall
Generate code to optimize tail calls of sibling functions. This
potentially allows generation of more efficient code. However the
functionality has not yet been fully tested, and is disabled by default.
 
@item -mor32-newlib
@opindex mor32-newlib
Use the headers for the simple OpenRISC 1000 newlib library when
preprocessing and includes this library when linking. This is a small C
library, designed for standalone applications, which offers only
standard output.
 
@item -mor32-newlib-uart
@opindex mor32-newlib-uart
Use the headers for the OpenRISC 1000 newlib library with UART support
when preprocessing and includes this library when linking. This is a
small C library, designed for standalone applications, which includes a
UART connection for I/O to and from standard output and standard input.
 
@end table
 
@node PDP-11 Options
@subsection PDP-11 Options
@cindex PDP-11 Options
/gnu-src/gcc-4.5.1/gcc/doc/contrib.texi
932,6 → 932,11
Daniel Towner and Hariharan Sandanagobalane contributed and
maintain the picoChip port.
 
@item
Jeremy Bennett of Embecosm and Jonas Bonn of South Pole contributed the
OpenRISC 1000 port, which in turn was based on earlier work by Rich
D'Addio, Damjan Lampret, Matjaz Breskvar and others.
 
@item
Tom Tromey for internationalization support and for his many Java
contributions and libgcj maintainership.
/gnu-src/gcc-4.5.1/gcc/config/or32/or32.c
2003,13 → 2003,17
In most cases these use the static functions declared above. They have
defaults, so must be undefined first, before being redefined.
 
The description of what they do is found with the function above, unless
it is a standard function, in which case it is defined here (as with
TARGET_ASM_NAMED_SECTION).
The description of what they do is found with the function above, unless it
is a standard function or a constant, in which case it is defined here (as
with TARGET_ASM_NAMED_SECTION).
 
The final declaration is of the global "targetm" structure. */
 
 
/* Default target_flags if no switches specified. */
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS (MASK_HARD_MUL)
 
/* Output assembly directives to switch to section name. The section should
have attributes as specified by flags, which is a bit mask of the SECTION_*
flags defined in ‘output.h’. If decl is non-NULL, it is the VAR_DECL or
/gnu-src/gcc-4.5.1/gcc/config/or32/or32.h
67,18 → 67,12
%{mor32-newlib-uart:%{!g:-lc -lor32uart -u free -lc} \
%{g:-lg -lor32uart -u free -lg}}"
 
#define TARGET_VERSION fprintf (stderr, " (OpenRISC 1000)");
#define TARGET_VERSION fprintf (stderr, " (OpenRISC 1000) Mask 0x%x", MASK_HARD_MUL);
 
/* Run-time compilation parameters selecting different hardware subsets. */
 
extern int target_flags;
 
/* Default target_flags if no switches specified.
 
JPB 30-Aug-10: Is this still what we want? It's not documented in the GCC
internals manual. */
#define TARGET_DEFAULT (MASK_HARD_MUL)
 
/* Target machine storage layout */
 
/* Define this if most significant bit is lowest numbered
/gnu-src/gcc-4.5.1/ChangeLog.or32
0,0 → 1,4
2010-09-04 Jeremy Bennett <jeremy.bennett@embecosm.com>
 
* NEWS. Updated with information about the OpenRISC 1000.
 
/gnu-src/gcc-4.5.1/NEWS
594,6 → 594,15
use_debug_exception_return. See the documentation for more details
about these attributes.
 
OpenRISC 1000
 
* GCC now generates global variables and functions without a leading
underscore.
* GCC now generates DWARF 2 debugging output by default (with -g).
* -mhard-mul is enabled by default.
* The -mor32-newlib and -mor32-newlib-uart options enable support for the
OpenRISC newlib library implementations.
 
picochip
 
RS/6000 (POWER/PowerPC)

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