URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 402 to Rev 403
- ↔ Reverse comparison
Rev 402 → Rev 403
/orpsocv2/bench/sysc/src/OrpsocAccess.cpp
57,10 → 57,10
OrpsocAccess::OrpsocAccess (Vorpsoc_top *orpsoc_top) |
{ |
// Assign processor accessor objects |
or1200_ctrl = orpsoc_top->v->or1200_top->or1200_cpu->or1200_ctrl; |
or1200_except = orpsoc_top->v->or1200_top->or1200_cpu->or1200_except; |
or1200_sprs = orpsoc_top->v->or1200_top->or1200_cpu->or1200_sprs; |
rf_a = orpsoc_top->v->or1200_top->or1200_cpu->or1200_rf->rf_a; |
or1200_ctrl = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_ctrl; |
or1200_except = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_except; |
or1200_sprs = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_sprs; |
rf_a = orpsoc_top->v->or1200_top0->or1200_cpu->or1200_rf->rf_a; |
// Assign main memory accessor objects |
// For old ram_wb: ram_wb_sc_sw = orpsoc_top->v->ram_wb0->ram0; |
ram_wb_sc_sw = orpsoc_top->v->wb_ram_b3_0; |
/orpsocv2/bench/verilog/timescale.v
File deleted
/orpsocv2/bench/verilog/orpsoc-testbench-defines.v
File deleted
/orpsocv2/bench/verilog/AT26DFxxx.v
89,7 → 89,8
parameter DEVICE = "AT25DF041A"; // Device selected |
parameter PRELOAD = 1; // preload memory with content in MEMORY_FILE |
parameter MEMORY_FILE = "flash.in"; // Memory pre-load |
|
parameter VERBOSE = 1; |
|
// ********************************************************************* // |
//Timing Parameters : |
// ******************************************************************** // |
584,8 → 585,9
#tV SO_reg = temp_data[i]; |
SO_on = 1'b1; |
if (i == 0) |
begin |
//$display ("Data: %h read from memory location %h",temp_data,read_addr); |
begin |
if (VERBOSE) |
$display ("Data: %h read from memory location %h",temp_data,read_addr); |
read_addr = read_addr + 1; // next byte |
i = 7; |
if (read_addr >= (MEMSIZE-1)) |
/orpsocv2/bench/verilog/include/timescale.v
0,0 → 1,41
////////////////////////////////////////////////////////////////////// |
//// //// |
//// ORPSoC Testbench Timescale //// |
//// //// |
//// Description //// |
//// ORPSoC testbench timescale file //// |
//// //// |
//// To Do: //// |
//// - //// |
//// //// |
//// Author(s): //// |
//// - jb, jb@orsoc.se //// |
//// //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2009 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
`timescale 1ns/10ps |
/orpsocv2/bench/verilog/smii_phy.v
96,22 → 96,14
|
always @(posedge clk) |
begin |
if (!rst_n) |
begin |
state_shiftreg <= 10'b0000000001; |
end |
if (smii_sync) /* sync signal from MAC */ |
state_shiftreg <= 10'b0000000010; |
else if (state_shiftreg[10]) |
state_shiftreg <= 10'b0000000001; |
else |
begin |
if (smii_sync) /* sync signal from MAC */ |
state_shiftreg <= 10'b0000000010; |
else if (state_shiftreg[10]) |
state_shiftreg <= 10'b0000000001; |
else |
state_shiftreg[10:2] <= state_shiftreg[9:1]; |
end // else: !if(!rst_n) |
end // always @ (posedge clk) |
|
|
state_shiftreg[10:2] <= state_shiftreg[9:1]; |
end |
|
/* counter from 0 to 9, counting the 10-bit segments we'll transmit |
via SMII*/ |
reg [3:0] segment_ctr; |
138,7 → 130,6
/* RX path logic PHY->(MII->SMII)->MAC */ |
/**************************************************************************/ |
|
reg rx_nibble_sel, rx_byte_valid; |
reg [7:0] rx_data_byte_rx_clk; |
|
reg [4:0] rx_dv_nib_0; |
147,14 → 138,12
|
// Allow us to check if RX DV has been low for a while |
reg [3:0] rx_dv_long_low_sr; |
wire rx_dv_long_low; |
wire dv_long_low; |
always @(posedge ethphy_mii_rx_clk) |
rx_dv_long_low_sr[3:0] <= {rx_dv_long_low_sr[2:0], ethphy_mii_rx_dv}; |
assign rx_dv_long_low = ~(|rx_dv_long_low_sr[3:0]); |
reg rx_dv; |
wire [8:0] rx_fifo_out; |
assign rx_dv_long_low = ~(|rx_dv_long_low_sr); |
wire [9:0] rx_fifo_out; |
wire rx_fifo_empty,rx_fifo_almost_empty; |
reg rx_fifo_pop; |
|
always @(posedge ethphy_mii_rx_clk or negedge rst_n) |
begin |
176,34 → 165,75
end |
end // always @ (posedge ethphy_mii_rx_clk or negedge rst_n) |
|
always @(posedge clk or negedge rst_n) |
begin |
if (!rst_n) rx_fifo_pop <= 0; |
else rx_fifo_pop <= (rx_fifo_almost_empty) ? (rx_fifo_pop ? ~rx_fifo_empty : rx_fifo_pop) : 1; |
wire rx_fifo_pop; |
|
|
reg ethphy_mii_rx_dv_r; |
wire ethphy_mii_rx_dv_re; |
wire ethphy_mii_rx_dv_fe; |
|
always @(posedge ethphy_mii_rx_clk) |
ethphy_mii_rx_dv_r <= ethphy_mii_rx_dv; |
|
rx_dv <= (state_shiftreg[10] & (((rx_segment_begin_num == (segment_ctr-1)) && !fast_ethernet)| fast_ethernet)) ? (rx_fifo_pop) : rx_dv; |
end |
assign ethphy_mii_rx_dv_re = ethphy_mii_rx_dv & !ethphy_mii_rx_dv_r; |
assign ethphy_mii_rx_dv_fe = !ethphy_mii_rx_dv & ethphy_mii_rx_dv_r; |
|
reg rx_fifo_final_pop; |
|
always @(posedge clk) |
begin |
/* remember which counter value we were at when rx enable/valid |
went high. |
This is only useful when not doing fast ethernet*/ |
if (!rst_n) |
rx_fifo_final_pop <= 0; |
else if (rx_fifo_final_pop & state_shiftreg[1] & |
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet)) |
rx_fifo_final_pop <= 0; |
else if (rx_fifo_pop & rx_fifo_empty) |
rx_fifo_final_pop <= 1; |
|
always @(posedge ethphy_mii_rx_clk) |
if (ethphy_mii_rx_dv_re) |
rx_segment_begin_num <= segment_ctr; |
|
/* rx en has gone high - remember the sequence number we're in */ |
if ((rx_segment_begin_num == 4'hf) & (~rx_dv_long_low)) |
rx_segment_begin_num <= segment_ctr; |
|
/* If rx enable goes low again, reset the segment number */ |
if (rx_dv_long_low) |
/* reset to 0xf */ |
rx_segment_begin_num <= 4'hf; |
end |
reg do_fifo_pop; |
always @(posedge clk) |
if (!rst_n) |
do_fifo_pop <= 0; |
else if (rx_fifo_empty) |
do_fifo_pop <= 0; |
else if (!rx_fifo_almost_empty) |
do_fifo_pop <= 1; |
|
|
assign rx_fifo_pop = (state_shiftreg[9] & do_fifo_pop) & |
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet) |
| fast_ethernet); |
|
reg rx_dv_r; |
wire rx_dv; |
|
// Error where rx_dv goes high one cycle too late, so is low for very first data frame - FIXME! |
//reg rx_dv; |
always @(posedge clk) |
if (!rst_n) |
rx_dv_r <= 0; |
else if (rx_fifo_final_pop & state_shiftreg[1] & |
(((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet)) |
rx_dv_r <= 0; |
else if (rx_fifo_pop) |
rx_dv_r <= rx_fifo_out[9]; |
|
assign rx_dv = rx_dv_r | rx_fifo_pop; |
|
|
reg sending_segment; |
always @(posedge clk) |
if (!rst_n) |
sending_segment <= 0; |
else if (rx_fifo_final_pop & state_shiftreg[1] & (((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet)) |
sending_segment <= 0; |
else if ((state_shiftreg[9] & do_fifo_pop) & (((rx_segment_begin_num == segment_ctr) & !fast_ethernet) | fast_ethernet)) |
sending_segment <= !rx_fifo_empty; |
|
/* A fifo, storing RX bytes coming from the PHY interface */ |
generic_fifo #(9, 64) rx_fifo |
generic_fifo #(10, 1024, 10) rx_fifo |
( |
// Outputs |
.psh_full (), |
214,46 → 244,61
.async_rst_n (rst_n), |
.psh_clk (ethphy_mii_rx_clk), |
.psh_we (rx_nib_first_r), |
.psh_d ({ethphy_mii_rx_err,ethphy_mii_rx_d,rx_dv_nib_0[3:0]}), |
.psh_d ({ethphy_mii_rx_dv,ethphy_mii_rx_err,ethphy_mii_rx_d,rx_dv_nib_0[3:0]}), |
.pop_clk (clk), |
.pop_re ((state_shiftreg[1] & rx_fifo_pop)&(((rx_segment_begin_num == segment_ctr) && !fast_ethernet)| fast_ethernet))); |
.pop_re (rx_fifo_pop) |
); |
|
|
`ifdef RX_SYNC_1 |
|
/* Assign the rx line out */ |
reg [9:0] smii_rx_frame_next; |
always @(posedge clk) |
smii_rx <= state_shiftreg[1] ? ethphy_mii_crs : /* 1st bit is MII CRS */ |
state_shiftreg[2] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) | |
rx_dv) : |
// inter-frame status byte or data byte |
state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) : |
state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) : |
state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[2]) : duplex) : |
state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[3]) : link) : |
state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[4]) : jabber) : |
state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[5]) : 1) : |
state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[6]) : 0) : |
state_shiftreg[10] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0; |
if (state_shiftreg[10]) |
smii_rx_frame_next <= rx_dv ? {rx_fifo_out[7:0],1'b1,ethphy_mii_crs} : |
{3'b101,jabber,link,duplex,fast_ethernet, |
ethphy_mii_rx_err,1'b0,ethphy_mii_crs}; |
|
`else // !`ifdef RX_SYNC_1 |
|
/* Assign the rx line out */ |
always @(posedge clk) |
smii_rx <= state_shiftreg[10] ? ethphy_mii_crs : /* 1st bit is MII CRS */ |
state_shiftreg[1] ? ((rx_dv & (segment_ctr==4'h0) & !fast_ethernet) | |
rx_dv) : |
// inter-frame status byte or data byte |
state_shiftreg[2] ? (rx_dv ? (rx_fifo_out[0]) : ethphy_mii_rx_err) : |
state_shiftreg[3] ? (rx_dv ? (rx_fifo_out[1]) : fast_ethernet) : |
state_shiftreg[4] ? (rx_dv ? (rx_fifo_out[2]) : duplex) : |
state_shiftreg[5] ? (rx_dv ? (rx_fifo_out[3]) : link) : |
state_shiftreg[6] ? (rx_dv ? (rx_fifo_out[4]) : jabber) : |
state_shiftreg[7] ? (rx_dv ? (rx_fifo_out[5]) : 1) : |
state_shiftreg[8] ? (rx_dv ? (rx_fifo_out[6]) : 0) : |
state_shiftreg[9] ? (rx_dv ? (rx_fifo_out[7]) : 1) : 0; |
`endif // !`ifdef RX_SYNC_1 |
smii_rx <= state_shiftreg[10] & smii_rx_frame_next[0] | |
state_shiftreg[1] & smii_rx_frame_next[1] | |
state_shiftreg[2] & smii_rx_frame_next[2] | |
state_shiftreg[3] & smii_rx_frame_next[3] | |
state_shiftreg[4] & smii_rx_frame_next[4] | |
state_shiftreg[5] & smii_rx_frame_next[5] | |
state_shiftreg[6] & smii_rx_frame_next[6] | |
state_shiftreg[7] & smii_rx_frame_next[7] | |
state_shiftreg[8] & smii_rx_frame_next[8] | |
state_shiftreg[9] & smii_rx_frame_next[9]; |
|
|
|
reg [79:0] rx_statename; |
always @* begin |
case (1) |
state_shiftreg[1] : |
rx_statename = "CRS"; |
state_shiftreg[2] : |
rx_statename = "RX_DV"; |
state_shiftreg[3]: |
rx_statename = "RXD0/RXERR"; |
state_shiftreg[4]: |
rx_statename = "RXD1/Fast"; |
state_shiftreg[5]: |
rx_statename = "RXD2/Dupl"; |
state_shiftreg[6]: |
rx_statename = "RXD3/Link"; |
state_shiftreg[7]: |
rx_statename = "RXD4/Jabb"; |
state_shiftreg[8]: |
rx_statename = "RXD5/UNV"; |
state_shiftreg[9]: |
rx_statename = "RXD6/FCD"; |
state_shiftreg[10] : |
rx_statename = "RXD7/AS1"; |
default: |
rx_statename = "XXXXXXX"; |
endcase // case (1) |
end // always @ * |
|
|
|
/* Status seq.: CRS, DV, ER, Speed, Duplex, Link, Jabber, UPV, FCD, 1 */ |
// {1'b1,1'b0,1'b1,jabber,link,duplex,,ethphy_mii_rx_err}); |
402,18 → 447,18
else /* Finish up */ |
begin |
tx_byte_to_phy <= 3; |
ethphy_mii_tx_en <= 0; |
end |
end |
else if (tx_byte_to_phy == 3) /* De-assert TX_EN */ |
begin |
tx_byte_to_phy <= 2'b00; |
ethphy_mii_tx_en <= 0; |
end |
end // else: !if(!rst_n) |
end // always @ (posedge ethphy_mii_tx_clk or negedge rst_n) |
|
/* A fifo, storing TX bytes coming from the SMII interface */ |
generic_fifo #(9, 64) tx_fifo |
generic_fifo #(9, 64, 6) tx_fifo |
( |
// Outputs |
.psh_full (tx_fifo_full), |
458,17 → 503,24
output reg [dw-1:0] pop_q; |
output pop_empty; |
output wire almost_empty; |
|
|
integer i; |
|
/* Actual FIFO memory */ |
reg [dw-1:0] fifo_mem [0:size-1]; |
|
initial |
begin |
for (i=0;i<size;i=i+1) |
begin |
fifo_mem[i] = {dw{1'b0}}; |
end |
end |
|
|
/* FIFO position ptr regs */ |
reg [size_log_2 - 1 : 0 ] wr_ptr, rd_ptr, ctr; |
|
integer i; |
|
|
/* FIFO full signal for push side */ |
//assign psh_full = (ptr == size-1) ? 1 : 0; |
480,17 → 532,24
//assign pop_empty = ctr==0; |
assign pop_empty = rd_ptr == wr_ptr; |
|
assign almost_empty = ctr < 2; |
assign almost_empty = ctr < 16; |
|
always @(posedge pop_re or negedge async_rst_n) |
begin |
if (!async_rst_n) |
rd_ptr <= 0; |
begin |
rd_ptr <= 0; |
pop_q <= 0; |
end |
else |
begin |
pop_q = fifo_mem[rd_ptr]; |
rd_ptr <= rd_ptr + 1; |
ctr <= ctr - 1; |
if (!pop_empty) |
begin |
pop_q <= fifo_mem[rd_ptr]; |
ctr <= ctr - 1; |
rd_ptr <= rd_ptr + 1; |
end |
|
end |
end |
|
512,5 → 571,3
|
|
endmodule // generic_fifo |
|
|
/orpsocv2/bench/verilog/orpsoc_testbench.v
45,7 → 45,7
reg rst_n = 1; // Active LOW |
|
always |
#((`BOARD_CLOCK_PERIOD_NS)/2) clk <= ~clk; |
#((`BOARD_CLOCK_PERIOD)/2) clk <= ~clk; |
|
// Reset, ACTIVE LOW |
initial |
96,11 → 96,11
`ifndef SIM_QUIET |
`define CPU_ic_top or1200_ic_top |
`define CPU_dc_top or1200_dc_top |
wire ic_en = orpsoc_testbench.dut.or1200_top.or1200_ic_top.ic_en; |
wire ic_en = orpsoc_testbench.dut.or1200_top0.or1200_ic_top.ic_en; |
always @(posedge ic_en) |
$display("Or1200 IC enabled at %t", $time); |
|
wire dc_en = orpsoc_testbench.dut.or1200_top.or1200_dc_top.dc_en; |
wire dc_en = orpsoc_testbench.dut.or1200_top0.or1200_dc_top.dc_en; |
always @(posedge dc_en) |
$display("Or1200 DC enabled at %t", $time); |
`endif |
128,7 → 128,7
initial |
begin |
`ifndef SIM_QUIET |
$display("\n* Starting simulation of design RTL.\n* Test: %s\n", |
$display("\n* Starting simulation of ORPSoC RTL.\n* Test: %s\n", |
`TEST_NAME_STRING ); |
`endif |
|
/orpsocv2/bench/verilog/mt48lc16m16a2.v
38,16 → 38,45
**************************************************************************/ |
|
`include "timescale.v" |
`include "test-defines.v" |
|
// Uncomment one of the following to have the appropriate size definitions |
// for the part. |
//`define MT48LC32M16 // 64MB part |
`define MT48LC16M16 // 32MB part |
//`define MT48LC4M16 // 8MB part |
|
module mt48lc16m16a2 (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm); |
|
parameter addr_bits = 13; |
parameter data_bits = 16; |
parameter col_bits = 9; |
parameter mem_sizes = 4194303; |
|
`ifdef MT48LC32M16 |
// Params. for mt48lc32m16a2 (64MB part) |
parameter addr_bits = 13; |
parameter col_bits = 10; |
parameter mem_sizes = 8388606; |
`endif |
|
`ifdef MT48LC16M16 |
// Params. for mt48lc16m16a2 (32MB part) |
parameter addr_bits = 13; |
parameter col_bits = 9; |
parameter mem_sizes = 4194303; |
`endif |
|
`ifdef MT48LC4M16 |
//Params for mt48lc4m16a2 (8MB part) |
parameter addr_bits = 12; |
parameter col_bits = 8; |
parameter mem_sizes = 1048575; |
`endif |
|
// Common to all parts |
parameter data_bits = 16; |
|
|
|
inout [data_bits - 1 : 0] Dq; |
input [addr_bits - 1 : 0] Addr; |
input [addr_bits - 1 : 0] Addr; |
input [1 : 0] Ba; |
input Clk; |
input Cke; |
61,7 → 90,7
reg [data_bits - 1 : 0] Bank1 [0 : mem_sizes]; |
reg [data_bits - 1 : 0] Bank2 [0 : mem_sizes]; |
reg [data_bits - 1 : 0] Bank3 [0 : mem_sizes]; |
|
reg [31 : 0] Bank0_32bit [0 : (mem_sizes/2)]; // Temporary 32-bit wide array to hold readmemh()'d data before loading into 16-bit wide array |
reg [1 : 0] Bank_addr [0 : 3]; // Bank Address Pipeline |
reg [col_bits - 1 : 0] Col_addr [0 : 3]; // Column Address Pipeline |
reg [3 : 0] Command [0 : 3]; // Command Operation Pipeline |
157,6 → 186,9
time RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3; |
time RP_chk0, RP_chk1, RP_chk2, RP_chk3; |
|
integer mem_cnt; |
|
|
initial begin |
Dq_reg = {data_bits{1'bz}}; |
Data_in_enable = 0; Data_out_enable = 0; |
171,8 → 203,32
RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0; |
RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0; |
$timeformat (-9, 1, " ns", 12); |
end |
//`define INIT_CLEAR_MEM_BANKS |
`ifdef INIT_CLEAR_MEM_BANKS // Added, jb |
// Initialse the memory before we use it, clearing x's |
for(mem_cnt = 0; mem_cnt < mem_sizes; mem_cnt = mem_cnt + 1) |
begin |
Bank0[mem_cnt] = 0; |
Bank1[mem_cnt] = 0; |
Bank2[mem_cnt] = 0; |
Bank3[mem_cnt] = 0; |
end |
`endif |
|
`ifdef PRELOAD_RAM // Added jb |
$display("* Preloading SDRAM bank 0.\n"); |
// Uses the vmem file for the internal SRAM, so words are 32-bits wide |
// and we need to copy them into the 16-bit wide array, which the simulator |
// can't figure out how to do, so we'll do it manually here. |
$readmemh("sram.vmem", Bank0_32bit); |
for (mem_cnt=0;mem_cnt < (mem_sizes/2); mem_cnt = mem_cnt + 1) |
begin |
Bank0[(mem_cnt*2)+1] = Bank0_32bit[mem_cnt][15:0]; |
Bank0[(mem_cnt*2)] = Bank0_32bit[mem_cnt][31:16]; |
end |
`endif |
end |
|
// System clock generator |
always begin |
@ (posedge Clk) begin |
1069,4 → 1125,36
$setuphold(posedge Dq_chk, Dq, tDS, tDH); |
endspecify |
|
task get_byte; |
input [31:0] addr; |
output [7:0] data; |
reg [1:0] bank; |
reg [15:0] short; |
|
begin |
bank = addr[24:23]; |
|
case(bank) |
2'b00: |
short = Bank0[addr[22:1]]; |
2'b01: |
short = Bank1[addr[22:1]]; |
2'b10: |
short = Bank2[addr[22:1]]; |
2'b11: |
short = Bank3[addr[22:1]]; |
endcase // case (bank) |
|
// Get the byte from the short |
if (!addr[0]) |
data = short[15:8]; |
else |
data = short[7:0]; |
|
//$display("SDRAM addr 0x%0h, bank %0d, short 0x%0h, byte 0x%0h", addr, bank, short, data); |
|
|
end |
endtask // get_byte |
|
endmodule |
/orpsocv2/bench/verilog/or1200_monitor.v
39,7 → 39,7
// |
// Top of OR1200 inside test bench |
// |
`define OR1200_TOP orpsoc_testbench.dut.or1200_top |
`define OR1200_TOP orpsoc_testbench.dut.or1200_top0 |
|
// |
// Define to enable lookup file generation |
439,7 → 439,7
|
|
`ifdef VERSATILE_SDRAM |
`define SDRAM_TOP design_testbench.sdram0 |
`define SDRAM_TOP orpsoc_testbench.sdram0 |
// Bit selects to define the bank |
// 32 MB part with 4 banks |
`define SDRAM_BANK_SEL_BITS 24:23 |
465,7 → 465,7
`endif // `ifdef VERSATILE_SDRAM |
|
`ifdef XILINX_DDR2 |
`define DDR2_TOP design_testbench.gen_cs[0] |
`define DDR2_TOP orpsoc_testbench.gen_cs[0] |
// Gets instruction word from correct bank |
task get_insn_from_xilinx_ddr2; |
input [31:0] addr; |
/orpsocv2/rtl/verilog/wb_conbus/wb_conbus_top.v
File deleted
/orpsocv2/rtl/verilog/wb_conbus/wb_conbus_arb.v
File deleted
/orpsocv2/rtl/verilog/eth/eth_spram_256x32.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_spram_256x32.v,v $ |
// Revision 1.10 2005/02/21 12:48:07 igorm |
// Warning fixes. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.9 2003/12/05 12:43:06 tadejm |
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16. |
// |
78,118 → 75,119
`include "timescale.v" |
|
module eth_spram_256x32( |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
// Generic synchronous single-port RAM interface |
clk, rst, ce, we, oe, addr, di, do |
|
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
|
|
); |
); |
parameter we_width = 4; |
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock, rising edge |
input rst; // Reset, active high |
input ce; // Chip enable input, active high |
input [we_width-1:0] we; // Write enable input, active high |
input oe; // Output enable input, active high |
input [7:0] addr; // address bus inputs |
input [31:0] di; // input data bus |
output [31:0] do; // output data bus |
|
|
// |
// Generic synchronous single-port RAM interface |
// |
input clk; // Clock, rising edge |
input rst; // Reset, active high |
input ce; // Chip enable input, active high |
input [3:0] we; // Write enable input, active high |
input oe; // Output enable input, active high |
input [7:0] addr; // address bus inputs |
input [31:0] di; // input data bus |
output [31:0] do; // output data bus |
|
|
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
`ifdef ETH_XILINX_RAMB4 |
|
/*RAMB4_S16 ram0 |
/*RAMB4_S16 ram0 |
( |
.DO (do[15:0]), |
.ADDR (addr), |
.DI (di[15:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
.DO (do[15:0]), |
.ADDR (addr), |
.DI (di[15:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
); |
|
RAMB4_S16 ram1 |
( |
.DO (do[31:16]), |
.ADDR (addr), |
.DI (di[31:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
.DO (do[31:16]), |
.ADDR (addr), |
.DI (di[31:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we), |
.RST (rst) |
);*/ |
|
RAMB4_S8 ram0 |
( |
.DO (do[7:0]), |
.ADDR ({1'b0, addr}), |
.DI (di[7:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we[0]), |
.RST (rst) |
); |
RAMB4_S8 ram0 |
( |
.DO (do[7:0]), |
.ADDR ({1'b0, addr}), |
.DI (di[7:0]), |
.EN (ce), |
.CLK (clk), |
.WE (we[0]), |
.RST (rst) |
); |
|
RAMB4_S8 ram1 |
( |
.DO (do[15:8]), |
.ADDR ({1'b0, addr}), |
.DI (di[15:8]), |
.EN (ce), |
.CLK (clk), |
.WE (we[1]), |
.RST (rst) |
); |
RAMB4_S8 ram1 |
( |
.DO (do[15:8]), |
.ADDR ({1'b0, addr}), |
.DI (di[15:8]), |
.EN (ce), |
.CLK (clk), |
.WE (we[1]), |
.RST (rst) |
); |
|
RAMB4_S8 ram2 |
( |
.DO (do[23:16]), |
.ADDR ({1'b0, addr}), |
.DI (di[23:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we[2]), |
.RST (rst) |
); |
RAMB4_S8 ram2 |
( |
.DO (do[23:16]), |
.ADDR ({1'b0, addr}), |
.DI (di[23:16]), |
.EN (ce), |
.CLK (clk), |
.WE (we[2]), |
.RST (rst) |
); |
|
RAMB4_S8 ram3 |
( |
.DO (do[31:24]), |
.ADDR ({1'b0, addr}), |
.DI (di[31:24]), |
.EN (ce), |
.CLK (clk), |
.WE (we[3]), |
.RST (rst) |
); |
RAMB4_S8 ram3 |
( |
.DO (do[31:24]), |
.ADDR ({1'b0, addr}), |
.DI (di[31:24]), |
.EN (ce), |
.CLK (clk), |
.WE (we[3]), |
.RST (rst) |
); |
|
`else // !ETH_XILINX_RAMB4 |
`ifdef ETH_VIRTUAL_SILICON_RAM |
`ifdef ETH_VIRTUAL_SILICON_RAM |
`ifdef ETH_BIST |
//vs_hdsp_256x32_bist ram0_bist |
vs_hdsp_256x32_bw_bist ram0_bist |
//vs_hdsp_256x32_bist ram0_bist |
vs_hdsp_256x32_bw_bist ram0_bist |
`else |
//vs_hdsp_256x32 ram0 |
vs_hdsp_256x32_bw ram0 |
//vs_hdsp_256x32 ram0 |
vs_hdsp_256x32_bw ram0 |
`endif |
( |
( |
.CK (clk), |
.CEN (!ce), |
.WEN (~we), |
198,26 → 196,26
.DI (di), |
.DOUT (do) |
|
`ifdef ETH_BIST |
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
`endif |
); |
|
`else // !ETH_VIRTUAL_SILICON_RAM |
`else // !ETH_VIRTUAL_SILICON_RAM |
|
`ifdef ETH_ARTISAN_RAM |
`ifdef ETH_BIST |
//art_hssp_256x32_bist ram0_bist |
art_hssp_256x32_bw_bist ram0_bist |
`else |
//art_hssp_256x32 ram0 |
art_hssp_256x32_bw ram0 |
`endif |
( |
`ifdef ETH_ARTISAN_RAM |
`ifdef ETH_BIST |
//art_hssp_256x32_bist ram0_bist |
art_hssp_256x32_bw_bist ram0_bist |
`else |
//art_hssp_256x32 ram0 |
art_hssp_256x32_bw ram0 |
`endif |
( |
.CLK (clk), |
.CEN (!ce), |
.WEN (~we), |
226,98 → 224,96
.D (di), |
.Q (do) |
|
`ifdef ETH_BIST |
`ifdef ETH_BIST |
, |
// debug chain signals |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
`endif |
); |
|
`else // !ETH_ARTISAN_RAM |
`ifdef ETH_ALTERA_ALTSYNCRAM |
`else // !ETH_ARTISAN_RAM |
`ifdef ETH_ALTERA_ALTSYNCRAM |
|
altera_spram_256x32 altera_spram_256x32_inst |
( |
.address (addr), |
.wren (ce & we), |
.clock (clk), |
.data (di), |
.q (do) |
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE |
altera_spram_256x32 altera_spram_256x32_inst |
( |
.address (addr), |
.wren (ce & we), |
.clock (clk), |
.data (di), |
.q (do) |
); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE |
|
`else // !ETH_ALTERA_ALTSYNCRAM |
`else // !ETH_ALTERA_ALTSYNCRAM |
|
|
// |
// Generic single-port synchronous RAM model |
// |
|
// |
// Generic single-port synchronous RAM model |
// |
// |
// Generic RAM's registers and wires |
// |
reg [ 7: 0] mem0 [255:0]; // RAM content |
reg [15: 8] mem1 [255:0]; // RAM content |
reg [23:16] mem2 [255:0]; // RAM content |
reg [31:24] mem3 [255:0]; // RAM content |
wire [31:0] q; // RAM output |
reg [7:0] raddr; // RAM read address |
|
// |
// Generic RAM's registers and wires |
// |
`ifdef ETH_SPRAM_BYTE_ENABLE |
reg [ 7: 0] mem0 [255:0]; // RAM content |
reg [15: 8] mem1 [255:0]; // RAM content |
reg [23:16] mem2 [255:0]; // RAM content |
reg [31:24] mem3 [255:0]; // RAM content |
// wire [31:0] q; // RAM output |
reg [7:0] raddr; // RAM read address |
// |
// Data output drivers |
// |
//assign do = (oe & ce) ? q : {32{1'bz}}; |
reg [31:0] mem[255:0]; |
|
// |
// RAM read and write |
// |
// |
// Data output drivers |
// |
//assign do = (oe & ce) ? q : {32{1'bz}}; |
assign do = (oe & ce) ? q : {32{1'bx}}; |
|
// read operation |
always@(posedge clk) |
if (ce) // && !we) |
raddr <= #1 addr; // read address needs to be registered to read clock |
// |
// RAM read and write |
// |
|
// assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]}; |
assign #1 do = {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]}; |
// read operation |
always@(posedge clk) |
if (ce) |
raddr <= addr; // read address needs to be registered to read clock |
|
// write operation |
always@(posedge clk) |
begin |
generate |
if (we_width > 1) |
begin |
|
assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], |
mem0[raddr]}; |
|
// write operation |
always@(posedge clk) |
begin |
if (ce && we[3]) |
mem3[addr] <= #1 di[31:24]; |
mem3[addr] <= di[31:24]; |
if (ce && we[2]) |
mem2[addr] <= #1 di[23:16]; |
mem2[addr] <= di[23:16]; |
if (ce && we[1]) |
mem1[addr] <= #1 di[15: 8]; |
mem1[addr] <= di[15: 8]; |
if (ce && we[0]) |
mem0[addr] <= #1 di[ 7: 0]; |
end |
mem0[addr] <= di[ 7: 0]; |
end |
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task print_ram; |
input [7:0] start; |
input [7:0] finish; |
integer rnum; |
begin |
for (rnum=start;rnum<=finish;rnum=rnum+1) |
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]); |
end |
endtask |
`else // !`ifdef ETH_SPRAM_BYTE_ENABLE |
reg [31:0] mem [255:0]; // RAM content |
reg [7:0] raddr; |
always @ (posedge clk) |
if (ce) |
raddr <= #1 addr; |
end // if (we_width > 1) |
else |
begin |
assign q = rst ? {32{1'b0}} : {mem[raddr]}; |
|
assign #1 do = mem[raddr]; |
// write operation |
always@(posedge clk) |
begin |
if (ce && we[0]) |
mem[addr] <= di[ 31: 0]; |
end |
|
end // else: !if(we_width > 1) |
endgenerate |
|
always @ (posedge clk) |
if (ce && we[0]) |
mem[addr] <= #1 di; |
|
// Task prints range of memory |
// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. |
task print_ram; |
326,14 → 322,13
integer rnum; |
begin |
for (rnum=start;rnum<=finish;rnum=rnum+1) |
$display("Addr %h = %0h",rnum,mem[rnum]); |
$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]); |
end |
endtask |
|
`endif |
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_ARTISAN_RAM |
`endif // !ETH_VIRTUAL_SILICON_RAM |
|
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_ARTISAN_RAM |
`endif // !ETH_VIRTUAL_SILICON_RAM |
`endif // !ETH_XILINX_RAMB4 |
|
endmodule |
/orpsocv2/rtl/verilog/eth/eth_rxethmac.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_rxethmac.v,v $ |
// Revision 1.13 2005/02/21 12:48:07 igorm |
// Warning fixes. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.12 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
252,16 → 249,16
|
always @ (posedge MRxClk) |
begin |
CrcHashGood <= #Tp StateData[0] & ByteCntEq6; |
CrcHashGood <= StateData[0] & ByteCntEq6; |
end |
|
always @ (posedge MRxClk) |
begin |
if(Reset | StateIdle) |
CrcHash[5:0] <= #Tp 6'h0; |
CrcHash[5:0] <= 6'h0; |
else |
if(StateData[0] & ByteCntEq6) |
CrcHash[5:0] <= #Tp Crc[31:26]; |
CrcHash[5:0] <= Crc[31:26]; |
end |
|
|
270,23 → 267,23
begin |
if(Reset) |
begin |
RxData_d[7:0] <= #Tp 8'h0; |
DelayData <= #Tp 1'b0; |
LatchedByte[7:0] <= #Tp 8'h0; |
RxData[7:0] <= #Tp 8'h0; |
RxData_d[7:0] <= 8'h0; |
DelayData <= 1'b0; |
LatchedByte[7:0] <= 8'h0; |
RxData[7:0] <= 8'h0; |
end |
else |
begin |
LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte |
DelayData <= #Tp StateData[0]; |
LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]}; // Latched byte |
DelayData <= StateData[0]; |
|
if(GenerateRxValid) |
RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state |
RxData_d[7:0] <= LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state |
else |
if(~DelayData) |
RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active. |
RxData_d[7:0] <= 8'h0; // Delaying data to be valid for two cycles. Zero when not active. |
|
RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte |
RxData[7:0] <= RxData_d[7:0]; // Output data byte |
end |
end |
|
295,17 → 292,17
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
else |
begin |
if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
else |
if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1) |
Broadcast <= #Tp 1'b1; |
Broadcast <= 1'b1; |
else |
if(RxAbort | RxEndFrm) |
Broadcast <= #Tp 1'b0; |
Broadcast <= 1'b0; |
end |
end |
|
313,13 → 310,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Multicast <= #Tp 1'b0; |
Multicast <= 1'b0; |
else |
begin |
if(StateData[0] & ByteCntEq1 & LatchedByte[0]) |
Multicast <= #Tp 1'b1; |
Multicast <= 1'b1; |
else if(RxAbort | RxEndFrm) |
Multicast <= #Tp 1'b0; |
Multicast <= 1'b0; |
end |
end |
|
330,13 → 327,13
begin |
if(Reset) |
begin |
RxValid_d <= #Tp 1'b0; |
RxValid <= #Tp 1'b0; |
RxValid_d <= 1'b0; |
RxValid <= 1'b0; |
end |
else |
begin |
RxValid_d <= #Tp GenerateRxValid; |
RxValid <= #Tp RxValid_d; |
RxValid_d <= GenerateRxValid; |
RxValid <= RxValid_d; |
end |
end |
|
347,13 → 344,13
begin |
if(Reset) |
begin |
RxStartFrm_d <= #Tp 1'b0; |
RxStartFrm <= #Tp 1'b0; |
RxStartFrm_d <= 1'b0; |
RxStartFrm <= 1'b0; |
end |
else |
begin |
RxStartFrm_d <= #Tp GenerateRxStartFrm; |
RxStartFrm <= #Tp RxStartFrm_d; |
RxStartFrm_d <= GenerateRxStartFrm; |
RxStartFrm <= RxStartFrm_d; |
end |
end |
|
366,13 → 363,13
begin |
if(Reset) |
begin |
RxEndFrm_d <= #Tp 1'b0; |
RxEndFrm <= #Tp 1'b0; |
RxEndFrm_d <= 1'b0; |
RxEndFrm <= 1'b0; |
end |
else |
begin |
RxEndFrm_d <= #Tp GenerateRxEndFrm; |
RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm; |
RxEndFrm_d <= GenerateRxEndFrm; |
RxEndFrm <= RxEndFrm_d | DribbleRxEndFrm; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_shiftreg.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_shiftreg.v,v $ |
// Revision 1.6 2005/03/08 14:45:09 igorm |
// Case statement improved for synthesys. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/08/14 18:16:59 mohor |
// LinkFail signal was not latching appropriate bit. |
// |
111,9 → 108,9
begin |
if(Reset) |
begin |
ShiftReg[7:0] <= #Tp 8'h0; |
Prsd[15:0] <= #Tp 16'h0; |
LinkFail <= #Tp 1'b0; |
ShiftReg[7:0] <= 8'h0; |
Prsd[15:0] <= 16'h0; |
LinkFail <= 1'b0; |
end |
else |
begin |
122,25 → 119,25
if(|ByteSelect) |
begin |
case (ByteSelect[3:0]) // synopsys parallel_case full_case |
4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10}; |
4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8]; |
4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0]; |
4'h1 : ShiftReg[7:0] <= {2'b01, ~WriteOp, WriteOp, Fiad[4:1]}; |
4'h2 : ShiftReg[7:0] <= {Fiad[0], Rgad[4:0], 2'b10}; |
4'h4 : ShiftReg[7:0] <= CtrlData[15:8]; |
4'h8 : ShiftReg[7:0] <= CtrlData[7:0]; |
endcase |
end |
else |
begin |
ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
ShiftReg[7:0] <= {ShiftReg[6:0], Mdi}; |
if(LatchByte[0]) |
begin |
Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi}; |
Prsd[7:0] <= {ShiftReg[6:0], Mdi}; |
if(Rgad == 5'h01) |
LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
LinkFail <= ~ShiftReg[1]; // this is bit [2], because it is not shifted yet |
end |
else |
begin |
if(LatchByte[1]) |
Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi}; |
Prsd[15:8] <= {ShiftReg[6:0], Mdi}; |
end |
end |
end |
/orpsocv2/rtl/verilog/eth/eth_rxcounters.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_rxcounters.v,v $ |
// Revision 1.6 2005/02/21 11:00:57 igorm |
// Delayed CRC fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/02/15 11:13:29 mohor |
// Format of the file changed a bit. |
// |
149,14 → 146,14
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
begin |
if(ResetByteCounter) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
if(IncrementByteCounter) |
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; |
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1; |
end |
end |
|
184,14 → 181,14
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
IFGCounter[4:0] <= #Tp 5'h0; |
IFGCounter[4:0] <= 5'h0; |
else |
begin |
if(ResetIFGCounter) |
IFGCounter[4:0] <= #Tp 5'h0; |
IFGCounter[4:0] <= 5'h0; |
else |
if(IncrementIFGCounter) |
IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1; |
IFGCounter[4:0] <= IFGCounter[4:0] + 1'b1; |
end |
end |
|
203,17 → 200,17
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt[3:0] <= #Tp 4'h0; |
DlyCrcCnt[3:0] <= 4'h0; |
else |
begin |
if(DlyCrcCnt[3:0] == 4'h9) |
DlyCrcCnt[3:0] <= #Tp 4'h0; |
DlyCrcCnt[3:0] <= 4'h0; |
else |
if(DlyCrcEn & StateSFD) |
DlyCrcCnt[3:0] <= #Tp 4'h1; |
DlyCrcCnt[3:0] <= 4'h1; |
else |
if(DlyCrcEn & (|DlyCrcCnt[3:0])) |
DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1; |
DlyCrcCnt[3:0] <= DlyCrcCnt[3:0] + 1'b1; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_txethmac.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_txethmac.v,v $ |
// Revision 1.9 2005/02/21 11:25:28 igorm |
// Delayed CRC fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2003/01/30 13:33:24 mohor |
// When padding was enabled and crc disabled, frame was not ended correctly. |
// |
230,14 → 227,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StopExcessiveDeferOccured <= #Tp 1'b0; |
StopExcessiveDeferOccured <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StopExcessiveDeferOccured <= #Tp 1'b0; |
StopExcessiveDeferOccured <= 1'b0; |
else |
if(ExcessiveDeferOccured) |
StopExcessiveDeferOccured <= #Tp 1'b1; |
StopExcessiveDeferOccured <= 1'b1; |
end |
end |
|
246,14 → 243,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ColWindow <= #Tp 1'b1; |
ColWindow <= 1'b1; |
else |
begin |
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0])) |
ColWindow <= #Tp 1'b0; |
ColWindow <= 1'b0; |
else |
if(StateIdle | StateIPG) |
ColWindow <= #Tp 1'b1; |
ColWindow <= 1'b1; |
end |
end |
|
262,14 → 259,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
StatusLatch <= #Tp 1'b0; |
StatusLatch <= 1'b0; |
else |
begin |
if(~TxStartFrm) |
StatusLatch <= #Tp 1'b0; |
StatusLatch <= 1'b0; |
else |
if(ExcessiveDeferOccured | StateIdle) |
StatusLatch <= #Tp 1'b1; |
StatusLatch <= 1'b1; |
end |
end |
|
278,9 → 275,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUsedData <= #Tp 1'b0; |
TxUsedData <= 1'b0; |
else |
TxUsedData <= #Tp |StartData; |
TxUsedData <= |StartData; |
end |
|
|
288,14 → 285,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDone <= #Tp 1'b0; |
TxDone <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxDone <= #Tp 1'b0; |
TxDone <= 1'b0; |
else |
if(StartTxDone) |
TxDone <= #Tp 1'b1; |
TxDone <= 1'b1; |
end |
end |
|
304,14 → 301,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxRetry <= #Tp 1'b0; |
TxRetry <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch) |
TxRetry <= #Tp 1'b0; |
TxRetry <= 1'b0; |
else |
if(StartTxRetry) |
TxRetry <= #Tp 1'b1; |
TxRetry <= 1'b1; |
end |
end |
|
320,14 → 317,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxAbort <= #Tp 1'b0; |
TxAbort <= 1'b0; |
else |
begin |
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured) |
TxAbort <= #Tp 1'b0; |
TxAbort <= 1'b0; |
else |
if(StartTxAbort) |
TxAbort <= #Tp 1'b1; |
TxAbort <= 1'b1; |
end |
end |
|
336,15 → 333,15
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCnt[3:0] <= #Tp 4'h0; |
RetryCnt[3:0] <= 4'h0; |
else |
begin |
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun |
| StateJam & NibCntEq7 & (~ColWindow | RetryMax)) |
RetryCnt[3:0] <= #Tp 4'h0; |
RetryCnt[3:0] <= 4'h0; |
else |
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt) |
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1; |
RetryCnt[3:0] <= RetryCnt[3:0] + 1'b1; |
end |
end |
|
382,9 → 379,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxEn <= #Tp 1'b0; |
MTxEn <= 1'b0; |
else |
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
MTxEn <= StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
|
392,9 → 389,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxD[3:0] <= #Tp 4'h0; |
MTxD[3:0] <= 4'h0; |
else |
MTxD[3:0] <= #Tp MTxD_d[3:0]; |
MTxD[3:0] <= MTxD_d[3:0]; |
end |
|
|
402,9 → 399,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
MTxErr <= #Tp 1'b0; |
MTxErr <= 1'b0; |
else |
MTxErr <= #Tp TooBig | UnderRun; |
MTxErr <= TooBig | UnderRun; |
end |
|
|
412,9 → 409,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
WillTransmit <= #Tp 1'b0; |
WillTransmit <= 1'b0; |
else |
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
WillTransmit <= StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam; |
end |
|
|
426,13 → 423,13
begin |
if(Reset) |
begin |
PacketFinished <= #Tp 1'b0; |
PacketFinished_q <= #Tp 1'b0; |
PacketFinished <= 1'b0; |
PacketFinished_q <= 1'b0; |
end |
else |
begin |
PacketFinished <= #Tp PacketFinished_d; |
PacketFinished_q <= #Tp PacketFinished; |
PacketFinished <= PacketFinished_d; |
PacketFinished_q <= PacketFinished; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_wishbone.v
37,218 → 37,6
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
// |
// CVS Revision History |
// |
// $Log: eth_wishbone.v,v $ |
// Revision 1.58 2005/03/21 20:07:18 igorm |
// Some small fixes + some troubles fixed. |
// |
// Revision 1.57 2005/02/21 11:35:33 igorm |
// Defer indication fixed. |
// |
// Revision 1.56 2004/04/30 10:30:00 igorm |
// Accidently deleted line put back. |
// |
// Revision 1.55 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
// - TxBDAddress is set to 0 after the TX is enabled in the MODER register. |
// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER |
// register. (thanks to Mathias and Torbjorn) |
// - Multicast reception was fixed. Thanks to Ulrich Gries |
// |
// Revision 1.54 2003/11/12 18:24:59 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
// Revision 1.53 2003/10/17 07:46:17 markom |
// mbist signals updated according to newest convention |
// |
// Revision 1.52 2003/01/30 14:51:31 mohor |
// Reset has priority in some flipflops. |
// |
// Revision 1.51 2003/01/30 13:36:22 mohor |
// A new bug (entered with previous update) fixed. When abort occured sometimes |
// data transmission was blocked. |
// |
// Revision 1.50 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// Revision 1.49 2003/01/21 12:09:40 mohor |
// When receiving normal data frame and RxFlow control was switched on, RXB |
// interrupt was not set. |
// |
// Revision 1.48 2003/01/20 12:05:26 mohor |
// When in full duplex, transmit was sometimes blocked. Fixed. |
// |
// Revision 1.47 2002/11/22 13:26:21 mohor |
// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used |
// anywhere. Removed. |
// |
// Revision 1.46 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// Revision 1.45 2002/11/19 17:33:34 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
// |
// Revision 1.44 2002/11/13 22:21:40 tadejm |
// RxError is not generated when small frame reception is enabled and small |
// frames are received. |
// |
// Revision 1.43 2002/10/18 20:53:34 mohor |
// case changed to casex. |
// |
// Revision 1.42 2002/10/18 17:04:20 tadejm |
// Changed BIST scan signals. |
// |
// Revision 1.41 2002/10/18 15:42:09 tadejm |
// Igor added WB burst support and repaired BUG when handling TX under-run and retry. |
// |
// Revision 1.40 2002/10/14 16:07:02 mohor |
// TxStatus is written after last access to the TX fifo is finished (in case of abort |
// or retry). TxDone is fixed. |
// |
// Revision 1.39 2002/10/11 15:35:20 mohor |
// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, |
// TxDone and TxRetry are generated after the current WISHBONE access is |
// finished. |
// |
// Revision 1.38 2002/10/10 16:29:30 mohor |
// BIST added. |
// |
// Revision 1.37 2002/09/11 14:18:46 mohor |
// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. |
// |
// Revision 1.36 2002/09/10 13:48:46 mohor |
// Reception is possible after RxPointer is read and not after BD is read. For |
// that reason RxBDReady is changed to RxReady. |
// Busy_IRQ interrupt connected. When there is no RxBD ready and frame |
// comes, interrupt is generated. |
// |
// Revision 1.35 2002/09/10 10:35:23 mohor |
// Ethernet debug registers removed. |
// |
// Revision 1.34 2002/09/08 16:31:49 mohor |
// Async reset for WB_ACK_O removed (when core was in reset, it was |
// impossible to access BDs). |
// RxPointers and TxPointers names changed to be more descriptive. |
// TxUnderRun synchronized. |
// |
// Revision 1.33 2002/09/04 18:47:57 mohor |
// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals |
// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal |
// was not used OK. |
// |
// Revision 1.32 2002/08/14 19:31:48 mohor |
// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No |
// need to multiply or devide any more. |
// |
// Revision 1.31 2002/07/25 18:29:01 mohor |
// WriteRxDataToMemory signal changed so end of frame (when last word is |
// written to fifo) is changed. |
// |
// Revision 1.30 2002/07/23 15:28:31 mohor |
// Ram , used for BDs changed from generic_spram to eth_spram_256x32. |
// |
// Revision 1.29 2002/07/20 00:41:32 mohor |
// ShiftEnded synchronization changed. |
// |
// Revision 1.28 2002/07/18 16:11:46 mohor |
// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. |
// |
// Revision 1.27 2002/07/11 02:53:20 mohor |
// RxPointer bug fixed. |
// |
// Revision 1.26 2002/07/10 13:12:38 mohor |
// Previous bug wasn't succesfully removed. Now fixed. |
// |
// Revision 1.25 2002/07/09 23:53:24 mohor |
// Master state machine had a bug when switching from master write to |
// master read. |
// |
// Revision 1.24 2002/07/09 20:44:41 mohor |
// m_wb_cyc_o signal released after every single transfer. |
// |
// Revision 1.23 2002/05/03 10:15:50 mohor |
// Outputs registered. Reset changed for eth_wishbone module. |
// |
// Revision 1.22 2002/04/24 08:52:19 mohor |
// Compiler directives added. Tx and Rx fifo size incremented. A "late collision" |
// bug fixed. |
// |
// Revision 1.21 2002/03/29 16:18:11 lampret |
// Small typo fixed. |
// |
// Revision 1.20 2002/03/25 16:19:12 mohor |
// Any address can be used for Tx and Rx BD pointers. Address does not need |
// to be aligned. |
// |
// Revision 1.19 2002/03/19 12:51:50 mohor |
// Comments in Slovene language removed. |
// |
// Revision 1.18 2002/03/19 12:46:52 mohor |
// casex changed with case, fifo reset changed. |
// |
// Revision 1.17 2002/03/09 16:08:45 mohor |
// rx_fifo was not always cleared ok. Fixed. |
// |
// Revision 1.16 2002/03/09 13:51:20 mohor |
// Status was not latched correctly sometimes. Fixed. |
// |
// Revision 1.15 2002/03/08 06:56:46 mohor |
// Big Endian problem when sending frames fixed. |
// |
// Revision 1.14 2002/03/02 19:12:40 mohor |
// Byte ordering changed (Big Endian used). casex changed with case because |
// Xilinx Foundation had problems. Tested in HW. It WORKS. |
// |
// Revision 1.13 2002/02/26 16:59:55 mohor |
// Small fixes for external/internal DMA missmatches. |
// |
// Revision 1.12 2002/02/26 16:22:07 mohor |
// Interrupts changed |
// |
// Revision 1.11 2002/02/15 17:07:39 mohor |
// Status was not written correctly when frames were discarted because of |
// address mismatch. |
// |
// Revision 1.10 2002/02/15 12:17:39 mohor |
// RxStartFrm cleared when abort or retry comes. |
// |
// Revision 1.9 2002/02/15 11:59:10 mohor |
// Changes that were lost when updating from 1.5 to 1.8 fixed. |
// |
// Revision 1.8 2002/02/14 20:54:33 billditt |
// Addition of new module eth_addrcheck.v |
// |
// Revision 1.7 2002/02/12 17:03:47 mohor |
// RxOverRun added to statuses. |
// |
// Revision 1.6 2002/02/11 09:18:22 mohor |
// Tx status is written back to the BD. |
// |
// Revision 1.5 2002/02/08 16:21:54 mohor |
// Rx status is written back to the BD. |
// |
// Revision 1.4 2002/02/06 14:10:21 mohor |
// non-DMA host interface added. Select the right configutation in eth_defines. |
// |
// Revision 1.3 2002/02/05 16:44:39 mohor |
// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 |
// MHz. Statuses, overrun, control frame transmission and reception still need |
// to be fixed. |
// |
// Revision 1.2 2002/02/01 12:46:51 mohor |
// Tx part finished. TxStatus needs to be fixed. Pause request needs to be |
// added. |
// |
// Revision 1.1 2002/01/23 10:47:59 mohor |
// Initial version. Equals to eth_wishbonedma.v at this moment. |
// |
// |
// |
|
`include "eth_defines.v" |
`include "timescale.v" |
255,476 → 43,539
|
|
module eth_wishbone |
( |
( |
|
// WISHBONE common |
WB_CLK_I, WB_DAT_I, WB_DAT_O, |
// WISHBONE common |
WB_CLK_I, WB_DAT_I, WB_DAT_O, |
|
// WISHBONE slave |
WB_ADR_I, WB_WE_I, WB_ACK_O, |
BDCs, |
// WISHBONE slave |
WB_ADR_I, WB_WE_I, WB_ACK_O, |
BDCs, |
|
Reset, |
Reset, |
|
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
// WISHBONE master |
m_wb_adr_o, m_wb_sel_o, m_wb_we_o, |
m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o, |
m_wb_stb_o, m_wb_ack_i, m_wb_err_i, |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o, m_wb_bte_o, |
m_wb_cti_o, m_wb_bte_o, |
`endif |
|
//TX |
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, |
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn, |
PerPacketPad, |
//TX |
MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, |
TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn, |
PerPacketPad, |
|
//RX |
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll, |
//RX |
MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2, |
|
// Register |
r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll, |
|
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
|
// Rx Status |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss, |
ReceivedPauseFrm, |
|
// Tx Status |
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost |
// Interrupts |
TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, |
|
// Rx Status |
InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble, |
ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss, |
ReceivedPauseFrm, |
|
// Tx Status |
RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost |
|
// Bist |
// Bist |
`ifdef ETH_BIST |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
, |
// debug chain signals |
mbist_si_i, // bist scan serial in |
mbist_so_o, // bist scan serial out |
mbist_ctrl_i // bist chain shift control |
`endif |
|
|
`ifdef WISHBONE_DEBUG |
, |
dbg_dat0 |
`endif |
|
); |
|
); |
|
parameter Tp = 1; |
|
//parameter Tp = 1; |
parameter Tp = 0; |
|
// WISHBONE common |
input WB_CLK_I; // WISHBONE clock |
input [31:0] WB_DAT_I; // WISHBONE data input |
output [31:0] WB_DAT_O; // WISHBONE data output |
|
// WISHBONE slave |
input [9:2] WB_ADR_I; // WISHBONE address input |
input WB_WE_I; // WISHBONE write enable input |
input [3:0] BDCs; // Buffer descriptors are selected |
output WB_ACK_O; // WISHBONE acknowledge output |
// WISHBONE common |
input WB_CLK_I; // WISHBONE clock |
input [31:0] WB_DAT_I; // WISHBONE data input |
output [31:0] WB_DAT_O; // WISHBONE data output |
|
// WISHBONE master |
output [29:0] m_wb_adr_o; // |
output [3:0] m_wb_sel_o; // |
output m_wb_we_o; // |
output [31:0] m_wb_dat_o; // |
output m_wb_cyc_o; // |
output m_wb_stb_o; // |
input [31:0] m_wb_dat_i; // |
input m_wb_ack_i; // |
input m_wb_err_i; // |
// WISHBONE slave |
input [9:2] WB_ADR_I; // WISHBONE address input |
input WB_WE_I; // WISHBONE write enable input |
input [3:0] BDCs; // Buffer descriptors are selected |
output WB_ACK_O; // WISHBONE acknowledge output |
|
`ifdef POLL_TXBDS |
reg [31:0] TxBDReadySamples; // -- jb |
wire TxBDNotReady; // -- jb |
`endif |
|
// WISHBONE master |
output [29:0] m_wb_adr_o; // |
output [3:0] m_wb_sel_o; // |
output m_wb_we_o; // |
output [31:0] m_wb_dat_o; // |
output m_wb_cyc_o; // |
output m_wb_stb_o; // |
input [31:0] m_wb_dat_i; // |
input m_wb_ack_i; // |
input m_wb_err_i; // |
|
`ifdef ETH_WISHBONE_B3 |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [1:0] m_wb_bte_o; // Burst Type Extension |
reg [2:0] m_wb_cti_o; // Cycle Type Identifier |
output [2:0] m_wb_cti_o; // Cycle Type Identifier |
`ifdef BURST_4BEAT |
output reg [1:0] m_wb_bte_o; // Burst Type Extension |
`else |
output [1:0] m_wb_bte_o; // Burst Type Extension |
`endif |
reg [2:0] m_wb_cti_o; // Cycle Type Identifier |
`endif |
|
input Reset; // Reset signal |
input Reset; // Reset signal |
|
// Rx Status signals |
input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode |
input LatchedCrcError; // CRC error |
input RxLateCollision; // Late collision occured while receiving frame |
input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall) |
input DribbleNibble; // Extra nibble received |
input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL |
input [15:0] RxLength; // Length of the incoming frame |
input LoadRxStatus; // Rx status was loaded |
input ReceivedPacketGood;// Received packet's length and CRC are good |
input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD |
input r_RxFlow; |
input r_PassAll; |
input ReceivedPauseFrm; |
// Rx Status signals |
input InvalidSymbol; // Invalid symbol was received during |
// reception in 100 Mbps mode |
input LatchedCrcError; // CRC error |
input RxLateCollision; // Late collision occured while receiving |
// frame |
input ShortFrame; // Frame shorter then the minimum size |
// (r_MinFL) was received while small |
// packets are enabled (r_RecSmall) |
input DribbleNibble; // Extra nibble received |
input ReceivedPacketTooBig;// Received packet is bigger than |
// r_MaxFL |
input [15:0] RxLength; // Length of the incoming frame |
input LoadRxStatus; // Rx status was loaded |
input ReceivedPacketGood;// Received packet's length and CRC are |
// good |
input AddressMiss; // When a packet is received AddressMiss |
// status is written to the Rx BD |
input r_RxFlow; |
input r_PassAll; |
input ReceivedPauseFrm; |
|
// Tx Status signals |
input [3:0] RetryCntLatched; // Latched Retry Counter |
input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made) |
input LateCollLatched; // Late collision occured |
input DeferLatched; // Defer indication (Frame was defered before sucessfully sent) |
output RstDeferLatched; |
input CarrierSenseLost; // Carrier Sense was lost during the frame transmission |
// Tx Status signals |
input [3:0] RetryCntLatched; // Latched Retry Counter |
input RetryLimit; // Retry limit reached (Retry Max value + |
// 1 attempts were made) |
input LateCollLatched; // Late collision occured |
input DeferLatched; // Defer indication (Frame was defered |
// before sucessfully sent) |
output RstDeferLatched; |
input CarrierSenseLost; // Carrier Sense was lost during the |
// frame transmission |
|
// Tx |
input MTxClk; // Transmit clock (from PHY) |
input TxUsedData; // Transmit packet used data |
input TxRetry; // Transmit packet retry |
input TxAbort; // Transmit packet abort |
input TxDone; // Transmission ended |
output TxStartFrm; // Transmit packet start frame |
output TxEndFrm; // Transmit packet end frame |
output [7:0] TxData; // Transmit packet data byte |
output TxUnderRun; // Transmit packet under-run |
output PerPacketCrcEn; // Per packet crc enable |
output PerPacketPad; // Per packet pading |
// Tx |
input MTxClk; // Transmit clock (from PHY) |
input TxUsedData; // Transmit packet used data |
input TxRetry; // Transmit packet retry |
input TxAbort; // Transmit packet abort |
input TxDone; // Transmission ended |
output TxStartFrm; // Transmit packet start frame |
output TxEndFrm; // Transmit packet end frame |
output [7:0] TxData; // Transmit packet data byte |
output TxUnderRun; // Transmit packet under-run |
output PerPacketCrcEn; // Per packet crc enable |
output PerPacketPad; // Per packet pading |
|
// Rx |
input MRxClk; // Receive clock (from PHY) |
input [7:0] RxData; // Received data byte (from PHY) |
input RxValid; // |
input RxStartFrm; // |
input RxEndFrm; // |
input RxAbort; // This signal is set when address doesn't match. |
output RxStatusWriteLatched_sync2; |
// Rx |
input MRxClk; // Receive clock (from PHY) |
input [7:0] RxData; // Received data byte (from PHY) |
input RxValid; // |
input RxStartFrm; // |
input RxEndFrm; // |
input RxAbort; // This signal is set when address doesn't |
// match. |
output RxStatusWriteLatched_sync2; |
|
//Register |
input r_TxEn; // Transmit enable |
input r_RxEn; // Receive enable |
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
//Register |
input r_TxEn; // Transmit enable |
input r_RxEn; // Receive enable |
input [7:0] r_TxBDNum; // Receive buffer descriptor number |
|
// Interrupts |
output TxB_IRQ; |
output TxE_IRQ; |
output RxB_IRQ; |
output RxE_IRQ; |
output Busy_IRQ; |
// Interrupts |
output TxB_IRQ; |
output TxE_IRQ; |
output RxB_IRQ; |
output RxE_IRQ; |
output Busy_IRQ; |
|
|
// Bist |
// Bist |
`ifdef ETH_BIST |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
input mbist_si_i; // bist scan serial in |
output mbist_so_o; // bist scan serial out |
input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control |
`endif |
|
reg TxB_IRQ; |
reg TxE_IRQ; |
reg RxB_IRQ; |
reg RxE_IRQ; |
`ifdef WISHBONE_DEBUG |
output [31:0] dbg_dat0; |
`endif |
|
reg TxStartFrm; |
reg TxEndFrm; |
reg [7:0] TxData; |
|
reg TxUnderRun; |
reg TxUnderRun_wb; |
|
reg TxBDRead; |
wire TxStatusWrite; |
reg TxB_IRQ; |
reg TxE_IRQ; |
reg RxB_IRQ; |
reg RxE_IRQ; |
|
reg [1:0] TxValidBytesLatched; |
reg TxStartFrm; |
reg TxEndFrm; |
reg [7:0] TxData; |
|
reg [15:0] TxLength; |
reg [15:0] LatchedTxLength; |
reg [14:11] TxStatus; |
reg TxUnderRun; |
reg TxUnderRun_wb; |
|
reg [14:13] RxStatus; |
reg TxBDRead; |
wire TxStatusWrite; |
|
reg TxStartFrm_wb; |
reg TxRetry_wb; |
reg TxAbort_wb; |
reg TxDone_wb; |
reg [1:0] TxValidBytesLatched; |
|
reg TxDone_wb_q; |
reg TxAbort_wb_q; |
reg TxRetry_wb_q; |
reg TxRetryPacket; |
reg TxRetryPacket_NotCleared; |
reg TxDonePacket; |
reg TxDonePacket_NotCleared; |
reg TxAbortPacket; |
reg TxAbortPacket_NotCleared; |
reg RxBDReady; |
reg RxReady; |
reg TxBDReady; |
reg [15:0] TxLength; |
reg [15:0] LatchedTxLength; |
reg [14:11] TxStatus; |
|
reg RxBDRead; |
reg [14:13] RxStatus; |
|
reg [31:0] TxDataLatched; |
reg [1:0] TxByteCnt; |
reg LastWord; |
reg ReadTxDataFromFifo_tck; |
reg TxStartFrm_wb; |
reg TxRetry_wb; |
reg TxAbort_wb; |
reg TxDone_wb; |
|
reg BlockingTxStatusWrite; |
reg BlockingTxBDRead; |
reg TxDone_wb_q; |
reg TxAbort_wb_q; |
reg TxRetry_wb_q; |
reg TxRetryPacket; |
reg TxRetryPacket_NotCleared; |
reg TxDonePacket; |
reg TxDonePacket_NotCleared; |
reg TxAbortPacket; |
reg TxAbortPacket_NotCleared; |
reg RxBDReady; |
reg RxBDOK; |
reg TxBDReady; |
|
reg Flop; |
reg RxBDRead; |
|
reg [7:1] TxBDAddress; |
reg [7:1] RxBDAddress; |
reg [31:0] TxDataLatched; |
reg [1:0] TxByteCnt; |
reg LastWord; |
reg ReadTxDataFromFifo_tck; |
|
reg TxRetrySync1; |
reg TxAbortSync1; |
reg TxDoneSync1; |
reg BlockingTxStatusWrite; |
reg BlockingTxBDRead; |
|
reg TxAbort_q; |
reg TxRetry_q; |
reg TxUsedData_q; |
reg Flop; |
|
reg [31:0] RxDataLatched2; |
reg [7:1] TxBDAddress; |
reg [7:1] RxBDAddress; |
|
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering |
reg TxRetrySync1; |
reg TxAbortSync1; |
reg TxDoneSync1; |
|
reg [1:0] RxValidBytes; |
reg [1:0] RxByteCnt; |
reg LastByteIn; |
reg ShiftWillEnd; |
reg TxAbort_q; |
reg TxRetry_q; |
reg TxUsedData_q; |
|
reg WriteRxDataToFifo; |
reg [15:0] LatchedRxLength; |
reg RxAbortLatched; |
reg [31:0] RxDataLatched2; |
|
reg ShiftEnded; |
reg RxOverrun; |
reg [31:8] RxDataLatched1; // Big Endian Byte Ordering |
|
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side |
reg BDRead; // BD Read access from WISHBONE side |
wire [31:0] RxBDDataIn; // Rx BD data in |
wire [31:0] TxBDDataIn; // Tx BD data in |
reg [1:0] RxValidBytes; |
reg [1:0] RxByteCnt; |
reg LastByteIn; |
reg ShiftWillEnd; |
|
reg TxEndFrm_wb; |
reg WriteRxDataToFifo; |
reg [15:0] LatchedRxLength; |
reg RxAbortLatched; |
|
wire TxRetryPulse; |
wire TxDonePulse; |
wire TxAbortPulse; |
reg ShiftEnded; |
reg RxOverrun; |
|
wire StartRxBDRead; |
reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side |
reg BDRead; // BD Read access from WISHBONE side |
wire [31:0] RxBDDataIn; // Rx BD data in |
wire [31:0] TxBDDataIn; // Tx BD data in |
|
wire StartTxBDRead; |
reg TxEndFrm_wb; |
|
wire TxIRQEn; |
wire WrapTxStatusBit; |
wire TxRetryPulse; |
wire TxDonePulse; |
wire TxAbortPulse; |
|
wire RxIRQEn; |
wire WrapRxStatusBit; |
wire StartRxBDRead; |
|
wire [1:0] TxValidBytes; |
wire StartTxBDRead; |
|
wire [7:1] TempTxBDAddress; |
wire [7:1] TempRxBDAddress; |
wire TxIRQEn; |
wire WrapTxStatusBit; |
|
wire RxStatusWrite; |
wire RxBufferFull; |
wire RxBufferAlmostEmpty; |
wire RxBufferEmpty; |
wire RxIRQEn; |
wire WrapRxStatusBit; |
|
reg WB_ACK_O; |
wire [1:0] TxValidBytes; |
|
wire [8:0] RxStatusIn; |
reg [8:0] RxStatusInLatched; |
wire [7:1] TempTxBDAddress; |
wire [7:1] TempRxBDAddress; |
|
reg WbEn, WbEn_q; |
reg RxEn, RxEn_q; |
reg TxEn, TxEn_q; |
reg r_TxEn_q; |
reg r_RxEn_q; |
wire RxStatusWrite; |
wire RxBufferFull; |
wire RxBufferAlmostEmpty; |
wire RxBufferEmpty; |
|
wire ram_ce; |
wire [3:0] ram_we; |
wire ram_oe; |
reg [7:0] ram_addr; |
reg [31:0] ram_di; |
wire [31:0] ram_do; |
reg WB_ACK_O; |
|
wire StartTxPointerRead; |
reg TxPointerRead; |
reg TxEn_needed; |
reg RxEn_needed; |
wire [8:0] RxStatusIn; |
reg [8:0] RxStatusInLatched; |
|
wire StartRxPointerRead; |
reg RxPointerRead; |
reg WbEn, WbEn_q; |
reg RxEn, RxEn_q; |
reg TxEn, TxEn_q; |
reg r_TxEn_q; |
reg r_RxEn_q; |
|
wire ram_ce; |
wire [3:0] ram_we; |
wire ram_oe; |
reg [7:0] ram_addr; |
reg [31:0] ram_di; |
wire [31:0] ram_do; |
|
wire StartTxPointerRead; |
reg TxPointerRead; |
reg TxEn_needed; |
reg RxEn_needed; |
|
wire StartRxPointerRead; |
reg RxPointerRead; |
|
// RX shift ending signals |
reg ShiftEnded_rck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
|
wire StartShiftWillEnd; |
|
// Pulse for wishbone side having finished writing back |
reg rx_wb_writeback_finished; |
// Indicator of last set of writes from the Wishbone master coming up |
reg rx_wb_last_writes; |
|
|
`ifdef TXBD_POLL |
reg [31:0] TxBDReadySamples; // -- jb |
wire TxBDNotReady; // -- jb |
`endif |
|
`ifdef ETH_WISHBONE_B3 |
assign m_wb_bte_o = 2'b00; // Linear burst |
`ifndef BURST_4BEAT |
assign m_wb_bte_o = 2'b00; // Linear burst |
`endif |
`endif |
|
assign m_wb_stb_o = m_wb_cyc_o; |
assign m_wb_stb_o = m_wb_cyc_o; |
|
always @ (posedge WB_CLK_I) |
begin |
WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; |
end |
always @ (posedge WB_CLK_I) |
begin |
WB_ACK_O <= (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q; |
end |
|
assign WB_DAT_O = ram_do; |
assign WB_DAT_O = ram_do; |
|
// Generic synchronous single-port RAM interface |
eth_spram_256x32 bd_ram ( |
.clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do) |
// Generic synchronous single-port RAM interface |
eth_spram_256x32 |
#(1) // Write enable width |
bd_ram |
( |
.clk (WB_CLK_I), |
.rst (Reset), |
.ce (ram_ce), |
.we (ram_we[0]), |
.oe (ram_oe), |
.addr (ram_addr), |
.di (ram_di), |
.do (ram_do) |
`ifdef ETH_BIST |
, |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
, |
.mbist_si_i (mbist_si_i), |
.mbist_so_o (mbist_so_o), |
.mbist_ctrl_i (mbist_ctrl_i) |
`endif |
); |
); |
|
assign ram_ce = 1'b1; |
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}}; |
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead); |
assign ram_ce = 1'b1; |
assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | |
{4{(TxStatusWrite | RxStatusWrite)}}; |
assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & |
(TxBDRead | TxPointerRead) | RxEn & RxEn_q & |
(RxBDRead | RxPointerRead); |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEn_needed <=#Tp 1'b0; |
else |
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q) |
TxEn_needed <=#Tp 1'b1; |
else |
if(TxPointerRead & TxEn & TxEn_q) |
TxEn_needed <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEn_needed <= 1'b0; |
else |
if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q) |
TxEn_needed <= 1'b1; |
else |
if(TxPointerRead & TxEn & TxEn_q) |
TxEn_needed <= 1'b0; |
end |
|
// Enabling access to the RAM for three devices. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn <=#Tp 1'b1; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp 8'h0; |
ram_di <=#Tp 32'h0; |
BDRead <=#Tp 1'b0; |
BDWrite <=#Tp 1'b0; |
end |
else |
begin |
// Switching between three stages depends on enable signals |
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_10, 5'b100_11 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp {RxBDAddress, RxPointerRead}; |
ram_di <=#Tp RxBDDataIn; |
end |
5'b100_01 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled |
ram_addr <=#Tp {TxBDAddress, TxPointerRead}; |
ram_di <=#Tp TxBDDataIn; |
end |
5'b010_00, 5'b010_10 : |
begin |
WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
end |
5'b010_01, 5'b010_11 : |
begin |
WbEn <=#Tp 1'b0; |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <=#Tp {TxBDAddress, TxPointerRead}; |
ram_di <=#Tp TxBDDataIn; |
end |
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : |
begin |
WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage) |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
end |
5'b100_00 : |
begin |
WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit |
end |
5'b000_00 : |
begin |
WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage. |
RxEn <=#Tp 1'b0; |
TxEn <=#Tp 1'b0; |
ram_addr <=#Tp WB_ADR_I[9:2]; |
ram_di <=#Tp WB_DAT_I; |
BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <=#Tp (|BDCs) & ~WB_WE_I; |
end |
endcase |
end |
end |
// Enabling access to the RAM for three devices. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn <= 1'b1; |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= 8'h0; |
ram_di <= 32'h0; |
BDRead <= 1'b0; |
BDWrite <= 1'b0; |
end |
else |
begin |
// Switching between three stages depends on enable signals |
case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case |
5'b100_10, 5'b100_11 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b1; // wb access stage and r_RxEn is enabled |
TxEn <= 1'b0; |
ram_addr <= {RxBDAddress, RxPointerRead}; |
ram_di <= RxBDDataIn; |
end |
5'b100_01 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // wb access stage, r_RxEn is disabled but |
// r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b010_00, 5'b010_10 : |
begin |
WbEn <= 1'b1; // RxEn access stage and r_TxEn is disabled |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b010_01, 5'b010_11 : |
begin |
WbEn <= 1'b0; |
RxEn <= 1'b0; |
TxEn <= 1'b1; // RxEn access stage and r_TxEn is enabled |
ram_addr <= {TxBDAddress, TxPointerRead}; |
ram_di <= TxBDDataIn; |
end |
5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 : |
begin |
WbEn <= 1'b1; // TxEn access stage (we always go to wb |
// access stage) |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
5'b100_00 : |
begin |
WbEn <= 1'b0; // WbEn access stage and there is no need |
// for other stages. WbEn needs to be |
// switched off for a bit |
end |
5'b000_00 : |
begin |
WbEn <= 1'b1; // Idle state. We go to WbEn access stage. |
RxEn <= 1'b0; |
TxEn <= 1'b0; |
ram_addr <= WB_ADR_I[9:2]; |
ram_di <= WB_DAT_I; |
BDWrite <= BDCs[3:0] & {4{WB_WE_I}}; |
BDRead <= (|BDCs) & ~WB_WE_I; |
end |
endcase |
end |
end |
|
|
// Delayed stage signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn_q <=#Tp 1'b0; |
RxEn_q <=#Tp 1'b0; |
TxEn_q <=#Tp 1'b0; |
r_TxEn_q <=#Tp 1'b0; |
r_RxEn_q <=#Tp 1'b0; |
end |
else |
begin |
WbEn_q <=#Tp WbEn; |
RxEn_q <=#Tp RxEn; |
TxEn_q <=#Tp TxEn; |
r_TxEn_q <=#Tp r_TxEn; |
r_RxEn_q <=#Tp r_RxEn; |
end |
end |
// Delayed stage signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
WbEn_q <= 1'b0; |
RxEn_q <= 1'b0; |
TxEn_q <= 1'b0; |
r_TxEn_q <= 1'b0; |
r_RxEn_q <= 1'b0; |
end |
else |
begin |
WbEn_q <= WbEn; |
RxEn_q <= RxEn; |
TxEn_q <= TxEn; |
r_TxEn_q <= r_TxEn; |
r_RxEn_q <= r_RxEn; |
end |
end |
|
// Changes for tx occur every second clock. Flop is used for this manner. |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Flop <=#Tp 1'b0; |
else |
if(TxDone | TxAbort | TxRetry_q) |
Flop <=#Tp 1'b0; |
else |
if(TxUsedData) |
Flop <=#Tp ~Flop; |
end |
// Changes for tx occur every second clock. Flop is used for this manner. |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Flop <= 1'b0; |
else |
if(TxDone | TxAbort | TxRetry_q) |
Flop <= 1'b0; |
else |
if(TxUsedData) |
Flop <= ~Flop; |
end |
|
wire ResetTxBDReady; |
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse; |
wire ResetTxBDReady; |
assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse; |
|
// Latching READY status of the Tx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDReady <=#Tp 1'b0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning. |
else // Only packets larger then 4 bytes are transmitted. |
if(ResetTxBDReady) |
TxBDReady <=#Tp 1'b0; |
end |
// Latching READY status of the Tx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDReady <= 1'b0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
// TxBDReady is sampled only once at the beginning. |
TxBDReady <= ram_do[15] & (ram_do[31:16] > 4); |
else |
// Only packets larger then 4 bytes are transmitted. |
if(ResetTxBDReady) |
TxBDReady <= 1'b0; |
end |
|
`ifdef POLL_TXBDS |
// Register TxBDReady 4 times, when all are low we know this one is not good to transmit |
`ifdef TXBD_POLL |
// Register TxBDReady 4 times, when all are low we know this one is not |
// good to transmit |
always @(posedge WB_CLK_I or posedge Reset) // -- jb |
begin |
if (Reset) TxBDReadySamples <= 32'hffffffff; |
732,1863 → 583,2261
if (r_TxEn) |
begin |
if (TxBDNotReady) |
TxBDReadySamples <= 32'hffffffff; |
TxBDReadySamples <= 32'hffffffff; |
else |
TxBDReadySamples[31:0] <= {TxBDReadySamples[30:0],TxBDReady}; |
end |
else |
TxBDReadySamples <= 32'hffffffff; |
else |
TxBDReadySamples <= 32'hffffffff; |
end // else: !if(Reset) |
end // always @ (posedge WB_CLK_I or posedge Reset) |
// When all low, this goes high -- jb |
assign TxBDNotReady = ~(|TxBDReadySamples); |
|
|
|
`endif |
|
assign TxBDNotReady = ~(|TxBDReadySamples); // When all low, this goes high // -- jb |
`endif // `ifdef POLL_TXBDS |
// Reading the Tx buffer descriptor |
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & |
~BlockingTxBDRead & ~TxBDReady; |
|
// Reading the Tx buffer descriptor |
assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDRead <= 1'b1; |
else |
if(StartTxBDRead) |
TxBDRead <= 1'b1; |
else |
if(TxBDReady) |
TxBDRead <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDRead <=#Tp 1'b1; |
else |
if(StartTxBDRead) |
TxBDRead <=#Tp 1'b1; |
else |
if(TxBDReady) |
TxBDRead <=#Tp 1'b0; |
end |
|
// Reading Tx BD pointer |
assign StartTxPointerRead = TxBDRead & TxBDReady; |
|
// Reading Tx BD pointer |
assign StartTxPointerRead = TxBDRead & TxBDReady; |
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerRead <= 1'b0; |
else |
if(StartTxPointerRead) |
TxPointerRead <= 1'b1; |
else |
if(TxEn_q) |
TxPointerRead <= 1'b0; |
end |
|
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerRead <=#Tp 1'b0; |
else |
if(StartTxPointerRead) |
TxPointerRead <=#Tp 1'b1; |
else |
if(TxEn_q) |
TxPointerRead <=#Tp 1'b0; |
end |
|
// Writing status back to the Tx buffer descriptor |
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared)& |
TxEn & TxEn_q & ~BlockingTxStatusWrite; |
|
// Writing status back to the Tx buffer descriptor |
assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite; |
|
|
// Status writing must occur only once. Meanwhile it is blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite <= 1'b0; |
else |
if(~TxDone_wb & ~TxAbort_wb) |
BlockingTxStatusWrite <= 1'b0; |
else |
if(TxStatusWrite) |
BlockingTxStatusWrite <= 1'b1; |
end |
|
// Status writing must occur only once. Meanwhile it is blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite <=#Tp 1'b0; |
else |
if(~TxDone_wb & ~TxAbort_wb) |
BlockingTxStatusWrite <=#Tp 1'b0; |
else |
if(TxStatusWrite) |
BlockingTxStatusWrite <=#Tp 1'b1; |
end |
|
reg BlockingTxStatusWrite_sync1; |
reg BlockingTxStatusWrite_sync2; |
reg BlockingTxStatusWrite_sync3; |
|
reg BlockingTxStatusWrite_sync1; |
reg BlockingTxStatusWrite_sync2; |
reg BlockingTxStatusWrite_sync3; |
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync1 <= 1'b0; |
else |
BlockingTxStatusWrite_sync1 <= BlockingTxStatusWrite; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync1 <=#Tp 1'b0; |
else |
BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite; |
end |
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync2 <= 1'b0; |
else |
BlockingTxStatusWrite_sync2 <= BlockingTxStatusWrite_sync1; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync2 <=#Tp 1'b0; |
else |
BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1; |
end |
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync3 <= 1'b0; |
else |
BlockingTxStatusWrite_sync3 <= BlockingTxStatusWrite_sync2; |
end |
|
// Synchronizing BlockingTxStatusWrite to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
BlockingTxStatusWrite_sync3 <=#Tp 1'b0; |
else |
BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2; |
end |
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & |
~BlockingTxStatusWrite_sync3; |
|
assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3; |
// TxBDRead state is activated only once. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxBDRead <= 1'b0; |
else |
if(StartTxBDRead) |
BlockingTxBDRead <= 1'b1; |
else |
if(~StartTxBDRead & ~TxBDReady) |
BlockingTxBDRead <= 1'b0; |
end |
|
// TxBDRead state is activated only once. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingTxBDRead <=#Tp 1'b0; |
else |
if(StartTxBDRead) |
BlockingTxBDRead <=#Tp 1'b1; |
else |
if(~StartTxBDRead & ~TxBDReady) |
BlockingTxBDRead <=#Tp 1'b0; |
end |
|
// Latching status from the tx buffer descriptor |
// Data is avaliable one cycle after the access is started (at that time |
// signal TxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStatus <= 4'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxStatus <= ram_do[14:11]; |
end |
|
// Latching status from the tx buffer descriptor |
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStatus <=#Tp 4'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxStatus <=#Tp ram_do[14:11]; |
end |
reg ReadTxDataFromMemory; |
wire WriteRxDataToMemory; |
reg WriteRxDataToMemory_r; |
|
reg ReadTxDataFromMemory; |
wire WriteRxDataToMemory; |
// Register WriteRxDataToMemory in Wishbone clock domain |
// so it doesn't get out of sync with burst capability indication signals |
always @(posedge WB_CLK_I or posedge Reset) |
if (Reset) |
WriteRxDataToMemory_r <= 0; |
else |
WriteRxDataToMemory_r <= WriteRxDataToMemory; |
|
reg MasterWbTX; |
reg MasterWbRX; |
|
reg MasterWbTX; |
reg MasterWbRX; |
reg [29:0] m_wb_adr_o; |
reg m_wb_cyc_o; |
reg [3:0] m_wb_sel_o; |
reg m_wb_we_o; |
|
reg [29:0] m_wb_adr_o; |
reg m_wb_cyc_o; |
reg [3:0] m_wb_sel_o; |
reg m_wb_we_o; |
wire TxLengthEq0; |
wire TxLengthLt4; |
|
wire TxLengthEq0; |
wire TxLengthLt4; |
reg BlockingIncrementTxPointer; |
reg [31:2] TxPointerMSB; |
reg [1:0] TxPointerLSB; |
reg [1:0] TxPointerLSB_rst; |
reg [31:2] RxPointerMSB; |
reg [1:0] RxPointerLSB_rst; |
|
reg BlockingIncrementTxPointer; |
reg [31:2] TxPointerMSB; |
reg [1:0] TxPointerLSB; |
reg [1:0] TxPointerLSB_rst; |
reg [31:2] RxPointerMSB; |
reg [1:0] RxPointerLSB_rst; |
wire RxBurstAcc; |
wire RxWordAcc; |
wire RxHalfAcc; |
wire RxByteAcc; |
|
wire RxBurstAcc; |
wire RxWordAcc; |
wire RxHalfAcc; |
wire RxByteAcc; |
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxLength <= ram_do[31:16]; |
else |
if(MasterWbTX & m_wb_ack_i) |
begin |
if(TxLengthLt4) |
TxLength <= 16'h0; |
else |
if(TxPointerLSB_rst==2'h0) |
TxLength <= TxLength - 3'h4; // Length is subtracted at |
// the data request |
else |
if(TxPointerLSB_rst==2'h1) |
TxLength <= TxLength - 3'h3; // Length is subtracted |
// at the data request |
else |
if(TxPointerLSB_rst==2'h2) |
TxLength <= TxLength - 3'h2; // Length is subtracted |
// at the data request |
else |
if(TxPointerLSB_rst==2'h3) |
TxLength <= TxLength - 3'h1; // Length is subtracted |
// at the data request |
end |
end |
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxLength <=#Tp 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
TxLength <=#Tp ram_do[31:16]; |
else |
if(MasterWbTX & m_wb_ack_i) |
begin |
if(TxLengthLt4) |
TxLength <=#Tp 16'h0; |
else |
if(TxPointerLSB_rst==2'h0) |
TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h1) |
TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h2) |
TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request |
else |
if(TxPointerLSB_rst==2'h3) |
TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request |
end |
end |
|
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchedTxLength <= 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
LatchedTxLength <= ram_do[31:16]; |
end |
|
//Latching length from the buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchedTxLength <=#Tp 16'h0; |
else |
if(TxEn & TxEn_q & TxBDRead) |
LatchedTxLength <=#Tp ram_do[31:16]; |
end |
assign TxLengthEq0 = TxLength == 0; |
assign TxLengthLt4 = TxLength < 4; |
|
assign TxLengthEq0 = TxLength == 0; |
assign TxLengthLt4 = TxLength < 4; |
reg cyc_cleared; |
reg IncrTxPointer; |
|
reg cyc_cleared; |
reg IncrTxPointer; |
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are |
// latched because TxPointerMSB is only used for word-aligned accesses. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerMSB <= 30'h0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerMSB <= ram_do[31:2]; |
else |
if(IncrTxPointer & ~BlockingIncrementTxPointer) |
// TxPointer is word-aligned |
TxPointerMSB <= TxPointerMSB + 1'b1; |
end |
|
// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched |
// because TxPointerMSB is only used for word-aligned accesses. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerMSB <=#Tp 30'h0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerMSB <=#Tp ram_do[31:2]; |
else |
if(IncrTxPointer & ~BlockingIncrementTxPointer) |
TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned |
end |
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are |
// performed, valid data does not necesserly start at byte 0 (could be byte |
// 0, 1, 2 or 3). This signals are used for proper selection of the start |
// byte (TxData and TxByteCnt) are set by this two bits. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB[1:0] <= ram_do[1:0]; |
end |
|
// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed, |
// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This |
// signals are used for proper selection of the start byte (TxData and TxByteCnt) are |
// set by this two bits. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB[1:0] <=#Tp 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB[1:0] <=#Tp ram_do[1:0]; |
end |
|
// Latching 2 MSB bits of the buffer descriptor. |
// After the read access, TxLength needs to be decremented for the number of |
// the valid bytes (1 to 4 bytes are valid in the first word). After the |
// first read all bytes are valid so this two bits are reset to zero. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB_rst[1:0] <= 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB_rst[1:0] <= ram_do[1:0]; |
else |
// After first access pointer is word alligned |
if(MasterWbTX & m_wb_ack_i) |
TxPointerLSB_rst[1:0] <= 0; |
end |
|
// Latching 2 MSB bits of the buffer descriptor. |
// After the read access, TxLength needs to be decremented for the number of the valid |
// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are |
// valid so this two bits are reset to zero. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxPointerLSB_rst[1:0] <=#Tp 0; |
else |
if(TxEn & TxEn_q & TxPointerRead) |
TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; |
else |
if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned |
TxPointerLSB_rst[1:0] <=#Tp 0; |
end |
|
reg [3:0] RxByteSel; |
wire MasterAccessFinished; |
|
reg [3:0] RxByteSel; |
wire MasterAccessFinished; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingIncrementTxPointer <= 0; |
else |
if(MasterAccessFinished) |
BlockingIncrementTxPointer <= 0; |
else |
if(IncrTxPointer) |
BlockingIncrementTxPointer <= 1'b1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockingIncrementTxPointer <=#Tp 0; |
else |
if(MasterAccessFinished) |
BlockingIncrementTxPointer <=#Tp 0; |
else |
if(IncrTxPointer) |
BlockingIncrementTxPointer <=#Tp 1'b1; |
end |
|
wire TxBufferAlmostFull; |
wire TxBufferFull; |
wire TxBufferEmpty; |
wire TxBufferAlmostEmpty; |
wire SetReadTxDataFromMemory; |
|
wire TxBufferAlmostFull; |
wire TxBufferFull; |
wire TxBufferEmpty; |
wire TxBufferAlmostEmpty; |
wire SetReadTxDataFromMemory; |
reg BlockReadTxDataFromMemory; |
|
reg BlockReadTxDataFromMemory; |
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead; |
|
assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromMemory <= 1'b0; |
else |
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) |
ReadTxDataFromMemory <= 1'b0; |
else |
if(SetReadTxDataFromMemory) |
ReadTxDataFromMemory <= 1'b1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromMemory <=#Tp 1'b0; |
else |
if(TxLengthEq0 | TxAbortPulse | TxRetryPulse) |
ReadTxDataFromMemory <=#Tp 1'b0; |
else |
if(SetReadTxDataFromMemory) |
ReadTxDataFromMemory <=#Tp 1'b1; |
end |
reg tx_burst_en; |
reg rx_burst_en; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
|
wire ReadTxDataFromMemory_2; |
wire tx_burst; |
|
|
reg tx_burst_en; |
reg rx_burst_en; |
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
|
wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory; |
wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en; |
assign ReadTxDataFromMemory_2 = ReadTxDataFromMemory & |
~BlockReadTxDataFromMemory | (|tx_burst_cnt); |
|
assign tx_burst = ReadTxDataFromMemory_2 & tx_burst_en; |
|
wire [31:0] TxData_wb; |
wire ReadTxDataFromFifo_wb; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockReadTxDataFromMemory <= 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & |
(~cyc_cleared) & (!(TxAbortPacket_NotCleared | |
TxRetryPacket_NotCleared))) |
BlockReadTxDataFromMemory <= 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | |
TxRetryPacket) |
BlockReadTxDataFromMemory <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
else |
if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared))) |
BlockReadTxDataFromMemory <=#Tp 1'b1; |
else |
if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket) |
BlockReadTxDataFromMemory <=#Tp 1'b0; |
end |
`define TX_BURST_EN_CONDITION (txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4))) |
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
|
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
|
assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i; |
wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt; |
reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt; |
reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt; |
wire rx_burst; |
wire enough_data_in_rxfifo_for_burst; |
wire enough_data_in_rxfifo_for_burst_plus1; |
|
wire rx_burst; |
wire enough_data_in_rxfifo_for_burst; |
wire enough_data_in_rxfifo_for_burst_plus1; |
// Enabling master wishbone access to the memory for two devices TX and RX. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= 30'h0; |
m_wb_cyc_o <= 1'b0; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'h0; |
cyc_cleared<= 1'b0; |
tx_burst_cnt<= 0; |
rx_burst_cnt<= 0; |
IncrTxPointer<= 1'b0; |
tx_burst_en<= 1'b1; |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b0; |
`ifdef BURST_4BEAT |
m_wb_bte_o <= 2'b00; |
`endif |
`endif |
end |
else |
begin |
// Switching between two stages depends on enable signals |
casex ({MasterWbTX, |
MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory_r, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}) // synopsys parallel_case |
|
8'b00_10_00_10, // Idle and MRB needed |
8'b10_1x_10_1x, // MRB continues |
8'b10_10_01_10, // Clear (previously MR) and MRB needed |
8'b01_1x_01_1x: // Clear (previously MW) and MRB needed |
begin |
MasterWbTX <= 1'b1; // tx burst |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
tx_burst_cnt <= tx_burst_cnt+3'h1; |
if(tx_burst_cnt==0) |
m_wb_adr_o <= TxPointerMSB; |
else |
m_wb_adr_o <= m_wb_adr_o+1'b1; |
|
// Enabling master wishbone access to the memory for two devices TX and RX. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp 30'h0; |
m_wb_cyc_o <=#Tp 1'b0; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'h0; |
cyc_cleared<=#Tp 1'b0; |
tx_burst_cnt<=#Tp 0; |
rx_burst_cnt<=#Tp 0; |
IncrTxPointer<=#Tp 1'b0; |
tx_burst_en<=#Tp 1'b1; |
rx_burst_en<=#Tp 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
`endif |
end |
else |
begin |
// Switching between two stages depends on enable signals |
casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case |
8'b00_10_00_10, // Idle and MRB needed |
8'b10_1x_10_1x, // MRB continues |
8'b10_10_01_10, // Clear (previously MR) and MRB needed |
8'b01_1x_01_1x : // Clear (previously MW) and MRB needed |
begin |
MasterWbTX <=#Tp 1'b1; // tx burst |
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b1; |
tx_burst_cnt <=#Tp tx_burst_cnt+3'h1; |
if(tx_burst_cnt==0) |
m_wb_adr_o <=#Tp TxPointerMSB; |
else |
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; |
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
tx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b010; |
`ifdef BURST_4BEAT |
m_wb_bte_o <= 2'b01; |
`endif |
`endif |
end |
end // case: 8'b00_10_00_10,... |
`ifdef ETH_RX_BURST_EN |
8'b00_x1_00_x1, // Idle and MWB needed |
8'b01_x1_10_x1, // MWB continues |
8'b01_01_01_01, // Clear (previously MW) and MWB needed |
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed |
begin |
MasterWbTX <= 1'b0; // rx burst |
MasterWbRX <= 1'b1; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b1; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
cyc_cleared<= 1'b0; |
rx_burst_cnt <= rx_burst_cnt+3'h1; |
|
if(tx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
tx_burst_en<=#Tp 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b010; |
`endif |
end |
end |
8'b00_x1_00_x1, // Idle and MWB needed |
8'b01_x1_10_x1, // MWB continues |
8'b01_01_01_01, // Clear (previously MW) and MWB needed |
8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed |
begin |
MasterWbTX <=#Tp 1'b0; // rx burst |
MasterWbRX <=#Tp 1'b1; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
IncrTxPointer<=#Tp 1'b0; |
cyc_cleared<=#Tp 1'b0; |
rx_burst_cnt <=#Tp rx_burst_cnt+3'h1; |
if(rx_burst_cnt==0) |
m_wb_adr_o <= RxPointerMSB; |
else |
m_wb_adr_o <= m_wb_adr_o+1'b1; |
|
if(rx_burst_cnt==0) |
m_wb_adr_o <=#Tp RxPointerMSB; |
else |
m_wb_adr_o <=#Tp m_wb_adr_o+1'b1; |
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
rx_burst_en<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
`ifdef BURST_4BEAT |
m_wb_cti_o <= 3'b010; |
m_wb_bte_o <= 2'b01; |
`endif |
`endif |
end |
end // case: 8'b00_x1_00_x1,... |
`endif // `ifdef ETH_RX_BURST_EN |
8'b00_x1_00_x0 ,//idle and MW is needed (data write to rx buffer) |
8'b01_x1_00_x0 :// Sometimes gets caught changing states - JB |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= !RxBufferEmpty; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= !RxBufferEmpty; |
m_wb_we_o <= !RxBufferEmpty; |
m_wb_sel_o <= RxByteSel; |
IncrTxPointer<= 1'b0; |
`ifdef ETH_WISHBONE_B3 |
`ifdef ETH_RX_BURST_EN |
`ifdef BURST_4BEAT |
if ((RxPointerMSB[3:2]==2'b00) & !RxBufferEmpty & |
enough_data_in_rxfifo_for_burst & !m_wb_cyc_o) |
// Added "& !_m_wb_cyc_o" here to stop burst signals |
// going high during a transfer |
begin |
rx_burst_en<= 1'b1; |
m_wb_cti_o <= 3'b010; |
m_wb_bte_o <= 2'b01; |
rx_burst_cnt<= 1; |
end |
`endif |
`endif |
`endif // `ifdef ETH_WISHBONE_B3 |
|
end |
8'b00_10_00_00 : // idle and MR is needed (data read from tx |
// buffer) |
begin |
MasterWbTX <= 1'b1; |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
IncrTxPointer<= 1'b1; |
`ifdef BURST_4BEAT |
|
if(rx_burst_cnt==(`ETH_BURST_LENGTH-1)) |
begin |
rx_burst_en<=#Tp 1'b0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b111; |
`endif |
end |
else |
begin |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b010; |
`endif |
end |
end |
8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
IncrTxPointer<=#Tp 1'b0; |
end |
8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <=#Tp 1'b1; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp TxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
IncrTxPointer<=#Tp 1'b1; |
end |
8'b10_10_01_00, // MR and MR is needed (data read from tx buffer) |
8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer) |
begin |
MasterWbTX <=#Tp 1'b1; |
MasterWbRX <=#Tp 1'b0; |
m_wb_adr_o <=#Tp TxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b0; |
m_wb_sel_o <=#Tp 4'hf; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b1; |
end |
8'b01_01_01_00, // MW and MW needed (data write to rx buffer) |
8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b1; |
m_wb_adr_o <=#Tp RxPointerMSB; |
m_wb_cyc_o <=#Tp 1'b1; |
m_wb_we_o <=#Tp 1'b1; |
m_wb_sel_o <=#Tp RxByteSel; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b0; |
end |
8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access) |
8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access) |
8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access) |
8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access) |
begin |
m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started |
cyc_cleared<=#Tp 1'b1; |
IncrTxPointer<=#Tp 1'b0; |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
rx_burst_cnt<=#Tp 0; |
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
`endif |
end |
8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access) |
8'bxx_00_01_00 : // Between cyc_cleared request was cleared |
begin |
MasterWbTX <=#Tp 1'b0; |
MasterWbRX <=#Tp 1'b0; |
m_wb_cyc_o <=#Tp 1'b0; |
cyc_cleared<=#Tp 1'b0; |
IncrTxPointer<=#Tp 1'b0; |
rx_burst_cnt<=#Tp 0; |
rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used. |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <=#Tp 3'b0; |
`endif |
end |
8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access) |
begin |
tx_burst_cnt<=#Tp 0; |
tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4)); |
end |
default: // Don't touch |
begin |
MasterWbTX <=#Tp MasterWbTX; |
MasterWbRX <=#Tp MasterWbRX; |
m_wb_cyc_o <=#Tp m_wb_cyc_o; |
m_wb_sel_o <=#Tp m_wb_sel_o; |
IncrTxPointer<=#Tp IncrTxPointer; |
end |
endcase |
end |
end |
// Attempt ethernet bugfix, start bursts later |
if ((TxPointerMSB[3:2]==2'b00) && `TX_BURST_EN_CONDITION) |
begin |
`ifdef TX_BURST_EN_VERBOSE |
$display("(%t)(%m): %b enabling tx_burst_en",$time, |
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2, |
WriteRxDataToMemory,MasterAccessFinished, |
cyc_cleared,tx_burst,rx_burst}); |
`endif |
tx_burst_en<= 1'b1; |
tx_burst_cnt <= 3'h1; |
|
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b010; |
m_wb_bte_o <= 2'b01; |
`endif |
end |
`endif |
end |
8'b10_10_01_00,// MR and MR is needed (data read from tx buffer) |
8'b01_1x_01_0x :// MW and MR is needed (data read from tx |
// buffer) |
begin |
MasterWbTX <= 1'b1; // Only switch to TX here |
// when not end of RX |
MasterWbRX <= 1'b0; |
m_wb_adr_o <= TxPointerMSB; |
m_wb_cyc_o <= 1'b1; |
m_wb_we_o <= 1'b0; |
m_wb_sel_o <= 4'hf; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b1; |
`ifdef BURST_4BEAT |
if ((TxPointerMSB[3:2]==2'b00) & `TX_BURST_EN_CONDITION) |
begin |
`ifdef TX_BURST_EN_VERBOSE |
$display("(%t)(%m): %b enabling tx_burst_en",$time, |
{MasterWbTX,MasterWbRX, |
ReadTxDataFromMemory_2, |
WriteRxDataToMemory, |
MasterAccessFinished, |
cyc_cleared, |
tx_burst, |
rx_burst}); |
`endif |
tx_burst_en<= 1'b1; |
tx_burst_cnt <= 3'h1; |
`ifdef ETH_WISHBONE_B3 |
m_wb_cti_o <= 3'b010; |
m_wb_bte_o <= 2'b01; |
`endif |
end |
`endif |
|
end |
8'b01_01_01_00,// MW and MW needed (data write to rx buffer) |
8'b10_x1_01_x0 ://MR and MW is needed (data write to rx buffer) |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= !RxBufferEmpty; |
rx_burst_cnt<= 0; |
m_wb_adr_o <= RxPointerMSB; |
m_wb_cyc_o <= !RxBufferEmpty; |
m_wb_we_o <= !RxBufferEmpty; |
m_wb_sel_o <= RxByteSel; |
`ifdef ETH_WISHBONE_B3 |
`ifdef ETH_RX_BURST_EN |
`ifdef BURST_4BEAT |
if ((RxPointerMSB[3:2]==2'b00) & |
enough_data_in_rxfifo_for_burst & !RxBufferEmpty) |
//enough_data_in_rxfifo_for_burst_plus1) |
|
wire TxFifoClear; |
|
begin |
rx_burst_en<= 1'b1; |
m_wb_cti_o <= 3'b010; |
m_wb_bte_o <= 2'b01; |
rx_burst_cnt<= 1; |
end |
`endif |
`endif // `ifdef ETH_RX_BURST_EN |
`endif // `ifdef ETH_WISHBONE_B3 |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
end |
8'b01_01_10_00,// MW and MW needed (cycle is cleared between |
// previous and next access) |
8'b01_1x_10_x0,// MW and MW or MR or MRB needed (cycle is |
// cleared between previous and next access) |
8'b10_10_10_00,// MR and MR needed (cycle is cleared between |
// previous and next access) |
8'b10_x1_10_0x :// MR and MR or MW or MWB (cycle is cleared |
// between previous and next access) |
begin |
m_wb_cyc_o <= 1'b0;// whatever and master read or write is |
// needed. We need to clear m_wb_cyc_o |
// before next access is started |
cyc_cleared<= 1'b1; |
IncrTxPointer<= 1'b0; |
tx_burst_cnt<= 0; |
`ifdef BURST_4BEAT |
// Caused a bug! |
// if (TxPointerMSB[3:2]==2'b00) |
//tx_burst_en<= `TX_BURST_EN_CONDITION; |
// Set this to 0 here |
tx_burst_en<= 0; |
|
`endif |
rx_burst_cnt<= 0; |
`ifdef ETH_WISHBONE_B3 |
m_wb_bte_o <= 2'b00; |
m_wb_cti_o <= 3'b0; |
`endif |
end |
8'bxx_00_10_00,// whatever and no master read or write is needed |
// (ack or err comes finishing previous access) |
8'bxx_00_01_00 : // Between cyc_cleared request was cleared |
begin |
MasterWbTX <= 1'b0; |
MasterWbRX <= 1'b0; |
m_wb_cyc_o <= 1'b0; |
cyc_cleared<= 1'b0; |
IncrTxPointer<= 1'b0; |
rx_burst_cnt<= 0; |
m_wb_bte_o <= 2'b00; |
m_wb_cti_o <= 3'b0; |
end |
8'b00_00_00_00: // whatever and no master read or write is |
// needed (ack or err comes finishing previous |
// access) |
begin |
tx_burst_cnt<= 0; |
`ifdef BURST_4BEAT |
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket); |
// This caused tx_burst to remain set between |
// transmits, and sometimes we would burst immediately |
// and maybe get the wrong data because the offset of |
// the buffer pointer wasn't 16-byte aligned. |
//if (TxPointerMSB[3:2]==2'b00) |
// tx_burst_en<= `TX_BURST_EN_CONDITION; |
|
eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH) |
tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb), |
.clk(WB_CLK_I), .reset(Reset), |
.write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), |
.clear(TxFifoClear), .full(TxBufferFull), |
.almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty), |
.empty(TxBufferEmpty), .cnt(txfifo_cnt) |
); |
// Fix for transmit problems... maybe - jb |
if(TxEn & TxEn_q & TxPointerRead & (ram_do[3:0]===4'h0)) |
begin |
`ifdef TX_BURST_EN_VERBOSE |
$display("(%t)(%m): %b enabling tx_burst_en",$time, |
{MasterWbTX,MasterWbRX,ReadTxDataFromMemory_2, |
WriteRxDataToMemory,MasterAccessFinished, |
cyc_cleared,tx_burst,rx_burst}); |
`endif |
tx_burst_en<= `TX_BURST_EN_CONDITION; |
end |
else |
tx_burst_en<= 0; |
`endif |
end |
default: // Don't touch |
begin |
MasterWbTX <= MasterWbTX; |
MasterWbRX <= MasterWbRX; |
m_wb_cyc_o <= m_wb_cyc_o; |
m_wb_sel_o <= m_wb_sel_o; |
IncrTxPointer<= IncrTxPointer; |
end |
endcase |
end |
end |
|
|
reg StartOccured; |
reg TxStartFrm_sync1; |
reg TxStartFrm_sync2; |
reg TxStartFrm_syncb1; |
reg TxStartFrm_syncb2; |
wire TxFifoClear; |
|
assign TxFifoClear = (TxAbortPacket | TxRetryPacket | StartTxPointerRead); |
|
eth_fifo |
#( |
`ETH_TX_FIFO_DATA_WIDTH, |
`ETH_TX_FIFO_DEPTH, |
`ETH_TX_FIFO_CNT_WIDTH |
) |
tx_fifo |
( |
.data_in(m_wb_dat_i), |
.data_out(TxData_wb), |
.clk(WB_CLK_I), |
.reset(Reset), |
.write(MasterWbTX & m_wb_ack_i), |
.read(ReadTxDataFromFifo_wb & ~TxBufferEmpty), |
.clear(TxFifoClear), |
.full(TxBufferFull), |
.almost_full(TxBufferAlmostFull), |
.almost_empty(TxBufferAlmostEmpty), |
.empty(TxBufferEmpty), |
.cnt(txfifo_cnt) |
); |
|
|
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_wb <=#Tp 1'b0; |
else |
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)) |
TxStartFrm_wb <=#Tp 1'b1; |
else |
if(TxStartFrm_syncb2) |
TxStartFrm_wb <=#Tp 1'b0; |
end |
reg StartOccured; |
reg TxStartFrm_sync1; |
reg TxStartFrm_sync2; |
reg TxStartFrm_syncb1; |
reg TxStartFrm_syncb2; |
|
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
StartOccured <=#Tp 1'b0; |
else |
if(TxStartFrm_wb) |
StartOccured <=#Tp 1'b1; |
else |
if(ResetTxBDReady) |
StartOccured <=#Tp 1'b0; |
end |
|
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync1 <=#Tp 1'b0; |
else |
TxStartFrm_sync1 <=#Tp TxStartFrm_wb; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync2 <=#Tp 1'b0; |
else |
TxStartFrm_sync2 <=#Tp TxStartFrm_sync1; |
end |
// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_wb <= 1'b0; |
else |
if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0)) |
TxStartFrm_wb <= 1'b1; |
else |
if(TxStartFrm_syncb2) |
TxStartFrm_wb <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb1 <=#Tp 1'b0; |
else |
TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2; |
end |
// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's |
// blocked. |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
StartOccured <= 1'b0; |
else |
if(TxStartFrm_wb) |
StartOccured <= 1'b1; |
else |
if(ResetTxBDReady) |
StartOccured <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb2 <=#Tp 1'b0; |
else |
TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1; |
end |
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync1 <= 1'b0; |
else |
TxStartFrm_sync1 <= TxStartFrm_wb; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm <=#Tp 1'b0; |
else |
if(TxStartFrm_sync2) |
TxStartFrm <=#Tp 1'b1; |
else |
if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) |
TxStartFrm <=#Tp 1'b0; |
end |
// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_sync2 <= 1'b0; |
else |
TxStartFrm_sync2 <= TxStartFrm_sync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb1 <= 1'b0; |
else |
TxStartFrm_syncb1 <= TxStartFrm_sync2; |
end |
|
// TxEndFrm_wb: indicator of the end of frame |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEndFrm_wb <=#Tp 1'b0; |
else |
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) |
TxEndFrm_wb <=#Tp 1'b1; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxEndFrm_wb <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxStartFrm_syncb2 <= 1'b0; |
else |
TxStartFrm_syncb2 <= TxStartFrm_syncb1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxStartFrm <= 1'b0; |
else |
if(TxStartFrm_sync2) |
TxStartFrm <= 1'b1; |
else |
if(TxUsedData_q | ~TxStartFrm_sync2 & |
(TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q))) |
TxStartFrm <= 1'b0; |
end |
// End: Generation of the TxStartFrm_wb which is then synchronized to the |
// MTxClk |
|
// Marks which bytes are valid within the word. |
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0; |
|
reg LatchValidBytes; |
reg LatchValidBytes_q; |
// TxEndFrm_wb: indicator of the end of frame |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxEndFrm_wb <= 1'b0; |
else |
if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData) |
TxEndFrm_wb <= 1'b1; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxEndFrm_wb <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes <=#Tp 1'b0; |
else |
if(TxLengthLt4 & TxBDReady) |
LatchValidBytes <=#Tp 1'b1; |
else |
LatchValidBytes <=#Tp 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes_q <=#Tp 1'b0; |
else |
LatchValidBytes_q <=#Tp LatchValidBytes; |
end |
// Marks which bytes are valid within the word. |
assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0; |
|
reg LatchValidBytes; |
reg LatchValidBytes_q; |
|
// Latching valid bytes |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxValidBytesLatched <=#Tp 2'h0; |
else |
if(LatchValidBytes & ~LatchValidBytes_q) |
TxValidBytesLatched <=#Tp TxValidBytes; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxValidBytesLatched <=#Tp 2'h0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes <= 1'b0; |
else |
if(TxLengthLt4 & TxBDReady) |
LatchValidBytes <= 1'b1; |
else |
LatchValidBytes <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
LatchValidBytes_q <= 1'b0; |
else |
LatchValidBytes_q <= LatchValidBytes; |
end |
|
assign TxIRQEn = TxStatus[14]; |
assign WrapTxStatusBit = TxStatus[13]; |
assign PerPacketPad = TxStatus[12]; |
assign PerPacketCrcEn = TxStatus[11]; |
|
// Latching valid bytes |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxValidBytesLatched <= 2'h0; |
else |
if(LatchValidBytes & ~LatchValidBytes_q) |
TxValidBytesLatched <= TxValidBytes; |
else |
if(TxRetryPulse | TxDonePulse | TxAbortPulse) |
TxValidBytesLatched <= 2'h0; |
end |
|
assign RxIRQEn = RxStatus[14]; |
assign WrapRxStatusBit = RxStatus[13]; |
|
assign TxIRQEn = TxStatus[14]; |
assign WrapTxStatusBit = TxStatus[13]; |
assign PerPacketPad = TxStatus[12]; |
assign PerPacketCrcEn = TxStatus[11]; |
|
// Temporary Tx and Rx buffer descriptor address |
`ifdef POLL_TXBDS |
assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) |
`else |
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) |
`endif |
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD |
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address) |
|
assign RxIRQEn = RxStatus[14]; |
assign WrapRxStatusBit = RxStatus[13]; |
|
// Latching Tx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDAddress <=#Tp 7'h0; |
else if (r_TxEn & (~r_TxEn_q)) |
TxBDAddress <=#Tp 7'h0; |
`ifdef POLL_TXBDS |
else if (TxStatusWrite | TxBDNotReady) |
`else |
else if (TxStatusWrite) |
|
// Temporary Tx and Rx buffer descriptor address |
`ifdef TXBD_POLL |
assign TempTxBDAddress[7:1] = {7{ (TxStatusWrite|TxBDNotReady) & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) -- jb |
`else |
assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD) |
`endif |
TxBDAddress <=#Tp TempTxBDAddress; |
end |
assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD |
{7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address) |
|
|
// Latching Rx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDAddress <=#Tp 7'h0; |
else if(r_RxEn & (~r_RxEn_q)) |
RxBDAddress <=#Tp r_TxBDNum[6:0]; |
else if(RxStatusWrite) |
RxBDAddress <=#Tp TempRxBDAddress; |
end |
// Latching Tx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxBDAddress <= 7'h0; |
else if (r_TxEn & (~r_TxEn_q)) |
TxBDAddress <= 7'h0; |
`ifdef TXBD_POLL |
else if (TxStatusWrite | TxBDNotReady) // -- jb |
`else |
else if (TxStatusWrite) |
`endif |
TxBDAddress <= TempTxBDAddress; |
end |
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost}; |
|
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched}; |
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched}; |
// Latching Rx buffer descriptor address |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDAddress <= 7'h0; |
else if(r_RxEn & (~r_RxEn_q)) |
RxBDAddress <= r_TxBDNum[6:0]; |
else if(RxStatusWrite) |
RxBDAddress <= TempRxBDAddress; |
end |
|
wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], |
RetryLimit, LateCollLatched, DeferLatched, |
CarrierSenseLost}; |
|
// Signals used for various purposes |
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q; |
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q; |
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q; |
assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, |
RxStatusInLatched}; |
assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, |
TxStatusInLatched}; |
|
|
// Signals used for various purposes |
assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q; |
assign TxDonePulse = TxDone_wb & ~TxDone_wb_q; |
assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q; |
|
// Generating delayed signals |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
begin |
TxAbort_q <=#Tp 1'b0; |
TxRetry_q <=#Tp 1'b0; |
TxUsedData_q <=#Tp 1'b0; |
end |
else |
begin |
TxAbort_q <=#Tp TxAbort; |
TxRetry_q <=#Tp TxRetry; |
TxUsedData_q <=#Tp TxUsedData; |
end |
end |
|
// Generating delayed signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
TxDone_wb_q <=#Tp 1'b0; |
TxAbort_wb_q <=#Tp 1'b0; |
TxRetry_wb_q <=#Tp 1'b0; |
end |
else |
begin |
TxDone_wb_q <=#Tp TxDone_wb; |
TxAbort_wb_q <=#Tp TxAbort_wb; |
TxRetry_wb_q <=#Tp TxRetry_wb; |
end |
end |
|
// Generating delayed signals |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
begin |
TxAbort_q <= 1'b0; |
TxRetry_q <= 1'b0; |
TxUsedData_q <= 1'b0; |
end |
else |
begin |
TxAbort_q <= TxAbort; |
TxRetry_q <= TxRetry; |
TxUsedData_q <= TxUsedData; |
end |
end |
|
reg TxAbortPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket <=#Tp 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket <=#Tp 1'b1; |
else |
TxAbortPacket <=#Tp 1'b0; |
end |
// Generating delayed signals |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
TxDone_wb_q <= 1'b0; |
TxAbort_wb_q <= 1'b0; |
TxRetry_wb_q <= 1'b0; |
end |
else |
begin |
TxDone_wb_q <= TxDone_wb; |
TxAbort_wb_q <= TxAbort_wb; |
TxRetry_wb_q <= TxRetry_wb; |
end |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxEn & TxEn_q & TxAbortPacket_NotCleared) |
TxAbortPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) | |
TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket_NotCleared <=#Tp 1'b1; |
end |
reg TxAbortPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & |
(~TxAbortPacketBlocked) | TxAbort_wb & (~MasterWbTX) & |
(~TxAbortPacketBlocked)) |
TxAbortPacket <= 1'b1; |
else |
TxAbortPacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacketBlocked <=#Tp 1'b0; |
else |
if(!TxAbort_wb & TxAbort_wb_q) |
TxAbortPacketBlocked <=#Tp 1'b0; |
else |
if(TxAbortPacket) |
TxAbortPacketBlocked <=#Tp 1'b1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxAbortPacket_NotCleared) |
TxAbortPacket_NotCleared <= 1'b0; |
else |
if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & |
MasterAccessFinished & (~TxAbortPacketBlocked) | TxAbort_wb & |
(~MasterWbTX) & (~TxAbortPacketBlocked)) |
TxAbortPacket_NotCleared <= 1'b1; |
end |
|
|
reg TxRetryPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket <=#Tp 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket <=#Tp 1'b1; |
else |
TxRetryPacket <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortPacketBlocked <= 1'b0; |
else |
if(!TxAbort_wb & TxAbort_wb_q) |
TxAbortPacketBlocked <= 1'b0; |
else |
if(TxAbortPacket) |
TxAbortPacketBlocked <= 1'b1; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
else |
if(StartTxBDRead) |
TxRetryPacket_NotCleared <=#Tp 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked | |
TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked) |
TxRetryPacket_NotCleared <=#Tp 1'b1; |
end |
reg TxRetryPacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & |
!TxRetryPacketBlocked) |
TxRetryPacket <= 1'b1; |
else |
TxRetryPacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacketBlocked <=#Tp 1'b0; |
else |
if(!TxRetry_wb & TxRetry_wb_q) |
TxRetryPacketBlocked <=#Tp 1'b0; |
else |
if(TxRetryPacket) |
TxRetryPacketBlocked <=#Tp 1'b1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(StartTxBDRead) |
TxRetryPacket_NotCleared <= 1'b0; |
else |
if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxRetryPacketBlocked | TxRetry_wb & !MasterWbTX & |
!TxRetryPacketBlocked) |
TxRetryPacket_NotCleared <= 1'b1; |
end |
|
|
reg TxDonePacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket <=#Tp 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked | |
TxDone_wb & !MasterWbTX & !TxDonePacketBlocked) |
TxDonePacket <=#Tp 1'b1; |
else |
TxDonePacket <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetryPacketBlocked <= 1'b0; |
else |
if(!TxRetry_wb & TxRetry_wb_q) |
TxRetryPacketBlocked <= 1'b0; |
else |
if(TxRetryPacket) |
TxRetryPacketBlocked <= 1'b1; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
else |
if(TxEn & TxEn_q & TxDonePacket_NotCleared) |
TxDonePacket_NotCleared <=#Tp 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) | |
TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked)) |
TxDonePacket_NotCleared <=#Tp 1'b1; |
end |
reg TxDonePacketBlocked; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & |
!TxDonePacketBlocked | TxDone_wb & !MasterWbTX & |
!TxDonePacketBlocked) |
TxDonePacket <= 1'b1; |
else |
TxDonePacket <= 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacketBlocked <=#Tp 1'b0; |
else |
if(!TxDone_wb & TxDone_wb_q) |
TxDonePacketBlocked <=#Tp 1'b0; |
else |
if(TxDonePacket) |
TxDonePacketBlocked <=#Tp 1'b1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxEn & TxEn_q & TxDonePacket_NotCleared) |
TxDonePacket_NotCleared <= 1'b0; |
else |
if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished |
& (~TxDonePacketBlocked) | TxDone_wb & !MasterWbTX |
& (~TxDonePacketBlocked)) |
TxDonePacket_NotCleared <= 1'b1; |
end |
|
|
// Indication of the last word |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LastWord <=#Tp 1'b0; |
else |
if((TxEndFrm | TxAbort | TxRetry) & Flop) |
LastWord <=#Tp 1'b0; |
else |
if(TxUsedData & Flop & TxByteCnt == 2'h3) |
LastWord <=#Tp TxEndFrm_wb; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDonePacketBlocked <= 1'b0; |
else |
if(!TxDone_wb & TxDone_wb_q) |
TxDonePacketBlocked <= 1'b0; |
else |
if(TxDonePacket) |
TxDonePacketBlocked <= 1'b1; |
end |
|
|
// Tx end frame generation |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxEndFrm <=#Tp 1'b0; |
else |
if(Flop & TxEndFrm | TxAbort | TxRetry_q) |
TxEndFrm <=#Tp 1'b0; |
else |
if(Flop & LastWord) |
begin |
case (TxValidBytesLatched) // synopsys parallel_case |
1 : TxEndFrm <=#Tp TxByteCnt == 2'h0; |
2 : TxEndFrm <=#Tp TxByteCnt == 2'h1; |
3 : TxEndFrm <=#Tp TxByteCnt == 2'h2; |
0 : TxEndFrm <=#Tp TxByteCnt == 2'h3; |
default : TxEndFrm <=#Tp 1'b0; |
endcase |
end |
end |
// Indication of the last word |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LastWord <= 1'b0; |
else |
if((TxEndFrm | TxAbort | TxRetry) & Flop) |
LastWord <= 1'b0; |
else |
if(TxUsedData & Flop & TxByteCnt == 2'h3) |
LastWord <= TxEndFrm_wb; |
end |
|
|
// Tx data selection (latching) |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxData <=#Tp 0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering |
2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering |
2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering |
2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering |
endcase |
else |
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3) |
TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering |
else |
if(TxUsedData & Flop) |
begin |
case(TxByteCnt) // synopsys parallel_case |
0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering |
1 : TxData <=#Tp TxDataLatched[23:16]; |
2 : TxData <=#Tp TxDataLatched[15:8]; |
3 : TxData <=#Tp TxDataLatched[7:0]; |
endcase |
end |
end |
// Tx end frame generation |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxEndFrm <= 1'b0; |
else |
if(Flop & TxEndFrm | TxAbort | TxRetry_q) |
TxEndFrm <= 1'b0; |
else |
if(Flop & LastWord) |
begin |
case (TxValidBytesLatched) // synopsys parallel_case |
1 : TxEndFrm <= TxByteCnt == 2'h0; |
2 : TxEndFrm <= TxByteCnt == 2'h1; |
3 : TxEndFrm <= TxByteCnt == 2'h2; |
0 : TxEndFrm <= TxByteCnt == 2'h3; |
default : TxEndFrm <= 1'b0; |
endcase |
end |
end |
|
|
// Latching tx data |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDataLatched[31:0] <=#Tp 32'h0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
TxDataLatched[31:0] <=#Tp TxData_wb[31:0]; |
end |
// Tx data selection (latching) |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxData <= 0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxData <= TxData_wb[31:24];// Big Endian Byte Ordering |
2'h1 : TxData <= TxData_wb[23:16];// Big Endian Byte Ordering |
2'h2 : TxData <= TxData_wb[15:08];// Big Endian Byte Ordering |
2'h3 : TxData <= TxData_wb[07:00];// Big Endian Byte Ordering |
endcase |
else |
if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3) |
TxData <= TxData_wb[31:24];// Big Endian Byte Ordering |
else |
if(TxUsedData & Flop) |
begin |
case(TxByteCnt) // synopsys parallel_case |
// Big Endian Byte Ordering |
0 : TxData <= TxDataLatched[31:24]; |
1 : TxData <= TxDataLatched[23:16]; |
2 : TxData <= TxDataLatched[15:8]; |
3 : TxData <= TxDataLatched[7:0]; |
endcase |
end |
end |
|
|
// Tx under run |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_wb <=#Tp 1'b0; |
else |
if(TxAbortPulse) |
TxUnderRun_wb <=#Tp 1'b0; |
else |
if(TxBufferEmpty & ReadTxDataFromFifo_wb) |
TxUnderRun_wb <=#Tp 1'b1; |
end |
// Latching tx data |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxDataLatched[31:0] <= 32'h0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & |
TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & |
TxByteCnt == 2'h0) |
TxDataLatched[31:0] <= TxData_wb[31:0]; |
end |
|
|
reg TxUnderRun_sync1; |
// Tx under run |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_wb <= 1'b0; |
else |
if(TxAbortPulse) |
TxUnderRun_wb <= 1'b0; |
else |
if(TxBufferEmpty & ReadTxDataFromFifo_wb) |
TxUnderRun_wb <= 1'b1; |
end |
|
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_sync1 <=#Tp 1'b0; |
else |
if(TxUnderRun_wb) |
TxUnderRun_sync1 <=#Tp 1'b1; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun_sync1 <=#Tp 1'b0; |
end |
|
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun <=#Tp 1'b0; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun <=#Tp 1'b0; |
else |
if(TxUnderRun_sync1) |
TxUnderRun <=#Tp 1'b1; |
end |
reg TxUnderRun_sync1; |
|
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun_sync1 <= 1'b0; |
else |
if(TxUnderRun_wb) |
TxUnderRun_sync1 <= 1'b1; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun_sync1 <= 1'b0; |
end |
|
// Tx Byte counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxByteCnt <=#Tp 2'h0; |
else |
if(TxAbort_q | TxRetry_q) |
TxByteCnt <=#Tp 2'h0; |
else |
if(TxStartFrm & ~TxUsedData) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxByteCnt <=#Tp 2'h1; |
2'h1 : TxByteCnt <=#Tp 2'h2; |
2'h2 : TxByteCnt <=#Tp 2'h3; |
2'h3 : TxByteCnt <=#Tp 2'h0; |
endcase |
else |
if(TxUsedData & Flop) |
TxByteCnt <=#Tp TxByteCnt + 1'b1; |
end |
// Tx under run |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxUnderRun <= 1'b0; |
else |
if(BlockingTxStatusWrite_sync2) |
TxUnderRun <= 1'b0; |
else |
if(TxUnderRun_sync1) |
TxUnderRun <= 1'b1; |
end |
|
|
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
reg ReadTxDataFromFifo_sync1; |
reg ReadTxDataFromFifo_sync2; |
reg ReadTxDataFromFifo_sync3; |
reg ReadTxDataFromFifo_syncb1; |
reg ReadTxDataFromFifo_syncb2; |
reg ReadTxDataFromFifo_syncb3; |
// Tx Byte counter |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
TxByteCnt <= 2'h0; |
else |
if(TxAbort_q | TxRetry_q) |
TxByteCnt <= 2'h0; |
else |
if(TxStartFrm & ~TxUsedData) |
case(TxPointerLSB) // synopsys parallel_case |
2'h0 : TxByteCnt <= 2'h1; |
2'h1 : TxByteCnt <= 2'h2; |
2'h2 : TxByteCnt <= 2'h3; |
2'h3 : TxByteCnt <= 2'h0; |
endcase |
else |
if(TxUsedData & Flop) |
TxByteCnt <= TxByteCnt + 1'b1; |
end |
|
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_tck <=#Tp 1'b0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0) |
ReadTxDataFromFifo_tck <=#Tp 1'b1; |
else |
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3) |
ReadTxDataFromFifo_tck <=#Tp 1'b0; |
end |
// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
reg ReadTxDataFromFifo_sync1; |
reg ReadTxDataFromFifo_sync2; |
reg ReadTxDataFromFifo_sync3; |
reg ReadTxDataFromFifo_syncb1; |
reg ReadTxDataFromFifo_syncb2; |
reg ReadTxDataFromFifo_syncb3; |
|
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync1 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync2 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1; |
end |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_tck <= 1'b0; |
else |
if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & |
TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & |
TxByteCnt == 2'h0) |
ReadTxDataFromFifo_tck <= 1'b1; |
else |
if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3) |
ReadTxDataFromFifo_tck <= 1'b0; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb1 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2; |
end |
// Synchronizing TxStartFrm_wb to MTxClk |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync1 <= 1'b0; |
else |
ReadTxDataFromFifo_sync1 <= ReadTxDataFromFifo_tck; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb2 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync2 <= 1'b0; |
else |
ReadTxDataFromFifo_sync2 <= ReadTxDataFromFifo_sync1; |
end |
|
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb3 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2; |
end |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb1 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb1 <= ReadTxDataFromFifo_sync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync3 <=#Tp 1'b0; |
else |
ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2; |
end |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb2 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb2 <= ReadTxDataFromFifo_syncb1; |
end |
|
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3; |
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I |
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_syncb3 <= 1'b0; |
else |
ReadTxDataFromFifo_syncb3 <= ReadTxDataFromFifo_syncb2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ReadTxDataFromFifo_sync3 <= 1'b0; |
else |
ReadTxDataFromFifo_sync3 <= ReadTxDataFromFifo_sync2; |
end |
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetrySync1 <=#Tp 1'b0; |
else |
TxRetrySync1 <=#Tp TxRetry; |
end |
assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & |
~ReadTxDataFromFifo_sync3; |
// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization |
// to the WB_CLK_I |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetry_wb <=#Tp 1'b0; |
else |
TxRetry_wb <=#Tp TxRetrySync1; |
end |
|
// Synchronizing TxRetry signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetrySync1 <= 1'b0; |
else |
TxRetrySync1 <= TxRetry; |
end |
|
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDoneSync1 <=#Tp 1'b0; |
else |
TxDoneSync1 <=#Tp TxDone; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxRetry_wb <= 1'b0; |
else |
TxRetry_wb <= TxRetrySync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDone_wb <=#Tp 1'b0; |
else |
TxDone_wb <=#Tp TxDoneSync1; |
end |
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortSync1 <=#Tp 1'b0; |
else |
TxAbortSync1 <=#Tp TxAbort; |
end |
// Synchronized TxDone_wb signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDoneSync1 <= 1'b0; |
else |
TxDoneSync1 <= TxDone; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbort_wb <=#Tp 1'b0; |
else |
TxAbort_wb <=#Tp TxAbortSync1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxDone_wb <= 1'b0; |
else |
TxDone_wb <= TxDoneSync1; |
end |
|
// Synchronizing TxAbort signal (synchronized to WISHBONE clock) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbortSync1 <= 1'b0; |
else |
TxAbortSync1 <= TxAbort; |
end |
|
reg RxAbortSync1; |
reg RxAbortSync2; |
reg RxAbortSync3; |
reg RxAbortSync4; |
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxAbort_wb <= 1'b0; |
else |
TxAbort_wb <= TxAbortSync1; |
end |
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q; |
|
// Reading the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDRead <=#Tp 1'b0; |
else |
if(StartRxBDRead & ~RxReady) |
RxBDRead <=#Tp 1'b1; |
else |
if(RxBDReady) |
RxBDRead <=#Tp 1'b0; |
end |
reg RxAbortSync1; |
reg RxAbortSync2; |
reg RxAbortSync3; |
reg RxAbortSync4; |
reg RxAbortSyncb1; |
reg RxAbortSyncb2; |
|
assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | |
r_RxEn & ~r_RxEn_q; |
|
// Reading of the next receive buffer descriptor starts after reception status is |
// written to the previous one. |
// Reading the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDRead <= 1'b0; |
else |
if(StartRxBDRead) |
RxBDRead <= 1'b1; |
else |
if(RxBDReady) |
RxBDRead <= 1'b0; |
end |
|
// Latching READY status of the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDReady <=#Tp 1'b0; |
else |
if(RxPointerRead) |
RxBDReady <=#Tp 1'b0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning |
end |
|
// Latching Rx buffer descriptor status |
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatus <=#Tp 2'h0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxStatus <=#Tp ram_do[14:13]; |
end |
// Reading of the next receive buffer descriptor starts after reception |
// status is written to the previous one. |
|
// Latching READY status of the Rx buffer descriptor |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDReady <= 1'b0; |
else |
if(RxPointerRead) |
RxBDReady <= 1'b0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
// RxBDReady is sampled only once at the beginning |
RxBDReady <= ram_do[15]; |
end // always @ (posedge WB_CLK_I or posedge Reset) |
|
// RxReady generation |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxReady <=#Tp 1'b0; |
else |
if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q) |
RxReady <=#Tp 1'b0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxReady <=#Tp 1'b1; |
end |
// Indicate we just read the RX buffer descriptor and that RxBDReady is |
// valid. |
reg rx_just_read_bd; |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_just_read_bd <= 0; |
else if (rx_just_read_bd) |
rx_just_read_bd <= 0; |
else |
rx_just_read_bd <= (RxEn & RxEn_q & RxBDRead); |
|
// Signal to indicate we've checked and the RxBD we want to use is not free |
reg rx_waiting_for_bd_to_become_free; |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_waiting_for_bd_to_become_free <= 0; |
else if (rx_just_read_bd & !RxBDReady) |
// Assert if we read the BD and it's not cool |
rx_waiting_for_bd_to_become_free <= 1; |
else if (RxBDOK) |
rx_waiting_for_bd_to_become_free <= 0; |
|
|
// Reading Rx BD pointer |
|
// Latching Rx buffer descriptor status |
// Data is avaliable one cycle after the access is started (at that time |
// signal RxEn is not active) |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatus <= 2'h0; |
else |
if(RxEn & RxEn_q & RxBDRead) |
RxStatus <= ram_do[14:13]; |
end |
|
assign StartRxPointerRead = RxBDRead & RxBDReady; |
|
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerRead <=#Tp 1'b0; |
else |
if(StartRxPointerRead) |
RxPointerRead <=#Tp 1'b1; |
else |
if(RxEn & RxEn_q) |
RxPointerRead <=#Tp 1'b0; |
end |
// RxBDOK generation |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxBDOK <= 1'b0; |
else |
if(rx_wb_writeback_finished | RxAbortSync2 & ~RxAbortSync3 | |
~r_RxEn & r_RxEn_q) |
RxBDOK <= 1'b0; |
else |
if(RxBDReady) |
RxBDOK <= 1'b1; |
end |
|
// Reading Rx BD pointer |
assign StartRxPointerRead = RxBDRead & RxBDReady; |
|
//Latching Rx buffer pointer from buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerMSB <=#Tp 30'h0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerMSB <=#Tp ram_do[31:2]; |
else |
if(MasterWbRX & m_wb_ack_i) |
RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes) |
end |
// Reading Tx BD Pointer |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerRead <= 1'b0; |
else |
if(StartRxPointerRead) |
RxPointerRead <= 1'b1; |
else |
if(RxEn & RxEn_q) |
RxPointerRead <= 1'b0; |
end |
|
|
//Latching last addresses from buffer descriptor (used as byte-half-word indicator); |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerLSB_rst[1:0] <=#Tp 0; |
else |
if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active |
RxPointerLSB_rst[1:0] <=#Tp 0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0]; |
end |
//Latching Rx buffer pointer from buffer descriptor; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerMSB <= 30'h0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerMSB <= ram_do[31:2]; |
else |
if(MasterWbRX & m_wb_ack_i) |
// Word access (always word access. m_wb_sel_o are used for |
// selecting bytes) |
RxPointerMSB <= RxPointerMSB + 1'b1; |
end |
|
|
always @ (RxPointerLSB_rst) |
begin |
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case |
2'h0 : RxByteSel[3:0] = 4'hf; |
2'h1 : RxByteSel[3:0] = 4'h7; |
2'h2 : RxByteSel[3:0] = 4'h3; |
2'h3 : RxByteSel[3:0] = 4'h1; |
endcase |
end |
//Latching last addresses from buffer descriptor (used as byte-half-word |
// indicator); |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(MasterWbRX & m_wb_ack_i) |
// After first write all RxByteSel are active |
RxPointerLSB_rst[1:0] <= 0; |
else |
if(RxEn & RxEn_q & RxPointerRead) |
RxPointerLSB_rst[1:0] <= ram_do[1:0]; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxEn_needed <=#Tp 1'b0; |
else |
if(~RxReady & r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <=#Tp 1'b1; |
else |
if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <=#Tp 1'b0; |
end |
always @ (RxPointerLSB_rst) |
begin |
case(RxPointerLSB_rst[1:0]) // synopsys parallel_case |
2'h0 : RxByteSel[3:0] = 4'hf; |
2'h1 : RxByteSel[3:0] = 4'h7; |
2'h2 : RxByteSel[3:0] = 4'h3; |
2'h3 : RxByteSel[3:0] = 4'h1; |
endcase |
end |
|
|
// Reception status is written back to the buffer descriptor after the end of frame is detected. |
assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q; |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxEn_needed <= 1'b0; |
else |
if(/*~RxReady &*/ r_RxEn & WbEn & ~WbEn_q) |
RxEn_needed <= 1'b1; |
else |
if(RxPointerRead & RxEn & RxEn_q) |
RxEn_needed <= 1'b0; |
end |
|
reg RxEnableWindow; |
|
// Indicating that last byte is being reveived |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LastByteIn <=#Tp 1'b0; |
else |
if(ShiftWillEnd & (&RxByteCnt) | RxAbort) |
LastByteIn <=#Tp 1'b0; |
else |
if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow) |
LastByteIn <=#Tp 1'b1; |
end |
// Reception status is written back to the buffer descriptor after the end |
// of frame is detected. |
assign RxStatusWrite = rx_wb_writeback_finished & RxEn & RxEn_q; |
|
reg ShiftEnded_rck; |
reg ShiftEndedSync1; |
reg ShiftEndedSync2; |
reg ShiftEndedSync3; |
reg ShiftEndedSync_c1; |
reg ShiftEndedSync_c2; |
reg RxEnableWindow; |
|
wire StartShiftWillEnd; |
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow; |
// Indicating that last byte is being reveived |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LastByteIn <= 1'b0; |
else |
if(ShiftWillEnd & (&RxByteCnt) | RxAbort) |
LastByteIn <= 1'b0; |
else |
if(RxValid /*& RxReady*/& RxEndFrm & ~(&RxByteCnt) & RxEnableWindow) |
LastByteIn <= 1'b1; |
end |
|
// Indicating that data reception will end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftWillEnd <=#Tp 1'b0; |
else |
if(ShiftEnded_rck | RxAbort) |
ShiftWillEnd <=#Tp 1'b0; |
else |
if(StartShiftWillEnd) |
ShiftWillEnd <=#Tp 1'b1; |
end |
assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & |
RxEnableWindow; |
|
// Indicating that data reception will end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftWillEnd <= 1'b0; |
else |
if(ShiftEnded_rck | RxAbort) |
ShiftWillEnd <= 1'b0; |
else |
if(StartShiftWillEnd) |
ShiftWillEnd <= 1'b1; |
end |
|
// Receive byte counter |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxByteCnt <= 2'h0; |
else |
if(ShiftEnded_rck | RxAbort) |
RxByteCnt <= 2'h0; |
else |
if(RxValid & RxStartFrm /*& RxReady*/) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxByteCnt <= 2'h1; |
2'h1 : RxByteCnt <= 2'h2; |
2'h2 : RxByteCnt <= 2'h3; |
2'h3 : RxByteCnt <= 2'h0; |
endcase |
else |
if(RxValid & RxEnableWindow /*& RxReady*/ | LastByteIn) |
RxByteCnt <= RxByteCnt + 1'b1; |
end |
|
// Receive byte counter |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxByteCnt <=#Tp 2'h0; |
else |
if(ShiftEnded_rck | RxAbort) |
RxByteCnt <=#Tp 2'h0; |
else |
if(RxValid & RxStartFrm & RxReady) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxByteCnt <=#Tp 2'h1; |
2'h1 : RxByteCnt <=#Tp 2'h2; |
2'h2 : RxByteCnt <=#Tp 2'h3; |
2'h3 : RxByteCnt <=#Tp 2'h0; |
endcase |
else |
if(RxValid & RxEnableWindow & RxReady | LastByteIn) |
RxByteCnt <=#Tp RxByteCnt + 1'b1; |
end |
|
// Indicates how many bytes are valid within the last word |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxValidBytes <= 2'h1; |
else |
if(RxValid & RxStartFrm) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxValidBytes <= 2'h1; |
2'h1 : RxValidBytes <= 2'h2; |
2'h2 : RxValidBytes <= 2'h3; |
2'h3 : RxValidBytes <= 2'h0; |
endcase |
else |
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow) |
RxValidBytes <= RxValidBytes + 1'b1; |
end |
|
// Indicates how many bytes are valid within the last word |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxValidBytes <=#Tp 2'h1; |
else |
if(RxValid & RxStartFrm) |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0 : RxValidBytes <=#Tp 2'h1; |
2'h1 : RxValidBytes <=#Tp 2'h2; |
2'h2 : RxValidBytes <=#Tp 2'h3; |
2'h3 : RxValidBytes <=#Tp 2'h0; |
endcase |
else |
if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow) |
RxValidBytes <=#Tp RxValidBytes + 1'b1; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched1 <= 24'h0; |
else |
if(RxValid /*& RxReady*/ & ~LastByteIn) |
if(RxStartFrm) |
begin |
case(RxPointerLSB_rst) // synopsys parallel_case |
// Big Endian Byte Ordering |
2'h0: RxDataLatched1[31:24] <= RxData; |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
else if (RxEnableWindow) |
begin |
case(RxByteCnt) // synopsys parallel_case |
// Big Endian Byte Ordering |
2'h0: RxDataLatched1[31:24] <= RxData; |
2'h1: RxDataLatched1[23:16] <= RxData; |
2'h2: RxDataLatched1[15:8] <= RxData; |
2'h3: RxDataLatched1 <= RxDataLatched1; |
endcase |
end |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched1 <=#Tp 24'h0; |
else |
if(RxValid & RxReady & ~LastByteIn) |
if(RxStartFrm) |
begin |
case(RxPointerLSB_rst) // synopsys parallel_case |
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <=#Tp RxData; |
2'h2: RxDataLatched1[15:8] <=#Tp RxData; |
2'h3: RxDataLatched1 <=#Tp RxDataLatched1; |
endcase |
end |
else if (RxEnableWindow) |
begin |
case(RxByteCnt) // synopsys parallel_case |
2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering |
2'h1: RxDataLatched1[23:16] <=#Tp RxData; |
2'h2: RxDataLatched1[15:8] <=#Tp RxData; |
2'h3: RxDataLatched1 <=#Tp RxDataLatched1; |
endcase |
end |
end |
wire SetWriteRxDataToFifo; |
|
wire SetWriteRxDataToFifo; |
// Assembling data that will be written to the rx_fifo |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched2 <= 32'h0; |
else |
if(SetWriteRxDataToFifo & ~ShiftWillEnd) |
// Big Endian Byte Ordering |
RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; |
else |
if(SetWriteRxDataToFifo & ShiftWillEnd) |
case(RxValidBytes) // synopsys parallel_case |
// Big Endian Byte Ordering |
0 : RxDataLatched2 <= {RxDataLatched1[31:8], RxData}; |
1 : RxDataLatched2 <= {RxDataLatched1[31:24], 24'h0}; |
2 : RxDataLatched2 <= {RxDataLatched1[31:16], 16'h0}; |
3 : RxDataLatched2 <= {RxDataLatched1[31:8], 8'h0}; |
endcase |
end |
|
// Assembling data that will be written to the rx_fifo |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxDataLatched2 <=#Tp 32'h0; |
else |
if(SetWriteRxDataToFifo & ~ShiftWillEnd) |
RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
else |
if(SetWriteRxDataToFifo & ShiftWillEnd) |
case(RxValidBytes) // synopsys parallel_case |
0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering |
1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0}; |
2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0}; |
3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0}; |
endcase |
end |
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
reg WriteRxDataToFifoSync3; |
|
reg WriteRxDataToFifoSync1; |
reg WriteRxDataToFifoSync2; |
reg WriteRxDataToFifoSync3; |
|
// Indicating start of the reception process |
assign SetWriteRxDataToFifo = (RxValid &/* RxReady &*/ ~RxStartFrm & |
RxEnableWindow & (&RxByteCnt)) | |
(RxValid &/* RxReady &*/ RxStartFrm & |
(&RxPointerLSB_rst)) | |
(ShiftWillEnd & LastByteIn & (&RxByteCnt)); |
|
// Indicating start of the reception process |
assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) | |
(RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) | |
(ShiftWillEnd & LastByteIn & (&RxByteCnt)); |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifo <= 1'b0; |
else |
if(SetWriteRxDataToFifo & ~RxAbort) |
WriteRxDataToFifo <= 1'b1; |
else |
if(WriteRxDataToFifoSync2 | RxAbort) |
WriteRxDataToFifo <= 1'b0; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifo <=#Tp 1'b0; |
else |
if(SetWriteRxDataToFifo & ~RxAbort) |
WriteRxDataToFifo <=#Tp 1'b1; |
else |
if(WriteRxDataToFifoSync2 | RxAbort) |
WriteRxDataToFifo <=#Tp 1'b0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync1 <= 1'b0; |
else |
if(WriteRxDataToFifo) |
WriteRxDataToFifoSync1 <= 1'b1; |
else |
WriteRxDataToFifoSync1 <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync1 <=#Tp 1'b0; |
else |
if(WriteRxDataToFifo) |
WriteRxDataToFifoSync1 <=#Tp 1'b1; |
else |
WriteRxDataToFifoSync1 <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync2 <= 1'b0; |
else |
WriteRxDataToFifoSync2 <= WriteRxDataToFifoSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync2 <=#Tp 1'b0; |
else |
WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync3 <= 1'b0; |
else |
WriteRxDataToFifoSync3 <= WriteRxDataToFifoSync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
WriteRxDataToFifoSync3 <=#Tp 1'b0; |
else |
WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2; |
end |
wire WriteRxDataToFifo_wb; |
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & |
~WriteRxDataToFifoSync3; |
// Receive fifo selection register - JB |
reg [3:0] rx_shift_ended_wb_shr; |
reg rx_ethside_fifo_sel; |
reg rx_wbside_fifo_sel; |
|
wire WriteRxDataToFifo_wb; |
assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3; |
// Shift in this - our detection of end of data RX |
always @(posedge WB_CLK_I) |
rx_shift_ended_wb_shr <= {rx_shift_ended_wb_shr[2:0], |
ShiftEndedSync1 & ~ShiftEndedSync2}; |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_ethside_fifo_sel <= 0; |
else |
if(rx_shift_ended_wb_shr[3:2] == 2'b01) |
// Switch over whenever we've finished receiving last frame's data |
rx_ethside_fifo_sel <= ~rx_ethside_fifo_sel; |
|
// Wishbone side looks at other FIFO when we write back the status of this |
// received frame |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_wbside_fifo_sel <= 0; |
else |
if(rx_wb_writeback_finished & RxEn & RxEn_q) |
// Switch over whenever we've finished receiving last frame's data |
rx_wbside_fifo_sel <= ~rx_wbside_fifo_sel; |
|
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
reg SyncRxStartFrm_q2; |
wire RxFifoReset; |
reg LatchedRxStartFrm; |
reg SyncRxStartFrm; |
reg SyncRxStartFrm_q; |
reg SyncRxStartFrm_q2; |
wire RxFifoReset; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxStartFrm <=#Tp 0; |
else |
if(RxStartFrm & ~SyncRxStartFrm_q) |
LatchedRxStartFrm <=#Tp 1; |
else |
if(SyncRxStartFrm_q) |
LatchedRxStartFrm <=#Tp 0; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxStartFrm <= 0; |
else |
if(RxStartFrm & ~SyncRxStartFrm_q) |
LatchedRxStartFrm <= 1; |
else |
if(SyncRxStartFrm_q) |
LatchedRxStartFrm <= 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm <=#Tp 0; |
else |
if(LatchedRxStartFrm) |
SyncRxStartFrm <=#Tp 1; |
else |
SyncRxStartFrm <=#Tp 0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm <= 0; |
else |
if(LatchedRxStartFrm) |
SyncRxStartFrm <= 1; |
else |
SyncRxStartFrm <= 0; |
end |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q <=#Tp 0; |
else |
SyncRxStartFrm_q <=#Tp SyncRxStartFrm; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q <= 0; |
else |
SyncRxStartFrm_q <= SyncRxStartFrm; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q2 <=#Tp 0; |
else |
SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
SyncRxStartFrm_q2 <= 0; |
else |
SyncRxStartFrm_q2 <= SyncRxStartFrm_q; |
end |
wire rx_startfrm_wb; |
assign rx_startfrm_wb = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; |
|
|
assign RxFifoReset = rx_startfrm_wb; |
|
|
wire [31:0] rx_fifo0_data_out; |
wire rx_fifo0_write; |
wire rx_fifo0_read; |
wire rx_fifo0_clear; |
wire rx_fifo0_full; |
wire rx_fifo0_afull; |
wire rx_fifo0_empty; |
wire rx_fifo0_aempty; |
|
assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2; |
|
wire [31:0] rx_fifo1_data_out; |
wire rx_fifo1_write; |
wire rx_fifo1_read; |
wire rx_fifo1_clear; |
wire rx_fifo1_full; |
wire rx_fifo1_afull; |
wire rx_fifo1_empty; |
wire rx_fifo1_aempty; |
|
eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH) |
rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o), |
.clk(WB_CLK_I), .reset(Reset), |
.write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i), |
.clear(RxFifoReset), .full(RxBufferFull), |
.almost_full(), .almost_empty(RxBufferAlmostEmpty), |
.empty(RxBufferEmpty), .cnt(rxfifo_cnt) |
); |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo0_cnt; |
wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rx_fifo1_cnt; |
|
// RX FIFO buffer 0 controls |
assign rx_fifo0_write = (!rx_ethside_fifo_sel) & WriteRxDataToFifo_wb & |
~rx_fifo0_full; |
|
assign rx_fifo0_read = (!rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i & |
~rx_fifo0_empty; |
|
assign rx_fifo0_clear = (!rx_ethside_fifo_sel) & RxFifoReset; |
|
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH; |
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH; |
assign WriteRxDataToMemory = ~RxBufferEmpty; |
assign rx_burst = rx_burst_en & WriteRxDataToMemory; |
// RX FIFO buffer 1 controls |
assign rx_fifo1_write = (rx_ethside_fifo_sel) & WriteRxDataToFifo_wb & |
~rx_fifo1_full; |
|
assign rx_fifo1_read = (rx_wbside_fifo_sel) & MasterWbRX & m_wb_ack_i & |
~rx_fifo1_empty; |
|
assign rx_fifo1_clear = (rx_ethside_fifo_sel) & RxFifoReset; |
|
eth_fifo #( |
`ETH_RX_FIFO_DATA_WIDTH, |
`ETH_RX_FIFO_DEPTH, |
`ETH_RX_FIFO_CNT_WIDTH |
) |
rx_fifo0 ( |
.clk (WB_CLK_I ), |
.reset (Reset ), |
// Inputs |
.data_in (RxDataLatched2 ), |
.write (rx_fifo0_write ), |
.read (rx_fifo0_read ), |
.clear (rx_fifo0_clear ), |
// Outputs |
.data_out (rx_fifo0_data_out), |
.full (rx_fifo0_full ), |
.almost_full (), |
.almost_empty (rx_fifo0_aempty ), |
.empty (rx_fifo0_empty ), |
.cnt (rx_fifo0_cnt ) |
); |
|
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEnded_rck <=#Tp 1'b0; |
else |
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) |
ShiftEnded_rck <=#Tp 1'b1; |
else |
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) |
ShiftEnded_rck <=#Tp 1'b0; |
end |
eth_fifo #( |
`ETH_RX_FIFO_DATA_WIDTH, |
`ETH_RX_FIFO_DEPTH, |
`ETH_RX_FIFO_CNT_WIDTH |
) |
rx_fifo1 ( |
.clk (WB_CLK_I ), |
.reset (Reset ), |
// Inputs |
.data_in (RxDataLatched2 ), |
.write (rx_fifo1_write ), |
.read (rx_fifo1_read ), |
.clear (rx_fifo1_clear ), |
// Outputs |
.data_out (rx_fifo1_data_out), |
.full (rx_fifo1_full ), |
.almost_full (), |
.almost_empty (rx_fifo1_aempty ), |
.empty (rx_fifo1_empty ), |
.cnt (rx_fifo1_cnt ) |
); |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync1 <=#Tp 1'b0; |
else |
ShiftEndedSync1 <=#Tp ShiftEnded_rck; |
end |
assign m_wb_dat_o = rx_wbside_fifo_sel ? |
rx_fifo1_data_out : rx_fifo0_data_out; |
assign rxfifo_cnt = rx_wbside_fifo_sel ? |
rx_fifo1_cnt : rx_fifo0_cnt; |
|
assign RxBufferAlmostEmpty = rx_wbside_fifo_sel ? |
rx_fifo1_aempty : rx_fifo0_aempty; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync2 <=#Tp 1'b0; |
else |
ShiftEndedSync2 <=#Tp ShiftEndedSync1; |
end |
assign RxBufferEmpty = rx_wbside_fifo_sel ? |
rx_fifo1_empty : rx_fifo0_empty; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync3 <=#Tp 1'b0; |
else |
if(ShiftEndedSync1 & ~ShiftEndedSync2) |
ShiftEndedSync3 <=#Tp 1'b1; |
else |
if(ShiftEnded) |
ShiftEndedSync3 <=#Tp 1'b0; |
end |
assign RxBufferFull = rx_wbside_fifo_sel ? |
rx_fifo1_full : rx_fifo0_full; |
|
|
|
|
// Generation of the end-of-frame signal |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEnded <=#Tp 1'b0; |
else |
if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded) |
ShiftEnded <=#Tp 1'b1; |
else |
if(RxStatusWrite) |
ShiftEnded <=#Tp 1'b0; |
end |
|
wire write_rx_data_to_memory_wait; |
assign write_rx_data_to_memory_wait = !RxBDOK | RxPointerRead; |
wire write_rx_data_to_memory_go; |
|
`ifdef ETH_RX_BURST_EN |
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=(`ETH_BURST_LENGTH); |
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>(`ETH_BURST_LENGTH - 1); |
// While receiving, don't flog the bus too hard, only write out when |
// we can burst. But when finishing keep going until we've emptied the fifo |
assign write_rx_data_to_memory_go = |
RxEnableWindow & (rx_wbside_fifo_sel == rx_ethside_fifo_sel) ? |
(rxfifo_cnt>(`ETH_BURST_LENGTH)+2) | |
(|rx_burst_cnt) : ~RxBufferEmpty; |
|
`else |
assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH; |
assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH; |
assign write_rx_data_to_memory_go = ~RxBufferEmpty; |
`endif // !`ifdef ETH_RX_BURST_EN |
|
assign WriteRxDataToMemory = write_rx_data_to_memory_go & !write_rx_data_to_memory_wait; |
|
assign rx_burst = rx_burst_en & WriteRxDataToMemory; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c1 <=#Tp 1'b0; |
else |
ShiftEndedSync_c1 <=#Tp ShiftEndedSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c2 <=#Tp 1'b0; |
else |
ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1; |
end |
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEnded_rck <= 1'b0; |
else |
if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd) |
ShiftEnded_rck <= 1'b1; |
else |
if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2) |
ShiftEnded_rck <= 1'b0; |
end |
|
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxEnableWindow <=#Tp 1'b0; |
else |
if(RxStartFrm) |
RxEnableWindow <=#Tp 1'b1; |
else |
if(RxEndFrm | RxAbort) |
RxEnableWindow <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync1 <= 1'b0; |
else |
ShiftEndedSync1 <= ShiftEnded_rck; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync2 <= 1'b0; |
else |
ShiftEndedSync2 <= ShiftEndedSync1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync1 <=#Tp 1'b0; |
else |
RxAbortSync1 <=#Tp RxAbortLatched; |
end |
// indicate end of wishbone RX is coming up |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_wb_last_writes <= 1'b0; |
else if (!rx_wb_last_writes) |
rx_wb_last_writes <= ShiftEndedSync1 & ~ShiftEndedSync2; |
else if (rx_wb_writeback_finished & RxEn & RxEn_q) |
rx_wb_last_writes <= 0; |
|
// Pulse indicating last of RX data has been written out |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
rx_wb_writeback_finished <= 0; |
else if (rx_wb_writeback_finished & RxEn & RxEn_q) |
rx_wb_writeback_finished <= 0; |
else |
rx_wb_writeback_finished <= rx_wb_last_writes & RxBufferEmpty & |
!WriteRxDataToFifo_wb; |
|
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync2 <=#Tp 1'b0; |
else |
RxAbortSync2 <=#Tp RxAbortSync1; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c1 <= 1'b0; |
else |
ShiftEndedSync_c1 <= ShiftEndedSync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync3 <=#Tp 1'b0; |
else |
RxAbortSync3 <=#Tp RxAbortSync2; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShiftEndedSync_c2 <= 1'b0; |
else |
ShiftEndedSync_c2 <= ShiftEndedSync_c1; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync4 <=#Tp 1'b0; |
else |
RxAbortSync4 <=#Tp RxAbortSync3; |
end |
// Generation of the end-of-frame signal |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxEnableWindow <= 1'b0; |
else |
if(RxStartFrm) |
RxEnableWindow <= 1'b1; |
else |
if(RxEndFrm | RxAbort) |
RxEnableWindow <= 1'b0; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb1 <=#Tp 1'b0; |
else |
RxAbortSyncb1 <=#Tp RxAbortSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb2 <=#Tp 1'b0; |
else |
RxAbortSyncb2 <=#Tp RxAbortSyncb1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync1 <= 1'b0; |
else |
RxAbortSync1 <= RxAbortLatched; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync2 <= 1'b0; |
else |
RxAbortSync2 <= RxAbortSync1; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortLatched <=#Tp 1'b0; |
else |
if(RxAbortSyncb2) |
RxAbortLatched <=#Tp 1'b0; |
else |
if(RxAbort) |
RxAbortLatched <=#Tp 1'b1; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync3 <= 1'b0; |
else |
RxAbortSync3 <= RxAbortSync2; |
end |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxAbortSync4 <= 1'b0; |
else |
RxAbortSync4 <= RxAbortSync3; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxLength[15:0] <=#Tp 16'h0; |
else |
if(LoadRxStatus) |
LatchedRxLength[15:0] <=#Tp RxLength[15:0]; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb1 <= 1'b0; |
else |
RxAbortSyncb1 <= RxAbortSync2; |
end |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortSyncb2 <= 1'b0; |
else |
RxAbortSyncb2 <= RxAbortSyncb1; |
end |
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusInLatched <=#Tp 'h0; |
else |
if(LoadRxStatus) |
RxStatusInLatched <=#Tp RxStatusIn; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbortLatched <= 1'b0; |
else |
if(RxAbortSyncb2) |
RxAbortLatched <= 1'b0; |
else |
if(RxAbort) |
RxAbortLatched <= 1'b1; |
end |
|
|
// Rx overrun |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxOverrun <=#Tp 1'b0; |
else |
if(RxStatusWrite) |
RxOverrun <=#Tp 1'b0; |
else |
if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <=#Tp 1'b1; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedRxLength[15:0] <= 16'h0; |
else |
if(LoadRxStatus) |
LatchedRxLength[15:0] <= RxLength[15:0]; |
end |
|
|
assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision}; |
|
wire TxError; |
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost; |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxStatusInLatched <= 'h0; |
else |
if(LoadRxStatus) |
RxStatusInLatched <= RxStatusIn; |
end |
|
wire RxError; |
|
// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames |
// are aborted when signal r_RecSmall is set to 0 in MODER register. |
// AddressMiss is identifying that a frame was received because of the promiscous |
// mode and is not an error |
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]); |
// Rx overrun |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxOverrun <= 1'b0; |
else |
if(RxStatusWrite) |
RxOverrun <= 1'b0; |
else |
if(RxBufferFull & WriteRxDataToFifo_wb) |
RxOverrun <= 1'b1; |
end |
|
|
|
reg RxStatusWriteLatched; |
reg RxStatusWriteLatched_sync1; |
reg RxStatusWriteLatched_sync2; |
reg RxStatusWriteLatched_syncb1; |
reg RxStatusWriteLatched_syncb2; |
wire TxError; |
assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost; |
|
wire RxError; |
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatusWriteLatched <=#Tp 1'b0; |
else |
if(RxStatusWriteLatched_syncb2) |
RxStatusWriteLatched <=#Tp 1'b0; |
else |
if(RxStatusWrite) |
RxStatusWriteLatched <=#Tp 1'b1; |
end |
// ShortFrame (RxStatusInLatched[2]) can not set an error because short |
// frames are aborted when signal r_RecSmall is set to 0 in MODER register. |
// AddressMiss is identifying that a frame was received because of the |
// promiscous mode and is not an error |
assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]); |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_sync1 <=#Tp 1'b0; |
RxStatusWriteLatched_sync2 <=#Tp 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched; |
RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1; |
end |
end |
|
reg RxStatusWriteLatched; |
reg RxStatusWriteLatched_sync1; |
reg RxStatusWriteLatched_sync2; |
reg RxStatusWriteLatched_syncb1; |
reg RxStatusWriteLatched_syncb2; |
|
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_syncb1 <=#Tp 1'b0; |
RxStatusWriteLatched_syncb2 <=#Tp 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2; |
RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1; |
end |
end |
|
// Latching and synchronizing RxStatusWrite signal. This signal is used for |
// clearing the ReceivedPauseFrm signal |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWriteLatched_syncb2) |
RxStatusWriteLatched <= 1'b0; |
else |
if(RxStatusWrite) |
RxStatusWriteLatched <= 1'b1; |
end |
|
|
// Tx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxB_IRQ <=#Tp 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxB_IRQ <=#Tp ~TxError; |
else |
TxB_IRQ <=#Tp 1'b0; |
end |
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_sync1 <= 1'b0; |
RxStatusWriteLatched_sync2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_sync1 <= RxStatusWriteLatched; |
RxStatusWriteLatched_sync2 <= RxStatusWriteLatched_sync1; |
end |
end |
|
|
// Tx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxE_IRQ <=#Tp 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxE_IRQ <=#Tp TxError; |
else |
TxE_IRQ <=#Tp 1'b0; |
end |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
begin |
RxStatusWriteLatched_syncb1 <= 1'b0; |
RxStatusWriteLatched_syncb2 <= 1'b0; |
end |
else |
begin |
RxStatusWriteLatched_syncb1 <= RxStatusWriteLatched_sync2; |
RxStatusWriteLatched_syncb2 <= RxStatusWriteLatched_syncb1; |
end |
end |
|
|
// Rx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxB_IRQ <=#Tp 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxB_IRQ <=#Tp (~RxError); |
else |
RxB_IRQ <=#Tp 1'b0; |
end |
|
// Tx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxB_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxB_IRQ <= ~TxError; |
else |
TxB_IRQ <= 1'b0; |
end |
|
// Rx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxE_IRQ <=#Tp 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxE_IRQ <=#Tp RxError; |
else |
RxE_IRQ <=#Tp 1'b0; |
end |
|
// Tx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
TxE_IRQ <= 1'b0; |
else |
if(TxStatusWrite & TxIRQEn) |
TxE_IRQ <= TxError; |
else |
TxE_IRQ <= 1'b0; |
end |
|
// Busy Interrupt |
|
reg Busy_IRQ_rck; |
reg Busy_IRQ_sync1; |
reg Busy_IRQ_sync2; |
reg Busy_IRQ_sync3; |
reg Busy_IRQ_syncb1; |
reg Busy_IRQ_syncb2; |
// Rx Done Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxB_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & |
(~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow))) |
RxB_IRQ <= (~RxError); |
else |
RxB_IRQ <= 1'b0; |
end |
|
|
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
Busy_IRQ_rck <=#Tp 1'b0; |
else |
if(RxValid & RxStartFrm & ~RxReady) |
Busy_IRQ_rck <=#Tp 1'b1; |
else |
if(Busy_IRQ_syncb2) |
Busy_IRQ_rck <=#Tp 1'b0; |
end |
// Rx Error Interrupt |
always @ (posedge WB_CLK_I or posedge Reset) |
begin |
if(Reset) |
RxE_IRQ <= 1'b0; |
else |
if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm |
& r_PassAll & (~r_RxFlow))) |
RxE_IRQ <= RxError; |
else |
RxE_IRQ <= 1'b0; |
end |
|
always @ (posedge WB_CLK_I) |
begin |
Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck; |
Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1; |
Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2; |
end |
// Set this high when we started receiving another packet while the wishbone |
// side was still writing out the last one. This makes sure we check at the |
// right time if the next buffer descriptor is free. |
reg rxstartfrm_occurred; |
always @ (posedge WB_CLK_I) |
if (Reset) |
rxstartfrm_occurred <= 0; |
else if (rx_just_read_bd) |
rxstartfrm_occurred <= 0; |
else if (((rx_ethside_fifo_sel != rx_wbside_fifo_sel) | StartRxBDRead | |
RxBDRead) & rx_startfrm_wb) |
rxstartfrm_occurred <= 1; |
|
always @ (posedge MRxClk) |
begin |
Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2; |
Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1; |
end |
|
|
assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3; |
reg busy_wb; |
always @ (posedge WB_CLK_I or posedge Reset) |
if(Reset) |
busy_wb <= 0; |
else if (busy_wb) |
busy_wb <= 0; |
else if |
// Indicate busy if either: |
// a) RX is idle and we get a start frame and current BD indicates not |
// ready. |
// b) RX is already receiving another packet and we got a startframe, |
// indicated by rx_startfrm_occurred, and we then read the BD and |
// it says it's not ready. |
// This actually may not work since it's in the MII RX clock domain. |
((rx_ethside_fifo_sel == rx_wbside_fifo_sel) & |
((rxstartfrm_occurred & rx_just_read_bd & ~RxBDReady) | |
(!rxstartfrm_occurred & !StartRxBDRead & !RxBDRead & rx_startfrm_wb & |
rx_waiting_for_bd_to_become_free)) |
) |
busy_wb <= 1; |
|
|
assign Busy_IRQ = busy_wb; |
|
always @(posedge Busy_IRQ) |
$display("(%t)(%m) Ethernet MAC BUSY signal asserted", $time); |
|
|
// Assign the debug output |
`ifdef WISHBONE_DEBUG |
// Top byte, burst progress counters |
assign dbg_dat0[31] = 0; |
assign dbg_dat0[30] = 0; |
assign dbg_dat0[29:28] = rx_burst_cnt; |
assign dbg_dat0[27] = 0; |
assign dbg_dat0[26] = 0; |
assign dbg_dat0[25:24] = tx_burst_cnt; |
|
// Third byte |
assign dbg_dat0[23] = 0; |
assign dbg_dat0[22] = 0; |
assign dbg_dat0[21] = rx_burst; |
assign dbg_dat0[20] = rx_burst_en; |
assign dbg_dat0[19] = 0; |
assign dbg_dat0[18] = 0; |
assign dbg_dat0[17] = tx_burst; |
assign dbg_dat0[16] = tx_burst_en; |
// Second byte - TxBDAddress - or TX BD address pointer |
assign dbg_dat0[15:8] = { 1'b0, TxBDAddress}; |
// Bottom byte - FSM controlling vector |
assign dbg_dat0[7:0] = {MasterWbTX,MasterWbRX, |
ReadTxDataFromMemory_2,WriteRxDataToMemory, |
MasterAccessFinished,cyc_cleared, |
tx_burst,rx_burst}; |
|
`endif |
|
|
|
/orpsocv2/rtl/verilog/eth/eth_txcounters.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_txcounters.v,v $ |
// Revision 1.6 2005/02/21 11:25:27 igorm |
// Delayed CRC fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/04/22 14:54:14 mohor |
// FCS should not be included in NibbleMinFl. |
// |
155,14 → 152,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
NibCnt <= #Tp 16'h0; |
NibCnt <= 16'h0; |
else |
begin |
if(ResetNibCnt) |
NibCnt <= #Tp 16'h0; |
NibCnt <= 16'h0; |
else |
if(IncrementNibCnt) |
NibCnt <= #Tp NibCnt + 1'b1; |
NibCnt <= NibCnt + 1'b1; |
end |
end |
|
187,14 → 184,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
begin |
if(ResetByteCnt) |
ByteCnt[15:0] <= #Tp 16'h0; |
ByteCnt[15:0] <= 16'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1; |
ByteCnt[15:0] <= ByteCnt[15:0] + 1'b1; |
end |
end |
|
208,14 → 205,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
begin |
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0]))) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_random.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_random.v,v $ |
// Revision 1.4 2003/06/13 11:26:08 mohor |
// Binary operator used instead of unary (xnor). |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
106,9 → 103,9
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
x[9:0] <= #Tp 0; |
x[9:0] <= 0; |
else |
x[9:0] <= #Tp {x[8:0], Feedback}; |
x[9:0] <= {x[8:0], Feedback}; |
end |
|
assign Feedback = ~(x[2] ^ x[9]); |
128,11 → 125,11
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RandomLatched <= #Tp 10'h000; |
RandomLatched <= 10'h000; |
else |
begin |
if(StateJam & StateJam_q) |
RandomLatched <= #Tp Random; |
RandomLatched <= Random; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_rxaddrcheck.v
40,11 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_rxaddrcheck.v,v $ |
// Revision 1.9 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.8 2002/11/19 17:34:52 mohor |
// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying |
// that a frame was received because of the promiscous mode. |
134,11 → 130,11
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxAbort <= #Tp 1'b0; |
RxAbort <= 1'b0; |
else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn) |
RxAbort <= #Tp 1'b1; |
RxAbort <= 1'b1; |
else |
RxAbort <= #Tp 1'b0; |
RxAbort <= 1'b0; |
end |
|
|
146,9 → 142,9
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
AddressMiss <= #Tp 1'b0; |
AddressMiss <= 1'b0; |
else if(ByteCntEq7 & RxCheckEn) |
AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
AddressMiss <= (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK))); |
end |
|
|
156,11 → 152,11
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
MulticastOK <= #Tp 1'b0; |
MulticastOK <= 1'b0; |
else if(RxEndFrm | RxAbort) |
MulticastOK <= #Tp 1'b0; |
MulticastOK <= 1'b0; |
else if(CrcHashGood & Multicast) |
MulticastOK <= #Tp HashBit; |
MulticastOK <= HashBit; |
end |
|
|
169,28 → 165,28
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
UnicastOK <= #Tp 1'b0; |
UnicastOK <= 1'b0; |
else |
if(RxCheckEn & ByteCntEq2) |
UnicastOK <= #Tp RxData[7:0] == MAC[47:40]; |
UnicastOK <= RxData[7:0] == MAC[47:40]; |
else |
if(RxCheckEn & ByteCntEq3) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[39:32]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq4) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[31:24]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq5) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[23:16]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq6) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[15:8]) & UnicastOK; |
else |
if(RxCheckEn & ByteCntEq7) |
UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK; |
UnicastOK <= ( RxData[7:0] == MAC[7:0]) & UnicastOK; |
else |
if(RxEndFrm | RxAbort) |
UnicastOK <= #Tp 1'b0; |
UnicastOK <= 1'b0; |
end |
|
assign IntHash = (CrcHash[5])? HASH1 : HASH0; |
/orpsocv2/rtl/verilog/eth/eth_fifo.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_fifo.v,v $ |
// Revision 1.4 2005/02/21 12:48:07 igorm |
// Warning fixes. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/04/22 13:45:52 mohor |
// Generic ram or Xilinx ram can be used in fifo (selectable by setting |
// ETH_FIFO_XILINX in eth_defines.v). |
68,8 → 65,6
parameter DEPTH = 8; |
parameter CNT_WIDTH = 4; |
|
parameter Tp = 1; |
|
input clk; |
input reset; |
input write; |
84,66 → 79,118
output empty; |
output [CNT_WIDTH-1:0] cnt; |
|
`ifdef ETH_FIFO_XILINX |
`else |
`ifdef ETH_ALTERA_ALTSYNCRAM |
`else |
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1]; |
// reg [DATA_WIDTH-1:0] data_out; |
`endif |
`endif |
|
reg [CNT_WIDTH-1:0] cnt; |
reg [CNT_WIDTH-2:0] read_pointer; |
reg [CNT_WIDTH-2:0] write_pointer; |
|
|
reg [CNT_WIDTH-1:0] cnt; |
reg final_read; |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
cnt <=#Tp 0; |
cnt <= 0; |
else |
if(clear) |
cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write}; |
cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write}; |
else |
if(read ^ write) |
if(read) |
cnt <=#Tp cnt - 1'b1; |
cnt <= cnt - 1'b1; |
else |
cnt <=#Tp cnt + 1'b1; |
cnt <= cnt + 1'b1; |
end |
|
|
`ifdef ETH_FIFO_GENERIC |
|
reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ; |
|
|
// This should make the synthesis tool infer RAMs |
reg [CNT_WIDTH-2:0] waddr, raddr, raddr_reg; |
reg clear_reg; // Register the clear pulse |
|
always @(posedge clk) |
if (reset) |
waddr <= 0; |
else if (write) |
waddr <= waddr + 1; |
|
wire raddr_reg_adv; |
reg read_reg; |
always @(posedge clk) |
read_reg <= read; |
|
// Advance the address after a read = first/next word fallthrough |
assign raddr_reg_adv = (cnt > 2) & read_reg; |
|
always @(posedge clk) |
if (reset) |
raddr <= 0; |
else if (clear) |
raddr <= waddr; |
else if (read | clear_reg ) |
raddr <= raddr + 1; |
|
always @ (posedge clk) |
if (write & ~full) |
fifo[waddr] <= data_in; |
|
|
always @(posedge clk) |
clear_reg <= clear; |
|
always @ (posedge clk) |
if (read | clear_reg) |
raddr_reg <= raddr; |
|
assign data_out = fifo[raddr_reg]; |
|
|
always @(posedge clk) |
if (reset) |
final_read <= 0; |
else if (final_read & read & !write) |
final_read <= ~final_read; |
else if ((cnt == 1) & read & !write) |
final_read <= 1; // Indicate last read data has been output |
|
|
assign empty = ~(|cnt); |
assign almost_empty = cnt==1; |
assign full = cnt == DEPTH; |
assign almost_full = &cnt[CNT_WIDTH-2:0]; |
|
`else // !`ifdef ETH_FIFO_GENERIC |
|
reg [CNT_WIDTH-2:0] read_pointer; |
reg [CNT_WIDTH-2:0] write_pointer; |
|
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
read_pointer <=#Tp 0; |
read_pointer <= 0; |
else |
if(clear) |
read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read}; |
//read_pointer <= { {(CNT_WIDTH-2){1'b0}}, read}; |
read_pointer <= { {(CNT_WIDTH-2){1'b0}}, 1'b1}; |
else |
if(read & ~empty) |
read_pointer <=#Tp read_pointer + 1'b1; |
read_pointer <= read_pointer + 1'b1; |
end |
|
always @ (posedge clk or posedge reset) |
begin |
if(reset) |
write_pointer <=#Tp 0; |
write_pointer <= 0; |
else |
if(clear) |
write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write}; |
write_pointer <= { {(CNT_WIDTH-2){1'b0}}, write}; |
else |
if(write & ~full) |
write_pointer <=#Tp write_pointer + 1'b1; |
write_pointer <= write_pointer + 1'b1; |
end |
|
assign empty = ~(|cnt); |
assign almost_empty = cnt == 1; |
assign full = cnt == DEPTH; |
assign almost_full = &cnt[CNT_WIDTH-2:0]; |
|
|
|
`ifdef ETH_FIFO_XILINX |
xilinx_dist_ram_16x32 fifo |
( .data_out(data_out), |
156,56 → 203,25
`else // !ETH_FIFO_XILINX |
`ifdef ETH_ALTERA_ALTSYNCRAM |
altera_dpram_16x32 altera_dpram_16x32_inst |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
`else // !ETH_ALTERA_ALTSYNCRAM |
( |
.data (data_in), |
.wren (write & ~full), |
.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer), |
.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ), |
.clock (clk), |
.q (data_out) |
); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE |
`endif // `ifdef ETH_ALTERA_ALTSYNCRAM |
`endif // !`ifdef ETH_FIFO_XILINX |
|
wire [CNT_WIDTH-2:0] waddr, raddr; |
reg [CNT_WIDTH-2:0] raddr_reg; |
wire we; |
|
assign waddr = clear ? {CNT_WIDTH-1{1'b0}} : write_pointer; |
assign raddr = clear ? {CNT_WIDTH-1{1'b0}} : read_pointer; |
|
assign we = (write & clear) | (write & ~full); |
|
always @ (posedge clk) |
if (we) |
fifo[waddr] <= #Tp data_in; |
|
always @ (posedge clk) |
raddr_reg <= raddr; |
|
assign #Tp data_out = fifo[raddr_reg]; |
assign empty = ~(|cnt); |
assign almost_empty = cnt == 1; |
assign full = cnt == DEPTH; |
assign almost_full = &cnt[CNT_WIDTH-2:0]; |
|
|
/* |
always @ (posedge clk) |
begin |
if(write & clear) |
fifo[0] <=#Tp data_in; |
else |
if(write & ~full) |
fifo[write_pointer] <=#Tp data_in; |
end |
|
`endif // !`ifdef ETH_FIFO_GENERIC |
|
|
always @ (posedge clk) |
begin |
if(clear) |
data_out <=#Tp fifo[0]; |
else |
data_out <=#Tp fifo[read_pointer]; |
end |
*/ |
`endif // !ETH_ALTERA_ALTSYNCRAM |
`endif // !ETH_FIFO_XILINX |
|
|
endmodule |
/orpsocv2/rtl/verilog/eth/eth_receivecontrol.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_receivecontrol.v,v $ |
// Revision 1.5 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.4 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
168,28 → 165,28
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
AddressOK <= #Tp 1'b0; |
AddressOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq0) |
AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; |
AddressOK <= RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40]; |
else |
if(DetectionWindow & ByteCntEq1) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq2) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq3) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq4) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK; |
else |
if(DetectionWindow & ByteCntEq5) |
AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; |
AddressOK <= (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK; |
else |
if(ReceiveEnd) |
AddressOK <= #Tp 1'b0; |
AddressOK <= 1'b0; |
end |
|
|
198,16 → 195,16
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
TypeLengthOK <= #Tp 1'b0; |
TypeLengthOK <= 1'b0; |
else |
if(DetectionWindow & ByteCntEq12) |
TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); |
TypeLengthOK <= ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]); |
else |
if(DetectionWindow & ByteCntEq13) |
TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; |
TypeLengthOK <= ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK; |
else |
if(ReceiveEnd) |
TypeLengthOK <= #Tp 1'b0; |
TypeLengthOK <= 1'b0; |
end |
|
|
216,17 → 213,17
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
OpCodeOK <= #Tp 1'b0; |
OpCodeOK <= 1'b0; |
else |
if(ByteCntEq16) |
OpCodeOK <= #Tp 1'b0; |
OpCodeOK <= 1'b0; |
else |
begin |
if(DetectionWindow & ByteCntEq14) |
OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00; |
OpCodeOK <= ByteCntEq14 & RxData[7:0] == 8'h00; |
|
if(DetectionWindow & ByteCntEq15) |
OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; |
OpCodeOK <= ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK; |
end |
end |
|
235,13 → 232,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
ReceivedPauseFrmWAddr <= #Tp 1'b0; |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ReceiveEnd) |
ReceivedPauseFrmWAddr <= #Tp 1'b0; |
ReceivedPauseFrmWAddr <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK) |
ReceivedPauseFrmWAddr <= #Tp 1'b1; |
ReceivedPauseFrmWAddr <= 1'b1; |
end |
|
|
250,16 → 247,16
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
AssembledTimerValue[15:0] <= #Tp 16'h0; |
AssembledTimerValue[15:0] <= 16'h0; |
else |
if(RxStartFrm) |
AssembledTimerValue[15:0] <= #Tp 16'h0; |
AssembledTimerValue[15:0] <= 16'h0; |
else |
begin |
if(DetectionWindow & ByteCntEq16) |
AssembledTimerValue[15:8] <= #Tp RxData[7:0]; |
AssembledTimerValue[15:8] <= RxData[7:0]; |
if(DetectionWindow & ByteCntEq17) |
AssembledTimerValue[7:0] <= #Tp RxData[7:0]; |
AssembledTimerValue[7:0] <= RxData[7:0]; |
end |
end |
|
268,13 → 265,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
DetectionWindow <= #Tp 1'b1; |
DetectionWindow <= 1'b1; |
else |
if(ByteCntEq18) |
DetectionWindow <= #Tp 1'b0; |
DetectionWindow <= 1'b0; |
else |
if(ReceiveEnd) |
DetectionWindow <= #Tp 1'b1; |
DetectionWindow <= 1'b1; |
end |
|
|
283,13 → 280,13
always @ (posedge MRxClk or posedge RxReset ) |
begin |
if(RxReset) |
LatchedTimerValue[15:0] <= #Tp 16'h0; |
LatchedTimerValue[15:0] <= 16'h0; |
else |
if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18) |
LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0]; |
LatchedTimerValue[15:0] <= AssembledTimerValue[15:0]; |
else |
if(ReceiveEnd) |
LatchedTimerValue[15:0] <= #Tp 16'h0; |
LatchedTimerValue[15:0] <= 16'h0; |
end |
|
|
298,13 → 295,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & RxEndFrm) |
DlyCrcCnt <= #Tp 3'h0; |
DlyCrcCnt <= 3'h0; |
else |
if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2]) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
|
|
316,13 → 313,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ByteCnt[4:0] <= #Tp 5'h0; |
ByteCnt[4:0] <= 5'h0; |
else |
if(ResetByteCnt) |
ByteCnt[4:0] <= #Tp 5'h0; |
ByteCnt[4:0] <= 5'h0; |
else |
if(IncrementByteCnt) |
ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1; |
ByteCnt[4:0] <= ByteCnt[4:0] + 1'b1; |
end |
|
|
349,13 → 346,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
PauseTimer[15:0] <= #Tp 16'h0; |
PauseTimer[15:0] <= 16'h0; |
else |
if(SetPauseTimer) |
PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0]; |
PauseTimer[15:0] <= LatchedTimerValue[15:0]; |
else |
if(DecrementPauseTimer) |
PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1; |
PauseTimer[15:0] <= PauseTimer[15:0] - 1'b1; |
end |
|
assign PauseTimerEq0 = ~(|PauseTimer[15:0]); |
367,13 → 364,13
begin |
if(TxReset) |
begin |
PauseTimerEq0_sync1 <= #Tp 1'b1; |
PauseTimerEq0_sync2 <= #Tp 1'b1; |
PauseTimerEq0_sync1 <= 1'b1; |
PauseTimerEq0_sync2 <= 1'b1; |
end |
else |
begin |
PauseTimerEq0_sync1 <= #Tp PauseTimerEq0; |
PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1; |
PauseTimerEq0_sync1 <= PauseTimerEq0; |
PauseTimerEq0_sync2 <= PauseTimerEq0_sync1; |
end |
end |
|
382,10 → 379,10
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
Pause <= #Tp 1'b0; |
Pause <= 1'b0; |
else |
if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut) |
Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2; |
Pause <= RxFlow & ~PauseTimerEq0_sync2; |
end |
|
|
393,12 → 390,12
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
Divider2 <= #Tp 1'b0; |
Divider2 <= 1'b0; |
else |
if(|PauseTimer[15:0] & RxFlow) |
Divider2 <= #Tp ~Divider2; |
Divider2 <= ~Divider2; |
else |
Divider2 <= #Tp 1'b0; |
Divider2 <= 1'b0; |
end |
|
|
410,13 → 407,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
SlotTimer[5:0] <= #Tp 6'h0; |
SlotTimer[5:0] <= 6'h0; |
else |
if(ResetSlotTimer) |
SlotTimer[5:0] <= #Tp 6'h0; |
SlotTimer[5:0] <= 6'h0; |
else |
if(IncrementSlotTimer) |
SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1; |
SlotTimer[5:0] <= SlotTimer[5:0] + 1'b1; |
end |
|
|
428,13 → 425,13
always @ (posedge MRxClk or posedge RxReset) |
begin |
if(RxReset) |
ReceivedPauseFrm <=#Tp 1'b0; |
ReceivedPauseFrm <= 1'b0; |
else |
if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll)) |
ReceivedPauseFrm <=#Tp 1'b0; |
ReceivedPauseFrm <= 1'b0; |
else |
if(ByteCntEq16 & TypeLengthOK & OpCodeOK) |
ReceivedPauseFrm <=#Tp 1'b1; |
ReceivedPauseFrm <= 1'b1; |
end |
|
|
/orpsocv2/rtl/verilog/eth/eth_register.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_register.v,v $ |
// Revision 1.6 2002/08/16 22:10:12 mohor |
// Synchronous reset added. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/08/16 12:33:27 mohor |
// Parameter ResetValue changed to capital letters. |
// |
77,7 → 74,7
`include "timescale.v" |
|
|
module eth_register(DataIn, DataOut, Write, Clk, Reset); |
module eth_register(DataIn, DataOut, Write, Clk, Reset, SyncReset); |
|
parameter WIDTH = 8; // default parameter of the register width |
parameter RESET_VALUE = 0; |
87,6 → 84,7
input Write; |
input Clk; |
input Reset; |
input SyncReset; |
|
output [WIDTH-1:0] DataOut; |
reg [WIDTH-1:0] DataOut; |
93,11 → 91,18
|
|
|
always @ (posedge Clk or posedge Reset) |
if(Reset) |
DataOut<=#1 RESET_VALUE; |
else |
if(Write) // write |
DataOut<=#1 DataIn; |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
DataOut<= RESET_VALUE; |
else |
if(SyncReset) |
DataOut<= RESET_VALUE; |
else |
if(Write) // write |
DataOut<= DataIn; |
end |
|
|
|
endmodule // Register |
/orpsocv2/rtl/verilog/eth/eth_clockgen.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_clockgen.v,v $ |
// Revision 1.4 2005/02/21 12:48:05 igorm |
// Warning fixes. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
99,15 → 96,15
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Counter[7:0] <= #Tp 8'h1; |
Counter[7:0] <= 8'h1; |
else |
begin |
if(CountEq0) |
begin |
Counter[7:0] <= #Tp CounterPreset[7:0]; |
Counter[7:0] <= CounterPreset[7:0]; |
end |
else |
Counter[7:0] <= #Tp Counter - 8'h1; |
Counter[7:0] <= Counter - 8'h1; |
end |
end |
|
116,11 → 113,11
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Mdc <= #Tp 1'b0; |
Mdc <= 1'b0; |
else |
begin |
if(CountEq0) |
Mdc <= #Tp ~Mdc; |
Mdc <= ~Mdc; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_miim.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_miim.v,v $ |
// Revision 1.7 2005/03/21 20:07:18 igorm |
// Some small fixes + some troubles fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2005/02/21 12:48:07 igorm |
// Warning fixes. |
// |
201,13 → 198,13
begin |
if(Reset) |
begin |
EndBusy_d <= #Tp 1'b0; |
EndBusy <= #Tp 1'b0; |
EndBusy_d <= 1'b0; |
EndBusy <= 1'b0; |
end |
else |
begin |
EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3; |
EndBusy <= #Tp EndBusy_d; |
EndBusy_d <= ~InProgress_q2 & InProgress_q3; |
EndBusy <= EndBusy_d; |
end |
end |
|
216,12 → 213,12
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
UpdateMIIRX_DATAReg <= #Tp 0; |
UpdateMIIRX_DATAReg <= 0; |
else |
if(EndBusy & ~WCtrlDataStart_q) |
UpdateMIIRX_DATAReg <= #Tp 1; |
UpdateMIIRX_DATAReg <= 1; |
else |
UpdateMIIRX_DATAReg <= #Tp 0; |
UpdateMIIRX_DATAReg <= 0; |
end |
|
|
231,32 → 228,32
begin |
if(Reset) |
begin |
WCtrlData_q1 <= #Tp 1'b0; |
WCtrlData_q2 <= #Tp 1'b0; |
WCtrlData_q3 <= #Tp 1'b0; |
WCtrlData_q1 <= 1'b0; |
WCtrlData_q2 <= 1'b0; |
WCtrlData_q3 <= 1'b0; |
|
RStat_q1 <= #Tp 1'b0; |
RStat_q2 <= #Tp 1'b0; |
RStat_q3 <= #Tp 1'b0; |
RStat_q1 <= 1'b0; |
RStat_q2 <= 1'b0; |
RStat_q3 <= 1'b0; |
|
ScanStat_q1 <= #Tp 1'b0; |
ScanStat_q2 <= #Tp 1'b0; |
SyncStatMdcEn <= #Tp 1'b0; |
ScanStat_q1 <= 1'b0; |
ScanStat_q2 <= 1'b0; |
SyncStatMdcEn <= 1'b0; |
end |
else |
begin |
WCtrlData_q1 <= #Tp WCtrlData; |
WCtrlData_q2 <= #Tp WCtrlData_q1; |
WCtrlData_q3 <= #Tp WCtrlData_q2; |
WCtrlData_q1 <= WCtrlData; |
WCtrlData_q2 <= WCtrlData_q1; |
WCtrlData_q3 <= WCtrlData_q2; |
|
RStat_q1 <= #Tp RStat; |
RStat_q2 <= #Tp RStat_q1; |
RStat_q3 <= #Tp RStat_q2; |
RStat_q1 <= RStat; |
RStat_q2 <= RStat_q1; |
RStat_q3 <= RStat_q2; |
|
ScanStat_q1 <= #Tp ScanStat; |
ScanStat_q2 <= #Tp ScanStat_q1; |
ScanStat_q1 <= ScanStat; |
ScanStat_q2 <= ScanStat_q1; |
if(MdcEn) |
SyncStatMdcEn <= #Tp ScanStat_q2; |
SyncStatMdcEn <= ScanStat_q2; |
end |
end |
|
266,24 → 263,24
begin |
if(Reset) |
begin |
WCtrlDataStart <= #Tp 1'b0; |
WCtrlDataStart_q <= #Tp 1'b0; |
RStatStart <= #Tp 1'b0; |
WCtrlDataStart <= 1'b0; |
WCtrlDataStart_q <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(EndBusy) |
begin |
WCtrlDataStart <= #Tp 1'b0; |
RStatStart <= #Tp 1'b0; |
WCtrlDataStart <= 1'b0; |
RStatStart <= 1'b0; |
end |
else |
begin |
if(WCtrlData_q2 & ~WCtrlData_q3) |
WCtrlDataStart <= #Tp 1'b1; |
WCtrlDataStart <= 1'b1; |
if(RStat_q2 & ~RStat_q3) |
RStatStart <= #Tp 1'b1; |
WCtrlDataStart_q <= #Tp WCtrlDataStart; |
RStatStart <= 1'b1; |
WCtrlDataStart_q <= WCtrlDataStart; |
end |
end |
end |
293,17 → 290,17
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
Nvalid <= #Tp 1'b0; |
Nvalid <= 1'b0; |
else |
begin |
if(~InProgress_q2 & InProgress_q3) |
begin |
Nvalid <= #Tp 1'b0; |
Nvalid <= 1'b0; |
end |
else |
begin |
if(ScanStat_q2 & ~SyncStatMdcEn) |
Nvalid <= #Tp 1'b1; |
Nvalid <= 1'b1; |
end |
end |
end |
313,40 → 310,40
begin |
if(Reset) |
begin |
WCtrlDataStart_q1 <= #Tp 1'b0; |
WCtrlDataStart_q2 <= #Tp 1'b0; |
WCtrlDataStart_q1 <= 1'b0; |
WCtrlDataStart_q2 <= 1'b0; |
|
RStatStart_q1 <= #Tp 1'b0; |
RStatStart_q2 <= #Tp 1'b0; |
RStatStart_q1 <= 1'b0; |
RStatStart_q2 <= 1'b0; |
|
InProgress_q1 <= #Tp 1'b0; |
InProgress_q2 <= #Tp 1'b0; |
InProgress_q3 <= #Tp 1'b0; |
InProgress_q1 <= 1'b0; |
InProgress_q2 <= 1'b0; |
InProgress_q3 <= 1'b0; |
|
LatchByte0_d <= #Tp 1'b0; |
LatchByte1_d <= #Tp 1'b0; |
LatchByte0_d <= 1'b0; |
LatchByte1_d <= 1'b0; |
|
LatchByte <= #Tp 2'b00; |
LatchByte <= 2'b00; |
end |
else |
begin |
if(MdcEn) |
begin |
WCtrlDataStart_q1 <= #Tp WCtrlDataStart; |
WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1; |
WCtrlDataStart_q1 <= WCtrlDataStart; |
WCtrlDataStart_q2 <= WCtrlDataStart_q1; |
|
RStatStart_q1 <= #Tp RStatStart; |
RStatStart_q2 <= #Tp RStatStart_q1; |
RStatStart_q1 <= RStatStart; |
RStatStart_q2 <= RStatStart_q1; |
|
LatchByte[0] <= #Tp LatchByte0_d; |
LatchByte[1] <= #Tp LatchByte1_d; |
LatchByte[0] <= LatchByte0_d; |
LatchByte[1] <= LatchByte1_d; |
|
LatchByte0_d <= #Tp LatchByte0_d2; |
LatchByte1_d <= #Tp LatchByte1_d2; |
LatchByte0_d <= LatchByte0_d2; |
LatchByte1_d <= LatchByte1_d2; |
|
InProgress_q1 <= #Tp InProgress; |
InProgress_q2 <= #Tp InProgress_q1; |
InProgress_q3 <= #Tp InProgress_q2; |
InProgress_q1 <= InProgress; |
InProgress_q2 <= InProgress_q1; |
InProgress_q3 <= InProgress_q2; |
end |
end |
end |
368,8 → 365,8
begin |
if(Reset) |
begin |
InProgress <= #Tp 1'b0; |
WriteOp <= #Tp 1'b0; |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
else |
begin |
378,15 → 375,15
if(StartOp) |
begin |
if(~InProgress) |
WriteOp <= #Tp WriteDataOp; |
InProgress <= #Tp 1'b1; |
WriteOp <= WriteDataOp; |
InProgress <= 1'b1; |
end |
else |
begin |
if(EndOp) |
begin |
InProgress <= #Tp 1'b0; |
WriteOp <= #Tp 1'b0; |
InProgress <= 1'b0; |
WriteOp <= 1'b0; |
end |
end |
end |
399,7 → 396,7
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
BitCounter[6:0] <= #Tp 7'h0; |
BitCounter[6:0] <= 7'h0; |
else |
begin |
if(MdcEn) |
407,12 → 404,12
if(InProgress) |
begin |
if(NoPre & ( BitCounter == 7'h0 )) |
BitCounter[6:0] <= #Tp 7'h21; |
BitCounter[6:0] <= 7'h21; |
else |
BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1; |
BitCounter[6:0] <= BitCounter[6:0] + 1'b1; |
end |
else |
BitCounter[6:0] <= #Tp 7'h0; |
BitCounter[6:0] <= 7'h0; |
end |
end |
end |
/orpsocv2/rtl/verilog/eth/eth_outputcontrol.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_outputcontrol.v,v $ |
// Revision 1.4 2002/07/09 20:11:59 mohor |
// Comment removed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
109,17 → 106,17
begin |
if(Reset) |
begin |
MdoEn_2d <= #Tp 1'b0; |
MdoEn_d <= #Tp 1'b0; |
MdoEn <= #Tp 1'b0; |
MdoEn_2d <= 1'b0; |
MdoEn_d <= 1'b0; |
MdoEn <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32; |
MdoEn_d <= #Tp MdoEn_2d; |
MdoEn <= #Tp MdoEn_d; |
MdoEn_2d <= SerialEn | InProgress & BitCounter<32; |
MdoEn_d <= MdoEn_2d; |
MdoEn <= MdoEn_d; |
end |
end |
end |
130,17 → 127,17
begin |
if(Reset) |
begin |
Mdo_2d <= #Tp 1'b0; |
Mdo_d <= #Tp 1'b0; |
Mdo <= #Tp 1'b0; |
Mdo_2d <= 1'b0; |
Mdo_d <= 1'b0; |
Mdo <= 1'b0; |
end |
else |
begin |
if(MdcEn_n) |
begin |
Mdo_2d <= #Tp ~SerialEn & BitCounter<32; |
Mdo_d <= #Tp ShiftedBit | Mdo_2d; |
Mdo <= #Tp Mdo_d; |
Mdo_2d <= ~SerialEn & BitCounter<32; |
Mdo_d <= ShiftedBit | Mdo_2d; |
Mdo <= Mdo_d; |
end |
end |
end |
/orpsocv2/rtl/verilog/eth/eth_maccontrol.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_maccontrol.v,v $ |
// Revision 1.7 2003/01/22 13:49:26 tadejm |
// When control packets were received, they were ignored in some cases. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.6 2002/11/22 01:57:06 mohor |
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort |
// synchronized. |
160,13 → 157,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataOutDetected <= #Tp 1'b0; |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxDoneIn | TxAbortIn) |
TxUsedDataOutDetected <= #Tp 1'b0; |
TxUsedDataOutDetected <= 1'b0; |
else |
if(TxUsedDataOut) |
TxUsedDataOutDetected <= #Tp 1'b1; |
TxUsedDataOutDetected <= 1'b1; |
end |
|
|
175,13 → 172,13
begin |
if(TxReset) |
begin |
TxAbortInLatched <= #Tp 1'b0; |
TxDoneInLatched <= #Tp 1'b0; |
TxAbortInLatched <= 1'b0; |
TxDoneInLatched <= 1'b0; |
end |
else |
begin |
TxAbortInLatched <= #Tp TxAbortIn; |
TxDoneInLatched <= #Tp TxDoneIn; |
TxAbortInLatched <= TxAbortIn; |
TxDoneInLatched <= TxDoneIn; |
end |
end |
|
191,13 → 188,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedAbort <= #Tp 1'b0; |
MuxedAbort <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedAbort <= #Tp 1'b0; |
MuxedAbort <= 1'b0; |
else |
if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected) |
MuxedAbort <= #Tp 1'b1; |
MuxedAbort <= 1'b1; |
end |
|
|
205,13 → 202,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
MuxedDone <= #Tp 1'b0; |
MuxedDone <= 1'b0; |
else |
if(TxStartFrmIn) |
MuxedDone <= #Tp 1'b0; |
MuxedDone <= 1'b0; |
else |
if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected) |
MuxedDone <= #Tp 1'b1; |
MuxedDone <= 1'b1; |
end |
|
|
/orpsocv2/rtl/verilog/eth/eth_transmitcontrol.v
40,11 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_transmitcontrol.v,v $ |
// Revision 1.6 2002/11/21 00:16:14 mohor |
// When TxUsedData and CtrlMux occur at the same time, byte counter needs |
// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/11/19 17:37:32 mohor |
// When control frame (PAUSE) was sent, status was written in the |
// eth_wishbone module and both TXB and TXC interrupts were set. Fixed. |
143,13 → 139,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
WillSendControlFrame <= #Tp 1'b0; |
WillSendControlFrame <= 1'b0; |
else |
if(TxCtrlEndFrm & CtrlMux) |
WillSendControlFrame <= #Tp 1'b0; |
WillSendControlFrame <= 1'b0; |
else |
if(TPauseRq & TxFlow) |
WillSendControlFrame <= #Tp 1'b1; |
WillSendControlFrame <= 1'b1; |
end |
|
|
157,13 → 153,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlStartFrm <= #Tp 1'b0; |
TxCtrlStartFrm <= 1'b0; |
else |
if(TxUsedDataIn_q & CtrlMux) |
TxCtrlStartFrm <= #Tp 1'b0; |
TxCtrlStartFrm <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected))) |
TxCtrlStartFrm <= #Tp 1'b1; |
TxCtrlStartFrm <= 1'b1; |
end |
|
|
172,12 → 168,12
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxCtrlEndFrm <= #Tp 1'b0; |
TxCtrlEndFrm <= 1'b0; |
else |
if(ControlEnd | ControlEnd_q) |
TxCtrlEndFrm <= #Tp 1'b1; |
TxCtrlEndFrm <= 1'b1; |
else |
TxCtrlEndFrm <= #Tp 1'b0; |
TxCtrlEndFrm <= 1'b0; |
end |
|
|
186,13 → 182,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
CtrlMux <= #Tp 1'b0; |
CtrlMux <= 1'b0; |
else |
if(WillSendControlFrame & ~TxUsedDataOut) |
CtrlMux <= #Tp 1'b1; |
CtrlMux <= 1'b1; |
else |
if(TxDoneIn) |
CtrlMux <= #Tp 1'b0; |
CtrlMux <= 1'b0; |
end |
|
|
201,13 → 197,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
SendingCtrlFrm <= #Tp 1'b0; |
SendingCtrlFrm <= 1'b0; |
else |
if(WillSendControlFrame & TxCtrlStartFrm) |
SendingCtrlFrm <= #Tp 1'b1; |
SendingCtrlFrm <= 1'b1; |
else |
if(TxDoneIn) |
SendingCtrlFrm <= #Tp 1'b0; |
SendingCtrlFrm <= 1'b0; |
end |
|
|
214,9 → 210,9
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
TxUsedDataIn_q <= #Tp 1'b0; |
TxUsedDataIn_q <= 1'b0; |
else |
TxUsedDataIn_q <= #Tp TxUsedDataIn; |
TxUsedDataIn_q <= TxUsedDataIn; |
end |
|
|
226,20 → 222,20
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
BlockTxDone <= #Tp 1'b0; |
BlockTxDone <= 1'b0; |
else |
if(TxCtrlStartFrm) |
BlockTxDone <= #Tp 1'b1; |
BlockTxDone <= 1'b1; |
else |
if(TxStartFrmIn) |
BlockTxDone <= #Tp 1'b0; |
BlockTxDone <= 1'b0; |
end |
|
|
always @ (posedge MTxClk) |
begin |
ControlEnd_q <= #Tp ControlEnd; |
TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm; |
ControlEnd_q <= ControlEnd; |
TxCtrlStartFrm_q <= TxCtrlStartFrm; |
end |
|
|
250,13 → 246,13
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
DlyCrcCnt <= #Tp 4'h0; |
DlyCrcCnt <= 4'h0; |
else |
if(ResetByteCnt) |
DlyCrcCnt <= #Tp 4'h0; |
DlyCrcCnt <= 4'h0; |
else |
if(IncrementDlyCrcCnt) |
DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1; |
DlyCrcCnt <= DlyCrcCnt + 1'b1; |
end |
|
|
269,16 → 265,16
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ByteCnt <= #Tp 6'h0; |
ByteCnt <= 6'h0; |
else |
if(ResetByteCnt) |
ByteCnt <= #Tp 6'h0; |
ByteCnt <= 6'h0; |
else |
if(IncrementByteCntBy2 & EnableCnt) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2; |
ByteCnt <= (ByteCnt[5:0] ) + 2'h2; |
else |
if(IncrementByteCnt & EnableCnt) |
ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1; |
ByteCnt <= (ByteCnt[5:0] ) + 1'b1; |
end |
|
|
319,10 → 315,10
always @ (posedge MTxClk or posedge TxReset) |
begin |
if(TxReset) |
ControlData[7:0] <= #Tp 8'h0; |
ControlData[7:0] <= 8'h0; |
else |
if(~ByteCnt[0]) |
ControlData[7:0] <= #Tp MuxedCtrlData[7:0]; |
ControlData[7:0] <= MuxedCtrlData[7:0]; |
end |
|
|
/orpsocv2/rtl/verilog/eth/eth_macstatus.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_macstatus.v,v $ |
// Revision 1.17 2005/03/21 20:07:18 igorm |
// Some small fixes + some troubles fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.16 2005/02/21 10:42:11 igorm |
// Defer indication fixed. |
// |
208,13 → 205,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedCrcError <=#Tp 1'b0; |
LatchedCrcError <= 1'b0; |
else |
if(RxStateSFD) |
LatchedCrcError <=#Tp 1'b0; |
LatchedCrcError <= 1'b0; |
else |
if(RxStateData[0]) |
LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0; |
LatchedCrcError <= RxCrcError & ~RxByteCntEq0; |
end |
|
|
222,12 → 219,12
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LatchedMRxErr <=#Tp 1'b0; |
LatchedMRxErr <= 1'b0; |
else |
if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting)) |
LatchedMRxErr <=#Tp 1'b1; |
LatchedMRxErr <= 1'b1; |
else |
LatchedMRxErr <=#Tp 1'b0; |
LatchedMRxErr <= 1'b0; |
end |
|
|
252,9 → 249,9
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
LoadRxStatus <=#Tp 1'b0; |
LoadRxStatus <= 1'b0; |
else |
LoadRxStatus <=#Tp TakeSample; |
LoadRxStatus <= TakeSample; |
end |
|
|
263,9 → 260,9
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceiveEnd <=#Tp 1'b0; |
ReceiveEnd <= 1'b0; |
else |
ReceiveEnd <=#Tp LoadRxStatus; |
ReceiveEnd <= LoadRxStatus; |
end |
|
|
277,13 → 274,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
InvalidSymbol <=#Tp 1'b0; |
InvalidSymbol <= 1'b0; |
else |
if(LoadRxStatus & ~SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b0; |
InvalidSymbol <= 1'b0; |
else |
if(SetInvalidSymbol) |
InvalidSymbol <=#Tp 1'b1; |
InvalidSymbol <= 1'b1; |
end |
|
|
295,13 → 292,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxLateCollision <=#Tp 1'b0; |
RxLateCollision <= 1'b0; |
else |
if(LoadRxStatus) |
RxLateCollision <=#Tp 1'b0; |
RxLateCollision <= 1'b0; |
else |
if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall)) |
RxLateCollision <=#Tp 1'b1; |
RxLateCollision <= 1'b1; |
end |
|
// Collision Window |
308,13 → 305,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
RxColWindow <=#Tp 1'b1; |
RxColWindow <= 1'b1; |
else |
if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1]) |
RxColWindow <=#Tp 1'b0; |
RxColWindow <= 1'b0; |
else |
if(RxStateIdle) |
RxColWindow <=#Tp 1'b1; |
RxColWindow <= 1'b1; |
end |
|
|
323,13 → 320,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ShortFrame <=#Tp 1'b0; |
ShortFrame <= 1'b0; |
else |
if(LoadRxStatus) |
ShortFrame <=#Tp 1'b0; |
ShortFrame <= 1'b0; |
else |
if(TakeSample) |
ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0]; |
ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0]; |
end |
|
|
338,13 → 335,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
DribbleNibble <=#Tp 1'b0; |
DribbleNibble <= 1'b0; |
else |
if(RxStateSFD) |
DribbleNibble <=#Tp 1'b0; |
DribbleNibble <= 1'b0; |
else |
if(~MRxDV & RxStateData[1]) |
DribbleNibble <=#Tp 1'b1; |
DribbleNibble <= 1'b1; |
end |
|
|
352,13 → 349,13
always @ (posedge MRxClk or posedge Reset) |
begin |
if(Reset) |
ReceivedPacketTooBig <=#Tp 1'b0; |
ReceivedPacketTooBig <= 1'b0; |
else |
if(LoadRxStatus) |
ReceivedPacketTooBig <=#Tp 1'b0; |
ReceivedPacketTooBig <= 1'b0; |
else |
if(TakeSample) |
ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0]; |
end |
|
|
367,10 → 364,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryCntLatched <=#Tp 4'h0; |
RetryCntLatched <= 4'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryCntLatched <=#Tp RetryCnt; |
RetryCntLatched <= RetryCnt; |
end |
|
|
378,10 → 375,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
RetryLimit <=#Tp 1'h0; |
RetryLimit <= 1'h0; |
else |
if(StartTxDone | StartTxAbort) |
RetryLimit <=#Tp MaxCollisionOccured; |
RetryLimit <= MaxCollisionOccured; |
end |
|
|
389,10 → 386,10
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
LateCollLatched <=#Tp 1'b0; |
LateCollLatched <= 1'b0; |
else |
if(StartTxDone | StartTxAbort) |
LateCollLatched <=#Tp LateCollision; |
LateCollLatched <= LateCollision; |
end |
|
|
401,13 → 398,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
DeferLatched <=#Tp 1'b0; |
DeferLatched <= 1'b0; |
else |
if(DeferIndication) |
DeferLatched <=#Tp 1'b1; |
DeferLatched <= 1'b1; |
else |
if(RstDeferLatched) |
DeferLatched <=#Tp 1'b0; |
DeferLatched <= 1'b0; |
end |
|
|
415,13 → 412,13
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
CarrierSenseLost <=#Tp 1'b0; |
CarrierSenseLost <= 1'b0; |
else |
if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD) |
CarrierSenseLost <=#Tp 1'b1; |
CarrierSenseLost <= 1'b1; |
else |
if(TxStartFrm) |
CarrierSenseLost <=#Tp 1'b0; |
CarrierSenseLost <= 1'b0; |
end |
|
|
/orpsocv2/rtl/verilog/eth/eth_rxstatem.v
42,11 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_rxstatem.v,v $ |
// Revision 1.6 2002/11/13 22:28:26 tadejm |
// StartIdle state changed (not important the size of the packet). |
// StartData1 activates only while ByteCnt is smaller than the MaxFrame. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
148,50 → 144,50
begin |
if(Reset) |
begin |
StateIdle <= #Tp 1'b0; |
StateDrop <= #Tp 1'b1; |
StatePreamble <= #Tp 1'b0; |
StateSFD <= #Tp 1'b0; |
StateData0 <= #Tp 1'b0; |
StateData1 <= #Tp 1'b0; |
StateIdle <= 1'b0; |
StateDrop <= 1'b1; |
StatePreamble <= 1'b0; |
StateSFD <= 1'b0; |
StateData0 <= 1'b0; |
StateData1 <= 1'b0; |
end |
else |
begin |
if(StartPreamble | StartSFD | StartDrop) |
StateIdle <= #Tp 1'b0; |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= #Tp 1'b1; |
StateIdle <= 1'b1; |
|
if(StartIdle) |
StateDrop <= #Tp 1'b0; |
StateDrop <= 1'b0; |
else |
if(StartDrop) |
StateDrop <= #Tp 1'b1; |
StateDrop <= 1'b1; |
|
if(StartSFD | StartIdle | StartDrop) |
StatePreamble <= #Tp 1'b0; |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= #Tp 1'b1; |
StatePreamble <= 1'b1; |
|
if(StartPreamble | StartIdle | StartData0 | StartDrop) |
StateSFD <= #Tp 1'b0; |
StateSFD <= 1'b0; |
else |
if(StartSFD) |
StateSFD <= #Tp 1'b1; |
StateSFD <= 1'b1; |
|
if(StartIdle | StartData1 | StartDrop) |
StateData0 <= #Tp 1'b0; |
StateData0 <= 1'b0; |
else |
if(StartData0) |
StateData0 <= #Tp 1'b1; |
StateData0 <= 1'b1; |
|
if(StartIdle | StartData0 | StartDrop) |
StateData1 <= #Tp 1'b0; |
StateData1 <= 1'b0; |
else |
if(StartData1) |
StateData1 <= #Tp 1'b1; |
StateData1 <= 1'b1; |
end |
end |
|
/orpsocv2/rtl/verilog/eth/eth_registers.v
40,10 → 40,7
// |
// CVS Revision History |
// |
// $Log: eth_registers.v,v $ |
// Revision 1.29 2005/03/21 20:07:18 igorm |
// Some small fixes + some troubles fixed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.28 2004/04/26 15:26:23 igorm |
// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the |
// previous update of the core. |
180,7 → 177,8
r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat, |
LinkFail, r_MAC, WCtrlDataStart, RStatStart, |
UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o, |
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm, |
dbg_dat, // jb |
StartTxDone, TxClk, RxClk, SetPauseTimer |
); |
|
273,6 → 271,9
input RxClk; |
input SetPauseTimer; |
|
input [31:0] dbg_dat; // debug data input - JB |
|
|
reg irq_txb; |
reg irq_txe; |
reg irq_rxb; |
316,9 → 317,11
wire HASH1_Sel = (Address == `ETH_HASH1_ADR ); |
wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR ); |
wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR ); |
wire DBG_REG_Sel = (Address == `ETH_DBG_ADR ); // JB |
wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR ); |
|
|
|
wire [2:0] MODER_Wr; |
wire [0:0] INT_SOURCE_Wr; |
wire [0:0] INT_MASK_Wr; |
407,6 → 410,7
wire [31:0] HASH0Out; |
wire [31:0] HASH1Out; |
wire [31:0] TXCTRLOut; |
wire [31:0] DBGOut; // JB |
|
// MODER Register |
eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0 |
415,7 → 419,8
.DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]), |
.Write (MODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1 |
( |
423,7 → 428,8
.DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]), |
.Write (MODER_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2 |
( |
431,7 → 437,8
.DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]), |
.Write (MODER_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0; |
|
442,12 → 449,11
.DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]), |
.Write (INT_MASK_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0; |
`ifdef ETH_IPGT |
assign IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0] = `ETH_IPGT_DEF_0; |
`else |
|
// IPGT Register |
eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0 |
( |
455,13 → 461,11
.DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]), |
.Write (IPGT_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif |
assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0; |
`ifdef ETH_IPGR1 |
assign IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0] = `ETH_IPGR1_DEF_0; |
`else |
|
// IPGR1 Register |
eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0 |
( |
469,14 → 473,11
.DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]), |
.Write (IPGR1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif |
assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0; |
|
`ifdef ETH_IPGR2 |
assign IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0] = `ETH_IPGR2_DEF_0; |
`else |
// IPGR2 Register |
eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0 |
( |
484,14 → 485,11
.DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]), |
.Write (IPGR2_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif |
assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0; |
|
`ifdef ETH_PACKETLEN |
assign PACKETLENOut = {`ETH_PACKETLEN_DEF_3,`ETH_PACKETLEN_DEF_2,`ETH_PACKETLEN_DEF_1,`ETH_PACKETLEN_DEF_0}; |
`else |
// PACKETLEN Register |
eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0 |
( |
499,7 → 497,8
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]), |
.Write (PACKETLEN_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1 |
( |
507,7 → 506,8
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]), |
.Write (PACKETLEN_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2 |
( |
515,7 → 515,8
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]), |
.Write (PACKETLEN_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3 |
( |
523,14 → 524,10
.DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]), |
.Write (PACKETLEN_Wr[3]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif // !`ifdef |
|
`ifdef ETH_COLLCONF |
assign COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0] = `ETH_COLLCONF_DEF_0; |
assign COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16] = `ETH_COLLCONF_DEF_2; |
`else |
// COLLCONF Register |
eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0 |
( |
538,7 → 535,8
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]), |
.Write (COLLCONF_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2 |
( |
546,9 → 544,9
.DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]), |
.Write (COLLCONF_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif |
assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0; |
assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0; |
|
559,7 → 557,8
.DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]), |
.Write (TX_BD_NUM_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0; |
|
570,7 → 569,8
.DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]), |
.Write (CTRLMODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0; |
|
581,7 → 581,8
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]), |
.Write (MIIMODER_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1 |
( |
589,7 → 590,8
.DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]), |
.Write (MIIMODER_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0; |
|
600,7 → 602,8
.DataOut (MIICOMMANDOut[0]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(1, 0) MIICOMMAND1 |
( |
608,7 → 611,8
.DataOut (MIICOMMANDOut[1]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (RStatStart) |
); |
eth_register #(1, 0) MIICOMMAND2 |
( |
616,7 → 620,8
.DataOut (MIICOMMANDOut[2]), |
.Write (MIICOMMAND_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (WCtrlDataStart) |
); |
assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0; |
|
627,7 → 632,8
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]), |
.Write (MIIADDRESS_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1 |
( |
635,7 → 641,8
.DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]), |
.Write (MIIADDRESS_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0; |
assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0; |
647,7 → 654,8
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]), |
.Write (MIITX_DATA_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1 |
( |
655,7 → 663,8
.DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]), |
.Write (MIITX_DATA_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0; |
|
666,14 → 675,11
.DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]), |
.Write (MIIRX_DATA_Wr), // not written from WB |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0; |
|
`ifdef ETH_MAC_ADDR |
assign MAC_ADDR0Out = {`ETH_MAC_ADDR0_DEF_3,`ETH_MAC_ADDR0_DEF_2,`ETH_MAC_ADDR0_DEF_1,`ETH_MAC_ADDR0_DEF_0}; |
assign MAC_ADDR1Out = {16'h0,`ETH_MAC_ADDR1_DEF_1,`ETH_MAC_ADDR1_DEF_0}; |
`else |
// MAC_ADDR0 Register |
eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0 |
( |
681,7 → 687,8
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]), |
.Write (MAC_ADDR0_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1 |
( |
689,7 → 696,8
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]), |
.Write (MAC_ADDR0_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2 |
( |
697,7 → 705,8
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]), |
.Write (MAC_ADDR0_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3 |
( |
705,7 → 714,8
.DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]), |
.Write (MAC_ADDR0_Wr[3]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
|
// MAC_ADDR1 Register |
715,7 → 725,8
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]), |
.Write (MAC_ADDR1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1 |
( |
723,13 → 734,11
.DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]), |
.Write (MAC_ADDR1_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0; |
`endif // !`ifdef ETH_MAC_ADDR |
`ifdef ETH_HASH0 |
assign HASH0Out = {`ETH_HASH0_DEF_3,`ETH_HASH0_DEF_2,`ETH_HASH0_DEF_1,`ETH_HASH0_DEF_0}; |
`else |
|
// RXHASH0 Register |
eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0 |
( |
737,7 → 746,8
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]), |
.Write (HASH0_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1 |
( |
745,7 → 755,8
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]), |
.Write (HASH0_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2 |
( |
753,7 → 764,8
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]), |
.Write (HASH0_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3 |
( |
761,12 → 773,10
.DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]), |
.Write (HASH0_Wr[3]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif // !`ifdef ETH_HASH0 |
`ifdef ETH_HASH1 |
assign HASH1Out = {`ETH_HASH1_DEF_3,`ETH_HASH1_DEF_2,`ETH_HASH1_DEF_1,`ETH_HASH1_DEF_0}; |
`else |
|
// RXHASH1 Register |
eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0 |
( |
774,7 → 784,8
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]), |
.Write (HASH1_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1 |
( |
782,7 → 793,8
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]), |
.Write (HASH1_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2 |
( |
790,7 → 802,8
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]), |
.Write (HASH1_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3 |
( |
798,9 → 811,10
.DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]), |
.Write (HASH1_Wr[3]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
`endif |
|
// TXCTRL Register |
eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0 |
( |
808,7 → 822,8
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]), |
.Write (TXCTRL_Wr[0]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1 |
( |
816,7 → 831,8
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]), |
.Write (TXCTRL_Wr[1]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (1'b0) |
); |
eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset |
( |
824,12 → 840,13
.DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]), |
.Write (TXCTRL_Wr[2]), |
.Clk (Clk), |
.Reset (Reset) |
.Reset (Reset), |
.SyncReset (RstTxPauseRq) |
); |
assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0; |
|
/* verilator lint_off COMBDLY */ |
|
|
// Reading data from registers |
always @ (Address or Read or MODEROut or INT_SOURCEOut or |
INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or |
863,7 → 880,7
`ETH_HASH0_ADR : DataOut<=HASH0Out; |
`ETH_HASH1_ADR : DataOut<=HASH1Out; |
`ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut; |
|
`ETH_DBG_ADR : DataOut<=dbg_dat; // debug data out -- JB |
default: DataOut<=32'h0; |
endcase |
end |
871,7 → 888,6
DataOut<=32'h0; |
end |
|
/* verilator lint_on COMBDLY */ |
|
assign r_RecSmall = MODEROut[16]; |
assign r_Pad = MODEROut[15]; |
939,13 → 955,13
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_txclk <=#Tp 1'b0; |
SetTxCIrq_txclk <= 1'b0; |
else |
if(TxCtrlEndFrm & StartTxDone & r_TxFlow) |
SetTxCIrq_txclk <=#Tp 1'b1; |
SetTxCIrq_txclk <= 1'b1; |
else |
if(ResetTxCIrq_sync2) |
SetTxCIrq_txclk <=#Tp 1'b0; |
SetTxCIrq_txclk <= 1'b0; |
end |
|
|
952,49 → 968,49
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync1 <=#Tp 1'b0; |
SetTxCIrq_sync1 <= 1'b0; |
else |
SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk; |
SetTxCIrq_sync1 <= SetTxCIrq_txclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync2 <=#Tp 1'b0; |
SetTxCIrq_sync2 <= 1'b0; |
else |
SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
SetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq_sync3 <=#Tp 1'b0; |
SetTxCIrq_sync3 <= 1'b0; |
else |
SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2; |
SetTxCIrq_sync3 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetTxCIrq <=#Tp 1'b0; |
SetTxCIrq <= 1'b0; |
else |
SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
SetTxCIrq <= SetTxCIrq_sync2 & ~SetTxCIrq_sync3; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync1 <=#Tp 1'b0; |
ResetTxCIrq_sync1 <= 1'b0; |
else |
ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2; |
ResetTxCIrq_sync1 <= SetTxCIrq_sync2; |
end |
|
always @ (posedge TxClk or posedge Reset) |
begin |
if(Reset) |
ResetTxCIrq_sync2 <=#Tp 1'b0; |
ResetTxCIrq_sync2 <= 1'b0; |
else |
ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1; |
ResetTxCIrq_sync2 <= SetTxCIrq_sync1; |
end |
|
|
1002,13 → 1018,13
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
SetRxCIrq_rxclk <= 1'b0; |
else |
if(SetPauseTimer & r_RxFlow) |
SetRxCIrq_rxclk <=#Tp 1'b1; |
SetRxCIrq_rxclk <= 1'b1; |
else |
if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3)) |
SetRxCIrq_rxclk <=#Tp 1'b0; |
SetRxCIrq_rxclk <= 1'b0; |
end |
|
|
1015,57 → 1031,57
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync1 <=#Tp 1'b0; |
SetRxCIrq_sync1 <= 1'b0; |
else |
SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk; |
SetRxCIrq_sync1 <= SetRxCIrq_rxclk; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync2 <=#Tp 1'b0; |
SetRxCIrq_sync2 <= 1'b0; |
else |
SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1; |
SetRxCIrq_sync2 <= SetRxCIrq_sync1; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq_sync3 <=#Tp 1'b0; |
SetRxCIrq_sync3 <= 1'b0; |
else |
SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2; |
SetRxCIrq_sync3 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge Clk or posedge Reset) |
begin |
if(Reset) |
SetRxCIrq <=#Tp 1'b0; |
SetRxCIrq <= 1'b0; |
else |
SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
SetRxCIrq <= SetRxCIrq_sync2 & ~SetRxCIrq_sync3; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync1 <=#Tp 1'b0; |
ResetRxCIrq_sync1 <= 1'b0; |
else |
ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2; |
ResetRxCIrq_sync1 <= SetRxCIrq_sync2; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync2 <=#Tp 1'b0; |
ResetRxCIrq_sync2 <= 1'b0; |
else |
ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1; |
ResetRxCIrq_sync2 <= ResetRxCIrq_sync1; |
end |
|
always @ (posedge RxClk or posedge Reset) |
begin |
if(Reset) |
ResetRxCIrq_sync3 <=#Tp 1'b0; |
ResetRxCIrq_sync3 <= 1'b0; |
else |
ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2; |
ResetRxCIrq_sync3 <= ResetRxCIrq_sync2; |
end |
|
|
1077,10 → 1093,10
irq_txb <= 1'b0; |
else |
if(TxB_IRQ) |
irq_txb <= #Tp 1'b1; |
irq_txb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[0]) |
irq_txb <= #Tp 1'b0; |
irq_txb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1089,10 → 1105,10
irq_txe <= 1'b0; |
else |
if(TxE_IRQ) |
irq_txe <= #Tp 1'b1; |
irq_txe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[1]) |
irq_txe <= #Tp 1'b0; |
irq_txe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1101,10 → 1117,10
irq_rxb <= 1'b0; |
else |
if(RxB_IRQ) |
irq_rxb <= #Tp 1'b1; |
irq_rxb <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[2]) |
irq_rxb <= #Tp 1'b0; |
irq_rxb <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1113,10 → 1129,10
irq_rxe <= 1'b0; |
else |
if(RxE_IRQ) |
irq_rxe <= #Tp 1'b1; |
irq_rxe <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[3]) |
irq_rxe <= #Tp 1'b0; |
irq_rxe <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1125,10 → 1141,10
irq_busy <= 1'b0; |
else |
if(Busy_IRQ) |
irq_busy <= #Tp 1'b1; |
irq_busy <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[4]) |
irq_busy <= #Tp 1'b0; |
irq_busy <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1137,10 → 1153,10
irq_txc <= 1'b0; |
else |
if(SetTxCIrq) |
irq_txc <= #Tp 1'b1; |
irq_txc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[5]) |
irq_txc <= #Tp 1'b0; |
irq_txc <= 1'b0; |
end |
|
always @ (posedge Clk or posedge Reset) |
1149,10 → 1165,10
irq_rxc <= 1'b0; |
else |
if(SetRxCIrq) |
irq_rxc <= #Tp 1'b1; |
irq_rxc <= 1'b1; |
else |
if(INT_SOURCE_Wr[0] & DataIn[6]) |
irq_rxc <= #Tp 1'b0; |
irq_rxc <= 1'b0; |
end |
|
// Generating interrupt signal |
/orpsocv2/rtl/verilog/eth/eth_crc.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_crc.v,v $ |
// Revision 1.3 2002/01/23 10:28:16 mohor |
// Link in the header changed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.2 2001/10/19 08:43:51 mohor |
// eth_timescale.v changed to timescale.v This is done because of the |
// simulation of the few cores in a one joined project. |
135,12 → 132,12
always @ (posedge Clk or posedge Reset) |
begin |
if (Reset) |
Crc <= #1 32'hffffffff; |
Crc <= 32'hffffffff; |
else |
if(Initialize) |
Crc <= #Tp 32'hffffffff; |
Crc <= 32'hffffffff; |
else |
Crc <= #Tp CrcNext; |
Crc <= CrcNext; |
end |
|
assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number |
/orpsocv2/rtl/verilog/eth/eth_txstatem.v
42,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_txstatem.v,v $ |
// Revision 1.6 2003/01/30 13:29:08 tadejm |
// Defer indication changed. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.5 2002/10/30 12:54:50 mohor |
// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. |
// |
200,69 → 197,69
begin |
if(Reset) |
begin |
StateIPG <= #Tp 1'b0; |
StateIdle <= #Tp 1'b0; |
StatePreamble <= #Tp 1'b0; |
StateData[1:0] <= #Tp 2'b0; |
StatePAD <= #Tp 1'b0; |
StateFCS <= #Tp 1'b0; |
StateJam <= #Tp 1'b0; |
StateJam_q <= #Tp 1'b0; |
StateBackOff <= #Tp 1'b0; |
StateDefer <= #Tp 1'b1; |
StateIPG <= 1'b0; |
StateIdle <= 1'b0; |
StatePreamble <= 1'b0; |
StateData[1:0] <= 2'b0; |
StatePAD <= 1'b0; |
StateFCS <= 1'b0; |
StateJam <= 1'b0; |
StateJam_q <= 1'b0; |
StateBackOff <= 1'b0; |
StateDefer <= 1'b1; |
end |
else |
begin |
StateData[1:0] <= #Tp StartData[1:0]; |
StateJam_q <= #Tp StateJam; |
StateData[1:0] <= StartData[1:0]; |
StateJam_q <= StateJam; |
|
if(StartDefer | StartIdle) |
StateIPG <= #Tp 1'b0; |
StateIPG <= 1'b0; |
else |
if(StartIPG) |
StateIPG <= #Tp 1'b1; |
StateIPG <= 1'b1; |
|
if(StartDefer | StartPreamble) |
StateIdle <= #Tp 1'b0; |
StateIdle <= 1'b0; |
else |
if(StartIdle) |
StateIdle <= #Tp 1'b1; |
StateIdle <= 1'b1; |
|
if(StartData[0] | StartJam) |
StatePreamble <= #Tp 1'b0; |
StatePreamble <= 1'b0; |
else |
if(StartPreamble) |
StatePreamble <= #Tp 1'b1; |
StatePreamble <= 1'b1; |
|
if(StartFCS | StartJam) |
StatePAD <= #Tp 1'b0; |
StatePAD <= 1'b0; |
else |
if(StartPAD) |
StatePAD <= #Tp 1'b1; |
StatePAD <= 1'b1; |
|
if(StartJam | StartDefer) |
StateFCS <= #Tp 1'b0; |
StateFCS <= 1'b0; |
else |
if(StartFCS) |
StateFCS <= #Tp 1'b1; |
StateFCS <= 1'b1; |
|
if(StartBackoff | StartDefer) |
StateJam <= #Tp 1'b0; |
StateJam <= 1'b0; |
else |
if(StartJam) |
StateJam <= #Tp 1'b1; |
StateJam <= 1'b1; |
|
if(StartDefer) |
StateBackOff <= #Tp 1'b0; |
StateBackOff <= 1'b0; |
else |
if(StartBackoff) |
StateBackOff <= #Tp 1'b1; |
StateBackOff <= 1'b1; |
|
if(StartIPG) |
StateDefer <= #Tp 1'b0; |
StateDefer <= 1'b0; |
else |
if(StartDefer) |
StateDefer <= #Tp 1'b1; |
StateDefer <= 1'b1; |
end |
end |
|
271,14 → 268,14
always @ (posedge MTxClk or posedge Reset) |
begin |
if(Reset) |
Rule1 <= #Tp 1'b0; |
Rule1 <= 1'b0; |
else |
begin |
if(StateIdle | StateBackOff) |
Rule1 <= #Tp 1'b0; |
Rule1 <= 1'b0; |
else |
if(StatePreamble | FullD) |
Rule1 <= #Tp 1'b1; |
Rule1 <= 1'b1; |
end |
end |
|
/orpsocv2/rtl/verilog/smii/smii_txrx.v
File deleted
orpsocv2/rtl/verilog/smii/smii_txrx.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/or1200/or1200_alu.v
===================================================================
--- orpsocv2/rtl/verilog/or1200/or1200_alu.v (revision 402)
+++ orpsocv2/rtl/verilog/or1200/or1200_alu.v (revision 403)
@@ -53,7 +53,7 @@
module or1200_alu(
a, b, mult_mac_result, macrc_op,
- alu_op, shrot_op, comp_op,
+ alu_op, alu_op2, shrot_op, comp_op,
cust5_op, cust5_limm,
result, flagforw, flag_we,
cyforw, cy_we, carry, flag
@@ -69,6 +69,7 @@
input [width-1:0] mult_mac_result;
input macrc_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
+input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
input [4:0] cust5_op;
@@ -142,7 +143,8 @@
//
// Central part of the ALU
//
-always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
+always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
+ or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ADDC
or result_csum
`endif
@@ -152,9 +154,22 @@
`else
casez (alu_op) // synopsys full_case parallel_case
`endif
- `OR1200_ALUOP_FF1: begin
+`ifdef OR1200_IMPL_ALU_FFL1
+ `OR1200_ALUOP_FFL1: begin
+`ifdef OR1200_CASE_DEFAULT
+ casez (alu_op2) // synopsys parallel_case
+`else
+ casez (alu_op2) // synopsys full_case parallel_case
+`endif
+ 0: begin // FF1
result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
- end
+ end
+ default: begin // FL1
+ result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
+ end
+ endcase // casez (alu_op2)
+ end // case: `OR1200_ALUOP_FFL1
+`endif
`OR1200_ALUOP_CUST5 : begin
result = result_cust5;
end
/orpsocv2/rtl/verilog/or1200/or1200_cpu.v
221,6 → 221,7
wire [dw-1:2] id_branch_addrtarget; |
wire [dw-1:2] ex_branch_addrtarget; |
wire [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
wire [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
wire [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
wire [`OR1200_COMPOP_WIDTH-1:0] comp_op; |
wire [`OR1200_BRANCHOP_WIDTH-1:0] pre_branch_op; |
484,6 → 485,7
.rf_rda(rf_rda), |
.rf_rdb(rf_rdb), |
.alu_op(alu_op), |
.alu_op2(alu_op2), |
.mac_op(mac_op), |
.shrot_op(shrot_op), |
.comp_op(comp_op), |
582,6 → 584,7
.mult_mac_result(mult_mac_result), |
.macrc_op(ex_macrc_op), |
.alu_op(alu_op), |
.alu_op2(alu_op2), |
.shrot_op(shrot_op), |
.comp_op(comp_op), |
.cust5_op(cust5_op), |
/orpsocv2/rtl/verilog/or1200/or1200_ctrl.v
62,8 → 62,8
wb_flushpipe, |
id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr, |
id_branch_op, ex_branch_op, ex_branch_taken, pc_we, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, mac_op, shrot_op, comp_op, |
rf_addrw, rfwb_op, fpu_op, |
rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op, |
comp_op, rf_addrw, rfwb_op, fpu_op, |
wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a, |
sel_b, id_lsu_op, |
cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt, |
100,6 → 100,7
output rf_rda; |
output rf_rdb; |
output [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
output [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
output [`OR1200_MACOP_WIDTH-1:0] mac_op; |
output [`OR1200_SHROTOP_WIDTH-1:0] shrot_op; |
output [`OR1200_RFWBOP_WIDTH-1:0] rfwb_op; |
144,6 → 145,7
reg [`OR1200_BRANCHOP_WIDTH-1:0] id_branch_op; |
reg [`OR1200_BRANCHOP_WIDTH-1:0] ex_branch_op; |
reg [`OR1200_ALUOP_WIDTH-1:0] alu_op; |
reg [`OR1200_ALUOP2_WIDTH-1:0] alu_op2; |
wire if_maci_op; |
`ifdef OR1200_MAC_IMPLEMENTED |
reg [`OR1200_MACOP_WIDTH-1:0] ex_mac_op; |
750,6 → 752,11
| (id_insn[3:0] == `OR1200_ALUOP_ADDC) |
`endif |
|
`ifdef OR1200_IMPL_ALU_FFL1 |
`else |
| (id_insn[3:0] == `OR1200_ALUOP_FFL1) |
`endif |
|
`ifdef OR1200_IMPL_ALU_ROTATE |
`else |
| ((id_insn[3:0] == `OR1200_ALUOP_SHROT) & |
844,7 → 851,22
end |
end |
|
|
// |
// Decode of alu_op2 (field of bits 9:8) |
// |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
if (rst == `OR1200_RST_VALUE) |
alu_op2 <= 0; |
else if (!ex_freeze & id_freeze | ex_flushpipe) |
alu_op2 <= 0; |
else if (!ex_freeze) begin |
alu_op2 <= id_insn[`OR1200_ALUOP2_POS]; |
end |
end |
|
|
// |
// Decode of spr_read, spr_write |
// |
always @(posedge clk or `OR1200_RST_EVENT rst) begin |
/orpsocv2/rtl/verilog/include/eth_defines.v
4,6 → 4,8
//// //// |
//// This file is part of the Ethernet IP core project //// |
//// http://www.opencores.org/projects/ethmac/ //// |
//// Altered by Julius Baxter, julius.baxter@orsoc.se, increasing //// |
//// TX fifo buffer size, and uncommenting WB_B3 compat define //// |
//// //// |
//// Author(s): //// |
//// - Igor Mohor (igorM@opencores.org) //// |
40,10 → 42,7
// |
// CVS Revision History |
// |
// $Log: eth_defines.v,v $ |
// Revision 1.34 2005/02/21 12:48:06 igorm |
// Warning fixes. |
// |
// $Log: not supported by cvs2svn $ |
// Revision 1.33 2003/11/12 18:24:58 tadejm |
// WISHBONE slave changed and tested from only 32-bit accesss to byte access. |
// |
182,6 → 181,8
|
`define ETH_MBIST_CTRL_WIDTH 3 // width of MBIST control bus |
|
// Generic FIFO implementation - hopefully synthesizable with Synplify |
`define ETH_FIFO_GENERIC |
// Ethernet implemented in Xilinx Chips (uncomment following lines) |
// `define ETH_FIFO_XILINX // Use Xilinx distributed ram for tx and rx fifo |
// `define ETH_XILINX_RAMB4 // Selection of the used memory for Buffer descriptors |
222,6 → 223,7
`define ETH_HASH1_ADR 8'h13 // 0x4C |
`define ETH_TX_CTRL_ADR 8'h14 // 0x50 |
`define ETH_RX_CTRL_ADR 8'h15 // 0x54 |
`define ETH_DBG_ADR 8'h16 // 0x58 |
|
|
`define ETH_MODER_DEF_0 8'h00 |
317,21 → 319,74
`define ETH_REGISTERED_OUTPUTS |
|
// Settings for TX FIFO |
//`define ETH_TX_FIFO_CNT_WIDTH 5 |
//`define ETH_TX_FIFO_DEPTH 16 |
// Settings for TX FIFO buffer for a while ethernet packet (1500 bytes) |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_DEPTH 375 |
`define ETH_TX_FIFO_DATA_WIDTH 32 |
|
// Defines for ethernet TX fifo size - impacts FPGA resource usage |
//`define ETH_TX_FULL_PACKET_FIFO // Full 1500 byte TX buffer - uncomment this |
//`define ETH_TX_256BYTE_FIFO // 256 byte TX buffer - uncomment this |
//`define ETH_TX_512BYTE_FIFO // 512 byte TX buffer - uncomment this |
`define ETH_TX_1KBYTE_FIFO // 1024 byte TX buffer - uncomment this |
|
`ifdef ETH_TX_FULL_PACKET_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 11 |
`define ETH_TX_FIFO_DEPTH 375 |
`else |
`ifdef ETH_TX_1KBYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 9 |
`define ETH_TX_FIFO_DEPTH 256 |
`else |
`ifdef ETH_TX_512BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 8 |
`define ETH_TX_FIFO_DEPTH 128 |
`else |
`ifdef ETH_TX_256BYTE_FIFO |
`define ETH_TX_FIFO_CNT_WIDTH 7 |
`define ETH_TX_FIFO_DEPTH 64 |
`else |
// Default is 64 bytes |
`define ETH_TX_FIFO_CNT_WIDTH 5 |
`define ETH_TX_FIFO_DEPTH 16 |
`endif |
`endif |
`endif // !`ifdef ETH_TX_512BYTE_FIFO |
`endif // !`ifdef ETH_TX_FULL_PACKET_FIFO |
|
|
|
// Settings for RX FIFO |
`define ETH_RX_FIFO_CNT_WIDTH 5 |
`define ETH_RX_FIFO_DEPTH 16 |
`define ETH_RX_FIFO_CNT_WIDTH 9 |
`define ETH_RX_FIFO_DEPTH 256 |
//`define ETH_RX_FIFO_CNT_WIDTH 8 |
//`define ETH_RX_FIFO_DEPTH 128 |
//`define ETH_RX_FIFO_CNT_WIDTH 7 |
//`define ETH_RX_FIFO_DEPTH 64 |
//`define ETH_RX_FIFO_CNT_WIDTH 6 |
//`define ETH_RX_FIFO_DEPTH 32 |
//`define ETH_RX_FIFO_CNT_WIDTH 5 |
//`define ETH_RX_FIFO_DEPTH 16 |
|
`define ETH_RX_FIFO_DATA_WIDTH 32 |
|
// Burst length |
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH |
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH |
`define BURST_4BEAT |
`ifdef BURST_4BEAT |
`define ETH_BURST_LENGTH 4 // Change also ETH_BURST_CNT_WIDTH |
`define ETH_BURST_CNT_WIDTH 3 // The counter must be width enough to count to ETH_BURST_LENGTH |
`endif |
|
//`define ETH_BURST_LENGTH 32 // Change also ETH_BURST_CNT_WIDTH |
//`define ETH_BURST_CNT_WIDTH 7 // The counter must be width enough to count to ETH_BURST_LENGTH |
|
// Undefine this to enable bursting for RX (writing to memory) |
`define ETH_RX_BURST_EN |
|
|
// WISHBONE interface is Revision B3 compliant (uncomment when needed) |
`define ETH_WISHBONE_B3 |
|
// Hack where the transmit logic polls each of the TX buffers instead of having to keep track of what's going on |
//`define TXBD_POLL |
|
// Define this to allow reading of the Wishbone control state machine on reg |
// address 0x58 |
`define WISHBONE_DEBUG |
/orpsocv2/rtl/verilog/include/or1200_defines.v
345,6 → 345,11
`define OR1200_IMPL_ALU_COMP2 |
|
// |
// Implement Find First/Last '1' |
// |
`define OR1200_IMPL_ALU_FFL1 |
|
// |
// Implement multiplier |
// |
// By default multiplier is implemented |
466,7 → 471,15
`define OR1200_ALUOP_MTSR 4'd14 |
`define OR1200_ALUOP_MFSR 4'd15 |
`define OR1200_ALUOP_CMOV 4'd14 |
`define OR1200_ALUOP_FF1 4'd15 |
`define OR1200_ALUOP_FFL1 4'd15 |
|
|
// ALU instructions second opcode field (previously multicycle field in |
// machine word) |
`define OR1200_ALUOP2_POS 9:8 |
`define OR1200_ALUOP2_WIDTH 2 |
|
|
// |
// MACOPs |
// |
625,9 → 638,6
// SHROT_OP position in machine word |
`define OR1200_SHROTOP_POS 7:6 |
|
// ALU instructions multicycle field in machine word |
`define OR1200_ALUMCYC_POS 9:8 |
|
// |
// Instruction opcode groups (basic) |
// |
867,7 → 877,7
// |
|
// Define it if you want DU implemented |
//`define OR1200_DU_IMPLEMENTED |
`define OR1200_DU_IMPLEMENTED |
|
// |
// Define if you want HW Breakpoints |
/orpsocv2/rtl/verilog/include/orpsoc-defines.v
35,7 → 35,7
|
// Define board clock - main system clock period |
// 20ns period = 50MHz freq. |
`define BOARD_CLOCK_PERIOD_NS 20 |
`define BOARD_CLOCK_PERIOD 20 |
|
// Included modules: define to include |
`define JTAG_DEBUG |
/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
509,7 → 509,7
// |
// Instantiation |
// |
or1200_top or1200_top |
or1200_top or1200_top0 |
( |
// Instruction bus, clocks, reset |
.iwb_clk_i (wb_clk), |
/orpsocv2/sim/bin/verilator.scr
File deleted
/orpsocv2/sim/bin/icarus.scr
File deleted
/orpsocv2/sim/bin/modelsim.scr
File deleted
/orpsocv2/sim/bin/definesgen.inc
0,0 → 1,38
# A make rule that creates the test defines verilog file. |
|
# Test defines.v file, called recursively, .PHONY to force its generation |
.PHONY: $(TEST_DEFINES_VLG) |
$(TEST_DEFINES_VLG): |
$(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@ |
$(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr "[:lower:]" "[:upper:]"` >> $@ |
$(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@ |
$(Q)if [ ! -z $$VCD ]; \ |
then echo "\`define VCD" >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DELAY ]; \ |
then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DEPTH ]; \ |
then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \ |
then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \ |
fi |
$(Q)if [ ! -z $$END_TIME ]; \ |
then echo "\`define END_TIME "$$END_TIME >> $@; \ |
fi |
$(Q)if [ ! -z $$END_INSNS ]; \ |
then echo "\`define END_INSNS "$$END_INSNS >> $@; \ |
fi |
$(Q)if [ ! -z $$PRELOAD_RAM ]; \ |
then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \ |
fi |
$(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \ |
then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \ |
fi |
$(Q)if [ ! -z $$VPI ]; \ |
then echo "\`define VPI_DEBUG" >> $@; \ |
fi |
$(Q)if [ ! -z $$SIM_QUIET ]; \ |
then echo "\`define SIM_QUIET" >> $@; \ |
fi |
/orpsocv2/sim/bin/Makefile
55,7 → 55,7
# Need this for individual test variables to not break |
TEST ?= or1200-simple |
|
TESTS ?= or1200-simple or1200-basic or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-except or1200-mac or1200-linkregtest or1200-tick or1200-ticksyscall uart-simple |
TESTS ?= or1200-simple or1200-basic or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-except or1200-mac or1200-ffl1 or1200-linkregtest or1200-tick or1200-ticksyscall uart-simple |
|
# Gets turned into verilog `define |
SIM_TYPE=RTL |
88,6 → 88,7
# Testbench paths |
BENCH_DIR=$(PROJECT_ROOT)/bench |
BENCH_VERILOG_DIR=$(BENCH_DIR)/verilog |
BENCH_VERILOG_INCLUDE_DIR=$(BENCH_VERILOG_DIR)/include |
#BENCH_VHDL_DIR=$(BENCH_DIR)/vhdl |
BENCH_SYSC_DIR=$(BENCH_DIR)/sysc |
BENCH_SYSC_SRC_DIR=$(BENCH_SYSC_DIR)/src |
248,7 → 249,7
$(Q)echo "+incdir+"$(RTL_VERILOG_INCLUDE_DIR) > $@; |
$(Q)echo "+incdir+"$(RTL_SIM_SRC_DIR) >> $@; |
$(Q)echo "+incdir+"$(BOOTROM_SW_DIR) >> $@; |
$(Q)echo "+incdir+"$(BENCH_VERILOG_DIR) >> $@; |
$(Q)echo "+incdir+"$(BENCH_VERILOG_INCLUDE_DIR) >> $@; |
$(Q)echo "+libext+.v" >> $@; |
$(Q)for module in $(RTL_VERILOG_MODULES); do if [ -d $(RTL_VERILOG_DIR)/$$module ]; then echo "-y " $(RTL_VERILOG_DIR)/$$module >> $@; fi; done |
$(Q)echo >> $@ |
347,76 → 348,30
$(Q) echo; echo "\t### Checking simulation results for "$(TEST)" test ###"; echo; |
$(Q)./$@ |
|
# Include the test-defines.v generation rule |
include ../bin/definesgen.inc |
|
# Test defines.v file, called recursively, .PHONY to force its generation |
.PHONY: $(TEST_DEFINES_VLG) |
$(TEST_DEFINES_VLG): |
$(Q)echo "\`define "$(SIM_TYPE)"_SIM" > $@ |
$(Q)echo "\`define SIMULATOR_"`echo $(SIMULATOR) | tr "[:lower:]" "[:upper:]"` > $@ |
$(Q)echo "\`define TEST_NAME_STRING \""$(TEST)"\"" >> $@ |
$(Q)if [ ! -z $$VCD ]; \ |
then echo "\`define VCD" >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DELAY ]; \ |
then echo "\`define VCD_DELAY "$$VCD_DELAY >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DEPTH ]; \ |
then echo "\`define VCD_DEPTH "$$VCD_DEPTH >> $@; \ |
fi |
$(Q)if [ ! -z $$VCD_DELAY_INSNS ]; \ |
then echo "\`define VCD_DELAY_INSNS "$$VCD_DELAY_INSNS >> $@; \ |
fi |
$(Q)if [ ! -z $$END_TIME ]; \ |
then echo "\`define END_TIME "$$END_TIME >> $@; \ |
fi |
$(Q)if [ ! -z $$END_INSNS ]; \ |
then echo "\`define END_INSNS "$$END_INSNS >> $@; \ |
fi |
$(Q)if [ ! -z $$PRELOAD_RAM ]; \ |
then echo "\`define PRELOAD_RAM "$$END_TIME >> $@; \ |
fi |
$(Q)if [ -z $$DISABLE_PROCESSOR_LOGS ]; \ |
then echo "\`define PROCESSOR_MONITOR_ENABLE_LOGS" >> $@; \ |
fi |
$(Q)if [ ! -z $$VPI ]; \ |
then echo "\`define VPI_DEBUG" >> $@; \ |
fi |
$(Q)if [ ! -z $$SIM_QUIET ]; \ |
then echo "\`define SIM_QUIET" >> $@; \ |
fi |
|
|
# $(Q)for module in $(GATELEVEL_MODULES); do echo "\`define "$$module"_IS_GATELEVEL " >> $@; done |
# More possible test defines go here |
|
# |
# Software make rules (called recursively) |
# |
|
# Software make rules (called recursively) |
# Path for the current test |
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim |
|
# Set PRELOAD_RAM=1 to preload the system memory, avoiding lengthy SPI FLASH |
# bootloader process. |
#ifeq ($(PRELOAD_RAM), 1) |
# Name of the image the RAM model will attempt to load via Verilog $readmemh |
# system function. |
SIM_SW_IMAGE ?=sram.vmem |
#else |
#SIM_SW_IMAGE ?=flash.in |
#endif |
|
.PHONY : sw |
sw: $(SIM_SW_IMAGE) |
|
flash.in: $(TEST_SW_DIR)/$(TEST).flashin |
$(Q)if [ -L $@ ]; then unlink $@; fi |
$(Q)ln -s $< $@ |
|
sram.vmem: $(TEST_SW_DIR)/$(TEST).vmem |
$(Q)if [ -L $@ ]; then unlink $@; fi |
$(Q)ln -s $< $@ |
|
.PHONY: $(TEST_SW_DIR)/$(TEST).flashin |
$(TEST_SW_DIR)/$(TEST).flashin: |
$(Q) echo; echo "\t### Compiling software ###"; echo; |
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).flashin |
|
.PHONY: $(TEST_SW_DIR)/$(TEST).vmem |
$(TEST_SW_DIR)/$(TEST).vmem: |
$(Q) echo; echo "\t### Compiling software ###"; echo; |
/orpsocv2/sw/bootrom/bootrom.S
39,7 → 39,7
|
#include "board.h" |
|
#ifdef BOOTLOADER_SPI_FLASH |
#ifdef BOOTROM_SPI_FLASH |
|
/* Assembly program to go into the boot ROM */ |
/* Currently just loads a program from SPI flash into RAM */ |
117,7 → 117,7
|
#endif |
|
#ifdef BOOTLOADER_GOTO_RESET |
#ifdef BOOTROM_GOTO_RESET |
/* Jump to reset vector in the SDRAM */ |
l.movhi r0, 0 |
l.movhi r4, SDRAM_BASE |
127,7 → 127,7
|
#endif |
|
#ifdef BOOTLOADER_LOOP_AT_ZERO |
#ifdef BOOTROM_LOOP_AT_ZERO |
|
/* Don't load app via SPI, instead just put an infinite loop into bottom |
of memory and jump there. |
147,7 → 147,7
|
#endif |
|
#ifdef BOOTLOADER_LOOP_IN_ROM |
#ifdef BOOTROM_LOOP_IN_ROM |
|
/* Don't load app via SPI, instead just put an infinite loop into bottom |
of memory and jump there. |
/orpsocv2/sw/tests/eth/sim/Makefile
1,5 → 1,7
include ../Makefile.inc |
SW_ROOT=../../.. |
|
include $(SW_ROOT)/Makefile.inc |
|
%.dis: %.elf |
$(Q)$(OR32_OBJDUMP) -d $< > $@ |
|
8,3 → 10,4
|
clean: |
$(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis |
|
/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
0,0 → 1,283
/* |
OR1200 Find First/Last '1' Test |
|
Checks l.ff1 and l.fl1 outputs for every bit position |
|
Julius Baxter, julius.baxter@orsoc.se |
|
*/ |
////////////////////////////////////////////////////////////////////// |
//// //// |
//// Copyright (C) 2010 Authors and OPENCORES.ORG //// |
//// //// |
//// This source file may be used and distributed without //// |
//// restriction provided that this copyright statement is not //// |
//// removed from the file and that any derivative work contains //// |
//// the original copyright notice and the associated disclaimer. //// |
//// //// |
//// This source file is free software; you can redistribute it //// |
//// and/or modify it under the terms of the GNU Lesser General //// |
//// Public License as published by the Free Software Foundation; //// |
//// either version 2.1 of the License, or (at your option) any //// |
//// later version. //// |
//// //// |
//// This source is distributed in the hope that it will be //// |
//// useful, but WITHOUT ANY WARRANTY; without even the implied //// |
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// |
//// PURPOSE. See the GNU Lesser General Public License for more //// |
//// details. //// |
//// //// |
//// You should have received a copy of the GNU Lesser General //// |
//// Public License along with this source; if not, download it //// |
//// from http://www.opencores.org/lgpl.shtml //// |
//// //// |
////////////////////////////////////////////////////////////////////// |
|
|
#include "spr-defs.h" |
#include "board.h" |
#include "or1200-defines.h" |
|
// Check MAC unit is enabled before trying to run this test |
#ifndef OR1200_IMPL_ALU_FFL1 |
# error |
# error Find First/Last '1' isntructions not enabled. |
# error |
#endif |
|
|
/* =================================================== [ exceptions ] === */ |
.section .vectors, "ax" |
|
|
/* ---[ 0x100: RESET exception ]----------------------------------------- */ |
.org 0x100 |
l.movhi r0, 0 |
/* Clear status register */ |
l.ori r1, r0, SPR_SR_SM |
l.mtspr r0, r1, SPR_SR |
/* Clear timer */ |
l.mtspr r0, r0, SPR_TTMR |
|
/* Jump to program initialisation code */ |
.global _start |
l.movhi r4, hi(_start) |
l.ori r4, r4, lo(_start) |
l.jr r4 |
l.nop |
|
|
/* =================================================== [ text ] === */ |
.section .text |
|
/* =================================================== [ start ] === */ |
|
.global _start |
_start: |
|
/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_ICP |
l.sfeq r26,r0 |
l.bf .L8 |
l.nop |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_ICCFGR |
l.andi r26,r24,SPR_ICCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
|
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_ICCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
|
.L7: |
l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
.L8: |
/* Data cache enable */ |
/* Check if DC present and skip enabling otherwise */ |
l.mfspr r24,r0,SPR_UPR |
l.andi r26,r24,SPR_UPR_DCP |
l.sfeq r26,r0 |
l.bf .L10 |
l.nop |
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r24,r0,SPR_DCCFGR |
l.andi r26,r24,SPR_DCCFGR_CBS |
l.srli r28,r26,7 |
l.ori r30,r0,16 |
l.sll r14,r30,r28 |
/* Establish number of cache sets |
r16 contains number of cache sets |
r28 contains log(# of cache sets) |
*/ |
l.andi r26,r24,SPR_DCCFGR_NCS |
l.srli r28,r26,3 |
l.ori r30,r0,1 |
l.sll r16,r30,r28 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r28 |
.L9: |
l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
.L10: |
// Kick off test |
l.jal _main |
l.nop |
|
|
|
/* =================================================== [ main ] === */ |
|
.global _main |
_main: |
l.movhi r3, 0 |
l.movhi r4, 0 // Bit we're checking works |
l.movhi r5, 0 |
l.ori r6, r0, 32 |
l.movhi r7, 0 // Register we'll put a value in to check with l.ff1 |
|
#define REPORT(reg) l.or r3, reg, r0 ; \ |
l.nop 0x2 |
|
|
ff1_loop: |
// Set a loop going, creating a register with a '1' in a known position |
// and checking the output of the l.ff1 |
l.ori r7, r0, 1 // Put 1 in bit 0 |
l.sll r7, r7, r4 // Shift '1' by r4 |
REPORT(r7) // Report value |
l.ff1 r5, r7 // Do Find First '1' op |
l.fl1 r8, r7 // Do Find Last '1' op |
REPORT(r5) // Report value |
REPORT(r8) // Report value |
l.addi r4, r4, 1 // Increment bit we're checking (will also be |
// result from l.ff1) |
REPORT(r4) // Report value |
l.sfne r5, r4 // r5 should = r4 |
l.bf ff1_error |
l.sfne r8, r4 // r8 should = r4 |
l.bf fl1_error |
l.sfne r6, r4 // Check if loop is finished |
l.bf ff1_loop // Keep checking |
l.nop |
l.j ffl1_test2 // All OK, next test |
l.nop |
|
ffl1_test2: |
// Try 3 values - all '0', all '1' and a block of values in between |
l.movhi r4, 0 |
l.movhi r5, 0xffff |
l.ori r5, r5, 0xffff |
l.movhi r6, 0x00ff |
l.ori r6, r6, 0xff00 |
// Test '0' |
REPORT(r4) |
l.ff1 r7, r4 |
l.fl1 r8, r4 |
REPORT(r7) |
REPORT(r8) |
l.sfnei r7, 0 |
l.bf ff1_error |
l.sfnei r8, 0 |
l.bf fl1_error |
|
// Test '0xffffffff' |
REPORT(r5) |
l.ff1 r7, r5 |
l.fl1 r8, r5 |
REPORT(r7) |
REPORT(r8) |
l.sfnei r7, 1 |
l.bf ff1_error |
l.sfnei r8, 32 |
l.bf fl1_error |
|
// Test '0x00ffff00' |
REPORT(r6) |
l.ff1 r7, r6 |
l.fl1 r8, r6 |
REPORT(r7) |
REPORT(r8) |
l.sfnei r7, 9 |
l.bf ff1_error |
l.sfnei r8, 24 |
l.bf fl1_error |
l.nop |
l.j ffl1_ok // Tests OK |
|
ff1_error: |
l.movhi r3, hi(0xbaaadff1) |
l.ori r3, r3, lo(0xbaaadff1) |
l.nop 0x1 |
|
|
fl1_error: |
l.movhi r3, hi(0xbaaadf11) |
l.ori r3, r3, lo(0xbaaadf11) |
l.nop 0x1 |
|
|
ffl1_ok: |
|
l.movhi r3, hi(0x8000000d) |
l.ori r3, r3, lo(0x8000000d) |
l.nop 0x1 |
|
/orpsocv2/sw/tests/sdram/sim/sdram-rows.c
5,7 → 5,7
* |
*/ |
|
#include "or32-utils.h" |
#include "cpu-utils.h" |
#include "board.h" |
#include "sdram.h" |
|
/orpsocv2/sw/tests/spi/sim/spi-simple.c
6,15 → 6,15
|
Nothing much actually gets tested here. |
|
Ensure the slave selects for the spi are enabled in design-defines.v |
Ensure the slave selects for the spi are enabled in orpsoc-defines.v |
|
*/ |
|
|
#include "or32-utils.h" |
#include "cpu-utils.h" |
#include "simple-spi.h" |
|
#include "design-defines.h" |
#include "orpsoc-defines.h" |
|
// Detect which of the SPI cores are enabled, tailor the test for that |
#ifndef SPI1 |
/orpsocv2/sw/tests/spi/sim/spi-interrupt.c
1,6 → 1,6
#include "board.h" |
#include "spr-defs.h" |
#include "or32-utils.h" |
#include "cpu-utils.h" |
#include "simple-spi.h" |
#include "int.h" |
|
7,7 → 7,7
#include "simple-spi.h" |
|
|
#include "design-defines.h" |
#include "orpsoc-defines.h" |
|
// Detect which of the SPI cores are enabled, tailor the test for that |
#ifndef SPI1 |
/orpsocv2/sw/tests/spi/sim/Makefile
1,5 → 1,7
include ../Makefile.inc |
SW_ROOT=../../.. |
|
include $(SW_ROOT)/Makefile.inc |
|
%.dis: %.elf |
$(Q)$(OR32_OBJDUMP) -d $< > $@ |
|
/orpsocv2/sw/Makefile.inc
46,29 → 46,47
# Special case for CPU drivers |
CPU_DRIVER ?=$(SW_ROOT)/drivers/or1200 |
|
# Rest of drivers, check if we have any that we should use board-specific |
# versions of. |
# Expecting BOARD_SPECIFIC_DRIVERS and BOARD_PATH to be set |
# If BOARD_PATH is set, we'll first scan that path for which drivers they have |
# and will override any locally named driver directories here. |
ifdef BOARD_PATH |
#$(info BOARD_PATH is being used: $(BOARD_PATH)) |
BOARD_SPECIFIC_DRIVERS=$(shell if [ -e $(BOARD_PATH)/sw/drivers ]; then ls $(BOARD_PATH)/sw/drivers; fi) |
endif |
|
COMMON_SW_DRIVERS=$(shell ls $(SW_ROOT)/drivers ) |
COMMON_SW_DRIVERS_EXCLUDE_BOARD_DRIVERS_CMD=$(shell for driver in $(BOARD_SPECIFIC_DRIVERS); do echo -n "grep -v $$driver"; done) |
COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS=$(shell echo $(COMMON_SW_DRIVERS) $(COMMON_SW_DRIVERS_EXCLUDE_BOARD_DRIVERS_CMD)) |
COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS=$(filter-out $(BOARD_SPECIFIC_DRIVERS),$(COMMON_SW_DRIVERS)) |
|
# Add paths to the common drivers |
SW_DRIVER_PATHS=$(shell for driver in $(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS); do echo $(SW_ROOT)/drivers/$$driver; done) |
# If anything in BOARD_SPECIFIC_DRIVERS, add it to SW_DRIVER_PATHS |
# It's expected BOARD_PATH points to the board's path and the heirarchy of |
# sw/drivers exists |
SW_DRIVER_PATHS += $(shell for driver in $(BOARD_SPECIFIC_DRIVERS); do echo $(BOARD_PATH)/sw/drivers/$$driver; done) |
# |
# Create paths pointing to each driver directory |
# |
SW_DRIVER_PATHS=$(addprefix $(SW_ROOT)/drivers/,$(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS)) |
# If any board paths add them here |
SW_DRIVER_PATHS += $(addprefix $(BOARD_PATH)/sw/drivers/,$(BOARD_SPECIFIC_DRIVERS)) |
|
# Now assemble all of the include paths for the drivers, prefix with -I for GCC |
DRIVER_INCLUDE_PATHS=$(shell for driverpath in $(SW_DRIVER_PATHS); do echo "-I$$driverpath/include"; done) |
|
# Add /include to each path - the expected include directories |
SW_DRIVER_INCLUDE_PATHS=$(addsuffix /include,$(SW_DRIVER_PATHS)) |
# Now add the -I to the front of each so we can pass this to GCC |
INCLUDE_FLAGS=$(addprefix -I,$(SW_DRIVER_INCLUDE_PATHS)) |
|
|
print-driver-paths: |
$(Q)echo "\tDrivers in use from common sw path"; echo; |
@echo $(COMMON_SW_DRIVERS); echo; echo |
$(Q)echo "\tDrivers in use from board sw path"; echo; |
@echo $(BOARD_SPECIFIC_DRIVERS); echo; echo; |
$(Q)echo "\tCommon sw drivers without board drivers"; echo; |
@echo $(COMMON_SW_DRIVERS_WITHOUT_BOARD_DRIVERS); echo; echo; |
$(Q)echo "\tAll drivers and their paths"; echo; |
@echo $(SW_DRIVER_PATHS); echo; echo |
|
|
# If BOARD_PATH isn't set, then we're not compiling for a board, so use the |
# generic board.h include path, otherwise, use that board's |
ifeq ($(BOARD_PATH),) |
DRIVER_INCLUDE_PATHS +=-I$(SW_ROOT)/board/include |
ifdef BOARD_PATH |
INCLUDE_FLAGS +=-I$(BOARD_PATH)/sw/board/include |
else |
DRIVER_INCLUDE_PATHS +=-I$(BOARD_PATH)/sw/board/include |
INCLUDE_FLAGS +=-I$(SW_ROOT)/board/include |
endif |
|
# For now, only apps path is in root sw directory |
93,7 → 111,7
MARCH_FLAGS ?=-mhard-mul -mhard-div -msoft-float |
|
OR32_CFLAGS ?=-g -nostdlib -O2 $(MARCH_FLAGS) \ |
$(DRIVER_INCLUDE_PATHS) \ |
$(INCLUDE_FLAGS) \ |
-I$(SW_ROOT)/lib/include |
|
OR32_LDFLAGS ?=-lgcc -T$(CPU_DRIVER)/link.ld -e 256 |
187,17 → 205,25
$(VECTORS_OBJ): |
$(Q)$(MAKE) -C $(CPU_DRIVER) crt0.o |
|
# This relies on the local clean rule of each makefile |
clean-all: distclean |
|
clean-support: |
$(Q)$(MAKE) -C ../support clean |
# Get a list of the tests |
SW_TESTS=$(shell ls $(SW_ROOT)/tests) |
# A list of the directories in each test directory (not always the same) and |
# get a list of what's in them. |
SW_TESTS_SUBDIRS=$(shell for test in $(SW_TESTS); do ls -d $(SW_ROOT)/tests/$$test/*; done) |
|
# List of software directories, exclude include/ |
SWDIRS=$(shell ls ../ | grep -v include) |
print-sw-tests: |
$(Q)echo; echo "\tSoftware tests"; echo; |
$(Q)echo $(SW_TESTS); echo |
|
distclean: |
$(Q)for dir in $(SWDIRS); do if [ -d ../$$dir ]; then $(MAKE) -C ../$$dir clean; fi; done |
print-sw-tests-subdirs: |
$(Q)echo; echo "\tSoftware tests subdirs"; echo; |
$(Q)echo $(SW_TESTS_SUBDIRS); echo |
|
# This relies on the local clean rule of each makefile |
clean-all: clean |
$(Q)for testssubdir in $(SW_TESTS_SUBDIRS); do $(MAKE) -C $$testssubdir clean; done |
$(Q)for dir in $(SW_DRIVER_PATHS); do $(MAKE) -C $$dir clean; done |
$(Q)for dir in `ls $(SW_APPS_PATH)`; do $(MAKE) -C $(SW_ROOT)/apps/$$dir clean; done |
$(Q)for dir in `ls $(SW_APPS_PATH)`; do $(MAKE) -C $(SW_ROOT)/apps/$$dir clean; done |
$(Q)rm -f $(PROCESSED_DEFINES) |
/orpsocv2/sw/board/include/board.h
3,6 → 3,7
|
#define IN_CLK 50000000 // Hz |
|
|
// |
// Defines for each core (memory map base, OR1200 interrupt line number, etc.) |
// |
/orpsocv2/sw/drivers/i2c_host_slave/Makefile
File deleted
/orpsocv2/sw/drivers/i2c_master_slave/i2c_master_slave.c
0,0 → 1,256
/************************************************************* |
* I2C functions for the Herveille i2c controller * |
* * |
* Provides functions to read from and write to the I2C bus. * |
* Master and slave mode are both supported * |
* * |
* Julius Baxter, julius@opencores.org * |
* * |
************************************************************/ |
|
#include "board.h" |
#include "cpu-utils.h" |
#include "i2c_master_slave.h" |
|
inline unsigned char i2c_master_slave_read_reg(int core, unsigned char addr) |
{ |
return REG8((i2c_base_adr[core] + addr)); |
} |
|
inline void i2c_master_slave_write_reg(int core, unsigned char addr, |
unsigned char data) |
{ |
REG8((i2c_base_adr[core] + addr)) = data; |
} |
|
int i2c_master_slave_wait_for_busy(int core) |
{ |
while (1) { |
// Check for busy flag in i2c status reg |
if (! |
(i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR) & |
I2C_MASTER_SLAVE_SR_BUSY)) |
return 0; |
} |
} |
|
int i2c_master_slave_wait_for_transfer(int core) |
{ |
volatile unsigned char status; |
// Wait for ongoing transmission to finish |
while (1) { |
status = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_SR); |
// If arbitration lost |
if ((status & I2C_MASTER_SLAVE_SR_ARB_LOST) == |
I2C_MASTER_SLAVE_SR_ARB_LOST) |
return 2; |
// If TIP bit = o , stop waiting |
else if (!(status & I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG)) |
return 0; |
} |
} |
|
/*********************************************************** |
* i2c_master_slave_init_core * |
* * |
* Setup i2c core: * |
* Write prescaler register with parmeter passed, enable * |
* core in control register, optionally enable interrupts * |
************************************************************/ |
int i2c_master_slave_init_core(int core, unsigned short prescaler, |
int interrupt_enable) |
{ |
|
// Setup I2C prescaler, |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERlo, |
prescaler & 0xff); |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_PRERhi, |
(prescaler >> 8) & 0xff); |
|
// Enable I2C controller and optionally interrupts |
if (interrupt_enable) |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR, |
I2C_MASTER_SLAVE_CTR_CORE_ENABLE | |
I2C_MASTER_SLAVE_CTR_INTR_ENABLE); |
else |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR, |
I2C_MASTER_SLAVE_CTR_CORE_ENABLE); |
|
return 0; |
|
} |
|
/*********************************************************** |
* i2c_master_slave_deact_core * |
* * |
* Deactivate i2c core: * |
* Clear core enable and interrupt enable bits * |
************************************************************/ |
int i2c_master_slave_deact_core(int core) |
{ |
|
|
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR, |
i2c_master_slave_read_reg(core, |
I2C_MASTER_SLAVE_CTR) & |
~(I2C_MASTER_SLAVE_CTR_CORE_ENABLE | |
I2C_MASTER_SLAVE_CTR_INTR_ENABLE)); |
|
|
return 0; |
|
} |
|
/*********************************************************** |
* i2c_master_slave_init_as_slave * |
* * |
* Setup i2c core to service slave accesses * |
* OR in slave enable bit to control register * |
* Set slave address * |
************************************************************/ |
int i2c_master_slave_init_as_slave(int core, char addr) |
{ |
|
// Set slave enable bit |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR, |
i2c_master_slave_read_reg(core, |
I2C_MASTER_SLAVE_CTR) |
| I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE); |
// Set slave address |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_SLADR, addr); |
|
return 0; |
|
} |
|
/*********************************************************** |
* i2c_master_slave_deact_as_slave * |
* * |
* Disable slave mode for this I2C core * |
* Deassert slave eanble bit in control register * |
************************************************************/ |
int i2c_master_slave_deact_as_slave(int core) |
{ |
// Clear slave enable bit |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CTR, |
i2c_master_slave_read_reg(core, |
I2C_MASTER_SLAVE_CTR) |
& ~I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE); |
|
return 0; |
} |
|
/*********************************************************** |
* i2c_master_slave_master_start * |
* * |
* Get the i2c bus. * |
************************************************************/ |
int i2c_master_slave_master_start(int core, unsigned char addr, int read) |
{ |
|
i2c_master_slave_wait_for_busy(core); |
|
// Set address in transfer register |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, |
(addr << 1) | read); |
|
// Start and write the address |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_START | |
I2C_MASTER_SLAVE_CR_WRITE); |
|
i2c_master_slave_wait_for_transfer(core); |
|
return 0; |
} |
|
/*********************************************************** |
* i2c_master_slave_master_write * |
* * |
* Send 1 byte of data * |
************************************************************/ |
int i2c_master_slave_master_write(int core, unsigned char data, |
int check_prev_ack, int stop) |
{ |
if (i2c_master_slave_wait_for_transfer(core)) |
return 1; |
|
// present data |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_TXR, data); |
|
if (!stop) |
// set command (write) |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_WRITE); |
else |
// set command (write) and stop |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_WRITE | |
I2C_MASTER_SLAVE_CR_STOP); |
|
return 0; |
} |
|
/*********************************************************** |
* i2c_master_slave_master_stop * |
* * |
* Send stop condition * |
************************************************************/ |
int i2c_master_slave_master_stop(int core) |
{ |
unsigned char status; |
unsigned char ready = 0; |
|
// Make I2C controller wait at end of finished byte |
if (i2c_master_slave_wait_for_transfer(core)) |
return 1; |
|
// Send stop condition |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_STOP); |
|
return 0; |
} |
|
/*********************************************************** |
* i2c_master_slave_master_read * |
* * |
* Read 1 byte of data * |
************************************************************/ |
int i2c_master_slave_master_read(int core, int check_prev_ack, |
int stop, char *data) |
{ |
|
// Make I2C controller wait at end of finished byte |
if (i2c_master_slave_wait_for_transfer(core)) |
return 1; |
|
if (stop) |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_READ | |
I2C_MASTER_SLAVE_CR_STOP); |
else |
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_READ); |
|
if (i2c_master_slave_wait_for_transfer(core)) |
return 1; |
|
*data = i2c_master_slave_read_reg(core, I2C_MASTER_SLAVE_RXR); |
|
return 0; |
} |
|
/*********************************************************** |
* i2c_master_slave_ack_interrupt * |
* * |
* Acknowledge interrupt has been serviced * |
************************************************************/ |
int i2c_master_slave_ack_interrupt(int core) |
{ |
|
i2c_master_slave_write_reg(core, I2C_MASTER_SLAVE_CR, |
I2C_MASTER_SLAVE_CR_IACK); |
|
return 0; |
} |
/orpsocv2/sw/drivers/i2c_master_slave/include/i2c_master_slave.h
0,0 → 1,58
/************************************************************* |
* I2C functions for Herveille i2c master_slave core * |
* * |
* Provides functions to read from and write to the I2C bus. * |
* Master and slave mode are both supported * |
* * |
* * |
************************************************************/ |
|
#ifndef _I2C_MASTER_SLAVE_H_ |
#define _I2C_MASTER_SLAVE_H_ |
|
extern const int i2c_base_adr[4]; |
//Memory mapping adresses |
|
#define I2C_MASTER_SLAVE_PRERlo 0x0 // Clock prescaler register |
#define I2C_MASTER_SLAVE_PRERhi 0x1 // Clock prescaler register |
#define I2C_MASTER_SLAVE_CTR 0x2 // Control register |
#define I2C_MASTER_SLAVE_TXR 0x3 // Transmit register |
#define I2C_MASTER_SLAVE_RXR 0x3 // Recive register |
#define I2C_MASTER_SLAVE_CR 0x4 // Control register |
#define I2C_MASTER_SLAVE_SR 0x4 // Status register |
#define I2C_MASTER_SLAVE_SLADR 0x7 // Slave address register |
|
#define I2C_MASTER_SLAVE_CTR_CORE_ENABLE 0x80 |
#define I2C_MASTER_SLAVE_CTR_INTR_ENABLE 0x40 |
#define I2C_MASTER_SLAVE_CTR_SLAVE_ENABLE 0x20 |
|
#define I2C_MASTER_SLAVE_CR_START 0x80 |
#define I2C_MASTER_SLAVE_CR_STOP 0x40 |
#define I2C_MASTER_SLAVE_CR_READ 0x20 |
#define I2C_MASTER_SLAVE_CR_WRITE 0x10 |
#define I2C_MASTER_SLAVE_CR_ACK 0x08 |
#define I2C_MASTER_SLAVE_CR_SL_CONT 0x02 |
#define I2C_MASTER_SLAVE_CR_IACK 0x01 |
|
#define I2C_MASTER_SLAVE_SR_RXACK 0x80 |
#define I2C_MASTER_SLAVE_SR_BUSY 0x40 |
#define I2C_MASTER_SLAVE_SR_ARB_LOST 0x20 |
#define I2C_MASTER_SLAVE_SR_SLAVE_MODE 0x10 |
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_AVAIL 0x08 |
#define I2C_MASTER_SLAVE_SR_SLAVE_DATA_REQ 0x04 |
#define I2C_MASTER_SLAVE_SR_TRANSFER_IN_PRG 0x02 |
#define I2C_MASTER_SLAVE_SR_IRQ_FLAG 0x01 |
|
int i2c_master_slave_init_core(int core, unsigned short prescaler, |
int interrupt_enable); |
int i2c_master_slave_deact_core(int core); |
int i2c_master_slave_init_as_slave(int core, char addr); |
int i2c_master_slave_deact_as_slave(int core); |
int i2c_master_slave_master_start(int core, unsigned char addr, int read); |
int i2c_master_slave_master_write(int core, unsigned char data, |
int check_prev_ack, int stop); |
int i2c_master_slave_master_stop(int core); |
int i2c_master_slave_master_read(int core, int check_prev_ack, int stop, |
char *data); |
int i2c_master_slave_ack_interrupt(int core); |
#endif |
/orpsocv2/sw/drivers/i2c_master_slave/Makefile
0,0 → 1,8
SW_ROOT=../.. |
|
COMPILE_SRCS=i2c_master_slave.c |
|
include $(SW_ROOT)/Makefile.inc |
|
clean: |
$(Q)rm -f *.a *.o |