URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 475 to Rev 476
- ↔ Reverse comparison
Rev 475 → Rev 476
/orpsocv2/rtl/verilog/include/or1200_defines.v
162,9 → 162,11
// |
//`define OR1200_IC_1W_512B |
//`define OR1200_IC_1W_4KB |
`define OR1200_IC_1W_8KB |
//`define OR1200_IC_1W_8KB |
`define OR1200_IC_1W_16KB |
//`define OR1200_DC_1W_4KB |
`define OR1200_DC_1W_8KB |
//`define OR1200_DC_1W_8KB |
`define OR1200_DC_1W_16KB |
|
`endif |
|
1249,6 → 1251,14
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 9 |
`define OR1200_ICTAG_W 20 |
`endif |
`ifdef OR1200_IC_1W_16KB |
`define OR1200_ICSIZE 14 // 16384 |
`define OR1200_ICINDX `OR1200_ICSIZE-2 // 12 |
`define OR1200_ICINDXH `OR1200_ICSIZE-1 // 13 |
`define OR1200_ICTAGL `OR1200_ICINDXH+1 // 14 |
`define OR1200_ICTAG `OR1200_ICSIZE-`OR1200_ICLS // 10 |
`define OR1200_ICTAG_W 19 |
`endif |
|
|
///////////////////////////////////////////////// |
1297,6 → 1307,14
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 9 |
`define OR1200_DCTAG_W 20 |
`endif |
`ifdef OR1200_DC_1W_16KB |
`define OR1200_DCSIZE 14 // 16384 |
`define OR1200_DCINDX `OR1200_DCSIZE-2 // 12 |
`define OR1200_DCINDXH `OR1200_DCSIZE-1 // 13 |
`define OR1200_DCTAGL `OR1200_DCINDXH+1 // 14 |
`define OR1200_DCTAG `OR1200_DCSIZE-`OR1200_DCLS // 10 |
`define OR1200_DCTAG_W 19 |
`endif |
|
|
///////////////////////////////////////////////// |
/orpsocv2/rtl/verilog/or1200/or1200_ic_tag.v
48,43 → 48,6
// Minor update: |
// Coding style changed. |
// |
// Revision 1.7 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.6 2004/04/08 11:00:46 simont |
// Add support for 512B instruction cache. |
// |
// Revision 1.5 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.3.4.1 2003/12/09 11:46:48 simons |
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. |
// |
// Revision 1.3 2002/10/24 22:19:04 mohor |
// Signal scanb_eni renamed to scanb_en |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.8 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.7 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.2 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
153,7 → 116,6
// Instantiation of TAG RAM block |
// |
`ifdef OR1200_IC_1W_512B |
//or1200_spram_32x24 ic_tag0( |
or1200_spram # |
( |
.aw(5), |
161,7 → 123,6
) |
`endif |
`ifdef OR1200_IC_1W_4KB |
//or1200_spram_256x21 ic_tag0( |
or1200_spram # |
( |
.aw(8), |
169,7 → 130,6
) |
`endif |
`ifdef OR1200_IC_1W_8KB |
//or1200_spram_512x20 ic_tag0( |
or1200_spram # |
( |
.aw(9), |
176,6 → 136,13
.dw(20) |
) |
`endif |
`ifdef OR1200_IC_1W_16KB |
or1200_spram # |
( |
.aw(10), |
.dw(19) |
) |
`endif |
ic_tag0 |
( |
`ifdef OR1200_BIST |
/orpsocv2/rtl/verilog/or1200/or1200_ic_ram.v
48,43 → 48,6
// Minor update: |
// Coding style changed. |
// |
// Revision 1.6 2004/06/08 18:17:36 lampret |
// Non-functional changes. Coding style fixes. |
// |
// Revision 1.5 2004/04/08 11:00:46 simont |
// Add support for 512B instruction cache. |
// |
// Revision 1.4 2004/04/05 08:29:57 lampret |
// Merged branch_qmem into main tree. |
// |
// Revision 1.2.4.1 2003/12/09 11:46:48 simons |
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. |
// |
// Revision 1.2 2002/10/17 20:04:40 lampret |
// Added BIST scan. Special VS RAMs need to be used to implement BIST. |
// |
// Revision 1.1 2002/01/03 08:16:15 lampret |
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. |
// |
// Revision 1.9 2001/10/21 17:57:16 lampret |
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF. |
// |
// Revision 1.8 2001/10/14 13:12:09 lampret |
// MP3 version. |
// |
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm |
// no message |
// |
// Revision 1.3 2001/08/09 13:39:33 lampret |
// Major clean-up. |
// |
// Revision 1.2 2001/07/22 03:31:54 lampret |
// Fixed RAM's oen bug. Cache bypass under development. |
// |
// Revision 1.1 2001/07/20 00:46:03 lampret |
// Development version of RTL. Libraries are missing. |
// |
// |
|
// synopsys translate_off |
`include "timescale.v" |
163,6 → 126,13
.dw(32) |
) |
`endif |
`ifdef OR1200_IC_1W_16KB |
or1200_spram # |
( |
.aw(12), |
.dw(32) |
) |
`endif |
ic_ram0 |
( |
`ifdef OR1200_BIST |
/orpsocv2/rtl/verilog/or1200/or1200_dc_tag.v
107,11 → 107,12
// |
// Instantiation of TAG RAM block |
// |
// Data widths are tag width plus one for valid |
`ifdef OR1200_DC_1W_4KB |
or1200_spram # |
( |
.aw(8), |
.dw(21 + 1) |
.dw(`OR1200_DCTAG_W + 1) |
) |
`endif |
`ifdef OR1200_DC_1W_8KB |
118,9 → 119,16
or1200_spram # |
( |
.aw(9), |
.dw(20 + 1) |
.dw(`OR1200_DCTAG_W + 1) |
) |
`endif |
`ifdef OR1200_DC_1W_16KB |
or1200_spram # |
( |
.aw(10), |
.dw(`OR1200_DCTAG_W + 1) |
) |
`endif |
dc_tag0 |
( |
`ifdef OR1200_BIST |
/orpsocv2/rtl/verilog/or1200/or1200_dc_ram.v
118,6 → 118,13
.dw(32) |
) |
`endif |
`ifdef OR1200_DC_1W_16KB |
or1200_spram_32_bw # |
( |
.aw(12), |
.dw(32) |
) |
`endif |
dc_ram |
( |
`ifdef OR1200_BIST |
/orpsocv2/sim/bin/Makefile
746,9 → 746,10
|
$(VLT_MODEL_LINKS): |
# Link all the required system C model files into the verilator work dir |
for SYSCMODEL in $(SYSC_MODELS); do \ |
$(Q)for SYSCMODEL in $(SYSC_MODELS); do \ |
if [ ! -e $(SIM_VLT_DIR)/$$SYSCMODEL.cpp ]; then \ |
echo "\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \ |
echo \ |
"\tLinking SystemC model $$SYSCMODEL Verilator model build path"; \ |
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp \ |
$(SIM_VLT_DIR)/$$SYSCMODEL.cpp; \ |
ln -s $(BENCH_SYSC_INCLUDE_DIR)/$$SYSCMODEL.h \ |
777,8 → 778,7
############################################################################### |
# Verilator profiled model build rules |
############################################################################### |
# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a |
# "make clean" and then a "make prepare-vlt_profiled" |
# To run this, first run a "make prepare-vlt-profiled" |
# This new make target copies athe results of the profiling back to the right |
# paths before we create everything again |
############################################################################### |