URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 491 to Rev 492
- ↔ Reverse comparison
Rev 491 → Rev 492
/orpsocv2/doc/orpsoc.texi
437,6 → 437,10
@item MGC_NO_VOPT |
When using Modelsim (specifying @code{SIMULATOR=modelsim}), if the version does not include the individual @code{vopt} executable, specify @code{MGC_NO_VOPT=1} when compiling. |
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@item VPI |
Pass @code{VPI=1} to have the an external JTAG debug module stall the processor just after bootup, and then provide a GDB stub (interacting with the Verilog sim via the VPI) to allow control of the system in a similar fashtion to that of a physical target controlled over JTAG via a debug proxy application. The port for GDB is hardcoded to 50002. See the code in @code{bench/verilog/vpi/c} for more details. |
If running with Modelsim, ensure the path @code{MGC_PATH} is set and points to a directory containing a path named @code{modeltech}, which should be the Modelsim install. |
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@end table |
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1364,8 → 1368,8
@c Generic Design build chapter |
@c **************************************************************************** |
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@node Generic |
@chapter Generic |
@node Generic Designs |
@chapter Generic Designs |
@cindex Generic design information |
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@menu |
1378,9 → 1382,8
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The paths under @code{boards/generic} contain designs similar to the reference design, in that they are not technology specific, and used for development of certain features of the processor, or peripherals. |
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An example is the fault tolerance testing build, in @code{boards/generic/ft}, which implements some custom modules in the testbench and ORPSoC top level design, and is in general a very minimal system just for testing. |
These builds are a TODO, but should provide technology-independent builds, with any specialist modules required to debug, or assist in development or demonstration of a module. |
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Additional builds, testing certain parts of the technology, can be developed here. |
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@c **************************************************************************** |
@c Software section |
/orpsocv2/boards/actel/ordb1a3pe1500/sim/bin/Makefile
200,6 → 200,16
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do. |
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored |
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit" |
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# VPI debugging interface variables |
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c |
VPI_SRC_VERILOG_DIR=vpi/verilog |
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch]) |
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# Modelsim VPI compile variables |
MODELTECH_VPILIB=msim_jp_vpi.sl |
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# Modelsim VPI settings |
ifeq ($(VPI), 1) |
VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB) |
328,6 → 338,11
# Finally, add include path from local bench path |
BENCH_VERILOG_SUBDIRS += $(BOARD_BENCH_VERILOG_DIR)/include |
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ifeq ($(VPI), 1) |
# Manually add the VPI bench verilog path |
COMMON_BENCH_VERILOG_SUBDIRS += $(VPI_SRC_VERILOG_DIR) |
endif |
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print-board-bench-subdirs: |
$(Q)echo "\tBoard bench subdirectories"; \ |
echo $(BOARD_BENCH_VERILOG_SUBDIRS) |
523,7 → 538,7
clean-sim: |
$(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo; |
$(Q)rm -rf *.* lib_* work transcript check-test-log |
# No VPI support for now. $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi |
$(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi |
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clean-bootrom: |
$(MAKE) -C $(BOOTROM_SW_DIR) clean |
/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
216,6 → 216,16
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do. |
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored |
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit" |
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# VPI debugging interface variables |
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c |
VPI_SRC_VERILOG_DIR=vpi/verilog |
VPI_SRCS=$(shell ls $(VPI_SRC_C_DIR)/*.[ch]) |
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# Modelsim VPI compile variables |
MODELTECH_VPILIB=msim_jp_vpi.sl |
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# Modelsim VPI settings |
ifeq ($(VPI), 1) |
VPI_LIBS=$(VPI_SRC_C_DIR)/$(MODELTECH_VPILIB) |
344,6 → 354,11
# Finally, add include path from local bench path |
BENCH_VERILOG_SUBDIRS += $(BOARD_BENCH_VERILOG_DIR)/include |
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ifeq ($(VPI), 1) |
# Manually add the VPI bench verilog path |
COMMON_BENCH_VERILOG_SUBDIRS += $(VPI_SRC_VERILOG_DIR) |
endif |
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print-board-bench-subdirs: |
$(Q)echo "\tBoard bench subdirectories"; \ |
echo $(BOARD_BENCH_VERILOG_SUBDIRS) |
531,7 → 546,7
clean-sim: |
$(Q) echo; echo "\t### Cleaning simulation run directory ###"; echo; |
$(Q)rm -rf *.* lib_* work transcript check-test-log |
# No VPI support for now. $(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi |
$(Q) if [ -e $(VPI_SRC_C_DIR) ]; then $(MAKE) -C $(VPI_SRC_C_DIR) clean; fi |
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clean-bootrom: |
$(MAKE) -C $(BOARD_BOOTROM_SW_DIR) clean |