URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
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- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 495 to Rev 496
- ↔ Reverse comparison
Rev 495 → Rev 496
/orpsocv2/doc/orpsoc.texi
978,11 → 978,13
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http://www.xilinx.com/products/devkits/HW-V5-ML501-UNI-G.htm |
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The OR1200 core and Wishbone bus is set to run at 66MHz. The OR1200 core, as defined here, is almost fully featured, with every hardware arithmetic option enabled, and the largest possible cache configuration, of 1024 sets with 8 words per line which is 32 kilobytes of cache each for instruction and data buses. |
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Not all peripherals are supported, and adding support for each is a goal. |
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At present the build contains a memory controller for the DDR2 SDRAM (based around a Xilinx MIG derived controller) and SSRAM. None of the other peripherals (VGA/AC97/PS2/USB/LCD) have controllers in the design yet. |
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The OpenCores 10/100 Ethernet MAC can be used for Ethernet, but still has some bugs to do with memory access, although it appears to be using the RGMII interface to the 10/10/1000 PHY on the ML501 OK. |
The OpenCores 10/100 Ethernet MAC can be used for Ethernet, but only with the PHY in 10/100 mode using the MII interface to the Marvel Alaska Ethernet PHY IC. There still may be bugs in the FIFO buffer configuration in the ethmac module when the Xilinx FIFO option is enabled via the ethmac_defines.v file. Adding GMII support to the MAC, is a TODO task. |
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The project is configured to generate either a @code{.bit} file for direct programming via JTAG, or a @code{.mcs} file with inbuilt bootloader software for the processor, meaning the board can be powered up and an application like ORPmon loaded without having to reprogram it from iMPACT between power cycles. |
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/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
48,13 → 48,12
volatile unsigned tx_done; |
static int next_tx_buf_num; |
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//#define OUR_IP_BYTES 0xc0,0xa8,0x64,0x9b // 192.168.100.155 |
//#define OUR_IP_LONG 0xc0a8649b |
#define OUR_IP_BYTES 0xc0,0xa8,0x64,0x9b // 192.168.100.155 |
#define OUR_IP_LONG 0xc0a8649b |
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#define OUR_IP_BYTES 0xc0,0xa8,0x0,0x5a // 192.168.0.90 |
#define OUR_IP_LONG 0xc0a8005a |
//#define OUR_IP_BYTES 0xc0,0xa8,0x0,0x5a // 192.168.0.90 |
//#define OUR_IP_LONG 0xc0a8005a |
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//#define OUR_IP_BYTES 0xc0,0xa8,0x1,0x22 // 192.168.1.34 |
//#define OUR_IP_LONG 0xc0a80122 |
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66,13 → 65,14
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static char our_ip[4] = {OUR_IP_BYTES}; |
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//#define DEST_IP_BYTES 0xc0,0xa8,0x64,0x69 // 192 .168.100.105 |
#define DEST_IP_BYTES 0xc0,0xa8,0x64,0x69 // 192 .168.100.105 |
//#define DEST_IP_BYTES 0xc0,0xa8,0x01,0x08 // 192 .168.1.8 |
#define DEST_IP_BYTES 0xc0,0xa8,0x00,0x0f // 192 .168.0.15 |
//#define DEST_IP_BYTES 0xc0,0xa8,0x00,0x0f // 192 .168.0.15 |
//#define DEST_IP_BYTES 0xac,0x1e,0x0,0x01 // 172.30.0.1 |
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//#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x01,0xff // 192 .168.1.255 |
#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x00,0xff // 192 .168.0.255 |
#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x64,0xff // 192.168.100.255 |
//#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x01,0xff // 192.168.1.255 |
//#define BCAST_DEST_IP_BYTES 0xc0,0xa8,0x00,0xff // 192.168.0.255 |
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/* Functions in this file */ |
void ethmac_setup(void); |
/orpsocv2/boards/xilinx/ml501/rtl/verilog/clkgen/clkgen.v
144,8 → 144,8
defparam dcm0.CLKFX_MULTIPLY = 4; |
defparam dcm0.CLKFX_DIVIDE = 3; |
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// Generate 50 MHz from CLKDV |
defparam dcm0.CLKDV_DIVIDE = 4.0; |
// Generate 66 MHz from CLKDV |
defparam dcm0.CLKDV_DIVIDE = 3.0; |
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BUFG dcm0_clk0_bufg |
(// Outputs |
/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/uart_defines.v
246,5 → 246,9
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd11 |
// 50MHz: prescaler 27.1 |
//`define PRESCALER_HIGH_PRESET 8'd0 |
//`define PRESCALER_LOW_PRESET 8'd27 |
// 66MHz: prescaler 36.1 |
`define PRESCALER_HIGH_PRESET 8'd0 |
`define PRESCALER_LOW_PRESET 8'd27 |
`define PRESCALER_LOW_PRESET 8'd36 |
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/orpsocv2/boards/xilinx/ml501/backend/par/bin/ml501.ucf
941,11 → 941,11
NET "eth0_col" IOBDELAY=NONE; |
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## # Timing ignores (to specify unconstrained paths) |
#FIXME? NET "*clkgen0/wb_clk_o" TNM_NET = "sys_clk"; # Wishbone clock |
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "sys_clk" TIG; |
TIMESPEC "TS_OPB_PHYTX" = FROM "sys_clk" TO "TXCLK_GRP" TIG; |
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "sys_clk" TIG; |
TIMESPEC "TS_OPB_PHYRX" = FROM "sys_clk" TO "RXCLK_GRP" TIG; |
NET "wb_clk" TNM_NET = "wb_clk_grp"; # Wishbone clock |
TIMESPEC "TS_PHYTX_OPB" = FROM "TXCLK_GRP" TO "wb_clk_grp" TIG; |
TIMESPEC "TS_OPB_PHYTX" = FROM "wb_clk_grp" TO "TXCLK_GRP" TIG; |
TIMESPEC "TS_PHYRX_OPB" = FROM "RXCLK_GRP" TO "wb_clk_grp" TIG; |
TIMESPEC "TS_OPB_PHYRX" = FROM "wb_clk_grp" TO "RXCLK_GRP" TIG; |
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## #------------------------------------------------------------------------------ |
## # IO Pad Location Constraints / Properties for AC97 Sound Controller |
/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
1,7 → 1,8
#ifndef _BOARD_H_ |
#define _BOARD_H_ |
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#define IN_CLK 50000000 // Hz |
//#define IN_CLK 50000000 // Hz |
#define IN_CLK 66666667 // Hz |
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// |
// ROM bootloader |