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  • This comparison shows the changes necessary to convert path 
    /openrisc/trunk
    from Rev 504 to Rev 505
    ↔ Reverse comparison
  •

Rev 504 → Rev 505

/orpsocv2/rtl/verilog/or1200/or1200_mult_mac.v
250,12 → 250,16
`OR1200_ALUOP_MUL: begin
// Actually doing unsigned multiply internally, and then negate on
// output as appropriate, so if sign bit is set, then is overflow
ovforw = mul_prod_r[31];
// unless incoming signs differ and result is 2^(width-1)
ovforw = (mul_prod_r[width-1] &&
!((a[width-1]^b[width-1]) && ~|mul_prod_r[width-2:0])) ||
|mul_prod_r[2*width-1:32];
 
ov_we = 1;
end
`OR1200_ALUOP_MULU : begin
// Overflow on unsigned multiply is simpler.
ovforw = mul_prod_r[32];
ovforw = |mul_prod_r[2*width-1:32];
ov_we = 1;
end
`endif // `ifdef OR1200_MULT_IMPLEMENTED
262,8 → 266,8
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIVU,
`OR1200_ALUOP_DIV: begin
// Overflow on divide by zero
ovforw = div_by_zero;
// Overflow on divide by zero or -2^(width-1)/-1
ovforw = div_by_zero || (a==32'h8000_0000 && b==32'hffff_ffff);
ov_we = 1;
end
`endif
/orpsocv2/sw/apps/spiflash/spiflash-program.ld
80,17 → 80,10
.bss SIZEOF(.data) + ADDR(.data) :
{
sbss = . ;
_sbss = . ;
__bss_start = ALIGN(0x8);
___bss_start = ALIGN(0x8);
_bss_start = ALIGN(0x8);
*(.bss)
*(COMMON)
end = ALIGN(0x8);
_end = ALIGN(0x8);
__end = ALIGN(0x8);
ebss = .;
_ebss = .;
_bss_end = .;
}
.stab 0 (NOLOAD) :
/orpsocv2/sw/apps/spiflash/README
42,7 → 42,7
ensure the BOARD_PATH variable is set correctly, too.
 
make spiflash-program.elf PROGRAMMINGFILE=/path/to/myapp.bin \
BOARD_PATH=`pwd`/../../../boards/actel/ordb1a3pe1500
BOARD=actel/ordb1a3pe1500
 
It's advisable to do a "make distclean" first, to clear out any previously
compiled software for other boards.
/orpsocv2/sw/drivers/simple-spi/simple-spi.c
9,43 → 9,47
#include "simple-spi.h"
#include "cpu-utils.h"
 
 
const int spi_base_adr[1] = {
#ifdef SPI_NUM_CORES
const int SPI_BASE_ADR[SPI_NUM_CORES] = {SPI_BASE_ADDRESSES_CSV};
#else
// For older builds - need to change them all over to newer format
#ifdef SPI0_BASE
SPI0_BASE
const int SPI_BASE_ADR[1] = {SPI0_BASE};
#else
0
// No SPI present
const int SPI_BASE_ADR[1] = {-1};
#endif
};
#endif
 
 
void
spi_core_enable(int core)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPE;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_disable(int core)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPE;
}
 
void
spi_core_interrupt_enable(int core)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPIE;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) |= SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_disable(int core)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) &= ~SIMPLESPI_SPCR_SPIE;
}
 
void
spi_core_interrupt_flag_clear(int core)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPSR)) = SIMPLESPI_SPSR_SPIF;
}
 
void
52,7 → 56,7
spi_core_clock_setup(int core, char polarity, char phase, char rate,
char ext_rate)
{
char spcr = REG8((spi_base_adr[core] + SIMPLESPI_SPCR));
char spcr = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR));
 
if (polarity)
spcr |= SIMPLESPI_SPCR_CPOL;
66,13 → 70,13
 
spcr = (spcr & ~SIMPLESPI_SPCR_SPR) | (rate & SIMPLESPI_SPCR_SPR);
 
REG8((spi_base_adr[core] + SIMPLESPI_SPCR)) = spcr;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPCR)) = spcr;
 
char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
char sper = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER));
sper = (sper & ~SIMPLESPI_SPER_ESPR) | (ext_rate & SIMPLESPI_SPER_ESPR);
 
REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER)) = sper;
 
}
 
79,11 → 83,11
void
spi_core_set_int_count(int core, char cnt)
{
char sper = REG8((spi_base_adr[core] + SIMPLESPI_SPER));
char sper = REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER));
sper = (sper & ~SIMPLESPI_SPER_ICNT) | cnt;
REG8((spi_base_adr[core] + SIMPLESPI_SPER)) = sper;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPER)) = sper;
}
// No decode on slave select lines, so assert correct bit to select slave
90,19 → 94,19
void
spi_core_slave_select(int core, char slave_sel_dec)
{
REG8((spi_base_adr[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SSPU)) = slave_sel_dec;
}
 
int
spi_core_data_avail(int core)
{
return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);
return !!!(REG8((SPI_BASE_ADR[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_RFEMPTY);
}
 
int
spi_core_write_avail(int core)
{
return !!!(REG8((spi_base_adr[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);
return !!!(REG8((SPI_BASE_ADR[core]+SIMPLESPI_SPSR))&SIMPLESPI_SPSR_WFFULL);
}
 
// Should call spi_core_write_avail() before calling this, we don't check
109,11 → 113,11
void
spi_core_write_data(int core, char data)
{
REG8((spi_base_adr[core] + SIMPLESPI_SPDR)) = data;
REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPDR)) = data;
}
 
char
spi_core_read_data(int core)
{
return REG8((spi_base_adr[core] + SIMPLESPI_SPDR));
return REG8((SPI_BASE_ADR[core] + SIMPLESPI_SPDR));
}
/orpsocv2/sw/drivers/or1200/or1200-utils.c
98,11 → 98,17
return timer_ticks;
}
 
/* Wait for 10ms */
/* Wait for 10ms, assumes CLK_HZ is 100, which it usually is.
Will be slightly inaccurate!*/
void
cpu_sleep_10ms(void)
{
unsigned long ttcr = mfspr(SPR_TTCR) & SPR_TTCR_PERIOD;
unsigned long first_time = cpu_get_timer_ticks();
while (first_time == cpu_get_timer_ticks());
while (first_time == cpu_get_timer_ticks()); // Wait for tick to occur
// Now wait until we're past the tick value we read before to know we've
// gone at least enough
while(ttcr > (mfspr(SPR_TTCR) & SPR_TTCR_PERIOD));
 
}

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