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    /openrisc/trunk
    from Rev 505 to Rev 506
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Rev 505 → Rev 506

/orpsocv2/rtl/verilog/include/orpsoc-defines.v
41,6 → 41,7
`define JTAG_DEBUG
`define UART0
`define RAM_WB
`define INTGEN
 
// end of included module defines - keep this comment line here
 
/orpsocv2/rtl/verilog/include/orpsoc-params.v
45,6 → 45,11
parameter uart0_data_width = 8;
parameter uart0_addr_width = 3;
 
// Interrupt generator (intgen) params
parameter intgen_wb_adr = 8'he1;
parameter intgen_data_width = 8;
parameter intgen_addr_width = 1;
 
// ROM
parameter wbs_i_rom0_data_width = 32;
parameter wbs_i_rom0_addr_width = 6;
93,10 → 98,10
// //
///////////////////////////////
parameter bbus_arb_wb_addr_match_width = 8;
parameter bbus_arb_wb_num_slaves = 1; // Update this when changing slaves!
parameter bbus_arb_wb_num_slaves = 2; // Update this when changing slaves!
// Slave addresses
parameter bbus_arb_slave0_adr = uart0_wb_adr;
parameter bbus_arb_slave1_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave1_adr = intgen_wb_adr;
parameter bbus_arb_slave2_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave3_adr = 0 /* UNASSIGNED */;
parameter bbus_arb_slave4_adr = 0 /* UNASSIGNED */;
/orpsocv2/rtl/verilog/intgen/intgen.v
0,0 → 1,70
/*
*
* Interrupt generation module
*
* A counter is loaded with a value over the Wishbone bus interface, which then
* counts down and issues an interrupt when the value is 1
*
*
* Register 0 - write only - counter value
*
* Register 1 - read/write - interrupt status/clear
*
*/
 
module intgen(
clk_i,
rst_i,
wb_adr_i,
wb_cyc_i,
wb_stb_i,
wb_dat_i,
wb_we_i,
wb_ack_o,
wb_dat_o,
 
irq_o
);
 
 
input clk_i;
input rst_i;
input wb_adr_i;
input wb_cyc_i;
input wb_stb_i;
input [7:0] wb_dat_i;
input wb_we_i;
output wb_ack_o;
output [7:0] wb_dat_o;
output reg irq_o;
reg [7:0] counter;
 
always @(posedge clk_i or posedge rst_i)
if (rst_i)
counter <= 0;
else if (wb_stb_i & wb_cyc_i & wb_we_i & !wb_adr_i)
// Write to adress 0 loads counter
counter <= wb_dat_i;
else if (|counter)
counter <= counter - 1;
always @(posedge clk_i or posedge rst_i)
if (rst_i)
irq_o <= 0;
else if (wb_stb_i & wb_cyc_i & wb_we_i & wb_adr_i)
// Clear on write to reg 1
irq_o <= 0;
else if (counter==8'd1)
irq_o <= 1;
 
assign wb_ack_o = wb_stb_i & wb_cyc_i;
assign wb_dat_o = (wb_adr_i) ? {7'd0,irq_o} : counter;
endmodule // intgen
 
 
/orpsocv2/rtl/verilog/orpsoc_top/orpsoc_top.v
231,7 → 231,22
wire wbs_d_uart0_err_o;
wire wbs_d_uart0_rty_o;
 
// intgen wires
wire [31:0] wbs_d_intgen_adr_i;
wire [7:0] wbs_d_intgen_dat_i;
wire [3:0] wbs_d_intgen_sel_i;
wire wbs_d_intgen_we_i;
wire wbs_d_intgen_cyc_i;
wire wbs_d_intgen_stb_i;
wire [2:0] wbs_d_intgen_cti_i;
wire [1:0] wbs_d_intgen_bte_i;
wire [7:0] wbs_d_intgen_dat_o;
wire wbs_d_intgen_ack_o;
wire wbs_d_intgen_err_o;
wire wbs_d_intgen_rty_o;
 
 
//
// Wishbone instruction bus arbiter
//
408,6 → 423,18
.wbs0_err_o (wbs_d_uart0_err_o),
.wbs0_rty_o (wbs_d_uart0_rty_o),
 
.wbs1_adr_i (wbs_d_intgen_adr_i),
.wbs1_dat_i (wbs_d_intgen_dat_i),
.wbs1_we_i (wbs_d_intgen_we_i),
.wbs1_cyc_i (wbs_d_intgen_cyc_i),
.wbs1_stb_i (wbs_d_intgen_stb_i),
.wbs1_cti_i (wbs_d_intgen_cti_i),
.wbs1_bte_i (wbs_d_intgen_bte_i),
.wbs1_dat_o (wbs_d_intgen_dat_o),
.wbs1_ack_o (wbs_d_intgen_ack_o),
.wbs1_err_o (wbs_d_intgen_err_o),
.wbs1_rty_o (wbs_d_intgen_rty_o),
 
// Clock, reset inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst));
811,7 → 838,31
////////////////////////////////////////////////////////////////////////
`endif // !`ifdef UART0
 
`ifdef INTGEN
 
wire intgen_irq;
 
intgen intgen0
(
.clk_i (wb_clk),
.rst_i (wb_rst),
.wb_adr_i (wbs_d_intgen_adr_i[intgen_addr_width-1:0]),
.wb_cyc_i (wbs_d_intgen_cyc_i),
.wb_stb_i (wbs_d_intgen_stb_i),
.wb_dat_i (wbs_d_intgen_dat_i),
.wb_we_i (wbs_d_intgen_we_i),
.wb_ack_o (wbs_d_intgen_ack_o),
.wb_dat_o (wbs_d_intgen_dat_o),
.irq_o (intgen_irq)
);
 
`endif // `ifdef INTGEN
assign wbs_d_intgen_err_o = 0;
assign wbs_d_intgen_rty_o = 0;
////////////////////////////////////////////////////////////////////////
//
// OR1200 Interrupt assignment
845,7 → 896,11
assign or1200_pic_ints[16] = 0;
assign or1200_pic_ints[17] = 0;
assign or1200_pic_ints[18] = 0;
`ifdef INTGEN
assign or1200_pic_ints[19] = intgen_irq;
`else
assign or1200_pic_ints[19] = 0;
`endif
endmodule // top
 
/orpsocv2/rtl/verilog/arbiter/arbiter_bytebus.v
75,7 → 75,7
wbs0_ack_o,
wbs0_err_o,
wbs0_rty_o,
/*
 
// Slave two
// Wishbone Slave interface
wbs1_adr_i,
89,7 → 89,7
wbs1_ack_o,
wbs1_err_o,
wbs1_rty_o,
 
/*
// Slave three
// Wishbone Slave interface
wbs2_adr_i,
420,7 → 420,7
input wbs0_err_o;
input wbs0_rty_o;
/*
 
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs1_adr_i;
output [wbs_dat_width-1:0] wbs1_dat_i;
434,7 → 434,7
input wbs1_err_o;
input wbs1_rty_o;
 
/*
// Wishbone Slave interface
output [wb_adr_width-1:0] wbs2_adr_i;
output [wbs_dat_width-1:0] wbs2_dat_i;
788,8 → 788,8
 
// Slave selects
assign wb_slave_sel[0] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave0_adr;
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
/*
assign wb_slave_sel[1] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave1_adr;
assign wb_slave_sel[2] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave2_adr;
assign wb_slave_sel[3] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave3_adr;
assign wb_slave_sel[4] = wbm_adr_o[`WB_ARB_ADDR_MATCH_SEL] == slave4_adr;
826,7 → 826,7
assign wbs_err_o_mux_i[0] = wbs0_err_o & wb_slave_sel[0];
assign wbs_rty_o_mux_i[0] = wbs0_rty_o & wb_slave_sel[0];
 
/*
 
// Slave 1 inputs
assign wbs1_adr_i = wbm_adr_o;
assign wbs1_dat_i = wbm_dat_o;
840,7 → 840,7
assign wbs_err_o_mux_i[1] = wbs1_err_o & wb_slave_sel[1];
assign wbs_rty_o_mux_i[1] = wbs1_rty_o & wb_slave_sel[1];
 
 
/*
// Slave 2 inputs
assign wbs2_adr_i = wbm_adr_o;
assign wbs2_dat_i = wbm_dat_o;
1095,9 → 1095,8
 
// Master out mux from slave in data
assign wbm_dat_byte_i = wb_slave_sel[0] ? wbs_dat_o_mux_i[0] :
/*
wb_slave_sel[1] ? wbs_dat_o_mux_i[1] :
wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
/* wb_slave_sel[2] ? wbs_dat_o_mux_i[2] :
wb_slave_sel[3] ? wbs_dat_o_mux_i[3] :
wb_slave_sel[4] ? wbs_dat_o_mux_i[4] :
wb_slave_sel[5] ? wbs_dat_o_mux_i[5] :
1118,8 → 1117,8
*/
wbs_dat_o_mux_i[0];
// Master out acks, or together
assign wbm_ack_i = wbs_ack_o_mux_i[0] /* |
wbs_ack_o_mux_i[1] |
assign wbm_ack_i = wbs_ack_o_mux_i[0] |
wbs_ack_o_mux_i[1] /* |
wbs_ack_o_mux_i[2] |
wbs_ack_o_mux_i[3] |
wbs_ack_o_mux_i[4] |
1142,8 → 1141,8
;
 
assign wbm_err_i = wbs_err_o_mux_i[0] |/*
wbs_err_o_mux_i[1] |
assign wbm_err_i = wbs_err_o_mux_i[0] |
wbs_err_o_mux_i[1] |/*
wbs_err_o_mux_i[2] |
wbs_err_o_mux_i[3] |
wbs_err_o_mux_i[4] |
1166,8 → 1165,8
watchdog_err ;
 
assign wbm_rty_i = wbs_rty_o_mux_i[0] /*|
wbs_rty_o_mux_i[1] |
assign wbm_rty_i = wbs_rty_o_mux_i[0] |
wbs_rty_o_mux_i[1] /*|
wbs_rty_o_mux_i[2] |
wbs_rty_o_mux_i[3] |
wbs_rty_o_mux_i[4] |
/orpsocv2/sw/tests/or1200/sim/or1200-intsyscall.S
0,0 → 1,218
#include "spr-defs.h"
#include "board.h"
/*
 
User IRQ and system call simultaneous interrupt test
Within the test we'll use following global variables:
 
r15 syscall interrupt counter
r16 syscall function counter
r17 irq interrupt counter
r18 intgen's base address
 
 
The test does the following:
Uses the intgen module to schedule interrupts to see if they clash
with system calls.
 
Julius Baxter, ORSoC AB, julius.baxter@orsoc.se
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
 
 
/* =================================================== [ exceptions ] === */
.section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
.org 0x100
l.movhi r0, 0
/* Clear status register */
l.ori r1, r0, SPR_SR_SM
l.mtspr r0, r1, SPR_SR
/* Clear timer */
l.mtspr r0, r0, SPR_TTMR
/* Init the stack */
.global _stack
l.movhi r1, hi(_stack)
l.ori r1, r1, lo(_stack)
l.addi r2, r0, -3
l.and r1, r1, r2
/* Jump to program initialisation code */
.global _start
l.movhi r4, hi(_start)
l.ori r4, r4, lo(_start)
l.jr r4
l.nop
 
/* =================================================== [ User interrupt ] === */
.org 0x800
.global _user_irq_handler
_user_irq_handler:
l.addi r17, r17, 1
/* Report values , 0x00000800 == user interrupt report*/
l.ori r3, r0, 0x0800
l.nop 2
l.or r3, r0, r17
l.nop 2
/* TODO - propably confirm it was intgen's IRQ that caused this */
/* Clear interrupt source */
l.ori r7, r18, 0x1 /* intgen IRQ clear address */
l.sb 0(r7), r0 /* Any write clears the bit */
/* Clear OR1200 PICSR */
l.mfspr r7, r0, SPR_PICSR
l.mtspr r0, r7, SPR_PICSR
 
l.rfe
 
/* ========================================================= [ syscall ] === */
.org 0xC00
.extern _syscall_function
.global _syscall_handler
_syscall_handler:
l.addi r15, r15, 1
l.mfspr r7, r0, SPR_ESR_BASE /* Put ESR in r7, set back to ESR later */
l.mfspr r8, r0, SPR_EPCR_BASE/* Put EPCR in r8,set back to EPCR later*/
/* Unset IEE and TEE bits of SR */
l.ori r4, r0, SPR_SR_IEE|SPR_SR_TEE
l.ori r5, r0, 0xffff
l.xor r5, r5, r4
l.and r5, r7, r5 /* New SR without interrupt bits set */
l.mtspr r0, r5, SPR_ESR_BASE /* SR after l.rfe */
/* Report values , 0x00000c00 == tick timer report*/
l.ori r3, r0, 0x0c00
l.nop 2
/* Get syscall number */
l.lwz r3, -4(r8) /* r8 = load(EPCR-4)= PC of l.sys that caused this */
l.andi r3, r3, 0xffff /* get 16-bit immediate syscall number */
l.nop 2
l.movhi r4, hi(_syscall_function)
l.ori r4, r4, lo(_syscall_function)
l.mtspr r0, r4, SPR_EPCR_BASE
l.rfe
 
 
/* =================================================== [ text section ] === */
.section .text
 
/* =================================================== [ start ] === */
 
.global _start
_start:
// Kick off test
l.jal _main
l.nop
 
/* =================================================== [ main ] === */
.global _main
_main:
l.movhi r15, 0
l.movhi r16, 0
l.movhi r17, 0
#
# unmask (enable) all ints
#
l.movhi r5,0xffff
l.ori r5,r5,0xffff
l.mtspr r0,r5,SPR_PICMR # set PICMR
 
/* Enable Interrupts */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_IEE
l.mtspr r0,r6,SPR_SR
 
// Assumes r18 is intgen's base address
l.movhi r18,hi(INTGEN_BASE)
#define INTGEN_LOAD(x) \
l.ori r5,r0,lo(x) ;\
l.sb 0(r18),r5
/* Test begin */
l.nop
INTGEN_LOAD(1)
l.sys 0x1
l.nop
INTGEN_LOAD(1)
l.nop
l.sys 0x2
l.nop
INTGEN_LOAD(2)
l.sys 0x3
l.nop
INTGEN_LOAD(2)
l.nop
l.sys 0x4
l.nop
l.ori r5,r0,1
l.sys 0x5
l.sb 0(r18),r5
l.nop
l.nop
l.nop
l.sfnei r16, 0xf /* Should equal 15, 0xf */
l.bf _fail
l.nop
 
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 2
l.ori r3, r0, 0
l.nop 1
_fail:
l.movhi r3, hi(0xbaaaaaad)
l.ori r3, r3, lo(0xbaaaaaad)
l.nop 1
.global _syscall_function
_syscall_function:
/* r7 and r8 hold actual real ESR and EPCR, respectively */
/* We'll restore them now */
l.mtspr r0, r7, SPR_ESR_BASE /* SR before syscall */
l.mtspr r0, r8, SPR_EPCR_BASE
l.add r16, r16, r3 /* Add syscall number to our counter */
l.movhi r4, hi(0x00400000) /* 4MB mark of memory */
/* Ensure memory access OK */
l.slli r3, r3, 2 /* Turn syscall number into a word address (<< 2) */
l.add r4, r4, r3 /* Access this offset from 4MB mark */
l.sw 0(r4), r16 /* Do a write to memory */
l.lwz r16, 0(r4) /* Do a read from memory */
/* Report running value of syscall counter */
l.or r3, r0, r16
l.nop 2
l.rfe /* Now continue from where we had the l.sys */
/orpsocv2/sw/Makefile.inc
124,7 → 124,9
$(INCLUDE_FLAGS) \
-I$(SW_ROOT)/lib/include \
 
OR32_LDFLAGS ?=-L$(SW_ROOT)/lib -lorpsoc -lgcc -T$(CPU_DRIVER)/link.ld -e 256
LINK_SCRIPT_OPT ?=-T$(CPU_DRIVER)/link.ld
 
OR32_LDFLAGS ?=-L$(SW_ROOT)/lib -lorpsoc -lgcc $(LINK_SCRIPT_OPT) -e 256
OR32_ARFLAGS ?=-r
# RTL_VERILOG_INCLUDE_DIR *MUST* be set!
# Backup one - default, but may be wrong!
/orpsocv2/sw/board/include/board.h
13,8 → 13,12
#define UART0_IRQ 2
#define UART0_BAUD_RATE 115200
 
#define SPI0_BASE 0xb0000000
#define SPI0_BASE 0xb0000000
 
#define INTGEN_BASE 0xe1000000
#define INTGEN_IRQ 19
 
 
//
// OR1200 tick timer period define
//

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