URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 54 to Rev 55
- ↔ Reverse comparison
Rev 54 → Rev 55
/orpsocv2/bench/verilog/or1200_monitor.v
93,7 → 93,7
// Development version of RTL. Libraries are missing. |
// |
// |
|
`include "timescale.v" |
`include "or1200_defines.v" |
`include "orpsoc_testbench_defines.v" |
|
/orpsocv2/rtl/verilog/components/smii/tmp.v
File deleted
orpsocv2/rtl/verilog/components/smii/tmp.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v (nonexistent)
@@ -1,250 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module obufdff
- (
- input d,
- output reg pad,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- pad <= #1 1'b0;
- else
- pad <= #1 d;
-endmodule
-module ibufdff
- (
- input pad,
- output reg q,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= #1 1'b0;
- else
- q <= #1 pad;
-endmodule
-module iobuftri
- (
- input i,
- input oe,
- output o,
- inout pad
- );
- assign #1 pad = oe ? i : 1'bz;
- assign #1 i = pad;
-endmodule
-module obuf
- (
- input i,
- inout pad
- );
- assign #1 pad = i;
-endmodule
-module smii_sync
- (
- output sync,
- output reg [1:10] state,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- state <= 10'b0000000001;
- else
- state <= {state[10],state[1:9]};
- assign sync = state[1];
-endmodule
-module smii_txrx
- (
- output tx,
- input rx,
- input [3:0] mtxd,
- input mtxen,
- input mtxerr,
- output mtx_clk,
- output reg [3:0] mrxd,
- output reg mrxdv,
- output reg mrxerr,
- output mrx_clk,
- output mcoll,
- output reg mcrs,
- input [1:10] state,
- input clk,
- input rst
- );
- reg [0:7] tx_data_reg;
- reg tx_data_reg_valid;
- reg a0;
- reg state_data;
- reg [3:0] rx_tmp;
- reg speed;
- reg duplex;
- reg link;
- reg jabber;
- reg mtx_clk_tmp, mrx_clk_tmp;
- reg [3:0] tx_cnt;
- reg [3:0] rx_cnt;
- always @ (posedge clk or posedge rst)
- if (rst)
- tx_cnt <= 4'd0;
- else
- if (speed)
- tx_cnt <= 4'd0;
- else if (state[10])
- if (tx_cnt == 4'd9)
- tx_cnt <= 4'd0;
- else
- tx_cnt <= tx_cnt + 4'd1;
- always @ (posedge clk or posedge rst)
- if (rst)
- mtx_clk_tmp <= 1'b0;
- else
- if ((state[10] | state[5]) & (tx_cnt == 4'd0))
- mtx_clk_tmp <= 1'b1;
- else if (state[2] | state[7])
- mtx_clk_tmp <= 1'b0;
- gbuf bufg1
- (
- .CLK(mtx_clk_tmp),
- .GL(mtx_clk)
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- begin
- tx_data_reg <= 8'd0;
- tx_data_reg_valid <= 1'b0;
- a0 <= 1'b0;
- end
- else
- if ((state[4] | state[9]) & (tx_cnt == 4'd0))
- begin
- if (!mtxen)
- a0 <= 1'b0;
- else
- a0 <= ~a0;
- if (!mtxen & !a0)
- tx_data_reg_valid <= 1'b0;
- else if (a0)
- tx_data_reg_valid <= 1'b1;
- if (mtxen & !a0)
- tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
- else if (mtxen & a0)
- tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
- end
- always @ (posedge clk or posedge rst)
- if (rst)
- state_data <= 1'b0;
- else
- if (state[1] & (tx_cnt == 4'd0))
- state_data <= tx_data_reg_valid;
- assign tx = state[1] ? mtxerr :
- state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
- state_data ? |(state[2:10] & tx_data_reg) :
- |(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
- always @ (posedge clk or posedge rst)
- if (rst)
- rx_cnt <= 4'd0;
- else
- if (speed)
- rx_cnt <= 4'd0;
- else if (!mrxdv & state[8] & rx_tmp[3])
- rx_cnt <= 4'd9;
- else if (state[10])
- if (rx_cnt == 4'd9)
- rx_cnt <= 4'd0;
- else
- rx_cnt <= rx_cnt + 4'd1;
- always @ (posedge clk or posedge rst)
- if (rst)
- begin
- {mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;
- rx_tmp <= 4'h0;
- mrxd <= 4'h0;
- end
- else
- begin
- rx_tmp[2:0] <= {rx,rx_tmp[2:1]};
- if (state[3])
- mcrs <= rx;
- if (state[4])
- rx_tmp[3] <= rx;
- if (rx_tmp[3])
- begin
- if (state[8])
- {mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};
- else if (state[2])
- mrxd <= #1 {rx,rx_tmp[2:0]};
- end
- else
- begin
- if (state[5])
- mrxerr <= #1 rx;
- if (state[6])
- speed <= #1 rx;
- if (state[7])
- duplex <= #1 rx;
- if (state[8])
- begin
- link <= #1 rx;
- mrxdv <= #1 1'b0;
- end
- if (state[9])
- jabber <= #1 rx;
- end
- end
- always @ (posedge clk or posedge rst)
- if (rst)
- mrx_clk_tmp <= 1'b0;
- else
- if ((state[1] | state[6]) & (rx_cnt == 4'd0))
- mrx_clk_tmp <= 1'b1;
- else if (state[3] | state[8])
- mrx_clk_tmp <= 1'b0;
- gbuf bufg2
- (
- .CLK(mrx_clk_tmp),
- .GL(mrx_clk)
- );
- assign mcoll = mcrs & mtxen;
-endmodule
orpsocv2/rtl/verilog/components/smii/smii_ACTEL.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/generic_gbuf.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/generic_gbuf.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/generic_gbuf.v (nonexistent)
@@ -1,50 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-`timescale 1 ns/100 ps
-module gbuf
- (
- output GL,
- input CLK
- );
-
- assign GL = CLK;
-
-endmodule
orpsocv2/rtl/verilog/components/smii/generic_gbuf.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/copyright.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/copyright.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/copyright.v (nonexistent)
@@ -1,40 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
orpsocv2/rtl/verilog/components/smii/copyright.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_sync.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_sync.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_sync.v (nonexistent)
@@ -1,61 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module smii_sync
- (
- // SMII sync
- output sync,
- // internal
- output reg [10:1] state,
- // clock amd reset
- input clk,
- input rst
- );
-
- // sync shall go high every 10:th cycle
- always @ (posedge clk or posedge rst)
- if (rst)
- state <= 10'b0000000001;
- else
- state <= {state[9:1],state[10]};
-
- assign sync = state[1];
-
-endmodule // smii_sync
orpsocv2/rtl/verilog/components/smii/smii_sync.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/generic_buffers.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/generic_buffers.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/generic_buffers.v (nonexistent)
@@ -1,94 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module obufdff
- (
- input d,
- output reg pad,
- input clk,
- input rst
- );
-
- always @ (posedge clk or posedge rst)
- if (rst)
- pad <= #1 1'b0;
- else
- pad <= #1 d;
-
-endmodule // obufdff
-
-module ibufdff
- (
- input pad,
- output reg q,
- input clk,
- input rst
- );
-
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= #1 1'b0;
- else
- q <= #1 pad;
-
-endmodule // ibufdff
-
-module iobuftri
- (
- input i,
- input oe,
- output o,
- inout pad
- );
-
- assign #1 pad = oe ? i : 1'bz;
- assign #1 o = pad;
-
-endmodule // iobuftri
-
-module obuf
- (
- input i,
- inout pad
- );
-
- assign #1 pad = i;
-
-endmodule // iobuftri
orpsocv2/rtl/verilog/components/smii/generic_buffers.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst.v (nonexistent)
@@ -1,185 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// SMII low pin count ethernet PHY interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-// wire declarations
-`for (i=1;i<=SMII;i++)
- // MII
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:`SMII] rx, tx;
-wire [1:`SMII] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-
-`ifndef SMII_SYNC_PER_PHY
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endif
-
-`for (i=1;i<=SMII;i++)
-// ethernet MAC
-eth_top eth_top::`i
- (
- // wb common
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- // wb slave
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- // wb master
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- // MII TX
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- // MII management
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-
- `ifdef SMII_SYNC_PER_PHY
-obufdff obufdff_sync::`i
- (
- .d(sync),
- .pad(eth_sync_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
- `endif
-
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-
-`endfor
-
orpsocv2/rtl/verilog/components/smii/smii_module_inst.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii.v (nonexistent)
@@ -1,242 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// SMII ////
-//// ////
-//// Description ////
-//// Low pin count serial MII ethernet interface ////
-//// ////
-//// To Do: ////
-//// - ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback, unneback@opencores.org ////
-//// ORSoC AB michael.unneback@orsoc.se ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module obufdff
- (
- input d,
- output reg pad,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- pad <= #1 1'b0;
- else
- pad <= #1 d;
-endmodule
-module ibufdff
- (
- input pad,
- output reg q,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= #1 1'b0;
- else
- q <= #1 pad;
-endmodule
-module iobuftri
- (
- input i,
- input oe,
- output o,
- inout pad
- );
- assign #1 pad = oe ? i : 1'bz;
- assign #1 i = pad;
-endmodule
-module obuf
- (
- input i,
- inout pad
- );
- assign #1 pad = i;
-endmodule
-module smii_sync
- (
- output sync,
- output reg [1:10] state,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- state <= 10'b0000000001;
- else
- state <= {state[10],state[1:9]};
- assign sync = state[1];
-endmodule
-module smii_txrx
- (
- output tx,
- input rx,
- input [3:0] mtxd,
- input mtxen,
- input mtxerr,
- output mtx_clk,
- output reg [3:0] mrxd,
- output reg mrxdv,
- output reg mrxerr,
- output mrx_clk,
- output mcoll,
- output reg mcrs,
- input [1:10] state,
- input clk,
- input rst
- );
- reg [0:7] tx_data_reg;
- reg tx_data_reg_valid;
- reg a0;
- reg state_data;
- reg [3:0] rx_tmp;
- reg speed;
- reg duplex;
- reg link;
- reg jabber;
- reg mtx_clk_tmp, mrx_clk_tmp;
- reg [3:0] tx_cnt;
- reg [3:0] rx_cnt;
- always @ (posedge clk or posedge rst)
- if (rst)
- tx_cnt <= 4'd0;
- else
- if (speed)
- tx_cnt <= 4'd0;
- else if (state[10])
- if (tx_cnt == 4'd9)
- tx_cnt <= 4'd0;
- else
- tx_cnt <= tx_cnt + 4'd1;
- always @ (posedge clk or posedge rst)
- if (rst)
- mtx_clk_tmp <= 1'b0;
- else
- if ((state[10] | state[5]) & (tx_cnt == 4'd0))
- mtx_clk_tmp <= 1'b1;
- else if (state[2] | state[7])
- mtx_clk_tmp <= 1'b0;
- assign #1 mtx_clk = mtx_clk_tmp;
- always @ (posedge clk or posedge rst)
- if (rst)
- begin
- tx_data_reg <= 8'd0;
- tx_data_reg_valid <= 1'b0;
- a0 <= 1'b0;
- end
- else
- if ((state[4] | state[9]) & (tx_cnt == 4'd0))
- begin
- if (!mtxen)
- a0 <= 1'b0;
- else
- a0 <= ~a0;
- if (!mtxen & !a0)
- tx_data_reg_valid <= 1'b0;
- else if (a0)
- tx_data_reg_valid <= 1'b1;
- if (mtxen & !a0)
- tx_data_reg[0:3] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
- else if (mtxen & a0)
- tx_data_reg[4:7] <= {mtxd[0],mtxd[1],mtxd[2],mtxd[3]};
- end
- always @ (posedge clk or posedge rst)
- if (rst)
- state_data <= 1'b0;
- else
- if (state[1] & (tx_cnt == 4'd0))
- state_data <= tx_data_reg_valid;
- assign tx = state[1] ? mtxerr :
- state[2] ? ((tx_data_reg_valid & (tx_cnt == 4'd0)) | state_data) :
- state_data ? |(state[2:10] & tx_data_reg) :
- |(state[2:10] & {mtxerr,speed,duplex,link,jabber,3'b111});
- always @ (posedge clk or posedge rst)
- if (rst)
- rx_cnt <= 4'd0;
- else
- if (speed)
- rx_cnt <= 4'd0;
- else if (!mrxdv & state[8] & rx_tmp[3])
- rx_cnt <= 4'd9;
- else if (state[10])
- if (rx_cnt == 4'd9)
- rx_cnt <= 4'd0;
- else
- rx_cnt <= rx_cnt + 4'd1;
- always @ (posedge clk or posedge rst)
- if (rst)
- begin
- {mcrs, mrxdv, mrxerr, speed, duplex, link, jabber} <= 7'b0001110;
- rx_tmp <= 4'h0;
- mrxd <= 4'h0;
- end
- else
- begin
- rx_tmp[2:0] <= {rx,rx_tmp[2:1]};
- if (state[3])
- mcrs <= rx;
- if (state[4])
- rx_tmp[3] <= rx;
- if (rx_tmp[3])
- begin
- if (state[8])
- {mrxdv,mrxd} <= #1 {rx_tmp[3],rx,rx_tmp[2:0]};
- else if (state[2])
- mrxd <= #1 {rx,rx_tmp[2:0]};
- end
- else
- begin
- if (state[5])
- mrxerr <= #1 rx;
- if (state[6])
- speed <= #1 rx;
- if (state[7])
- duplex <= #1 rx;
- if (state[8])
- begin
- link <= #1 rx;
- mrxdv <= #1 1'b0;
- end
- if (state[9])
- jabber <= #1 rx;
- end
- end
- always @ (posedge clk or posedge rst)
- if (rst)
- mrx_clk_tmp <= 1'b0;
- else
- if ((state[1] | state[6]) & (rx_cnt == 4'd0))
- mrx_clk_tmp <= 1'b1;
- else if (state[3] | state[8])
- mrx_clk_tmp <= 1'b0;
- assign #1 mrx_clk = mrx_clk_tmp;
- assign mcoll = mcrs & mtxen;
-endmodule
orpsocv2/rtl/verilog/components/smii/smii.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v (nonexistent)
@@ -1,116 +0,0 @@
-`for (i=1;i<=SMII;i++)
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:1] rx, tx;
-wire [1:1] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`for (i=1;i<=SMII;i++)
-eth_top eth_top::`i
- (
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endfor
orpsocv2/rtl/verilog/components/smii/smii_module_inst_1.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v (nonexistent)
@@ -1,116 +0,0 @@
-`for (i=1;i<=SMII;i++)
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:2] rx, tx;
-wire [1:2] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`for (i=1;i<=SMII;i++)
-eth_top eth_top::`i
- (
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endfor
orpsocv2/rtl/verilog/components/smii/smii_module_inst_2.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v (nonexistent)
@@ -1,116 +0,0 @@
-`for (i=1;i<=SMII;i++)
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:3] rx, tx;
-wire [1:3] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`for (i=1;i<=SMII;i++)
-eth_top eth_top::`i
- (
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endfor
orpsocv2/rtl/verilog/components/smii/smii_module_inst_3.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v (nonexistent)
@@ -1,116 +0,0 @@
-`for (i=1;i<=SMII;i++)
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:4] rx, tx;
-wire [1:4] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`for (i=1;i<=SMII;i++)
-eth_top eth_top::`i
- (
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endfor
orpsocv2/rtl/verilog/components/smii/smii_module_inst_4.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v (nonexistent)
@@ -1,116 +0,0 @@
-`for (i=1;i<=SMII;i++)
-wire m::`i::tx_clk;
-wire [3:0] m::`i::txd;
-wire m::`i::txen;
-wire m::`i::txerr;
-wire m::`i::rx_clk;
-wire [3:0] m::`i::rxd;
-wire m::`i::rxdv;
-wire m::`i::rxerr;
-wire m::`i::coll;
-wire m::`i::crs;
-`endfor
-wire [1:10] state;
-wire sync;
-wire [1:8] rx, tx;
-wire [1:8] mdc_o, md_i, md_o, md_oe;
-smii_sync smii_sync1
- (
- .sync(sync),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_sync
- (
- .d(sync),
- .pad(eth_sync_pad_o),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`for (i=1;i<=SMII;i++)
-eth_top eth_top::`i
- (
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_dat_i(wbs_eth::`i::_cfg_dat_i),
- .wb_dat_o(wbs_eth::`i::_cfg_dat_o),
- .wb_adr_i(wbs_eth::`i::_cfg_adr_i[11:2]),
- .wb_sel_i(wbs_eth::`i::_cfg_sel_i),
- .wb_we_i(wbs_eth::`i::_cfg_we_i),
- .wb_cyc_i(wbs_eth::`i::_cfg_cyc_i),
- .wb_stb_i(wbs_eth::`i::_cfg_stb_i),
- .wb_ack_o(wbs_eth::`i::_cfg_ack_o),
- .wb_err_o(wbs_eth::`i::_cfg_err_o),
- .m_wb_adr_o(wbm_eth::`i::_adr_o),
- .m_wb_sel_o(wbm_eth::`i::_sel_o),
- .m_wb_we_o(wbm_eth::`i::_we_o),
- .m_wb_dat_o(wbm_eth::`i::_dat_o),
- .m_wb_dat_i(wbm_eth::`i::_dat_i),
- .m_wb_cyc_o(wbm_eth::`i::_cyc_o),
- .m_wb_stb_o(wbm_eth::`i::_stb_o),
- .m_wb_ack_i(wbm_eth::`i::_ack_i),
- .m_wb_err_i(wbm_eth::`i::_err_i),
- .m_wb_cti_o(wbm_eth::`i::_cti_o),
- .m_wb_bte_o(wbm_eth::`i::_bte_o),
- .mtx_clk_pad_i(m::`i::tx_clk),
- .mtxd_pad_o(m::`i::txd),
- .mtxen_pad_o(m::`i::txen),
- .mtxerr_pad_o(m::`i::txerr),
- .mrx_clk_pad_i(m::`i::rx_clk),
- .mrxd_pad_i(m::`i::rxd),
- .mrxdv_pad_i(m::`i::rxdv),
- .mrxerr_pad_i(m::`i::rxerr),
- .mcoll_pad_i(m::`i::coll),
- .mcrs_pad_i(m::`i::crs),
- .mdc_pad_o(mdc_o[`i]),
- .md_pad_i(md_i[`i]),
- .md_pad_o(md_o[`i]),
- .md_padoe_o(md_oe[`i]),
- .int_o(eth_int[`i])
- );
-iobuftri iobuftri::`i
- (
- .i(md_o[`i]),
- .oe(md_oe[`i]),
- .o(md_i[`i]),
- .pad(eth_md_pad_io[`i])
- );
-obuf obuf::`i
- (
- .i(mdc_o[`i]),
- .pad(eth_mdc_pad_o[`i])
- );
-smii_txrx smii_txrx::`i
- (
- .tx(tx[`i]),
- .rx(rx[`i]),
- .mtx_clk(m::`i::tx_clk),
- .mtxd(m::`i::txd),
- .mtxen(m::`i::txen),
- .mtxerr(m::`i::txerr),
- .mrx_clk(m::`i::rx_clk),
- .mrxd(m::`i::rxd),
- .mrxdv(m::`i::rxdv),
- .mrxerr(m::`i::rxerr),
- .mcoll(m::`i::coll),
- .mcrs(m::`i::crs),
- .state(state),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-obufdff obufdff_tx::`i
- (
- .d(tx[`i]),
- .pad(eth_tx_pad_o[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-ibufdff ibufdff_rx::`i
- (
- .pad(eth_rx_pad_i[`i]),
- .q(rx[`i]),
- .clk(eth_clk),
- .rst(wb_rst)
- );
-`endfor
orpsocv2/rtl/verilog/components/smii/smii_module_inst_8.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/Makefile
===================================================================
--- orpsocv2/rtl/verilog/components/smii/Makefile (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/Makefile (nonexistent)
@@ -1,25 +0,0 @@
-comp1:
- vppreproc -DSMII=1 smii_module_inst.v > tmp.v
- vppp --simple +define+SMII+1 tmp.v > smii_module_inst_1.v
-
-comp2:
- vppreproc -DSMII=2 smii_module_inst.v > tmp.v
- vppp --simple +define+SMII+2 tmp.v > smii_module_inst_2.v
-
-comp3:
- vppreproc -DSMII=3 smii_module_inst.v > tmp.v
- vppp --simple +define+SMII+3 tmp.v > smii_module_inst_3.v
-
-comp4:
- vppreproc -DSMII=4 smii_module_inst.v > tmp.v
- vppp --simple +define+SMII+4 tmp.v > smii_module_inst_4.v
-
-comp8:
- vppreproc -DSMII=8 smii_module_inst.v > tmp.v
- vppp --simple +define+SMII+8 tmp.v > smii_module_inst_8.v
-
-smii:
- vppp --simple +define+ACTEL generic_buffers.v smii_sync.v smii_txrx.v | cat copyright.v - > smii_ACTEL.v
- vppp --simple generic_buffers.v smii_sync.v smii_txrx.v | cat copyright.v - > smii.v
-
-all: comp1 comp2 comp3 comp4 comp8 smii
orpsocv2/rtl/verilog/components/smii/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/smii/smii_txrx.v
===================================================================
--- orpsocv2/rtl/verilog/components/smii/smii_txrx.v (revision 54)
+++ orpsocv2/rtl/verilog/components/smii/smii_txrx.v (revision 55)
@@ -325,47 +325,3 @@
assign sync = state[1];
endmodule // smii_sync
-
-module obufdff
- (
- input d,
- output reg pad,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- pad <= 1'b0;
- else
- pad <= d;
-endmodule
-module ibufdff
- (
- input pad,
- output reg q,
- input clk,
- input rst
- );
- always @ (posedge clk or posedge rst)
- if (rst)
- q <= 1'b0;
- else
- q <= pad;
-endmodule
-module iobuftri
- (
- input i,
- input oe,
- output o,
- inout pad
- );
- assign pad = oe ? i : 1'bz;
- assign o = pad;
-endmodule
-module obuf
- (
- input i,
- inout pad
- );
- assign pad = i;
-endmodule
orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_16_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v (nonexistent)
@@ -1,429 +0,0 @@
-`timescale 1ns/1ns
-module delay #
- (
- parameter depth = 3,
- parameter width = 2
- )
- (
- input [width-1:0] d,
- output [width-1:0] q,
- input clear,
- input clk,
- input rst
- );
- reg [width-1:0] dffs [1:depth];
- integer i;
- always @ (posedge clk or posedge rst)
- if (rst)
- for ( i=1; i < depth+1; i= i + 1)
- dffs[i] <= {depth{1'b0}};
- else
- if (clear)
- for ( i=1; i < depth+1; i= i + 1)
- dffs[i] <= {depth{1'b0}};
- else
- begin
- dffs[1] <= d;
- for ( i=2; i < depth+1; i= i + 1)
- dffs[i] <= dffs[i-1];
- end
- assign q = dffs[depth];
-endmodule
- `timescale 1ns/1ns
-module wb_sdram_ctrl_fsm (
- output reg [14:0] a,
- output reg accept_cmd,
- output reg [2:0] cmd,
- output reg cs_n,
- output reg rd_ack,
- output reg ref_ack,
- output reg wr_ack,
- input clear,
- input dly_100us,
- input end_of_burst,
- input ref_req,
- input sdram_clk,
- input wb_ack,
- input [24:1] wb_adr_i,
- input wb_cyc,
- input wb_rst,
- input wb_stb,
- input wb_we
-);
- parameter
- IDLE = 17,
- ACT_ROW = 12,
- AREF = 10,
- ARF1 = 16,
- ARF2 = 18,
- AWAIT_CMD = 9,
- LMR = 3,
- NOP1 = 0,
- NOP2 = 13,
- NOP3 = 14,
- NOP4 = 8,
- NOP5 = 7,
- PRE = 5,
- PRECHARGECLEAR = 15,
- PRECHARGERD = 6,
- PRECHARGETERM = 4,
- PRECHARGEWR = 11,
- READ = 2,
- WRITE = 1;
- reg [18:0] state;
- reg [18:0] nextstate;
- always @* begin
- nextstate = 19'b0000000000000000000;
- a[14:0] = {2'b00,13'b0000000000000};
- accept_cmd = 1'b0;
- cmd[2:0] = 3'b111;
- cs_n = 1'b0;
- rd_ack = 1'b0;
- ref_ack = 1'b0;
- wr_ack = 1'b0;
- case (1'b1)
- state[IDLE] : begin
- cs_n = 1'b1;
- if (dly_100us) nextstate[PRE] = 1'b1;
- else nextstate[IDLE] = 1'b1;
- end
- state[ACT_ROW] : begin
- a[14:0] = {wb_adr_i[24:23],wb_adr_i[22:10]};
- cmd[2:0] = 3'b011;
- nextstate[NOP4] = 1'b1;
- end
- state[AREF] : begin
- cmd[2:0] = 3'b001;
- ref_ack = 1'b1;
- nextstate[AWAIT_CMD] = 1'b1;
- end
- state[ARF1] : begin
- cmd[2:0] = 3'b001;
- nextstate[NOP2] = 1'b1;
- end
- state[ARF2] : begin
- cmd[2:0] = 3'b001;
- nextstate[NOP3] = 1'b1;
- end
- state[AWAIT_CMD] : begin
- accept_cmd = 1'b1;
- cs_n = 1'b1;
- if (ref_req) nextstate[AREF] = 1'b1;
- else if (wb_stb & wb_cyc) nextstate[ACT_ROW] = 1'b1;
- else nextstate[AWAIT_CMD] = 1'b1;
- end
- state[LMR] : begin
- a[14:0] = {2'b00,3'b000,1'b1,2'b00,3'd2,1'b0,3'b000};
- cmd[2:0] = 3'b000;
- nextstate[AWAIT_CMD] = 1'b1;
- end
- state[NOP1] : nextstate[ARF1] = 1'b1;
- state[NOP2] : nextstate[ARF2] = 1'b1;
- state[NOP3] : nextstate[LMR] = 1'b1;
- state[NOP4] : if (wb_we) nextstate[WRITE] = 1'b1;
- else nextstate[READ] = 1'b1;
- state[NOP5] : begin
- if (clear) nextstate[ACT_ROW] = 1'b1;
- else if (wb_ack | (!wb_cyc & !wb_stb)) nextstate[AWAIT_CMD] = 1'b1;
- else nextstate[NOP5] = 1'b1;
- end
- state[PRE] : begin
- a[14:0] = {2'b00,13'b0010000000000};
- cmd[2:0] = 3'b010;
- nextstate[NOP1] = 1'b1;
- end
- state[PRECHARGECLEAR]: begin
- a[14:0] = {2'b00,13'b0010000000000};
- accept_cmd = 1'b1;
- cmd[2:0] = 3'b010;
- nextstate[ACT_ROW] = 1'b1;
- end
- state[PRECHARGERD] : begin
- a[14:0] = {2'b00,13'b0010000000000};
- cmd[2:0] = 3'b010;
- if (clear) nextstate[ACT_ROW] = 1'b1;
- else nextstate[NOP5] = 1'b1;
- end
- state[PRECHARGETERM] : begin
- a[14:0] = {2'b00,13'b0010000000000};
- cmd[2:0] = 3'b010;
- nextstate[AWAIT_CMD] = 1'b1;
- end
- state[PRECHARGEWR] : begin
- a[14:0] = {2'b00,13'b0010000000000};
- cmd[2:0] = 3'b010;
- nextstate[AWAIT_CMD] = 1'b1;
- end
- state[READ] : begin
- a[14:0] = {wb_adr_i[24:23],{4'b0000,wb_adr_i[9:1]}};
- cmd[2:0] = 3'b101;
- rd_ack = 1'b1;
- if (!wb_cyc & !wb_stb) nextstate[PRECHARGETERM] = 1'b1;
- else if (clear) nextstate[PRECHARGECLEAR] = 1'b1;
- else if (end_of_burst) nextstate[PRECHARGERD] = 1'b1;
- else nextstate[READ] = 1'b1;
- end
- state[WRITE] : begin
- a[14:0] = {wb_adr_i[24:23],{4'b0000,wb_adr_i[9:1]}};
- cmd[2:0] = 3'b100;
- wr_ack = 1'b1;
- if (end_of_burst) nextstate[PRECHARGEWR] = 1'b1;
- else nextstate[WRITE] = 1'b1;
- end
- endcase
- end
- always @(posedge sdram_clk or posedge wb_rst) begin
- if (wb_rst)
- state <= 19'b0000000000000000001 << IDLE;
- else
- state <= nextstate;
- end
- reg [111:0] statename;
- always @* begin
- case (1)
- state[IDLE] : statename = "IDLE";
- state[ACT_ROW] : statename = "ACT_ROW";
- state[AREF] : statename = "AREF";
- state[ARF1] : statename = "ARF1";
- state[ARF2] : statename = "ARF2";
- state[AWAIT_CMD] : statename = "AWAIT_CMD";
- state[LMR] : statename = "LMR";
- state[NOP1] : statename = "NOP1";
- state[NOP2] : statename = "NOP2";
- state[NOP3] : statename = "NOP3";
- state[NOP4] : statename = "NOP4";
- state[NOP5] : statename = "NOP5";
- state[PRE] : statename = "PRE";
- state[PRECHARGECLEAR]: statename = "PRECHARGECLEAR";
- state[PRECHARGERD] : statename = "PRECHARGERD";
- state[PRECHARGETERM] : statename = "PRECHARGETERM";
- state[PRECHARGEWR] : statename = "PRECHARGEWR";
- state[READ] : statename = "READ";
- state[WRITE] : statename = "WRITE";
- default : statename = "XXXXXXXXXXXXXX";
- endcase
- end
-endmodule
-`timescale 1ns/1ns
-`timescale 1ns/1ns
-module wb_sdram_ctrl_fifo
- (
- input [16-1:0] d_i,
- input we_i,
- input clear,
- input clk_i,
- output [32-1:0] wb_dat_o,
- input wb_cyc_i,
- input wb_stb_i,
- output wb_ack_o,
- input wb_clk,
- input rst
- );
- reg [32-1:0] ram [0:3];
- reg [16-1:0] tmp;
- reg [2-1:0] adr_i;
- wire [2-1:0] adr_i_next;
- reg [2-1:0] adr_o;
- wire [2-1:0] adr_o_next;
- reg a0;
- always @ (posedge clk_i or posedge rst)
- if (rst)
- a0 <= 1'b0;
- else
- if (clear)
- a0 <= 1'b0;
- else if (we_i)
- a0 <= ~a0;
- always @ (posedge clk_i or posedge rst)
- if (rst)
- tmp <= 16'd0;
- else
- tmp <= d_i;
- assign adr_i_next = (adr_i==3) ? 2'd0 : adr_i + 2'd1;
- always @ (posedge clk_i or posedge rst)
- if (rst)
- adr_i <= 2'd0;
- else
- if (clear)
- adr_i <= 2'd0;
- else if (we_i & a0)
- adr_i <= adr_i_next;
- assign adr_o_next = (adr_o==3) ? 2'd0 : adr_o + 2'd1;
- always @ (posedge clk_i or posedge rst)
- if (rst)
- adr_o <= {2{1'b0}};
- else
- if (clear)
- adr_o <= 2'd0;
- else if (wb_cyc_i & wb_stb_i & !(adr_i==adr_o))
- adr_o <= adr_o_next;
- assign wb_ack_o = wb_cyc_i & wb_stb_i & !(adr_i==adr_o);
- always @ (posedge clk_i)
- if (we_i & (a0==1'b1))
- ram[adr_i] <= {tmp,d_i};
- assign wb_dat_o = ram[adr_o];
-endmodule
- `timescale 1ns/1ns
-module wb_sdram_ctrl
- (
- input [31:0] wb_dat_i,
- output [31:0] wb_dat_o,
- input [3:0] wb_sel_i,
- input [24:2] wb_adr_i,
- input wb_we_i,
- input [2:0] wb_cti_i,
- input wb_stb_i,
- input wb_cyc_i,
- output wb_ack_o,
- output sdr_cke_o,
- output reg sdr_cs_n_o,
- output reg sdr_ras_n_o,
- output reg sdr_cas_n_o,
- output reg sdr_we_n_o,
- output reg [12:0] sdr_a_o,
- output reg [1:0] sdr_ba_o,
- inout [16-1:0] sdr_dq_io,
- output reg [16/8-1:0] sdr_dqm_o,
- input sdram_clk,
- input wb_clk,
- input wb_rst
- );
- reg ref_req;
- wire ref_ack;
- wire rd_ack, rd_ack_o, wr_ack, wr_ack_o, cmd_ack;
- reg [2-1:0] ba;
- reg [13-1:0] row;
- wire terminate, adr_fail, clear;
- wire end_of_burst;
- wire burst_counter_set;
- reg [9-1:0] burst_counter;
- wire [2:0] burst_counter_next;
- reg [2:0] burst_counter_init;
- wire fifo_we;
- wire [1:0] sdr_ba;
- wire [12:0] sdr_a;
- reg sdr_dq_oe_reg;
- wire [16-1:0] sdr_dq_i, sdr_dq_o;
- wire [16/8-1:0] sdr_dqm;
- reg [12:0] counter;
- wire counter_zf;
- assign counter_zf = (counter==13'd0);
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- counter <= 13'd4095;
- else if (counter_zf)
- counter <= 13'd390;
- else
- counter <= counter - 13'd1;
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- ref_req <= 1'b0;
- else
- if (counter_zf)
- ref_req <= 1'b1;
- else if (ref_ack)
- ref_req <= 1'b0;
- assign burst_counter_next = burst_counter[2:0] + {{2{1'b0}},1'b1};
- always @ (posedge sdram_clk or posedge wb_rst)
- if (wb_rst)
- begin
- ba <= 2'd0;
- row <= 13'd0;
- burst_counter_init <= 2'd0;
- burst_counter <= 9'd0;
- end
- else
- if (burst_counter_set)
- begin
- ba <= wb_adr_i[24:23];
- row <= wb_adr_i[22:10];
- burst_counter_init <= {wb_adr_i[2-1+2:2],1'b0};
- burst_counter <= {wb_adr_i[9+2:2],1'b0};
- end
- else if (rd_ack | wr_ack)
- begin
- burst_counter[2:0] <= burst_counter_next;
- end
- assign end_of_burst = (wb_cti_i==3'b000) ? (burst_counter[0]==1'b1) : (burst_counter_next == burst_counter_init);
- wb_sdram_ctrl_fsm fsm0
- (
- .dly_100us(counter_zf),
- .ref_req(ref_req),
- .ref_ack(ref_ack),
- .accept_cmd(burst_counter_set),
- .rd_ack(rd_ack),
- .wr_ack(wr_ack),
- .clear(clear),
- .wb_stb(wb_stb_i),
- .wb_cyc(wb_cyc_i),
- .wb_we(wb_we_i),
- .wb_ack(wb_ack_o & ((wb_cti_i==3'b000) | (wb_cti_i==3'b111))),
- .end_of_burst(end_of_burst),
- .wb_adr_i({wb_adr_i[24:23],wb_adr_i[22:10],burst_counter}),
- .a({sdr_ba,sdr_a}),
- .cmd({ras, cas, we}),
- .cs_n(sdr_cs_n),
- .sdram_clk(sdram_clk),
- .wb_rst(wb_rst)
- );
- assign sdr_dqm = ((burst_counter[0]==1'b0) & wr_ack) ? ~wb_sel_i[3:2] :
- ((burst_counter[0]==1'b1) & wr_ack) ? ~wb_sel_i[1:0] :
- 2'b00;
- always @ (posedge sdram_clk or posedge wb_rst)
- if (wb_rst)
- begin
- sdr_cs_n_o <= 1'b1;
- {sdr_ras_n_o, sdr_cas_n_o, sdr_we_n_o} <= 3'b111;
- {sdr_ba_o,sdr_a_o} <= 15'd0;
- sdr_dqm_o <= {16/8{1'b0}};
- end
- else
- begin
- sdr_cs_n_o <= #1 sdr_cs_n;
- {sdr_ras_n_o, sdr_cas_n_o, sdr_we_n_o} <= #1 {ras, cas, we};
- {sdr_ba_o,sdr_a_o} <= #1 {sdr_ba,sdr_a};
- sdr_dqm_o <= #1 sdr_dqm;
- end
- assign sdr_cke_o = 1'b1;
- assign sdr_dq_o = (burst_counter[0]==1'b0) ? wb_dat_i[31:16] : wb_dat_i[15:0];
- assign sdr_dq_oe = wr_ack;
- reg [16-1:0] sdr_dq_o_reg;
- always @ (posedge sdram_clk or posedge wb_rst)
- if (wb_rst)
- {sdr_dq_oe_reg,sdr_dq_o_reg} <= {1'b0,16'd0};
- else
- {sdr_dq_oe_reg,sdr_dq_o_reg} <= {sdr_dq_oe,sdr_dq_o};
- assign #1 sdr_dq_io = sdr_dq_oe_reg ? sdr_dq_o_reg : {16{1'bz}};
- assign #1 sdr_dq_i = sdr_dq_io;
- delay #
- (
- .depth(2+1),
- .width(1)
- )
- delay1
- (
- .d(rd_ack),
- .q(fifo_we),
- .clear(clear | terminate),
- .clk(sdram_clk),
- .rst(wb_rst)
- );
- assign wr_ack_o = wr_ack & burst_counter[0];
- wb_sdram_ctrl_fifo fifo
- (
- .d_i(sdr_dq_i),
- .we_i(fifo_we),
- .clear(clear | terminate),
- .clk_i(sdram_clk),
- .wb_dat_o(wb_dat_o),
- .wb_cyc_i(wb_cyc_i),
- .wb_stb_i(wb_stb_i),
- .wb_ack_o(rd_ack_o),
- .wb_clk(wb_clk),
- .rst(wb_rst)
- );
- assign terminate = ~wb_cyc_i & ~wb_stb_i;
- assign adr_fail = ~(wb_adr_i[24:4]=={ba,row,burst_counter[9-1:3]});
- assign clear = adr_fail & rd_ack_o;
- assign wb_ack_o = (rd_ack_o & !adr_fail) | wr_ack_o;
-endmodule
orpsocv2/rtl/verilog/components/wb_sdram_ctrl/wb_sdram_ctrl_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v (nonexistent)
@@ -1,2052 +0,0 @@
-`timescale 1ns/10ps
-module dbg_crc32_d1 (data, enable, shift, rst, sync_rst, crc_out, clk, crc_match);
-input data;
-input enable;
-input shift;
-input rst;
-input sync_rst;
-input clk;
-output crc_out;
-output crc_match;
-reg [31:0] crc;
-wire [31:0] new_crc;
-assign new_crc[0] = data ^ crc[31];
-assign new_crc[1] = data ^ crc[0] ^ crc[31];
-assign new_crc[2] = data ^ crc[1] ^ crc[31];
-assign new_crc[3] = crc[2];
-assign new_crc[4] = data ^ crc[3] ^ crc[31];
-assign new_crc[5] = data ^ crc[4] ^ crc[31];
-assign new_crc[6] = crc[5];
-assign new_crc[7] = data ^ crc[6] ^ crc[31];
-assign new_crc[8] = data ^ crc[7] ^ crc[31];
-assign new_crc[9] = crc[8];
-assign new_crc[10] = data ^ crc[9] ^ crc[31];
-assign new_crc[11] = data ^ crc[10] ^ crc[31];
-assign new_crc[12] = data ^ crc[11] ^ crc[31];
-assign new_crc[13] = crc[12];
-assign new_crc[14] = crc[13];
-assign new_crc[15] = crc[14];
-assign new_crc[16] = data ^ crc[15] ^ crc[31];
-assign new_crc[17] = crc[16];
-assign new_crc[18] = crc[17];
-assign new_crc[19] = crc[18];
-assign new_crc[20] = crc[19];
-assign new_crc[21] = crc[20];
-assign new_crc[22] = data ^ crc[21] ^ crc[31];
-assign new_crc[23] = data ^ crc[22] ^ crc[31];
-assign new_crc[24] = crc[23];
-assign new_crc[25] = crc[24];
-assign new_crc[26] = data ^ crc[25] ^ crc[31];
-assign new_crc[27] = crc[26];
-assign new_crc[28] = crc[27];
-assign new_crc[29] = crc[28];
-assign new_crc[30] = crc[29];
-assign new_crc[31] = crc[30];
-always @ (posedge clk or posedge rst)
-begin
- if(rst)
- crc[31:0] <= #1 32'hffffffff;
- else if(sync_rst)
- crc[31:0] <= #1 32'hffffffff;
- else if(enable)
- crc[31:0] <= #1 new_crc;
- else if (shift)
- crc[31:0] <= #1 {crc[30:0], 1'b0};
-end
-assign crc_match = (crc == 32'h0);
-assign crc_out = crc[31];
-endmodule
-`timescale 1ns/10ps
-module dbg_register (
- data_in,
- data_out,
- write,
- clk,
- reset
- );
-parameter WIDTH = 8;
-parameter RESET_VALUE = 0;
-input [WIDTH-1:0] data_in;
-input write;
-input clk;
-input reset;
-output [WIDTH-1:0] data_out;
-reg [WIDTH-1:0] data_out;
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- data_out[WIDTH-1:0] <= #1 RESET_VALUE;
- else if(write)
- data_out[WIDTH-1:0] <= #1 data_in[WIDTH-1:0];
-end
-endmodule
-`timescale 1ns/10ps
-module dbg_cpu_registers (
- data_i,
- we_i,
- tck_i,
- bp_i,
- rst_i,
- cpu_clk_i,
- ctrl_reg_o,
- cpu_stall_o,
- cpu_rst_o
- );
-input [2 -1:0] data_i;
-input we_i;
-input tck_i;
-input bp_i;
-input rst_i;
-input cpu_clk_i;
-output [2 -1:0]ctrl_reg_o;
-output cpu_stall_o;
-output cpu_rst_o;
-reg cpu_reset;
-wire [2:1] cpu_op_out;
-reg stall_bp, stall_bp_csff, stall_bp_tck;
-reg stall_reg, stall_reg_csff, stall_reg_cpu;
-reg cpu_reset_csff;
-reg cpu_rst_o;
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if(rst_i)
- stall_bp <= #1 1'b0;
- else if(bp_i)
- stall_bp <= #1 1'b1;
- else if(stall_reg_cpu)
- stall_bp <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- stall_bp_csff <= #1 1'b0;
- stall_bp_tck <= #1 1'b0;
- end
- else
- begin
- stall_bp_csff <= #1 stall_bp;
- stall_bp_tck <= #1 stall_bp_csff;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- stall_reg_csff <= #1 1'b0;
- stall_reg_cpu <= #1 1'b0;
- end
- else
- begin
- stall_reg_csff <= #1 stall_reg;
- stall_reg_cpu <= #1 stall_reg_csff;
- end
-end
-assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- stall_reg <= #1 1'b0;
- else if (stall_bp_tck)
- stall_reg <= #1 1'b1;
- else if (we_i)
- stall_reg <= #1 data_i[0];
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- cpu_reset <= #1 1'b0;
- else if(we_i)
- cpu_reset <= #1 data_i[1];
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- cpu_reset_csff <= #1 1'b0;
- cpu_rst_o <= #1 1'b0;
- end
- else
- begin
- cpu_reset_csff <= #1 cpu_reset;
- cpu_rst_o <= #1 cpu_reset_csff;
- end
-end
-assign ctrl_reg_o = {cpu_reset, stall_reg};
-endmodule
-`timescale 1ns/10ps
-module dbg_cpu(
- tck_i,
- tdi_i,
- tdo_o,
- shift_dr_i,
- pause_dr_i,
- update_dr_i,
- cpu_ce_i,
- crc_match_i,
- crc_en_o,
- shift_crc_o,
- rst_i,
- cpu_clk_i,
- cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
- cpu_stb_o,
- cpu_we_o, cpu_ack_i, cpu_rst_o
- );
-input tck_i;
-input tdi_i;
-output tdo_o;
-input shift_dr_i;
-input pause_dr_i;
-input update_dr_i;
-input cpu_ce_i;
-input crc_match_i;
-output crc_en_o;
-output shift_crc_o;
-input rst_i;
-input cpu_clk_i;
-output [31:0] cpu_addr_o;
-output [31:0] cpu_data_o;
-input cpu_bp_i;
-output cpu_stall_o;
-input [31:0] cpu_data_i;
-output cpu_stb_o;
-output cpu_we_o;
-input cpu_ack_i;
-output cpu_rst_o;
-reg cpu_stb_o;
-wire cpu_reg_stall;
-reg tdo_o;
-reg cpu_ack_q;
-reg cpu_ack_csff;
-reg cpu_ack_tck;
-reg [31:0] cpu_dat_tmp, cpu_data_dsff;
-reg [31:0] cpu_addr_dsff;
-reg cpu_we_dsff;
-reg [52 -1 :0] dr;
-wire enable;
-wire cmd_cnt_en;
-reg [3 -1:0] cmd_cnt;
-wire cmd_cnt_end;
-reg cmd_cnt_end_q;
-reg addr_len_cnt_en;
-reg [5:0] addr_len_cnt;
-wire addr_len_cnt_end;
-reg addr_len_cnt_end_q;
-reg crc_cnt_en;
-reg [6 -1:0] crc_cnt;
-wire crc_cnt_end;
-reg crc_cnt_end_q;
-reg data_cnt_en;
-reg [19:0] data_cnt;
-reg [16:0] data_cnt_limit;
-wire data_cnt_end;
-reg data_cnt_end_q;
-reg crc_match_reg;
-reg [3'd4 -1:0] acc_type;
-reg [6'd32 -1:0] adr;
-reg [5'd16 -1:0] len;
-reg [5'd16:0] len_var;
-wire [2 -1:0]ctrl_reg;
-reg start_rd_tck;
-reg rd_tck_started;
-reg start_rd_csff;
-reg start_cpu_rd;
-reg start_cpu_rd_q;
-reg start_wr_tck;
-reg start_wr_csff;
-reg start_cpu_wr;
-reg start_cpu_wr_q;
-reg status_cnt_en;
-wire status_cnt_end;
-wire half, long;
-reg half_q, long_q;
-reg [3 -1:0] status_cnt;
-reg [3'd4 -1:0] status;
-reg cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
-reg underrun_tck;
-reg busy_cpu;
-reg busy_tck;
-reg cpu_end;
-reg cpu_end_rst;
-reg cpu_end_rst_csff;
-reg cpu_end_csff;
-reg cpu_end_tck, cpu_end_tck_q;
-reg busy_csff;
-reg latch_data;
-reg update_dr_csff, update_dr_cpu;
-wire [2 -1:0] cpu_reg_data_i;
-wire cpu_reg_we;
-reg set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
-wire [31:0] input_data;
-wire len_eq_0;
-wire crc_cnt_31;
-reg fifo_full;
-reg [7:0] mem [0:3];
-reg cpu_ce_csff;
-reg mem_ptr_init;
-reg [3'd4 -1: 0] curr_cmd;
-wire curr_cmd_go;
-reg curr_cmd_go_q;
-wire curr_cmd_wr_comm;
-wire curr_cmd_wr_ctrl;
-wire curr_cmd_rd_comm;
-wire curr_cmd_rd_ctrl;
-wire acc_type_read;
-wire acc_type_write;
-assign enable = cpu_ce_i & shift_dr_i;
-assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
-assign shift_crc_o = enable & status_cnt_end;
-assign curr_cmd_go = (curr_cmd == 4'h0) && cmd_cnt_end;
-assign curr_cmd_wr_comm = (curr_cmd == 4'h2) && cmd_cnt_end;
-assign curr_cmd_wr_ctrl = (curr_cmd == 4'h4) && cmd_cnt_end;
-assign curr_cmd_rd_comm = (curr_cmd == 4'h1) && cmd_cnt_end;
-assign curr_cmd_rd_ctrl = (curr_cmd == 4'h3) && cmd_cnt_end;
-assign acc_type_read = (acc_type == 4'h6);
-assign acc_type_write = (acc_type == 4'h2);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- latch_data <= #1 1'b0;
- dr <= #1 {52{1'b0}};
- end
- else if (curr_cmd_rd_comm && crc_cnt_31)
- begin
- dr[52 -1:0] <= #1 {acc_type, adr, len};
- end
- else if (curr_cmd_rd_ctrl && crc_cnt_31)
- begin
- dr[52 -1:0] <= #1 {ctrl_reg, {52 -2{1'b0}}};
- end
- else if (acc_type_read && curr_cmd_go && crc_cnt_31)
- begin
- dr[31:0] <= #1 input_data[31:0];
- latch_data <= #1 1'b1;
- end
- else if (acc_type_read && curr_cmd_go && crc_cnt_end)
- begin
- case (acc_type)
- 4'h6: begin
- if(long & (~long_q))
- begin
- dr[31:0] <= #1 input_data[31:0];
- latch_data <= #1 1'b1;
- end
- else
- begin
- dr[31:0] <= #1 {dr[30:0], 1'b0};
- latch_data <= #1 1'b0;
- end
- end
- endcase
- end
- else if (enable && (!addr_len_cnt_end))
- begin
- dr <= #1 {dr[52 -2:0], tdi_i};
- end
-end
-assign cmd_cnt_en = enable & (~cmd_cnt_end);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- cmd_cnt <= #1 {3{1'b0}};
- else if (update_dr_i)
- cmd_cnt <= #1 {3{1'b0}};
- else if (cmd_cnt_en)
- cmd_cnt <= #1 cmd_cnt + 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- curr_cmd <= #1 {3'd4{1'b0}};
- else if (update_dr_i)
- curr_cmd <= #1 {3'd4{1'b0}};
- else if (cmd_cnt == (3'd4 -1))
- curr_cmd <= #1 {dr[3'd4-2 :0], tdi_i};
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- curr_cmd_go_q <= #1 1'b0;
- else
- curr_cmd_go_q <= #1 curr_cmd_go;
-end
-always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
-begin
- if (enable && (!addr_len_cnt_end))
- begin
- if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
- addr_len_cnt_en = 1'b1;
- else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
- addr_len_cnt_en = 1'b1;
- else
- addr_len_cnt_en = 1'b0;
- end
- else
- addr_len_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- addr_len_cnt <= #1 6'h0;
- else if (update_dr_i)
- addr_len_cnt <= #1 6'h0;
- else if (addr_len_cnt_en)
- addr_len_cnt <= #1 addr_len_cnt + 1'b1;
-end
-always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
-begin
- if (enable && (!data_cnt_end))
- begin
- if (cmd_cnt_end && curr_cmd_go && acc_type_write)
- data_cnt_en = 1'b1;
- else if (crc_cnt_end && curr_cmd_go && acc_type_read)
- data_cnt_en = 1'b1;
- else
- data_cnt_en = 1'b0;
- end
- else
- data_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- data_cnt <= #1 {19{1'b0}};
- else if (update_dr_i)
- data_cnt <= #1 {19{1'b0}};
- else if (data_cnt_en)
- data_cnt <= #1 data_cnt + 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- data_cnt_limit <= #1 {16{1'b0}};
- else if (update_dr_i)
- data_cnt_limit <= #1 len + 1'b1;
-end
-always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
-begin
- if (enable && (!crc_cnt_end) && cmd_cnt_end)
- begin
- if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
- crc_cnt_en = 1'b1;
- else if (data_cnt_end && curr_cmd_go && acc_type_write)
- crc_cnt_en = 1'b1;
- else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
- crc_cnt_en = 1'b1;
- else
- crc_cnt_en = 1'b0;
- end
- else
- crc_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_cnt <= #1 {6{1'b0}};
- else if(crc_cnt_en)
- crc_cnt <= #1 crc_cnt + 1'b1;
- else if (update_dr_i)
- crc_cnt <= #1 {6{1'b0}};
-end
-assign cmd_cnt_end = cmd_cnt == 3'd4;
-assign addr_len_cnt_end = addr_len_cnt == 52;
-assign crc_cnt_end = crc_cnt == 6'd32;
-assign crc_cnt_31 = crc_cnt == 6'd31;
-assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- crc_cnt_end_q <= #1 1'b0;
- cmd_cnt_end_q <= #1 1'b0;
- data_cnt_end_q <= #1 1'b0;
- addr_len_cnt_end_q <= #1 1'b0;
- end
- else
- begin
- crc_cnt_end_q <= #1 crc_cnt_end;
- cmd_cnt_end_q <= #1 cmd_cnt_end;
- data_cnt_end_q <= #1 data_cnt_end;
- addr_len_cnt_end_q <= #1 addr_len_cnt_end;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- status_cnt <= #1 {3{1'b0}};
- else if (update_dr_i)
- status_cnt <= #1 {3{1'b0}};
- else if (status_cnt_en)
- status_cnt <= #1 status_cnt + 1'b1;
-end
-always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
- curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
- acc_type_read or data_cnt_end or addr_len_cnt_end)
-begin
- if (enable && (!status_cnt_end))
- begin
- if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
- status_cnt_en = 1'b1;
- else if (crc_cnt_end && curr_cmd_go && acc_type_write)
- status_cnt_en = 1'b1;
- else if (data_cnt_end && curr_cmd_go && acc_type_read)
- status_cnt_en = 1'b1;
- else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
- status_cnt_en = 1'b1;
- else
- status_cnt_en = 1'b0;
- end
- else
- status_cnt_en = 1'b0;
-end
-assign status_cnt_end = status_cnt == 3'd4;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- acc_type <= #1 {3'd4{1'b0}};
- adr <= #1 {6'd32{1'b0}};
- len <= #1 {5'd16{1'b0}};
- set_addr <= #1 1'b0;
- end
- else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
- begin
- acc_type <= #1 dr[3'd4 + 6'd32 + 5'd16 -1 : 6'd32 + 5'd16];
- adr <= #1 dr[6'd32 + 5'd16 -1 : 5'd16];
- len <= #1 dr[5'd16 -1:0];
- set_addr <= #1 1'b1;
- end
- else if(cpu_end_tck)
- begin
- adr <= #1 cpu_addr_dsff;
- end
- else
- set_addr <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_match_reg <= #1 1'b0;
- else if(crc_cnt_end & (~crc_cnt_end_q))
- crc_match_reg <= #1 crc_match_i;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- else if(update_dr_i)
- len_var <= #1 len + 1'b1;
- else if (start_rd_tck)
- begin
- if (len_var > 'd4)
- len_var <= #1 len_var - 3'd4;
- else
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- end
-end
-assign len_eq_0 = len_var == 'h0;
-assign half = data_cnt[3:0] == 4'd15;
-assign long = data_cnt[4:0] == 5'd31;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- half_q <= #1 1'b0;
- long_q <= #1 1'b0;
- end
- else
- begin
- half_q <= #1 half;
- long_q <= #1 long;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- start_wr_tck <= #1 1'b0;
- cpu_dat_tmp <= #1 32'h0;
- end
- else if (curr_cmd_go && acc_type_write)
- begin
- if (long_q)
- begin
- start_wr_tck <= #1 1'b1;
- cpu_dat_tmp <= #1 dr[31:0];
- end
- else
- begin
- start_wr_tck <= #1 1'b0;
- end
- end
- else
- start_wr_tck <= #1 1'b0;
-end
-always @ (posedge cpu_clk_i)
-begin
- cpu_data_dsff <= #1 cpu_dat_tmp;
-end
-assign cpu_data_o = cpu_data_dsff;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- start_rd_tck <= #1 1'b0;
- else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
- start_rd_tck <= #1 1'b1;
- else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
- start_rd_tck <= #1 1'b1;
- else
- start_rd_tck <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- rd_tck_started <= #1 1'b0;
- else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
- rd_tck_started <= #1 1'b0;
- else if (start_rd_tck)
- rd_tck_started <= #1 1'b1;
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- start_rd_csff <= #1 1'b0;
- start_cpu_rd <= #1 1'b0;
- start_cpu_rd_q <= #1 1'b0;
- start_wr_csff <= #1 1'b0;
- start_cpu_wr <= #1 1'b0;
- start_cpu_wr_q <= #1 1'b0;
- set_addr_csff <= #1 1'b0;
- set_addr_cpu <= #1 1'b0;
- set_addr_cpu_q <= #1 1'b0;
- cpu_ack_q <= #1 1'b0;
- end
- else
- begin
- start_rd_csff <= #1 start_rd_tck;
- start_cpu_rd <= #1 start_rd_csff;
- start_cpu_rd_q <= #1 start_cpu_rd;
- start_wr_csff <= #1 start_wr_tck;
- start_cpu_wr <= #1 start_wr_csff;
- start_cpu_wr_q <= #1 start_cpu_wr;
- set_addr_csff <= #1 set_addr;
- set_addr_cpu <= #1 set_addr_csff;
- set_addr_cpu_q <= #1 set_addr_cpu;
- cpu_ack_q <= #1 cpu_ack_i;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- cpu_stb_o <= #1 1'b0;
- else if (cpu_ack_i)
- cpu_stb_o <= #1 1'b0;
- else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
- cpu_stb_o <= #1 1'b1;
-end
-assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- cpu_addr_dsff <= #1 32'h0;
- else if (set_addr_cpu && (!set_addr_cpu_q))
- cpu_addr_dsff <= #1 adr;
- else if (cpu_ack_i && (!cpu_ack_q))
- cpu_addr_dsff <= #1 cpu_addr_dsff + 3'd4;
-end
-assign cpu_addr_o = cpu_addr_dsff;
-always @ (posedge cpu_clk_i)
-begin
- cpu_we_dsff <= #1 curr_cmd_go && acc_type_write;
-end
-assign cpu_we_o = cpu_we_dsff;
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- cpu_end <= #1 1'b0;
- else if (cpu_ack_i && (!cpu_ack_q))
- cpu_end <= #1 1'b1;
- else if (cpu_end_rst)
- cpu_end <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- cpu_end_csff <= #1 1'b0;
- cpu_end_tck <= #1 1'b0;
- cpu_end_tck_q <= #1 1'b0;
- end
- else
- begin
- cpu_end_csff <= #1 cpu_end;
- cpu_end_tck <= #1 cpu_end_csff;
- cpu_end_tck_q <= #1 cpu_end_tck;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- cpu_end_rst_csff <= #1 1'b0;
- cpu_end_rst <= #1 1'b0;
- end
- else
- begin
- cpu_end_rst_csff <= #1 cpu_end_tck;
- cpu_end_rst <= #1 cpu_end_rst_csff;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- busy_cpu <= #1 1'b0;
- else if (cpu_end_rst)
- busy_cpu <= #1 1'b0;
- else if (cpu_stb_o)
- busy_cpu <= #1 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- busy_csff <= #1 1'b0;
- busy_tck <= #1 1'b0;
- update_dr_csff <= #1 1'b0;
- update_dr_cpu <= #1 1'b0;
- end
- else
- begin
- busy_csff <= #1 busy_cpu;
- busy_tck <= #1 busy_csff;
- update_dr_csff <= #1 update_dr_i;
- update_dr_cpu <= #1 update_dr_csff;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- cpu_overrun <= #1 1'b0;
- else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
- cpu_overrun <= #1 1'b1;
- else if(update_dr_cpu)
- cpu_overrun <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- underrun_tck <= #1 1'b0;
- else if(latch_data && (!fifo_full) && (!data_cnt_end))
- underrun_tck <= #1 1'b1;
- else if(update_dr_i)
- underrun_tck <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- cpu_overrun_csff <= #1 1'b0;
- cpu_overrun_tck <= #1 1'b0;
- cpu_ack_csff <= #1 1'b0;
- cpu_ack_tck <= #1 1'b0;
- end
- else
- begin
- cpu_overrun_csff <= #1 cpu_overrun;
- cpu_overrun_tck <= #1 cpu_overrun_csff;
- cpu_ack_csff <= #1 cpu_ack_i;
- cpu_ack_tck <= #1 cpu_ack_csff;
- end
-end
-always @ (posedge cpu_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- cpu_ce_csff <= #1 1'b0;
- mem_ptr_init <= #1 1'b0;
- end
- else
- begin
- cpu_ce_csff <= #1 cpu_ce_i;
- mem_ptr_init <= #1 ~cpu_ce_csff;
- end
-end
-always @ (posedge cpu_clk_i)
-begin
- if (cpu_ack_i && (!cpu_ack_q))
- begin
- mem[0] <= #1 cpu_data_i[31:24];
- mem[1] <= #1 cpu_data_i[23:16];
- mem[2] <= #1 cpu_data_i[15:08];
- mem[3] <= #1 cpu_data_i[07:00];
- end
-end
-assign input_data = {mem[0], mem[1], mem[2], mem[3]};
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- fifo_full <= #1 1'h0;
- else if (update_dr_i)
- fifo_full <= #1 1'h0;
- else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full))
- fifo_full <= #1 1'b1;
- else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full))
- fifo_full <= #1 1'h0;
-end
-always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
-begin
- if (pause_dr_i)
- begin
- tdo_o = busy_tck;
- end
- else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
- begin
- tdo_o = ~crc_match_i;
- end
- else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
- begin
- tdo_o = dr[31];
- end
- else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
- begin
- tdo_o = ~crc_match_reg;
- end
- else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
- begin
- tdo_o = ~crc_match_reg;
- end
- else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
- begin
- tdo_o = dr[3'd4 + 6'd32 + 5'd16 -1];
- end
- else if (status_cnt_en)
- begin
- tdo_o = status[3];
- end
- else
- begin
- tdo_o = 1'b0;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- status <= #1 {3'd4{1'b0}};
- end
- else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
- begin
- status <= #1 {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
- end
- else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
- begin
- status <= #1 {1'b0, 1'b0, underrun_tck, crc_match_reg};
- end
- else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
- begin
- status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
- end
- else if (shift_dr_i && (!status_cnt_end))
- begin
- status <= #1 {status[3'd4 -2:0], status[3'd4 -1]};
- end
-end
-assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
-assign cpu_reg_data_i = dr[52 -1:52 -2];
-dbg_cpu_registers i_dbg_cpu_registers
- (
- .data_i (cpu_reg_data_i),
- .we_i (cpu_reg_we),
- .tck_i (tck_i),
- .bp_i (cpu_bp_i),
- .rst_i (rst_i),
- .cpu_clk_i (cpu_clk_i),
- .ctrl_reg_o (ctrl_reg),
- .cpu_stall_o (cpu_reg_stall),
- .cpu_rst_o (cpu_rst_o)
- );
-endmodule
-`timescale 1ns/10ps
-module dbg_wb(
- tck_i,
- tdi_i,
- tdo_o,
- shift_dr_i,
- pause_dr_i,
- update_dr_i,
- wishbone_ce_i,
- crc_match_i,
- crc_en_o,
- shift_crc_o,
- rst_i,
- wb_clk_i,
- wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
- wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
- );
-input tck_i;
-input tdi_i;
-output tdo_o;
-input shift_dr_i;
-input pause_dr_i;
-input update_dr_i;
-input wishbone_ce_i;
-input crc_match_i;
-output crc_en_o;
-output shift_crc_o;
-input rst_i;
-input wb_clk_i;
-output [31:0] wb_adr_o;
-output [31:0] wb_dat_o;
-input [31:0] wb_dat_i;
-output wb_cyc_o;
-output wb_stb_o;
-output [3:0] wb_sel_o;
-output wb_we_o;
-input wb_ack_i;
-output wb_cab_o;
-input wb_err_i;
-output [2:0] wb_cti_o;
-output [1:0] wb_bte_o;
-reg wb_cyc_o;
-reg tdo_o;
-reg [31:0] wb_dat_tmp, wb_dat_dsff;
-reg [31:0] wb_adr_dsff;
-reg [3:0] wb_sel_dsff;
-reg wb_we_dsff;
-reg [(3'd4 + 6'd32 + 5'd16) -1 :0] dr;
-wire enable;
-wire cmd_cnt_en;
-reg [3 -1:0] cmd_cnt;
-wire cmd_cnt_end;
-reg cmd_cnt_end_q;
-reg addr_len_cnt_en;
-reg [5:0] addr_len_cnt;
-wire addr_len_cnt_end;
-reg addr_len_cnt_end_q;
-reg crc_cnt_en;
-reg [6 -1:0] crc_cnt;
-wire crc_cnt_end;
-reg crc_cnt_end_q;
-reg data_cnt_en;
-reg [(5'd16 + 3):0] data_cnt;
-reg [5'd16:0] data_cnt_limit;
-wire data_cnt_end;
-reg data_cnt_end_q;
-reg crc_match_reg;
-reg [3'd4 -1:0] acc_type;
-reg [6'd32 -1:0] adr;
-reg [5'd16 -1:0] len;
-reg [5'd16:0] len_var;
-reg start_rd_tck;
-reg rd_tck_started;
-reg start_rd_csff;
-reg start_wb_rd;
-reg start_wb_rd_q;
-reg start_wr_tck;
-reg start_wr_csff;
-reg start_wb_wr;
-reg start_wb_wr_q;
-reg status_cnt_en;
-wire status_cnt_end;
-wire byte, half, long;
-reg byte_q, half_q, long_q;
-reg [3 -1:0] status_cnt;
-reg [3'd4 -1:0] status;
-reg wb_error, wb_error_csff, wb_error_tck;
-reg wb_overrun, wb_overrun_csff, wb_overrun_tck;
-reg underrun_tck;
-reg busy_wb;
-reg busy_tck;
-reg wb_end;
-reg wb_end_rst;
-reg wb_end_rst_csff;
-reg wb_end_csff;
-reg wb_end_tck, wb_end_tck_q;
-reg busy_csff;
-reg latch_data;
-reg update_dr_csff, update_dr_wb;
-reg set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
-wire [31:0] input_data;
-wire len_eq_0;
-wire crc_cnt_31;
-reg [1:0] ptr;
-reg [2:0] fifo_cnt;
-wire fifo_full;
-wire fifo_empty;
-reg [7:0] mem [0:3];
-reg [2:0] mem_ptr_dsff;
-reg wishbone_ce_csff;
-reg mem_ptr_init;
-reg [3'd4 -1: 0] curr_cmd;
-wire curr_cmd_go;
-reg curr_cmd_go_q;
-wire curr_cmd_wr_comm;
-wire curr_cmd_rd_comm;
-wire acc_type_read;
-wire acc_type_write;
-wire acc_type_8bit;
-wire acc_type_16bit;
-wire acc_type_32bit;
-assign enable = wishbone_ce_i & shift_dr_i;
-assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
-assign shift_crc_o = enable & status_cnt_end;
-assign curr_cmd_go = (curr_cmd == 4'h0) && cmd_cnt_end;
-assign curr_cmd_wr_comm = (curr_cmd == 4'h2) && cmd_cnt_end;
-assign curr_cmd_rd_comm = (curr_cmd == 4'h1) && cmd_cnt_end;
-assign acc_type_read = (acc_type == 4'h4 || acc_type == 4'h5 || acc_type == 4'h6);
-assign acc_type_write = (acc_type == 4'h0 || acc_type == 4'h1 || acc_type == 4'h2);
-assign acc_type_8bit = (acc_type == 4'h4 || acc_type == 4'h0);
-assign acc_type_16bit = (acc_type == 4'h5 || acc_type == 4'h1);
-assign acc_type_32bit = (acc_type == 4'h6 || acc_type == 4'h2);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- ptr <= #1 2'h0;
- else if (update_dr_i)
- ptr <= #1 2'h0;
- else if (curr_cmd_go && acc_type_read && crc_cnt_31)
- ptr <= #1 ptr + 1'b1;
- else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
- ptr <= ptr + 1'd1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- latch_data <= #1 1'b0;
- dr <= #1 {(3'd4 + 6'd32 + 5'd16){1'b0}};
- end
- else if (curr_cmd_rd_comm && crc_cnt_31)
- begin
- dr[3'd4 + 6'd32 + 5'd16 -1:0] <= #1 {acc_type, adr, len};
- end
- else if (acc_type_read && curr_cmd_go && crc_cnt_31)
- begin
- dr[31:0] <= #1 input_data[31:0];
- latch_data <= #1 1'b1;
- end
- else if (acc_type_read && curr_cmd_go && crc_cnt_end)
- begin
- if (acc_type == 4'h4)
- begin
- if(byte & (~byte_q))
- begin
- case (ptr)
- 2'b00 : dr[31:24] <= #1 input_data[31:24];
- 2'b01 : dr[31:24] <= #1 input_data[23:16];
- 2'b10 : dr[31:24] <= #1 input_data[15:8];
- 2'b11 : dr[31:24] <= #1 input_data[7:0];
- endcase
- latch_data <= #1 1'b1;
- end
- else
- begin
- dr[31:24] <= #1 {dr[30:24], 1'b0};
- latch_data <= #1 1'b0;
- end
- end
- else if (acc_type == 4'h5)
- begin
- if(half & (~half_q))
- begin
- if (ptr[1])
- dr[31:16] <= #1 input_data[15:0];
- else
- dr[31:16] <= #1 input_data[31:16];
- latch_data <= #1 1'b1;
- end
- else
- begin
- dr[31:16] <= #1 {dr[30:16], 1'b0};
- latch_data <= #1 1'b0;
- end
- end
- else if (acc_type == 4'h6)
- begin
- if(long & (~long_q))
- begin
- dr[31:0] <= #1 input_data[31:0];
- latch_data <= #1 1'b1;
- end
- else
- begin
- dr[31:0] <= #1 {dr[30:0], 1'b0};
- latch_data <= #1 1'b0;
- end
- end
- end
- else if (enable && (!addr_len_cnt_end))
- begin
- dr <= #1 {dr[(3'd4 + 6'd32 + 5'd16) -2:0], tdi_i};
- end
-end
-assign cmd_cnt_en = enable & (~cmd_cnt_end);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- cmd_cnt <= #1 {3{1'b0}};
- else if (update_dr_i)
- cmd_cnt <= #1 {3{1'b0}};
- else if (cmd_cnt_en)
- cmd_cnt <= #1 cmd_cnt + 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- curr_cmd <= #1 {3'd4{1'b0}};
- else if (update_dr_i)
- curr_cmd <= #1 {3'd4{1'b0}};
- else if (cmd_cnt == (3'd4 -1))
- curr_cmd <= #1 {dr[3'd4-2 :0], tdi_i};
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- curr_cmd_go_q <= #1 1'b0;
- else
- curr_cmd_go_q <= #1 curr_cmd_go;
-end
-always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
-begin
- if (enable && (!addr_len_cnt_end))
- begin
- if (cmd_cnt_end && curr_cmd_wr_comm)
- addr_len_cnt_en = 1'b1;
- else if (crc_cnt_end && curr_cmd_rd_comm)
- addr_len_cnt_en = 1'b1;
- else
- addr_len_cnt_en = 1'b0;
- end
- else
- addr_len_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- addr_len_cnt <= #1 6'h0;
- else if (update_dr_i)
- addr_len_cnt <= #1 6'h0;
- else if (addr_len_cnt_en)
- addr_len_cnt <= #1 addr_len_cnt + 1'b1;
-end
-always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
-begin
- if (enable && (!data_cnt_end))
- begin
- if (cmd_cnt_end && curr_cmd_go && acc_type_write)
- data_cnt_en = 1'b1;
- else if (crc_cnt_end && curr_cmd_go && acc_type_read)
- data_cnt_en = 1'b1;
- else
- data_cnt_en = 1'b0;
- end
- else
- data_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- data_cnt <= #1 {(5'd16 + 3){1'b0}};
- else if (update_dr_i)
- data_cnt <= #1 {(5'd16 + 3){1'b0}};
- else if (data_cnt_en)
- data_cnt <= #1 data_cnt + 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- data_cnt_limit <= #1 {5'd16{1'b0}};
- else if (update_dr_i)
- data_cnt_limit <= #1 len + 1'b1;
-end
-always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
-begin
- if (enable && (!crc_cnt_end) && cmd_cnt_end)
- begin
- if (addr_len_cnt_end && curr_cmd_wr_comm)
- crc_cnt_en = 1'b1;
- else if (data_cnt_end && curr_cmd_go && acc_type_write)
- crc_cnt_en = 1'b1;
- else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
- crc_cnt_en = 1'b1;
- else
- crc_cnt_en = 1'b0;
- end
- else
- crc_cnt_en = 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_cnt <= #1 {6{1'b0}};
- else if(crc_cnt_en)
- crc_cnt <= #1 crc_cnt + 1'b1;
- else if (update_dr_i)
- crc_cnt <= #1 {6{1'b0}};
-end
-assign cmd_cnt_end = cmd_cnt == 3'd4;
-assign addr_len_cnt_end = addr_len_cnt == (3'd4 + 6'd32 + 5'd16);
-assign crc_cnt_end = crc_cnt == 6'd32;
-assign crc_cnt_31 = crc_cnt == 6'd31;
-assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- crc_cnt_end_q <= #1 1'b0;
- cmd_cnt_end_q <= #1 1'b0;
- data_cnt_end_q <= #1 1'b0;
- addr_len_cnt_end_q <= #1 1'b0;
- end
- else
- begin
- crc_cnt_end_q <= #1 crc_cnt_end;
- cmd_cnt_end_q <= #1 cmd_cnt_end;
- data_cnt_end_q <= #1 data_cnt_end;
- addr_len_cnt_end_q <= #1 addr_len_cnt_end;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- status_cnt <= #1 {3{1'b0}};
- else if (update_dr_i)
- status_cnt <= #1 {3{1'b0}};
- else if (status_cnt_en)
- status_cnt <= #1 status_cnt + 1'b1;
-end
-always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
-begin
- if (enable && (!status_cnt_end))
- begin
- if (crc_cnt_end && curr_cmd_wr_comm)
- status_cnt_en = 1'b1;
- else if (crc_cnt_end && curr_cmd_go && acc_type_write)
- status_cnt_en = 1'b1;
- else if (data_cnt_end && curr_cmd_go && acc_type_read)
- status_cnt_en = 1'b1;
- else if (addr_len_cnt_end && curr_cmd_rd_comm)
- status_cnt_en = 1'b1;
- else
- status_cnt_en = 1'b0;
- end
- else
- status_cnt_en = 1'b0;
-end
-assign status_cnt_end = status_cnt == 3'd4;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- acc_type <= #1 {3'd4{1'b0}};
- adr <= #1 {6'd32{1'b0}};
- len <= #1 {5'd16{1'b0}};
- set_addr <= #1 1'b0;
- end
- else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
- begin
- acc_type <= #1 dr[3'd4 + 6'd32 + 5'd16 -1 : 6'd32 + 5'd16];
- adr <= #1 dr[6'd32 + 5'd16 -1 : 5'd16];
- len <= #1 dr[5'd16 -1:0];
- set_addr <= #1 1'b1;
- end
- else if(wb_end_tck)
- begin
- adr <= #1 wb_adr_dsff;
- end
- else
- set_addr <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_match_reg <= #1 1'b0;
- else if(crc_cnt_end & (~crc_cnt_end_q))
- crc_match_reg <= #1 crc_match_i;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- else if(update_dr_i)
- len_var <= #1 len + 1'b1;
- else if (start_rd_tck)
- begin
- case (acc_type)
- 4'h4 :
- if (len_var > 'd1)
- len_var <= #1 len_var - 1'd1;
- else
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- 4'h5:
- if (len_var > 'd2)
- len_var <= #1 len_var - 2'd2;
- else
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- 4'h6:
- if (len_var > 'd4)
- len_var <= #1 len_var - 3'd4;
- else
- len_var <= #1 {1'b0, {5'd16{1'b0}}};
- default: len_var <= #1 {1'bx, {5'd16{1'bx}}};
- endcase
- end
-end
-assign len_eq_0 = len_var == 'h0;
-assign byte = data_cnt[2:0] == 3'd7;
-assign half = data_cnt[3:0] == 4'd15;
-assign long = data_cnt[4:0] == 5'd31;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- byte_q <= #1 1'b0;
- half_q <= #1 1'b0;
- long_q <= #1 1'b0;
- end
- else
- begin
- byte_q <= #1 byte;
- half_q <= #1 half;
- long_q <= #1 long;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- start_wr_tck <= #1 1'b0;
- wb_dat_tmp <= #1 32'h0;
- end
- else if (curr_cmd_go && acc_type_write)
- begin
- case (acc_type)
- 4'h0 : begin
- if (byte_q)
- begin
- start_wr_tck <= #1 1'b1;
- wb_dat_tmp <= #1 {4{dr[7:0]}};
- end
- else
- begin
- start_wr_tck <= #1 1'b0;
- end
- end
- 4'h1 : begin
- if (half_q)
- begin
- start_wr_tck <= #1 1'b1;
- wb_dat_tmp <= #1 {2{dr[15:0]}};
- end
- else
- begin
- start_wr_tck <= #1 1'b0;
- end
- end
- 4'h2 : begin
- if (long_q)
- begin
- start_wr_tck <= #1 1'b1;
- wb_dat_tmp <= #1 dr[31:0];
- end
- else
- begin
- start_wr_tck <= #1 1'b0;
- end
- end
- endcase
- end
- else
- start_wr_tck <= #1 1'b0;
-end
-always @ (posedge wb_clk_i)
-begin
- wb_dat_dsff <= #1 wb_dat_tmp;
-end
-assign wb_dat_o = wb_dat_dsff;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- start_rd_tck <= #1 1'b0;
- else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)
- start_rd_tck <= #1 1'b1;
- else if ((!start_rd_tck) && curr_cmd_go && acc_type_read && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
- start_rd_tck <= #1 1'b1;
- else
- start_rd_tck <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- rd_tck_started <= #1 1'b0;
- else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
- rd_tck_started <= #1 1'b0;
- else if (start_rd_tck)
- rd_tck_started <= #1 1'b1;
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- start_rd_csff <= #1 1'b0;
- start_wb_rd <= #1 1'b0;
- start_wb_rd_q <= #1 1'b0;
- start_wr_csff <= #1 1'b0;
- start_wb_wr <= #1 1'b0;
- start_wb_wr_q <= #1 1'b0;
- set_addr_csff <= #1 1'b0;
- set_addr_wb <= #1 1'b0;
- set_addr_wb_q <= #1 1'b0;
- end
- else
- begin
- start_rd_csff <= #1 start_rd_tck;
- start_wb_rd <= #1 start_rd_csff;
- start_wb_rd_q <= #1 start_wb_rd;
- start_wr_csff <= #1 start_wr_tck;
- start_wb_wr <= #1 start_wr_csff;
- start_wb_wr_q <= #1 start_wb_wr;
- set_addr_csff <= #1 set_addr;
- set_addr_wb <= #1 set_addr_csff;
- set_addr_wb_q <= #1 set_addr_wb;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_cyc_o <= #1 1'b0;
- else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
- wb_cyc_o <= #1 1'b1;
- else if (wb_ack_i || wb_err_i)
- wb_cyc_o <= #1 1'b0;
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_adr_dsff <= #1 32'h0;
- else if (set_addr_wb && (!set_addr_wb_q))
- wb_adr_dsff <= #1 adr;
- else if (wb_ack_i)
- begin
- if ((acc_type == 4'h0) || (acc_type == 4'h4))
- wb_adr_dsff <= #1 wb_adr_dsff + 1'd1;
- else if ((acc_type == 4'h1) || (acc_type == 4'h5))
- wb_adr_dsff <= #1 wb_adr_dsff + 2'd2;
- else
- wb_adr_dsff <= #1 wb_adr_dsff + 3'd4;
- end
-end
-assign wb_adr_o = wb_adr_dsff;
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_sel_dsff[3:0] <= #1 4'h0;
- else
- begin
- case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit})
- {2'd0, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h8;
- {2'd0, 3'b010} : wb_sel_dsff[3:0] <= #1 4'hC;
- {2'd0, 3'b001} : wb_sel_dsff[3:0] <= #1 4'hF;
- {2'd1, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h4;
- {2'd2, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h2;
- {2'd2, 3'b010} : wb_sel_dsff[3:0] <= #1 4'h3;
- {2'd3, 3'b100} : wb_sel_dsff[3:0] <= #1 4'h1;
- default: wb_sel_dsff[3:0] <= #1 4'hx;
- endcase
- end
-end
-assign wb_sel_o = wb_sel_dsff;
-always @ (posedge wb_clk_i)
-begin
- wb_we_dsff <= #1 curr_cmd_go && acc_type_write;
-end
-assign wb_we_o = wb_we_dsff;
-assign wb_cab_o = 1'b0;
-assign wb_stb_o = wb_cyc_o;
-assign wb_cti_o = 3'h0;
-assign wb_bte_o = 2'h0;
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_end <= #1 1'b0;
- else if (wb_ack_i || wb_err_i)
- wb_end <= #1 1'b1;
- else if (wb_end_rst)
- wb_end <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wb_end_csff <= #1 1'b0;
- wb_end_tck <= #1 1'b0;
- wb_end_tck_q <= #1 1'b0;
- end
- else
- begin
- wb_end_csff <= #1 wb_end;
- wb_end_tck <= #1 wb_end_csff;
- wb_end_tck_q <= #1 wb_end_tck;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wb_end_rst_csff <= #1 1'b0;
- wb_end_rst <= #1 1'b0;
- end
- else
- begin
- wb_end_rst_csff <= #1 wb_end_tck;
- wb_end_rst <= #1 wb_end_rst_csff;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- busy_wb <= #1 1'b0;
- else if (wb_end_rst)
- busy_wb <= #1 1'b0;
- else if (wb_cyc_o)
- busy_wb <= #1 1'b1;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- busy_csff <= #1 1'b0;
- busy_tck <= #1 1'b0;
- update_dr_csff <= #1 1'b0;
- update_dr_wb <= #1 1'b0;
- end
- else
- begin
- busy_csff <= #1 busy_wb;
- busy_tck <= #1 busy_csff;
- update_dr_csff <= #1 update_dr_i;
- update_dr_wb <= #1 update_dr_csff;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_error <= #1 1'b0;
- else if(wb_err_i)
- wb_error <= #1 1'b1;
- else if(update_dr_wb)
- wb_error <= #1 1'b0;
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- wb_overrun <= #1 1'b0;
- else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
- wb_overrun <= #1 1'b1;
- else if(update_dr_wb)
- wb_overrun <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- underrun_tck <= #1 1'b0;
- else if(latch_data && fifo_empty && (!data_cnt_end))
- underrun_tck <= #1 1'b1;
- else if(update_dr_i)
- underrun_tck <= #1 1'b0;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wb_error_csff <= #1 1'b0;
- wb_error_tck <= #1 1'b0;
- wb_overrun_csff <= #1 1'b0;
- wb_overrun_tck <= #1 1'b0;
- end
- else
- begin
- wb_error_csff <= #1 wb_error;
- wb_error_tck <= #1 wb_error_csff;
- wb_overrun_csff <= #1 wb_overrun;
- wb_overrun_tck <= #1 wb_overrun_csff;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wishbone_ce_csff <= #1 1'b0;
- mem_ptr_init <= #1 1'b0;
- end
- else
- begin
- wishbone_ce_csff <= #1 wishbone_ce_i;
- mem_ptr_init <= #1 ~wishbone_ce_csff;
- end
-end
-always @ (posedge wb_clk_i or posedge rst_i)
-begin
- if (rst_i)
- mem_ptr_dsff <= #1 3'h0;
- else if(mem_ptr_init)
- mem_ptr_dsff <= #1 3'h0;
- else if (wb_ack_i)
- begin
- if (acc_type == 4'h4)
- mem_ptr_dsff <= #1 mem_ptr_dsff + 1'd1;
- else if (acc_type == 4'h5)
- mem_ptr_dsff <= #1 mem_ptr_dsff + 2'd2;
- end
-end
-always @ (posedge wb_clk_i)
-begin
- if (wb_ack_i)
- begin
- case (wb_sel_dsff)
- 4'b1000 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
- 4'b0100 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[23:16];
- 4'b0010 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
- 4'b0001 : mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[07:00];
- 4'b1100 :
- begin
- mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[31:24];
- mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[23:16];
- end
- 4'b0011 :
- begin
- mem[mem_ptr_dsff[1:0]] <= #1 wb_dat_i[15:08];
- mem[mem_ptr_dsff[1:0]+1'b1] <= #1 wb_dat_i[07:00];
- end
- 4'b1111 :
- begin
- mem[0] <= #1 wb_dat_i[31:24];
- mem[1] <= #1 wb_dat_i[23:16];
- mem[2] <= #1 wb_dat_i[15:08];
- mem[3] <= #1 wb_dat_i[07:00];
- end
- default :
- begin
- mem[0] <= #1 8'hxx;
- mem[1] <= #1 8'hxx;
- mem[2] <= #1 8'hxx;
- mem[3] <= #1 8'hxx;
- end
- endcase
- end
-end
-assign input_data = {mem[0], mem[1], mem[2], mem[3]};
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- fifo_cnt <= #1 3'h0;
- else if (update_dr_i)
- fifo_cnt <= #1 3'h0;
- else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full))
- begin
- case (acc_type)
- 4'h4 : fifo_cnt <= #1 fifo_cnt + 1'd1;
- 4'h5: fifo_cnt <= #1 fifo_cnt + 2'd2;
- 4'h6: fifo_cnt <= #1 fifo_cnt + 3'd4;
- default: fifo_cnt <= #1 3'bxxx;
- endcase
- end
- else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty))
- begin
- case (acc_type)
- 4'h4 : fifo_cnt <= #1 fifo_cnt - 1'd1;
- 4'h5: fifo_cnt <= #1 fifo_cnt - 2'd2;
- 4'h6: fifo_cnt <= #1 fifo_cnt - 3'd4;
- default: fifo_cnt <= #1 3'bxxx;
- endcase
- end
-end
-assign fifo_full = fifo_cnt == 3'h4;
-assign fifo_empty = fifo_cnt == 3'h0;
-always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
- curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
- or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
- or addr_len_cnt_end or addr_len_cnt_end_q)
-begin
- if (pause_dr_i)
- begin
- tdo_o = busy_tck;
- end
- else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
- begin
- tdo_o = ~crc_match_i;
- end
- else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
- begin
- tdo_o = dr[31];
- end
- else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
- begin
- tdo_o = ~crc_match_reg;
- end
- else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
- begin
- tdo_o = ~crc_match_reg;
- end
- else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
- begin
- tdo_o = dr[3'd4 + 6'd32 + 5'd16 -1];
- end
- else if (status_cnt_en)
- begin
- tdo_o = status[3];
- end
- else
- begin
- tdo_o = 1'b0;
- end
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- status <= #1 {3'd4{1'b0}};
- end
- else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
- begin
- status <= #1 {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
- end
- else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
- begin
- status <= #1 {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
- end
- else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
- begin
- status <= #1 {1'b0, 1'b0, 1'b0, crc_match_reg};
- end
- else if (shift_dr_i && (!status_cnt_end))
- begin
- status <= #1 {status[3'd4 -2:0], status[3'd4 -1]};
- end
-end
-endmodule
-`timescale 1ns/10ps
-module dbg_top(
- tck_i,
- tdi_i,
- tdo_o,
- rst_i,
- shift_dr_i,
- pause_dr_i,
- update_dr_i,
- debug_select_i
- ,
- wb_clk_i,
- wb_adr_o,
- wb_dat_o,
- wb_dat_i,
- wb_cyc_o,
- wb_stb_o,
- wb_sel_o,
- wb_we_o,
- wb_ack_i,
- wb_cab_o,
- wb_err_i,
- wb_cti_o,
- wb_bte_o
- ,
- cpu0_clk_i,
- cpu0_addr_o,
- cpu0_data_i,
- cpu0_data_o,
- cpu0_bp_i,
- cpu0_stall_o,
- cpu0_stb_o,
- cpu0_we_o,
- cpu0_ack_i,
- cpu0_rst_o
- );
-input tck_i;
-input tdi_i;
-output tdo_o;
-input rst_i;
-input shift_dr_i;
-input pause_dr_i;
-input update_dr_i;
-input debug_select_i;
-input wb_clk_i;
-output [31:0] wb_adr_o;
-output [31:0] wb_dat_o;
-input [31:0] wb_dat_i;
-output wb_cyc_o;
-output wb_stb_o;
-output [3:0] wb_sel_o;
-output wb_we_o;
-input wb_ack_i;
-output wb_cab_o;
-input wb_err_i;
-output [2:0] wb_cti_o;
-output [1:0] wb_bte_o;
-reg wishbone_module;
-reg wishbone_ce;
-wire tdi_wb;
-wire tdo_wb;
-wire crc_en_wb;
-wire shift_crc_wb;
-input cpu0_clk_i;
-output [31:0] cpu0_addr_o;
-input [31:0] cpu0_data_i;
-output [31:0] cpu0_data_o;
-input cpu0_bp_i;
-output cpu0_stall_o;
-output cpu0_stb_o;
-output cpu0_we_o;
-input cpu0_ack_i;
-output cpu0_rst_o;
-reg cpu0_debug_module;
-reg cpu0_ce;
-wire cpu0_tdi;
-wire cpu0_tdo;
-wire cpu0_crc_en;
-wire cpu0_shift_crc;
-wire cpu1_crc_en = 1'b0;
-wire cpu1_shift_crc = 1'b0;
-reg [3 -1:0] data_cnt;
-reg [6 -1:0] crc_cnt;
-reg [3 -1:0] status_cnt;
-reg [4 + 1 -1:0] module_dr;
-reg [4 -1:0] module_id;
-wire module_latch_en;
-wire data_cnt_end;
-wire crc_cnt_end;
-wire status_cnt_end;
-reg crc_cnt_end_q;
-reg module_select;
-reg module_select_error;
-wire crc_out;
-wire crc_match;
-wire data_shift_en;
-wire selecting_command;
-reg tdo_o;
-wire shift_crc;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- data_cnt <= #1 {3{1'b0}};
- else if(shift_dr_i & (~data_cnt_end))
- data_cnt <= #1 data_cnt + 1'b1;
- else if (update_dr_i)
- data_cnt <= #1 {3{1'b0}};
-end
-assign data_cnt_end = data_cnt == 4 + 1;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_cnt <= #1 {6{1'b0}};
- else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
- crc_cnt <= #1 crc_cnt + 1'b1;
- else if (update_dr_i)
- crc_cnt <= #1 {6{1'b0}};
-end
-assign crc_cnt_end = crc_cnt == 32;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_cnt_end_q <= #1 1'b0;
- else
- crc_cnt_end_q <= #1 crc_cnt_end;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- status_cnt <= #1 {3{1'b0}};
- else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
- status_cnt <= #1 status_cnt + 1'b1;
- else if (update_dr_i)
- status_cnt <= #1 {3{1'b0}};
-end
-assign status_cnt_end = status_cnt == 3'd4;
-assign selecting_command = shift_dr_i & (data_cnt == 3'h0) & debug_select_i;
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- module_select <= #1 1'b0;
- else if(selecting_command & tdi_i)
- module_select <= #1 1'b1;
- else if (update_dr_i)
- module_select <= #1 1'b0;
-end
-always @ (module_id)
-begin
- cpu0_debug_module <= #1 1'b0;
- wishbone_module <= #1 1'b0;
- module_select_error <= #1 1'b0;
- case (module_id)
- 4'h1 : cpu0_debug_module <= #1 1'b1;
- 4'h0 : wishbone_module <= #1 1'b1;
- default : module_select_error <= #1 1'b1;
- endcase
-end
-assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- module_id <= {4{1'b1}};
- else if(module_latch_en & crc_match)
- module_id <= #1 module_dr[4 + 1 -2:0];
-end
-assign data_shift_en = shift_dr_i & (~data_cnt_end);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- module_dr <= #1 4 + 1'h0;
- else if (data_shift_en)
- module_dr[4 + 1 -1:0] <= #1 {module_dr[4 + 1 -2:0], tdi_i};
-end
-dbg_crc32_d1 i_dbg_crc32_d1_in
- (
- .data (tdi_i),
- .enable (shift_dr_i),
- .shift (1'b0),
- .rst (rst_i),
- .sync_rst (update_dr_i),
- .crc_out (),
- .clk (tck_i),
- .crc_match (crc_match)
- );
-reg tdo_module_select;
-wire crc_en;
-wire crc_en_dbg;
-reg crc_started;
-assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
-assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- crc_started <= #1 1'b0;
- else if (crc_en)
- crc_started <= #1 1'b1;
- else if (update_dr_i)
- crc_started <= #1 1'b0;
-end
-reg tdo_tmp;
-dbg_crc32_d1 i_dbg_crc32_d1_out
- (
- .data (tdo_tmp),
- .enable (crc_en),
- .shift (shift_dr_i & crc_started & (~crc_en)),
- .rst (rst_i),
- .sync_rst (update_dr_i),
- .crc_out (crc_out),
- .clk (tck_i),
- .crc_match ()
- );
-always @ (status_cnt or crc_match or module_select_error or crc_out)
-begin
- case (status_cnt)
- 3'd0 : begin
- tdo_module_select = ~crc_match;
- end
- 3'd1 : begin
- tdo_module_select = module_select_error;
- end
- 3'd2 : begin
- tdo_module_select = 1'b0;
- end
- 3'd3 : begin
- tdo_module_select = 1'b0;
- end
- 3'd4 : begin
- tdo_module_select = crc_out;
- end
- default : begin tdo_module_select = 1'b0; end
- endcase
-end
-assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
-always @ (shift_crc or crc_out or tdo_module_select
- or wishbone_ce or tdo_wb
- or cpu0_ce or cpu0_tdo
- )
-begin
- if (shift_crc)
- tdo_tmp = crc_out;
- else if (wishbone_ce)
- tdo_tmp = tdo_wb;
- else if (cpu0_ce)
- tdo_tmp = cpu0_tdo;
- else
- tdo_tmp = tdo_module_select;
-end
-always @ (negedge tck_i)
-begin
- tdo_o <= #1 tdo_tmp;
-end
-always @ (posedge tck_i or posedge rst_i)
-begin
- if (rst_i)
- begin
- wishbone_ce <= #1 1'b0;
- cpu0_ce <= #1 1'b0;
- end
- else if(selecting_command & (~tdi_i))
- begin
- if (wishbone_module)
- wishbone_ce <= #1 1'b1;
- if (cpu0_debug_module)
- cpu0_ce <= #1 1'b1;
- end
- else if (update_dr_i)
- begin
- wishbone_ce <= #1 1'b0;
- cpu0_ce <= #1 1'b0;
- end
-end
-assign tdi_wb = wishbone_ce & tdi_i;
-assign cpu0_tdi = cpu0_ce & tdi_i;
-dbg_wb i_dbg_wb (
- .tck_i (tck_i),
- .tdi_i (tdi_wb),
- .tdo_o (tdo_wb),
- .shift_dr_i (shift_dr_i),
- .pause_dr_i (pause_dr_i),
- .update_dr_i (update_dr_i),
- .wishbone_ce_i (wishbone_ce),
- .crc_match_i (crc_match),
- .crc_en_o (crc_en_wb),
- .shift_crc_o (shift_crc_wb),
- .rst_i (rst_i),
- .wb_clk_i (wb_clk_i),
- .wb_adr_o (wb_adr_o),
- .wb_dat_o (wb_dat_o),
- .wb_dat_i (wb_dat_i),
- .wb_cyc_o (wb_cyc_o),
- .wb_stb_o (wb_stb_o),
- .wb_sel_o (wb_sel_o),
- .wb_we_o (wb_we_o),
- .wb_ack_i (wb_ack_i),
- .wb_cab_o (wb_cab_o),
- .wb_err_i (wb_err_i),
- .wb_cti_o (wb_cti_o),
- .wb_bte_o (wb_bte_o)
- );
-dbg_cpu i_dbg_cpu_or1k (
- .tck_i (tck_i),
- .tdi_i (cpu0_tdi),
- .tdo_o (cpu0_tdo),
- .shift_dr_i (shift_dr_i),
- .pause_dr_i (pause_dr_i),
- .update_dr_i (update_dr_i),
- .cpu_ce_i (cpu0_ce),
- .crc_match_i (crc_match),
- .crc_en_o (cpu0_crc_en),
- .shift_crc_o (cpu0_shift_crc),
- .rst_i (rst_i),
- .cpu_clk_i (cpu0_clk_i),
- .cpu_addr_o (cpu0_addr_o),
- .cpu_data_i (cpu0_data_i),
- .cpu_data_o (cpu0_data_o),
- .cpu_bp_i (cpu0_bp_i),
- .cpu_stall_o (cpu0_stall_o),
- .cpu_stb_o (cpu0_stb_o),
- .cpu_we_o (cpu0_we_o),
- .cpu_ack_i (cpu0_ack_i),
- .cpu_rst_o (cpu0_rst_o)
- );
-endmodule
orpsocv2/rtl/verilog/components/debug_if/dbg_top_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v (nonexistent)
@@ -1,1280 +0,0 @@
-// debug_if_from_mod_synchronization_module.v
-// debug_if_defines.v
-module debug_if_from_mod_synchronization_module
-(
- src_rst_i ,
- src_clr_i ,
- src_clk_i ,
- src_clk_en_i ,
- src_mux_comb_i ,
- src_i ,
- src_o ,
- sff_rst_i ,
- sff_clr_i ,
- sff_clk_i ,
- sff_clk_en_i ,
- sff_o ,
- dst_rst_i ,
- dst_clr_i ,
- dst_clk_i ,
- dst_clk_en_i ,
- dst_o
-) ;
-parameter width = 1 ; // Width parameter of Input and Output signals
-parameter rst_val = 0 ; // Reset value parameter of Flip-Flop Output signals
-input src_rst_i ; // Source reset
-input src_clr_i ; // Source clear
-input src_clk_i ; // Source clock
-input src_clk_en_i ; // Source clock enable for source Flip-Flop
-input src_mux_comb_i ; // Source multiplexer select for combinatorial source input (i.e. from input PAD)
-input [width - 1: 0] src_i ; // Source input
-output [width - 1: 0] src_o ; // Source output - not synchronized
-input sff_rst_i ; // Synchronizer reset (i.e. same as destination reset)
-input sff_clr_i ; // Synchronizer clear
-input sff_clk_i ; // Synchronizer clock (i.e. same as destination clock)
-input sff_clk_en_i ; // Synchronizer clok enable for synchronizer Flip-Flop
-output [width - 1: 0] sff_o ; // Synchronizer output
-input dst_rst_i ; // Destination reset
-input dst_clr_i ; // Destination clear
-input dst_clk_i ; // Destination clock
-input dst_clk_en_i ; // Destination clock enable for destination Flip-Flop
-output [width - 1: 0] dst_o ; // Destination output
-reg [width - 1: 0] src_o ;
-reg [width - 1: 0] sff_o ;
-reg [width - 1: 0] dst_o ;
-reg [width - 1: 0] src ;
-reg [width - 1: 0] sff_i ;
-always @(posedge src_clk_i undefined)
-begin
- if (src_rst_i == undefined)
- src <= rst_val ;
- else if (src_clr_i)
- src <= rst_val ;
- else if (src_clk_en_i)
- src <= src_i ;
-end
-always @(src_i or src or src_mux_comb_i)
-begin
- if (src_mux_comb_i)
- src_o = src_i ;
- else
- src_o = src ;
-end
-always @(src_o)
- sff_i = src_o ;
-always @(posedge sff_clk_i or posedge sff_rst_i)
-begin
- if (sff_rst_i)
- sff_o <= rst_val ;
- else if (sff_clr_i)
- sff_o <= rst_val ;
- else if (sff_clk_en_i)
- sff_o <= sff_i ;
-end
-always @(posedge dst_clk_i or posedge dst_rst_i)
-begin
- if (dst_rst_i)
- dst_o <= rst_val ;
- else if (dst_clr_i)
- dst_o <= rst_val ;
- else if (dst_clk_en_i)
- dst_o <= sff_o ;
-end
-endmodule // debug_if_synchronization_module
-// debug_if_to_mod_synchronization_module.v
-// debug_if_defines.v
-module debug_if_to_mod_synchronization_module
-(
- src_rst_i ,
- src_clr_i ,
- src_clk_i ,
- src_clk_en_i ,
- src_mux_comb_i ,
- src_i ,
- src_o ,
- sff_rst_i ,
- sff_clr_i ,
- sff_clk_i ,
- sff_clk_en_i ,
- sff_o ,
- dst_rst_i ,
- dst_clr_i ,
- dst_clk_i ,
- dst_clk_en_i ,
- dst_o
-) ;
-parameter width = 1 ; // Width parameter of Input and Output signals
-parameter rst_val = 0 ; // Reset value parameter of Flip-Flop Output signals
-input src_rst_i ; // Source reset
-input src_clr_i ; // Source clear
-input src_clk_i ; // Source clock
-input src_clk_en_i ; // Source clock enable for source Flip-Flop
-input src_mux_comb_i ; // Source multiplexer select for combinatorial source input (i.e. from input PAD)
-input [width - 1: 0] src_i ; // Source input
-output [width - 1: 0] src_o ; // Source output - not synchronized
-input sff_rst_i ; // Synchronizer reset (i.e. same as destination reset)
-input sff_clr_i ; // Synchronizer clear
-input sff_clk_i ; // Synchronizer clock (i.e. same as destination clock)
-input sff_clk_en_i ; // Synchronizer clok enable for synchronizer Flip-Flop
-output [width - 1: 0] sff_o ; // Synchronizer output
-input dst_rst_i ; // Destination reset
-input dst_clr_i ; // Destination clear
-input dst_clk_i ; // Destination clock
-input dst_clk_en_i ; // Destination clock enable for destination Flip-Flop
-output [width - 1: 0] dst_o ; // Destination output
-reg [width - 1: 0] src_o ;
-reg [width - 1: 0] sff_o ;
-reg [width - 1: 0] dst_o ;
-reg [width - 1: 0] src ;
-reg [width - 1: 0] sff_i ;
-always @(posedge src_clk_i or posedge src_rst_i)
-begin
- if (src_rst_i)
- src <= rst_val ;
- else if (src_clr_i)
- src <= rst_val ;
- else if (src_clk_en_i)
- src <= src_i ;
-end
-always @(src_i or src or src_mux_comb_i)
-begin
- if (src_mux_comb_i)
- src_o = src_i ;
- else
- src_o = src ;
-end
-always @(src_o)
- sff_i = src_o ;
-always @(posedge sff_clk_i undefined)
-begin
- if (sff_rst_i == undefined)
- sff_o <= rst_val ;
- else if (sff_clr_i)
- sff_o <= rst_val ;
- else if (sff_clk_en_i)
- sff_o <= sff_i ;
-end
-always @(posedge dst_clk_i undefined)
-begin
- if (dst_rst_i == undefined)
- dst_o <= rst_val ;
- else if (dst_clr_i)
- dst_o <= rst_val ;
- else if (dst_clk_en_i)
- dst_o <= sff_o ;
-end
-endmodule // debug_if_synchronization_module
-// debug_if_crc.v
-// debug_if_defines.v
-// synopsys translate_off
-// timescale.v
-`timescale 1ns/10ps
-// synopsys translate_on
-module debug_if_crc
-(
- clk_i , // TAP clock
- rst_i , // TAP reset
- clear_i , // clear CRC register
- enable_i , // enable CRC calculation
- shift_i , // shift CRC register
- data_i , // serial DATA input
- crc_msb_o , // serial CRC output
- crc_ok_o // CRC status
-) ;
-input clk_i ;
-input rst_i ;
-input clear_i ;
-input enable_i ;
-input shift_i ;
-input data_i ;
-output crc_msb_o ;
-output crc_ok_o ;
-reg [ 7: 0] crc_reg ;
-wire [ 7: 0] crc_poly ;
-wire poly_sel ;
-wire crc_reg_msb ;
-wire crc_poly_msb ;
-assign crc_poly = 8'h83 ;
-assign crc_reg_msb = crc_reg [7] ;
-assign crc_poly_msb = crc_poly[7] ;
-assign poly_sel = (data_i) ^^ (crc_poly_msb && crc_reg_msb) ;
-always @(posedge clk_i or posedge rst_i)
- begin
- if (rst_i)
- crc_reg <= 8'h00;
- else if (clear_i)
- crc_reg <= 8'h00;
- else if (enable_i) begin
- crc_reg[7] <= crc_reg[6] ^ (crc_poly[6] & poly_sel) ;
- crc_reg[6] <= crc_reg[5] ^ (crc_poly[5] & poly_sel) ;
- crc_reg[5] <= crc_reg[4] ^ (crc_poly[4] & poly_sel) ;
- crc_reg[4] <= crc_reg[3] ^ (crc_poly[3] & poly_sel) ;
- crc_reg[3] <= crc_reg[2] ^ (crc_poly[2] & poly_sel) ;
- crc_reg[2] <= crc_reg[1] ^ (crc_poly[1] & poly_sel) ;
- crc_reg[1] <= crc_reg[0] ^ (crc_poly[0] & poly_sel) ;
- crc_reg[0] <= poly_sel ;
- end
- else if (shift_i)
- crc_reg[7:0] <= {crc_reg[6:0], 1'b0} ;
- end
-assign crc_ok_o = ~(|crc_reg) ;
-assign crc_msb_o = crc_reg_msb ;
-endmodule
-// debug_if_bus_module.v
-// debug_if_defines.v
-// synopsys translate_off
-// timescale.v
-`timescale 1ns/10ps
-// synopsys translate_on
-module debug_if_bus_module
-(
- tck_pad_i , // JTAG Test ClocK pad
- trst_neg_pad_i , // JTAG Test ReSeT negated pad
- mod_tap_reset_i ,
- mod_clear_i ,
- mod_sync_cmd_i ,
- mod_sync_stat_i ,
- mod_synced_cmd_o ,
- mod_synced_stat_o ,
- mod_command_i ,
- mod_byte_sel_i ,
- mod_address_i ,
- mod_write_data_i ,
- mod_read_data_o ,
- mod_bus_ack_o ,
- mod_bus_rty_o ,
- mod_bus_err_o ,
- wb_clk_i ,
- wb_rst_i ,
- wb_cyc_o ,
- wb_stb_o ,
- wb_we_o ,
- wb_sel_o ,
- wb_adr_o ,
- wb_dat_o ,
- wb_dat_i ,
- wb_ack_i ,
- wb_rty_i ,
- wb_err_i ,
- cpu_bp_i ,
- cpu_stall_o ,
- cpu_rst_o
-) ;
-input tck_pad_i ; // JTAG Test ClocK pad
-input trst_neg_pad_i ; // JTAG Test ReSeT negated pad
-input mod_tap_reset_i ;
-input mod_clear_i ;
-input mod_sync_cmd_i ;
-input mod_sync_stat_i ;
-output mod_synced_cmd_o ;
-output mod_synced_stat_o ;
-input [ 3: 0] mod_command_i ;
-input [ 3: 0] mod_byte_sel_i ;
-input [31: 0] mod_address_i ;
-input [31: 0] mod_write_data_i ;
-output [31: 0] mod_read_data_o ;
-output mod_bus_ack_o ;
-output mod_bus_rty_o ;
-output mod_bus_err_o ;
-input wb_clk_i ;
-input wb_rst_i ;
-output wb_cyc_o ;
-output wb_stb_o ;
-output wb_we_o ;
-output [ 3: 0] wb_sel_o ;
-output [31: 0] wb_adr_o ;
-output [31: 0] wb_dat_o ;
-input [31: 0] wb_dat_i ;
-input wb_ack_i ;
-input wb_rty_i ;
-input wb_err_i ;
-input cpu_bp_i ;
-output cpu_stall_o ;
-output cpu_rst_o ;
-reg wb_cyc_o ;
-reg wb_stb_o ;
-reg wb_we_o ;
-wire [ 3: 0] src_mod_sync ;
-wire [ 3: 0] dst_mod_sync ;
-wire dst_mod_sync_cmd ;
-wire dst_mod_sync_stat ;
-wire wb_mod_clear ;
-wire wb_tap_reset ;
-reg dst_mod_sync_cmd_d1 ;
-reg dst_mod_sync_cmd_d2 ;
-reg dst_mod_sync_stat_d ;
-wire [ 1: 0] src_mod_synced ;
-wire [ 1: 0] dst_mod_synced ;
-wire dst_mod_synced_cmd ;
-wire dst_mod_synced_stat ;
-reg dst_mod_synced_stat_d ;
-wire [71: 0] src_mod_data ;
-wire [71: 0] dst_mod_data ;
-wire dst_mod_data_sync_en ;
-wire [ 3: 0] dst_command ;
-wire [ 3: 0] dst_byte_sel ;
-wire [31: 0] dst_address ;
-wire [31: 0] dst_write_data ;
-wire [34: 0] src_wb_data ;
-wire [34: 0] dst_wb_data ;
-wire dst_wb_data_clk_en ;
-reg mod_clear_d ;
-wire command_valid ;
-reg status_ready ;
-reg src_wb_ack ;
-reg src_wb_rty ;
-reg src_wb_err ;
-reg cpu_stall_reg ;
-reg cpu_reset_reg ;
-reg [31: 0] src_wb_rdat ;
-assign src_mod_sync[3:0] = {mod_tap_reset_i, mod_clear_i, mod_sync_stat_i, mod_sync_cmd_i} ;
-debug_if_to_mod_synchronization_module #(4, 8) i_debug_if_to_mod_synchronization_module // #(width, reset) value
-(
- .src_rst_i ( trst_neg_pad_i ),
- .src_clr_i ( mod_tap_reset_i ),
- .src_clk_i ( tck_pad_i ),
- .src_clk_en_i ( 1'b1 ),
- .src_mux_comb_i ( 1'b0 ),
- .src_i ( src_mod_sync ),
- .src_o ( ),
- .sff_rst_i ( wb_rst_i ),
- .sff_clr_i ( 1'b0 ),
- .sff_clk_i ( wb_clk_i ),
- .sff_clk_en_i ( 1'b1 ),
- .sff_o ( ),
- .dst_rst_i ( wb_rst_i ),
- .dst_clr_i ( 1'b0 ),
- .dst_clk_i ( wb_clk_i ),
- .dst_clk_en_i ( 1'b1 ),
- .dst_o ( dst_mod_sync )
-) ;
-assign dst_mod_sync_cmd = dst_mod_sync[0] ;
-assign dst_mod_sync_stat = dst_mod_sync[1] ;
-assign wb_mod_clear = dst_mod_sync[2] ;
-assign wb_tap_reset = dst_mod_sync[3] ;
-always @(posedge wb_clk_i undefined)
- begin
- if (wb_rst_i == undefined) begin
- dst_mod_sync_cmd_d1 <= 1'b0 ;
- dst_mod_sync_cmd_d2 <= 1'b0 ;
- dst_mod_sync_stat_d <= 1'b0 ;
- end
- else begin
- dst_mod_sync_cmd_d1 <= dst_mod_sync_cmd ;
- dst_mod_sync_cmd_d2 <= dst_mod_sync_cmd_d1 ;
- if (dst_mod_sync_stat && !dst_mod_sync_stat_d && status_ready)
- dst_mod_sync_stat_d <= 1'b1 ;
- else if (!dst_mod_sync_stat)
- dst_mod_sync_stat_d <= 1'b0 ;
- end
- end
-assign src_mod_synced[1:0] = {dst_mod_sync_stat_d, dst_mod_sync_cmd_d1} ;
-debug_if_from_mod_synchronization_module #(2, 0) i_debug_if_from_mod_synchronization_module // #(width, reset) value
-(
- .src_rst_i ( wb_rst_i ),
- .src_clr_i ( 1'b0 ),
- .src_clk_i ( wb_clk_i ),
- .src_clk_en_i ( 1'b1 ),
- .src_mux_comb_i ( 1'b0 ),
- .src_i ( src_mod_synced ),
- .src_o ( ),
- .sff_rst_i ( trst_neg_pad_i ),
- .sff_clr_i ( mod_tap_reset_i ),
- .sff_clk_i ( tck_pad_i ),
- .sff_clk_en_i ( 1'b1 ),
- .sff_o ( ),
- .dst_rst_i ( trst_neg_pad_i ),
- .dst_clr_i ( mod_tap_reset_i ),
- .dst_clk_i ( tck_pad_i ),
- .dst_clk_en_i ( 1'b1 ),
- .dst_o ( dst_mod_synced )
-) ;
-assign dst_mod_synced_cmd = dst_mod_synced[0] ;
-assign dst_mod_synced_stat = dst_mod_synced[1] ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- dst_mod_synced_stat_d <= 1'b0 ;
- else if (mod_tap_reset_i)
- dst_mod_synced_stat_d <= 1'b0 ;
- else
- dst_mod_synced_stat_d <= dst_mod_synced_stat ;
- end
-assign mod_synced_cmd_o = dst_mod_synced_cmd ;
-assign mod_synced_stat_o = dst_mod_synced_stat_d ;
-assign src_mod_data[71:0] = {mod_command_i[3:0], mod_byte_sel_i[3:0],
- mod_address_i[31:0], mod_write_data_i[31:0]} ;
-assign dst_mod_data_sync_en = dst_mod_sync_cmd && !dst_mod_sync_cmd_d1 ;
-debug_if_to_mod_synchronization_module #(72, 0) i1_debug_if_to_mod_synchronization_module // #(width, reset) value
-(
- .src_rst_i ( 1'b1 ),
- .src_clr_i ( 1'b1 ),
- .src_clk_i ( 1'b1 ),
- .src_clk_en_i ( 1'b1 ),
- .src_mux_comb_i ( 1'b1 ),
- .src_i ( src_mod_data ),
- .src_o ( ),
- .sff_rst_i ( wb_rst_i ),
- .sff_clr_i ( 1'b0 ),
- .sff_clk_i ( wb_clk_i ),
- .sff_clk_en_i ( dst_mod_data_sync_en ),
- .sff_o ( dst_mod_data ),
- .dst_rst_i ( undefined ),
- .dst_clr_i ( 1'b1 ),
- .dst_clk_i ( 1'b1 ),
- .dst_clk_en_i ( 1'b1 ),
- .dst_o ( )
-) ;
-assign dst_command [ 3:0] = dst_mod_data[71:68] ;
-assign dst_byte_sel [ 3:0] = dst_mod_data[67:64] ;
-assign dst_address [31:0] = dst_mod_data[63:32] ;
-assign dst_write_data[31:0] = dst_mod_data[31: 0] ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- mod_clear_d <= 1'b1 ;
- else if (mod_tap_reset_i)
- mod_clear_d <= 1'b1 ;
- else
- mod_clear_d <= mod_clear_i ;
- end
-assign src_wb_data[ 2:0] = mod_clear_i ? 3'h0 : {src_wb_ack, src_wb_rty, src_wb_err} ;
-assign src_wb_data[34:3] = src_wb_rdat[31:0] ;
-assign dst_wb_data_clk_en = (dst_mod_synced_stat && !dst_mod_synced_stat_d) ||
- (mod_clear_i && !mod_clear_d) ;
-debug_if_from_mod_synchronization_module #(35, 0) i1_debug_if_from_mod_synchronization_module // #(width, reset) value
-(
- .src_rst_i ( undefined ),
- .src_clr_i ( 1'b1 ),
- .src_clk_i ( 1'b1 ),
- .src_clk_en_i ( 1'b1 ),
- .src_mux_comb_i ( 1'b1 ),
- .src_i ( src_wb_data ),
- .src_o ( ),
- .sff_rst_i ( trst_neg_pad_i ),
- .sff_clr_i ( mod_tap_reset_i ),
- .sff_clk_i ( tck_pad_i ),
- .sff_clk_en_i ( dst_wb_data_clk_en ),
- .sff_o ( dst_wb_data ),
- .dst_rst_i ( 1'b1 ),
- .dst_clr_i ( 1'b1 ),
- .dst_clk_i ( 1'b1 ),
- .dst_clk_en_i ( 1'b1 ),
- .dst_o ( )
-) ;
-assign mod_read_data_o = dst_wb_data[34:3] ;
-assign mod_bus_ack_o = dst_wb_data[2] ;
-assign mod_bus_rty_o = dst_wb_data[1] ;
-assign mod_bus_err_o = dst_wb_data[0] ;
-assign command_valid = dst_mod_sync_cmd_d1 && !dst_mod_sync_cmd_d2 ;
-always @(posedge wb_clk_i undefined)
- begin
- if (wb_rst_i == undefined)
- status_ready <= 1'b0 ;
- else if (wb_tap_reset)
- status_ready <= 1'b0 ;
- else begin
- if (command_valid)
- status_ready <= 1'b0 ;
- else if ( (dst_command[3:0] == 4'd04) ||
- (dst_command[3:0] == 4'd05) ||
- (dst_command[3:0] == 4'd06) ||
- (((dst_command[3:0] == 4'd02) ||
- (dst_command[3:0] == 4'd03)) &&
- (wb_stb_o && (wb_ack_i || wb_rty_i || wb_err_i))) )
- status_ready <= 1'b1 ;
- end
- end
-assign wb_sel_o = dst_byte_sel [ 3:0] ;
-assign wb_adr_o = dst_address [31:0] ;
-assign wb_dat_o = dst_write_data[31:0] ;
-always @(posedge wb_clk_i undefined)
- begin
- if (wb_rst_i == undefined) begin
- wb_cyc_o <= 1'b0 ;
- wb_stb_o <= 1'b0 ;
- wb_we_o <= 1'b0 ;
- end
- else if (wb_tap_reset) begin
- wb_cyc_o <= 1'b0 ;
- wb_stb_o <= 1'b0 ;
- wb_we_o <= 1'b0 ;
- end
- else begin
- if (wb_ack_i || wb_rty_i || wb_err_i ||
- (command_valid &&
- (dst_command[3:0] == 4'd04))) begin
- wb_cyc_o <= 1'b0 ;
- wb_stb_o <= 1'b0 ;
- end
- else if (command_valid &&
- ((dst_command[3:0] == 4'd02) ||
- (dst_command[3:0] == 4'd03))) begin
- wb_cyc_o <= 1'b1 ;
- wb_stb_o <= 1'b1 ;
- end
- if (command_valid && (dst_command[3:0] == 4'd02))
- wb_we_o <= 1'b1 ;
- else if (command_valid && (dst_command[3:0] == 4'd03))
- wb_we_o <= 1'b0 ;
- end
- end
-always @(posedge wb_clk_i undefined)
- begin
- if (wb_rst_i == undefined) begin
- src_wb_ack <= 1'b0 ;
- src_wb_rty <= 1'b0 ;
- src_wb_err <= 1'b0 ;
- end
- else if (wb_tap_reset) begin
- src_wb_ack <= 1'b0 ;
- src_wb_rty <= 1'b0 ;
- src_wb_err <= 1'b0 ;
- end
- else if (wb_stb_o && (wb_ack_i || wb_rty_i || wb_err_i)) begin
- src_wb_ack <= wb_ack_i ;
- src_wb_rty <= wb_rty_i ;
- src_wb_err <= wb_err_i ;
- end
- else if (command_valid) begin
- src_wb_ack <= 1'b0 ;
- src_wb_rty <= 1'b0 ;
- src_wb_err <= 1'b0 ;
- end
- else if (wb_mod_clear) begin
- src_wb_ack <= 1'b0 ;
- src_wb_rty <= 1'b0 ;
- src_wb_err <= 1'b0 ;
- end
- end
-always @(posedge wb_clk_i undefined)
- begin
- if (wb_rst_i == undefined) begin
- cpu_stall_reg <= 1'b0 ;
- cpu_reset_reg <= 1'b0 ;
- end
- else if (wb_tap_reset) begin
- cpu_stall_reg <= 1'b0 ;
- cpu_reset_reg <= 1'b0 ;
- end
- else begin
- if (cpu_bp_i)
- cpu_stall_reg <= 1'b1 ;
- else if (command_valid && (dst_command[3:0] == 4'd05))
- cpu_stall_reg <= dst_write_data[0] ;
- if (command_valid && (dst_command[3:0] == 4'd05))
- cpu_reset_reg <= dst_write_data[1] ;
- end
- end
-assign cpu_stall_o = cpu_stall_reg || cpu_bp_i ;
-assign cpu_rst_o = cpu_reset_reg ;
-always @(posedge wb_clk_i/* undefined*/)
- begin
- if (wb_rst_i == undefined)
- src_wb_rdat[31:0] <= 32'h0 ;
- else if (wb_tap_reset)
- src_wb_rdat[31:0] <= 32'h0 ;
- else begin
- if (wb_stb_o && wb_ack_i && (dst_command[3:0] == 4'd03))
- src_wb_rdat[31:0] <= wb_dat_i ;
- else if (command_valid && (dst_command[3:0] == 4'd06))
- src_wb_rdat[31:0] <= 32'h0 | (cpu_reset_reg << 1) |
- (cpu_stall_reg << 0) ;
- end
- end
-endmodule
-// debug_if.v
-// debug_if_defines.v
-// synopsys translate_off
-// timescale.v
-`timescale 1ns/10ps
-// synopsys translate_on
-module debug_if
-(
- tck_pad_i , // JTAG Test ClocK pad
- trst_neg_pad_i , // JTAG Test ReSeT negated pad
- tdi_i , // TAP TDO signal
- tdo_o , // DEBUG TDO signal
- debug_select_i ,
- capture_dr_i ,
- shift_dr_i ,
- pause_dr_i ,
- update_dr_i ,
- mod_wb_clk_i ,
- mod_wb_rst_i ,
- mod_wb_cyc_o ,
- mod_wb_stb_o ,
- mod_wb_we_o ,
- mod_wb_sel_o ,
- mod_wb_adr_o ,
- mod_wb_dat_o ,
- mod_wb_dat_i ,
- mod_wb_ack_i ,
- mod_wb_rty_i ,
- mod_wb_err_i ,
- mod_cpu_bp_i ,
- mod_cpu_stall_o ,
- mod_cpu_rst_o
-) ;
-input tck_pad_i ; // JTAG Test ClocK pad
-input trst_neg_pad_i ; // JTAG Test ReSeT negated pad
-input tdi_i ; // TAP TDO signal
-output tdo_o ; // DEBUG TDO signal
-input debug_select_i ;
-input capture_dr_i ;
-input shift_dr_i ;
-input pause_dr_i ;
-input update_dr_i ;
-input [ (4'd1+1)-1: 0] mod_wb_clk_i ;
-input [ (4'd1+1)-1: 0] mod_wb_rst_i ;
-output [ (4'd1+1)-1: 0] mod_wb_cyc_o ;
-output [ (4'd1+1)-1: 0] mod_wb_stb_o ;
-output [ (4'd1+1)-1: 0] mod_wb_we_o ;
-output [ 4*(4'd1+1)-1: 0] mod_wb_sel_o ;
-output [32*(4'd1+1)-1: 0] mod_wb_adr_o ;
-output [32*(4'd1+1)-1: 0] mod_wb_dat_o ;
-input [32*(4'd1+1)-1: 0] mod_wb_dat_i ;
-input [ (4'd1+1)-1: 0] mod_wb_ack_i ;
-input [ (4'd1+1)-1: 0] mod_wb_rty_i ;
-input [ (4'd1+1)-1: 0] mod_wb_err_i ;
-input [ (4'd1+1)-1: 0] mod_cpu_bp_i ;
-output [ (4'd1+1)-1: 0] mod_cpu_stall_o ;
-output [ (4'd1+1)-1: 0] mod_cpu_rst_o ;
-reg tdo_o ;
-reg [ 6: 0] shift_cnt ;
-reg [79: 0] shift_reg ;
-wire latch_module_valid ;
-wire latch_cancel_valid ;
-wire latch_reg_valid ;
-reg [15: 0] cs_module ;
-reg [ 3: 0] cs_modnum ;
-reg [ 3: 0] command ;
-reg [ 3: 0] byte_sel ;
-reg [31: 0] address ;
-reg [31: 0] write_data ;
-reg [31: 0] read_data ;
-wire bus_ack ;
-wire bus_rty ;
-wire bus_err ;
-wire [ 7: 0] impl_ver ;
-wire [ 7: 0] debug_ver ;
-wire [23: 0] status ;
-reg stat_crc_err ;
-reg stat_overrun ;
-reg stat_wrong_mod ;
-reg stat_bus_err ;
-reg stat_bus_rty ;
-reg stat_bus_ack ;
-wire stat_hw_busy ;
-wire stat_hw_sync ;
-reg stat_hw_busy_reg ;
-reg stat_hw_sync_reg ;
-reg stat_wrong_cmd ;
-wire crc_out_clear ;
-wire crc_out_enable ;
-wire crc_out_shift ;
-wire crc_in_clear ;
-wire crc_in_enable ;
-wire crc_in_shift ;
-wire crc_out_msb ;
-wire crc_in_ok ;
-reg crc_in_ok_reg ;
-reg [2:0] cur_state ;
-reg [2:0] nxt_state ;
-reg tap_reset ;
-reg sync_cmd ;
-reg sync_stat ;
-wire synced_cmd ;
-wire synced_stat ;
-reg synced_stat_d ;
-wire mod_tap_reset ;
-wire [15: 0] mod_clear ;
-wire [15: 0] mod_sync_cmd ;
-wire [15: 0] mod_sync_stat ;
-wire [15: 0] mod_synced_cmd ;
-wire [15: 0] mod_synced_stat ;
-wire [511: 0] mod_read_data ;
-wire [15: 0] mod_bus_ack ;
-wire [15: 0] mod_bus_rty ;
-wire [15: 0] mod_bus_err ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- shift_cnt <= 7'd0 ;
- else if (!debug_select_i)
- shift_cnt <= 7'd0 ;
- else begin
- if (capture_dr_i)
- shift_cnt <= 7'd0 ;
- else if (shift_dr_i && (shift_cnt < 7'd82))
- shift_cnt <= shift_cnt + 1'b1 ;
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- shift_reg[79:0] <= 80'h0 ;
- else if (!debug_select_i)
- shift_reg[79:0] <= 80'h0 ;
- else begin
- if (capture_dr_i) begin
- shift_reg[79:72] <= 8'h0 ;
- shift_reg[71:40] <= read_data[31:0] ;
- shift_reg[39:16] <= status [23:0] ;
- shift_reg[15: 8] <= impl_ver [ 7:0] ;
- shift_reg[ 7: 0] <= debug_ver[ 7:0] ;
- end
- else if (shift_dr_i)
- shift_reg[79:0] <= {tdi_i, shift_reg[79:1]} ;
- end
- end
-always @(shift_cnt or shift_reg or crc_out_msb)
- begin
- if ((shift_cnt >= 7'd72) && (shift_cnt < 7'd80))
- tdo_o = crc_out_msb ;
- else
- tdo_o = shift_reg[0] ;
- end
-assign latch_module_valid = crc_in_ok_reg &&
- (shift_reg[3:0] == 4'd01) && !stat_hw_busy_reg &&
- (shift_reg[43:40] <= 4'd1) ;
-assign latch_cancel_valid = crc_in_ok_reg &&
- (shift_reg[3:0] == 4'd04) && !stat_hw_sync_reg ;
-assign latch_reg_valid = crc_in_ok_reg &&
- (((shift_reg[3:0] == 4'd02 ) && !stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd03 ) && !stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd05) && !stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd06 ) && !stat_hw_busy_reg)) ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i) begin
- cs_module[15:0] <= 16'h1 ;
- cs_modnum <= 4'd0 ;
- end
- else if (!debug_select_i) begin
- cs_module[15:0] <= 16'h1 ;
- cs_modnum <= 4'd0 ;
- end
- else if (update_dr_i && latch_module_valid) begin
- case (shift_reg[43:40])
- 4'd15 : cs_module[15:0] <= 16'h8000 ;
- 4'd14 : cs_module[15:0] <= 16'h4000 ;
- 4'd13 : cs_module[15:0] <= 16'h2000 ;
- 4'd12 : cs_module[15:0] <= 16'h1000 ;
- 4'd11 : cs_module[15:0] <= 16'h0800 ;
- 4'd10 : cs_module[15:0] <= 16'h0400 ;
- 4'd09 : cs_module[15:0] <= 16'h0200 ;
- 4'd08 : cs_module[15:0] <= 16'h0100 ;
- 4'd07 : cs_module[15:0] <= 16'h0080 ;
- 4'd06 : cs_module[15:0] <= 16'h0040 ;
- 4'd05 : cs_module[15:0] <= 16'h0020 ;
- 4'd04 : cs_module[15:0] <= 16'h0010 ;
- 4'd03 : cs_module[15:0] <= 16'h0008 ;
- 4'd02 : cs_module[15:0] <= 16'h0004 ;
- 4'd01 : cs_module[15:0] <= 16'h0002 ;
- 4'd00 : cs_module[15:0] <= 16'h0001 ;
- default : cs_module[15:0] <= 16'hxxxx ;
- endcase
- case (shift_reg[43:40])
- 4'd15 : cs_modnum <= 4'd15 ;
- 4'd14 : cs_modnum <= 4'd14 ;
- 4'd13 : cs_modnum <= 4'd13 ;
- 4'd12 : cs_modnum <= 4'd12 ;
- 4'd11 : cs_modnum <= 4'd11 ;
- 4'd10 : cs_modnum <= 4'd10 ;
- 4'd09 : cs_modnum <= 4'd9 ;
- 4'd08 : cs_modnum <= 4'd8 ;
- 4'd07 : cs_modnum <= 4'd7 ;
- 4'd06 : cs_modnum <= 4'd6 ;
- 4'd05 : cs_modnum <= 4'd5 ;
- 4'd04 : cs_modnum <= 4'd4 ;
- 4'd03 : cs_modnum <= 4'd3 ;
- 4'd02 : cs_modnum <= 4'd2 ;
- 4'd01 : cs_modnum <= 4'd1 ;
- 4'd00 : cs_modnum <= 4'd0 ;
- default : cs_modnum <= 4'hx ;
- endcase
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- command[3:0] <= 4'd04 ;
- else if (!debug_select_i)
- command[3:0] <= 4'd04 ;
- else if (update_dr_i && (latch_reg_valid || latch_cancel_valid))
- command[3:0] <= shift_reg[3:0] ;
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- byte_sel[3:0] <= 4'h0 ;
- else if (!debug_select_i)
- byte_sel[3:0] <= 4'h0 ;
- else if (debug_select_i && update_dr_i && latch_reg_valid)
- byte_sel[3:0] <= shift_reg[7:4] ;
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- address[31:0] <= 32'h0 ;
- else if (!debug_select_i)
- address[31:0] <= 32'h0 ;
- else if (debug_select_i && update_dr_i && latch_reg_valid)
- address[31:0] <= shift_reg[39:8] ;
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- write_data[31:0] <= 32'h0 ;
- else if (!debug_select_i)
- write_data[31:0] <= 32'h0 ;
- else if (debug_select_i && update_dr_i && latch_reg_valid)
- write_data[31:0] <= shift_reg[71:40] ;
- end
-assign impl_ver[7:0] = 8'h00 ;
-assign debug_ver[7:0] = 8'h03 ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- stat_crc_err <= 1'b0 ;
- else if (!debug_select_i)
- stat_crc_err <= 1'b0 ;
- else begin
- if (update_dr_i && crc_in_ok_reg)
- stat_crc_err <= 1'b0 ;
- else if (update_dr_i)
- stat_crc_err <= 1'b1 ;
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- stat_overrun <= 1'b0 ;
- else if (!debug_select_i)
- stat_overrun <= 1'b0 ;
- else begin
- if (update_dr_i &&
- (((shift_reg[3:0] == 4'd02 ) && stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd03 ) && stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd05) && stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd06 ) && stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd01 ) && stat_hw_busy_reg) ||
- ((shift_reg[3:0] == 4'd04) && stat_hw_sync_reg)))
- stat_overrun <= 1'b1 ;
- else if (update_dr_i)
- stat_overrun <= 1'b0 ;
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- stat_wrong_mod <= 1'b0 ;
- else if (!debug_select_i)
- stat_wrong_mod <= 1'b0 ;
- else begin
- if (update_dr_i &&
- (shift_reg[3:0] == 4'd01) &&
- (shift_reg[43:40] > 4'd1))
- stat_wrong_mod <= 1'b1 ;
- else if (update_dr_i)
- stat_wrong_mod <= 1'b0 ;
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i) begin
- stat_bus_ack <= 1'b0 ;
- stat_bus_rty <= 1'b0 ;
- stat_bus_err <= 1'b0 ;
- end
- else if (!debug_select_i) begin
- stat_bus_ack <= 1'b0 ;
- stat_bus_rty <= 1'b0 ;
- stat_bus_err <= 1'b0 ;
- end
- else begin
- if (update_dr_i && !stat_hw_busy_reg) begin
- stat_bus_ack <= 1'b0 ;
- stat_bus_rty <= 1'b0 ;
- stat_bus_err <= 1'b0 ;
- end
- else if (synced_stat && !synced_stat_d) begin
- stat_bus_ack <= bus_ack ;
- stat_bus_rty <= bus_rty ;
- stat_bus_err <= bus_err ;
- end
- end
- end
-assign stat_hw_busy = sync_cmd || synced_cmd || sync_stat || synced_stat ;
-assign stat_hw_sync = sync_cmd || synced_cmd ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i) begin
- stat_hw_busy_reg <= 1'b0 ;
- stat_hw_sync_reg <= 1'b0 ;
- end
- else if (!debug_select_i) begin
- stat_hw_busy_reg <= 1'b0 ;
- stat_hw_sync_reg <= 1'b0 ;
- end
- else begin
- if (capture_dr_i) begin
- stat_hw_busy_reg <= stat_hw_busy ;
- stat_hw_sync_reg <= stat_hw_sync ;
- end
- end
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- stat_wrong_cmd <= 1'b0 ;
- else if (!debug_select_i)
- stat_wrong_cmd <= 1'b0 ;
- else begin
- if (update_dr_i &&
- ((shift_reg[3:0] == 4'd00 ) ||
- (shift_reg[3:0] == 4'd02 ) ||
- (shift_reg[3:0] == 4'd03 ) ||
- (shift_reg[3:0] == 4'd05) ||
- (shift_reg[3:0] == 4'd06 ) ||
- (shift_reg[3:0] == 4'd01 ) ||
- (shift_reg[3:0] == 4'd04)))
- stat_wrong_cmd <= 1'b0 ;
- else if (update_dr_i)
- stat_wrong_cmd <= 1'b1 ;
- end
- end
-assign status[0] = stat_crc_err ;
-assign status[1] = stat_overrun ;
-assign status[2] = stat_wrong_mod ;
-assign status[3] = stat_bus_err ;
-assign status[4] = stat_bus_rty ;
-assign status[5] = stat_bus_ack ;
-assign status[6] = stat_hw_busy ;
-assign status[7] = stat_wrong_cmd ;
-assign status[23:8] = 'h0 ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- synced_stat_d <= 1'b0 ;
- else if (!debug_select_i)
- synced_stat_d <= 1'b0 ;
- else
- synced_stat_d <= synced_stat ;
- end
-assign crc_out_clear = capture_dr_i ;
-assign crc_out_enable = debug_select_i && shift_dr_i && (shift_cnt < 7'd72) ;
-assign crc_out_shift = debug_select_i && shift_dr_i && (shift_cnt >= 7'd72) ;
-assign crc_in_clear = capture_dr_i ;
-assign crc_in_enable = debug_select_i && shift_dr_i ;
-assign crc_in_shift = 1'b0 ;
-debug_if_crc i_debug_if_crc_out
-(
- .clk_i ( tck_pad_i ), // TAP clock
- .rst_i ( trst_neg_pad_i ), // TAP reset
- .clear_i ( crc_out_clear ), // clear CRC register
- .enable_i ( crc_out_enable ), // enable CRC calculation
- .shift_i ( crc_out_shift ), // shift CRC register
- .data_i ( shift_reg[0] ), // serial DATA input
- .crc_msb_o ( crc_out_msb ), // serial CRC output
- .crc_ok_o ( ) // CRC status
-) ;
-debug_if_crc i_debug_if_crc_in
-(
- .clk_i ( tck_pad_i ), // TAP clock
- .rst_i ( trst_neg_pad_i ), // TAP reset
- .clear_i ( crc_in_clear ), // clear CRC register
- .enable_i ( crc_in_enable ), // enable CRC calculation
- .shift_i ( crc_in_shift ), // shift CRC register
- .data_i ( tdi_i ), // serial DATA input
- .crc_msb_o ( ), // serial CRC output
- .crc_ok_o ( crc_in_ok ) // CRC status
-) ;
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- crc_in_ok_reg <= 1'b1 ;
- else if (!debug_select_i)
- crc_in_ok_reg <= 1'b1 ;
- else
- crc_in_ok_reg <= crc_in_ok ;
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- cur_state <= 3'h0 ;
- else if (!debug_select_i)
- cur_state <= 3'h0 ;
- else
- cur_state <= nxt_state ;
- end
-always @(cur_state or synced_cmd or synced_stat or
- update_dr_i or latch_reg_valid or latch_cancel_valid)
- begin
- case (cur_state)
- 3'h4 :
- begin
- if (synced_cmd) begin
- nxt_state = 3'h1 ;
- sync_cmd = 1'b0 ;
- end
- else begin
- nxt_state = 3'h4 ;
- sync_cmd = 1'b1 ;
- end
- sync_stat = 1'b0 ;
- end
- 3'h1 :
- begin
- if (!synced_cmd) begin
- nxt_state = 3'h2 ;
- sync_stat = 1'b1 ;
- end
- else begin
- nxt_state = 3'h1 ;
- sync_stat = 1'b0 ;
- end
- sync_cmd = 1'b0 ;
- end
- 3'h2 :
- begin
- if (synced_stat) begin
- nxt_state = 3'h3 ;
- sync_cmd = 1'b0 ;
- sync_stat = 1'b0 ;
- end
- else if (update_dr_i && latch_cancel_valid) begin
- nxt_state = 3'h4 ;
- sync_cmd = 1'b1 ;
- sync_stat = 1'b0 ;
- end
- else begin
- nxt_state = 3'h2 ;
- sync_cmd = 1'b0 ;
- sync_stat = 1'b1 ;
- end
- end
- 3'h3 :
- begin
- if (!synced_stat) begin
- nxt_state = 3'h0 ;
- sync_cmd = 1'b0 ;
- end
- else if (update_dr_i && latch_cancel_valid) begin
- nxt_state = 3'h4 ;
- sync_cmd = 1'b1 ;
- end
- else begin
- nxt_state = 3'h3 ;
- sync_cmd = 1'b0 ;
- end
- sync_stat = 1'b0 ;
- end
- default : // 3'h0
- begin
- if (update_dr_i && (latch_reg_valid || latch_cancel_valid)) begin
- nxt_state = 3'h4 ;
- sync_cmd = 1'b1 ;
- end
- else begin
- nxt_state = 3'h0 ;
- sync_cmd = 1'b0 ;
- end
- sync_stat = 1'b0 ;
- end
- endcase
- end
-always @(posedge tck_pad_i or posedge trst_neg_pad_i)
- begin
- if (trst_neg_pad_i)
- tap_reset <= 1'b1 ;
- else if (!debug_select_i)
- tap_reset <= 1'b1 ;
- else
- tap_reset <= 1'b0 ;
- end
-assign mod_tap_reset = tap_reset ;
-assign mod_clear [15:0] = ~cs_module[15:0] ;
-assign mod_sync_cmd [15:0] = {16{sync_cmd}} & cs_module[15:0] ;
-assign mod_sync_stat[15:0] = {16{sync_stat}} & cs_module[15:0] ;
-assign synced_cmd = |mod_synced_cmd [15:0] ;
-assign synced_stat = |mod_synced_stat[15:0] ;
-always @(cs_modnum or mod_read_data)
- begin
- case (cs_modnum[3:0])
- 4'd15 : read_data = mod_read_data[32] ;
- 4'd14 : read_data = mod_read_data[32] ;
- 4'd13 : read_data = mod_read_data[32] ;
- 4'd12 : read_data = mod_read_data[32] ;
- 4'd11 : read_data = mod_read_data[32] ;
- 4'd10 : read_data = mod_read_data[32] ;
- 4'd09 : read_data = mod_read_data[32] ;
- 4'd08 : read_data = mod_read_data[32] ;
- 4'd07 : read_data = mod_read_data[32] ;
- 4'd06 : read_data = mod_read_data[32] ;
- 4'd05 : read_data = mod_read_data[32] ;
- 4'd04 : read_data = mod_read_data[32] ;
- 4'd03 : read_data = mod_read_data[32] ;
- 4'd02 : read_data = mod_read_data[32] ;
- 4'd01 : read_data = mod_read_data[32] ;
- 4'd00 : read_data = mod_read_data[32] ;
- default : read_data = 32'hxxxx_xxxx ;
- endcase
- end
-assign bus_ack = |mod_bus_ack[15:0] ;
-assign bus_rty = |mod_bus_rty[15:0] ;
-assign bus_err = |mod_bus_err[15:0] ;
-debug_if_bus_module i0_debug_if_bus_module
-(
- .tck_pad_i ( tck_pad_i ),
- .trst_neg_pad_i ( trst_neg_pad_i ),
- .mod_tap_reset_i ( mod_tap_reset ),
- .mod_clear_i ( mod_clear [4'd00] ),
- .mod_sync_cmd_i ( mod_sync_cmd [4'd00] ),
- .mod_sync_stat_i ( mod_sync_stat [4'd00] ),
- .mod_synced_cmd_o ( mod_synced_cmd [4'd00] ),
- .mod_synced_stat_o ( mod_synced_stat[4'd00] ),
- .mod_command_i ( command [ 3:0] ),
- .mod_byte_sel_i ( byte_sel [ 3:0] ),
- .mod_address_i ( address [31:0] ),
- .mod_write_data_i ( write_data [31:0] ),
- .mod_read_data_o ( mod_read_data [32] ),
- .mod_bus_ack_o ( mod_bus_ack [4'd00] ),
- .mod_bus_rty_o ( mod_bus_rty [4'd00] ),
- .mod_bus_err_o ( mod_bus_err [4'd00] ),
- .wb_clk_i ( mod_wb_clk_i [4'd00] ),
- .wb_rst_i ( mod_wb_rst_i [4'd00] ),
- .wb_cyc_o ( mod_wb_cyc_o [4'd00] ),
- .wb_stb_o ( mod_wb_stb_o [4'd00] ),
- .wb_we_o ( mod_wb_we_o [4'd00] ),
- .wb_sel_o ( mod_wb_sel_o [4] ),
- .wb_adr_o ( mod_wb_adr_o [32] ),
- .wb_dat_o ( mod_wb_dat_o [32] ),
- .wb_dat_i ( mod_wb_dat_i [32] ),
- .wb_ack_i ( mod_wb_ack_i [4'd00] ),
- .wb_rty_i ( mod_wb_rty_i [4'd00] ),
- .wb_err_i ( mod_wb_err_i [4'd00] ),
- .cpu_bp_i ( mod_cpu_bp_i [4'd00] ),
- .cpu_stall_o ( mod_cpu_stall_o[4'd00] ),
- .cpu_rst_o ( mod_cpu_rst_o [4'd00] )
-) ;
-debug_if_bus_module i1_debug_if_bus_module
-(
- .tck_pad_i ( tck_pad_i ),
- .trst_neg_pad_i ( trst_neg_pad_i ),
- .mod_tap_reset_i ( mod_tap_reset ),
- .mod_clear_i ( mod_clear [4'd01] ),
- .mod_sync_cmd_i ( mod_sync_cmd [4'd01] ),
- .mod_sync_stat_i ( mod_sync_stat [4'd01] ),
- .mod_synced_cmd_o ( mod_synced_cmd [4'd01] ),
- .mod_synced_stat_o ( mod_synced_stat[4'd01] ),
- .mod_command_i ( command [ 3:0] ),
- .mod_byte_sel_i ( byte_sel [ 3:0] ),
- .mod_address_i ( address [31:0] ),
- .mod_write_data_i ( write_data [31:0] ),
- .mod_read_data_o ( mod_read_data [32] ),
- .mod_bus_ack_o ( mod_bus_ack [4'd01] ),
- .mod_bus_rty_o ( mod_bus_rty [4'd01] ),
- .mod_bus_err_o ( mod_bus_err [4'd01] ),
- .wb_clk_i ( mod_wb_clk_i [4'd01] ),
- .wb_rst_i ( mod_wb_rst_i [4'd01] ),
- .wb_cyc_o ( mod_wb_cyc_o [4'd01] ),
- .wb_stb_o ( mod_wb_stb_o [4'd01] ),
- .wb_we_o ( mod_wb_we_o [4'd01] ),
- .wb_sel_o ( mod_wb_sel_o [4] ),
- .wb_adr_o ( mod_wb_adr_o [32] ),
- .wb_dat_o ( mod_wb_dat_o [32] ),
- .wb_dat_i ( mod_wb_dat_i [32] ),
- .wb_ack_i ( mod_wb_ack_i [4'd01] ),
- .wb_rty_i ( mod_wb_rty_i [4'd01] ),
- .wb_err_i ( mod_wb_err_i [4'd01] ),
- .cpu_bp_i ( mod_cpu_bp_i [4'd01] ),
- .cpu_stall_o ( mod_cpu_stall_o[4'd01] ),
- .cpu_rst_o ( mod_cpu_rst_o [4'd01] )
-) ;
- assign mod_synced_cmd [4'd02] = 1'b0 ;
- assign mod_synced_stat[4'd02] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd02] = 1'b0 ;
- assign mod_bus_rty [4'd02] = 1'b0 ;
- assign mod_bus_err [4'd02] = 1'b0 ;
- assign mod_synced_cmd [4'd03] = 1'b0 ;
- assign mod_synced_stat[4'd03] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd03] = 1'b0 ;
- assign mod_bus_rty [4'd03] = 1'b0 ;
- assign mod_bus_err [4'd03] = 1'b0 ;
- assign mod_synced_cmd [4'd04] = 1'b0 ;
- assign mod_synced_stat[4'd04] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd04] = 1'b0 ;
- assign mod_bus_rty [4'd04] = 1'b0 ;
- assign mod_bus_err [4'd04] = 1'b0 ;
- assign mod_synced_cmd [4'd05] = 1'b0 ;
- assign mod_synced_stat[4'd05] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd05] = 1'b0 ;
- assign mod_bus_rty [4'd05] = 1'b0 ;
- assign mod_bus_err [4'd05] = 1'b0 ;
- assign mod_synced_cmd [4'd06] = 1'b0 ;
- assign mod_synced_stat[4'd06] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd06] = 1'b0 ;
- assign mod_bus_rty [4'd06] = 1'b0 ;
- assign mod_bus_err [4'd06] = 1'b0 ;
- assign mod_synced_cmd [4'd07] = 1'b0 ;
- assign mod_synced_stat[4'd07] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd07] = 1'b0 ;
- assign mod_bus_rty [4'd07] = 1'b0 ;
- assign mod_bus_err [4'd07] = 1'b0 ;
- assign mod_synced_cmd [4'd08] = 1'b0 ;
- assign mod_synced_stat[4'd08] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd08] = 1'b0 ;
- assign mod_bus_rty [4'd08] = 1'b0 ;
- assign mod_bus_err [4'd08] = 1'b0 ;
- assign mod_synced_cmd [4'd09] = 1'b0 ;
- assign mod_synced_stat[4'd09] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd09] = 1'b0 ;
- assign mod_bus_rty [4'd09] = 1'b0 ;
- assign mod_bus_err [4'd09] = 1'b0 ;
- assign mod_synced_cmd [4'd10] = 1'b0 ;
- assign mod_synced_stat[4'd10] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd10] = 1'b0 ;
- assign mod_bus_rty [4'd10] = 1'b0 ;
- assign mod_bus_err [4'd10] = 1'b0 ;
- assign mod_synced_cmd [4'd11] = 1'b0 ;
- assign mod_synced_stat[4'd11] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd11] = 1'b0 ;
- assign mod_bus_rty [4'd11] = 1'b0 ;
- assign mod_bus_err [4'd11] = 1'b0 ;
- assign mod_synced_cmd [4'd12] = 1'b0 ;
- assign mod_synced_stat[4'd12] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd12] = 1'b0 ;
- assign mod_bus_rty [4'd12] = 1'b0 ;
- assign mod_bus_err [4'd12] = 1'b0 ;
- assign mod_synced_cmd [4'd13] = 1'b0 ;
- assign mod_synced_stat[4'd13] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd13] = 1'b0 ;
- assign mod_bus_rty [4'd13] = 1'b0 ;
- assign mod_bus_err [4'd13] = 1'b0 ;
- assign mod_synced_cmd [4'd14] = 1'b0 ;
- assign mod_synced_stat[4'd14] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd14] = 1'b0 ;
- assign mod_bus_rty [4'd14] = 1'b0 ;
- assign mod_bus_err [4'd14] = 1'b0 ;
- assign mod_synced_cmd [4'd15] = 1'b0 ;
- assign mod_synced_stat[4'd15] = 1'b0 ;
- assign mod_read_data [32] = 32'h0 ;
- assign mod_bus_ack [4'd15] = 1'b0 ;
- assign mod_bus_rty [4'd15] = 1'b0 ;
- assign mod_bus_err [4'd15] = 1'b0 ;
-endmodule
orpsocv2/rtl/verilog/components/debug_if/debug_if_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/tap/tap_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/tap/tap_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/tap/tap_ip.v (nonexistent)
@@ -1,373 +0,0 @@
-`timescale 1ns/10ps
-module tap_top(
- tms_pad_i,
- tck_pad_i,
- trst_pad_i,
- tdi_pad_i,
- tdo_pad_o,
- tdo_padoe_o,
- shift_dr_o,
- pause_dr_o,
- update_dr_o,
- capture_dr_o,
- extest_select_o,
- sample_preload_select_o,
- mbist_select_o,
- debug_select_o,
- tdo_o,
- debug_tdi_i,
- bs_chain_tdi_i,
- mbist_tdi_i
- );
-input tms_pad_i;
-input tck_pad_i;
-input trst_pad_i;
-input tdi_pad_i;
-output tdo_pad_o;
-output tdo_padoe_o;
-output shift_dr_o;
-output pause_dr_o;
-output update_dr_o;
-output capture_dr_o;
-output extest_select_o;
-output sample_preload_select_o;
-output mbist_select_o;
-output debug_select_o;
-output tdo_o;
-input debug_tdi_i;
-input bs_chain_tdi_i;
-input mbist_tdi_i;
-reg test_logic_reset;
-reg run_test_idle;
-reg select_dr_scan;
-reg capture_dr;
-reg shift_dr;
-reg exit1_dr;
-reg pause_dr;
-reg exit2_dr;
-reg update_dr;
-reg select_ir_scan;
-reg capture_ir;
-reg shift_ir, shift_ir_neg;
-reg exit1_ir;
-reg pause_ir;
-reg exit2_ir;
-reg update_ir;
-reg extest_select;
-reg sample_preload_select;
-reg idcode_select;
-reg mbist_select;
-reg debug_select;
-reg bypass_select;
-reg tdo_pad_o;
-reg tdo_padoe_o;
-reg tms_q1, tms_q2, tms_q3, tms_q4;
-wire tms_reset;
-assign tdo_o = tdi_pad_i;
-assign shift_dr_o = shift_dr;
-assign pause_dr_o = pause_dr;
-assign update_dr_o = update_dr;
-assign capture_dr_o = capture_dr;
-assign extest_select_o = extest_select;
-assign sample_preload_select_o = sample_preload_select;
-assign mbist_select_o = mbist_select;
-assign debug_select_o = debug_select;
-always @ (posedge tck_pad_i)
-begin
- tms_q1 <= #1 tms_pad_i;
- tms_q2 <= #1 tms_q1;
- tms_q3 <= #1 tms_q2;
- tms_q4 <= #1 tms_q3;
-end
-assign tms_reset = tms_q1 & tms_q2 & tms_q3 & tms_q4 & tms_pad_i;
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- test_logic_reset<=#1 1'b1;
- else if (tms_reset)
- test_logic_reset<=#1 1'b1;
- else
- begin
- if(tms_pad_i & (test_logic_reset | select_ir_scan))
- test_logic_reset<=#1 1'b1;
- else
- test_logic_reset<=#1 1'b0;
- end
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- run_test_idle<=#1 1'b0;
- else if (tms_reset)
- run_test_idle<=#1 1'b0;
- else
- if(~tms_pad_i & (test_logic_reset | run_test_idle | update_dr | update_ir))
- run_test_idle<=#1 1'b1;
- else
- run_test_idle<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_dr_scan<=#1 1'b0;
- else if (tms_reset)
- select_dr_scan<=#1 1'b0;
- else
- if(tms_pad_i & (run_test_idle | update_dr | update_ir))
- select_dr_scan<=#1 1'b1;
- else
- select_dr_scan<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_dr<=#1 1'b0;
- else if (tms_reset)
- capture_dr<=#1 1'b0;
- else
- if(~tms_pad_i & select_dr_scan)
- capture_dr<=#1 1'b1;
- else
- capture_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_dr<=#1 1'b0;
- else if (tms_reset)
- shift_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_dr | shift_dr | exit2_dr))
- shift_dr<=#1 1'b1;
- else
- shift_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_dr<=#1 1'b0;
- else if (tms_reset)
- exit1_dr<=#1 1'b0;
- else
- if(tms_pad_i & (capture_dr | shift_dr))
- exit1_dr<=#1 1'b1;
- else
- exit1_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_dr<=#1 1'b0;
- else if (tms_reset)
- pause_dr<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_dr | pause_dr))
- pause_dr<=#1 1'b1;
- else
- pause_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_dr<=#1 1'b0;
- else if (tms_reset)
- exit2_dr<=#1 1'b0;
- else
- if(tms_pad_i & pause_dr)
- exit2_dr<=#1 1'b1;
- else
- exit2_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_dr<=#1 1'b0;
- else if (tms_reset)
- update_dr<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_dr | exit2_dr))
- update_dr<=#1 1'b1;
- else
- update_dr<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- select_ir_scan<=#1 1'b0;
- else if (tms_reset)
- select_ir_scan<=#1 1'b0;
- else
- if(tms_pad_i & select_dr_scan)
- select_ir_scan<=#1 1'b1;
- else
- select_ir_scan<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- capture_ir<=#1 1'b0;
- else if (tms_reset)
- capture_ir<=#1 1'b0;
- else
- if(~tms_pad_i & select_ir_scan)
- capture_ir<=#1 1'b1;
- else
- capture_ir<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- shift_ir<=#1 1'b0;
- else if (tms_reset)
- shift_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (capture_ir | shift_ir | exit2_ir))
- shift_ir<=#1 1'b1;
- else
- shift_ir<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit1_ir<=#1 1'b0;
- else if (tms_reset)
- exit1_ir<=#1 1'b0;
- else
- if(tms_pad_i & (capture_ir | shift_ir))
- exit1_ir<=#1 1'b1;
- else
- exit1_ir<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- pause_ir<=#1 1'b0;
- else if (tms_reset)
- pause_ir<=#1 1'b0;
- else
- if(~tms_pad_i & (exit1_ir | pause_ir))
- pause_ir<=#1 1'b1;
- else
- pause_ir<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- exit2_ir<=#1 1'b0;
- else if (tms_reset)
- exit2_ir<=#1 1'b0;
- else
- if(tms_pad_i & pause_ir)
- exit2_ir<=#1 1'b1;
- else
- exit2_ir<=#1 1'b0;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- update_ir<=#1 1'b0;
- else if (tms_reset)
- update_ir<=#1 1'b0;
- else
- if(tms_pad_i & (exit1_ir | exit2_ir))
- update_ir<=#1 1'b1;
- else
- update_ir<=#1 1'b0;
-end
-reg [4-1:0] jtag_ir;
-reg [4-1:0] latched_jtag_ir, latched_jtag_ir_neg;
-reg instruction_tdo;
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- jtag_ir[4-1:0] <= #1 4'b0;
- else if(capture_ir)
- jtag_ir <= #1 4'b0101;
- else if(shift_ir)
- jtag_ir[4-1:0] <= #1 {tdi_pad_i, jtag_ir[4-1:1]};
-end
-always @ (negedge tck_pad_i)
-begin
- instruction_tdo <= #1 jtag_ir[0];
-end
-reg [31:0] idcode_reg;
-reg idcode_tdo;
-always @ (posedge tck_pad_i)
-begin
- if(idcode_select & shift_dr)
- idcode_reg <= #1 {tdi_pad_i, idcode_reg[31:1]};
- else
- idcode_reg <= #1 32'h14951185;
-end
-always @ (negedge tck_pad_i)
-begin
- idcode_tdo <= #1 idcode_reg;
-end
-reg bypassed_tdo;
-reg bypass_reg;
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if (trst_pad_i)
- bypass_reg<=#1 1'b0;
- else if(shift_dr)
- bypass_reg<=#1 tdi_pad_i;
-end
-always @ (negedge tck_pad_i)
-begin
- bypassed_tdo <=#1 bypass_reg;
-end
-always @ (posedge tck_pad_i or posedge trst_pad_i)
-begin
- if(trst_pad_i)
- latched_jtag_ir <=#1 4'b0010;
- else if (tms_reset)
- latched_jtag_ir <=#1 4'b0010;
- else if(update_ir)
- latched_jtag_ir <=#1 jtag_ir;
-end
-always @ (latched_jtag_ir)
-begin
- extest_select = 1'b0;
- sample_preload_select = 1'b0;
- idcode_select = 1'b0;
- mbist_select = 1'b0;
- debug_select = 1'b0;
- bypass_select = 1'b0;
- case(latched_jtag_ir)
- 4'b0000: extest_select = 1'b1;
- 4'b0001: sample_preload_select = 1'b1;
- 4'b0010: idcode_select = 1'b1;
- 4'b1001: mbist_select = 1'b1;
- 4'b1000: debug_select = 1'b1;
- 4'b1111: bypass_select = 1'b1;
- default: bypass_select = 1'b1;
- endcase
-end
-always @ (shift_ir_neg or exit1_ir or instruction_tdo or latched_jtag_ir_neg or idcode_tdo or
- debug_tdi_i or bs_chain_tdi_i or mbist_tdi_i or
- bypassed_tdo)
-begin
- if(shift_ir_neg)
- tdo_pad_o = instruction_tdo;
- else
- begin
- case(latched_jtag_ir_neg)
- 4'b0010: tdo_pad_o = idcode_tdo;
- 4'b1000: tdo_pad_o = debug_tdi_i;
- 4'b0001: tdo_pad_o = bs_chain_tdi_i;
- 4'b0000: tdo_pad_o = bs_chain_tdi_i;
- 4'b1001: tdo_pad_o = mbist_tdi_i;
- default: tdo_pad_o = bypassed_tdo;
- endcase
- end
-end
-always @ (negedge tck_pad_i)
-begin
- tdo_padoe_o <= #1 shift_ir | shift_dr | (pause_dr & debug_select);
-end
-always @ (negedge tck_pad_i)
-begin
- shift_ir_neg <= #1 shift_ir;
- latched_jtag_ir_neg <= #1 latched_jtag_ir;
-end
-endmodule
orpsocv2/rtl/verilog/components/tap/tap_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/tap/Makefile
===================================================================
--- orpsocv2/rtl/verilog/components/tap/Makefile (revision 54)
+++ orpsocv2/rtl/verilog/components/tap/Makefile (nonexistent)
@@ -1,4 +0,0 @@
-tap_ip:
- vppp --simple tap_top.v > tap_ip.v
-
-all: tap_ip
orpsocv2/rtl/verilog/components/tap/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/uart16550/uart_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/uart16550/uart_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/uart16550/uart_ip.v (nonexistent)
@@ -1,3379 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// raminfr.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// Inferrable Distributed RAM for FIFOs ////
-//// ////
-//// Known problems (limits): ////
-//// None . ////
-//// ////
-//// To Do: ////
-//// Nothing so far. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// ////
-//// Created: 2002/07/22 ////
-//// Last Updated: 2002/07/22 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: raminfr.v,v $
-// Revision 1.2 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.1 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-
-//Following is the Verilog code for a dual-port RAM with asynchronous read.
-`include "uart_defines.v"
-module raminfr
- (clk, we, a, dpra, di, dpo);
-
-parameter addr_width = 4;
-parameter data_width = 8;
-parameter depth = 16;
-
-input clk;
-input we;
-input [addr_width-1:0] a;
-input [addr_width-1:0] dpra;
-input [data_width-1:0] di;
-//output [data_width-1:0] spo;
-output [data_width-1:0] dpo;
-reg [data_width-1:0] ram [depth-1:0];
-`ifdef SYNC_RAM
- reg [data_width-1:0] dpo;
-`else
- wire [data_width-1:0] dpo;
-`endif
-
-wire [data_width-1:0] di;
-wire [addr_width-1:0] a;
-wire [addr_width-1:0] dpra;
-
- always @(posedge clk) begin
- if (we)
- ram[a] <= di;
- end
-
-`ifdef SYNC_RAM
- always @(negedge clk)
- dpo = ram[dpra];
-`else
- assign dpo = ram[dpra];
-`endif
-
-endmodule
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_sync_flops.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core receiver logic ////
-//// ////
-//// Known problems (limits): ////
-//// None known ////
-//// ////
-//// To Do: ////
-//// Thourough testing. ////
-//// ////
-//// Author(s): ////
-//// - Andrej Erzen (andreje@flextronics.si) ////
-//// - Tadej Markovic (tadejm@flextronics.si) ////
-//// ////
-//// Created: 2004/05/20 ////
-//// Last Updated: 2004/05/20 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_sync_flops.v,v $
-// Revision 1.1 2004/05/21 11:43:25 tadejm
-// Added to synchronize RX input to Wishbone clock.
-//
-//
-
-
-`include "timescale.v"
-
-
-module uart_sync_flops
-(
- // internal signals
- rst_i,
- clk_i,
- stage1_rst_i,
- stage1_clk_en_i,
- async_dat_i,
- sync_dat_o
-);
-
-parameter Tp = 1;
-parameter width = 1;
-parameter init_value = 1'b0;
-
-input rst_i; // reset input
-input clk_i; // clock input
-input stage1_rst_i; // synchronous reset for stage 1 FF
-input stage1_clk_en_i; // synchronous clock enable for stage 1 FF
-input [width-1:0] async_dat_i; // asynchronous data input
-output [width-1:0] sync_dat_o; // synchronous data output
-
-
-//
-// Interal signal declarations
-//
-
-reg [width-1:0] sync_dat_o;
-reg [width-1:0] flop_0;
-
-
-// first stage
-always @ (posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- flop_0 <= #Tp {width{init_value}};
- else
- flop_0 <= #Tp async_dat_i;
-end
-
-// second stage
-always @ (posedge clk_i or posedge rst_i)
-begin
- if (rst_i)
- sync_dat_o <= #Tp {width{init_value}};
- else if (stage1_rst_i)
- sync_dat_o <= #Tp {width{init_value}};
- else if (stage1_clk_en_i)
- sync_dat_o <= #Tp flop_0;
-end
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_regs.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// Registers of the uart 16550 core ////
-//// ////
-//// Known problems (limits): ////
-//// Inserts 1 wait state in all WISHBONE transfers ////
-//// ////
-//// To Do: ////
-//// Nothing or verification. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: (See log for the revision history ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_regs.v,v $
-// Revision 1.42 2004/11/22 09:21:59 igorm
-// Timeout interrupt should be generated only when there is at least ony
-// character in the fifo.
-//
-// Revision 1.41 2004/05/21 11:44:41 tadejm
-// Added synchronizer flops for RX input.
-//
-// Revision 1.40 2003/06/11 16:37:47 gorban
-// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
-//
-// Revision 1.39 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.38 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.37 2001/12/27 13:24:09 mohor
-// lsr[7] was not showing overrun errors.
-//
-// Revision 1.36 2001/12/20 13:25:46 mohor
-// rx push changed to be only one cycle wide.
-//
-// Revision 1.35 2001/12/19 08:03:34 mohor
-// Warnings cleared.
-//
-// Revision 1.34 2001/12/19 07:33:54 mohor
-// Synplicity was having troubles with the comment.
-//
-// Revision 1.33 2001/12/17 10:14:43 mohor
-// Things related to msr register changed. After THRE IRQ occurs, and one
-// character is written to the transmit fifo, the detection of the THRE bit in the
-// LSR is delayed for one character time.
-//
-// Revision 1.32 2001/12/14 13:19:24 mohor
-// MSR register fixed.
-//
-// Revision 1.31 2001/12/14 10:06:58 mohor
-// After reset modem status register MSR should be reset.
-//
-// Revision 1.30 2001/12/13 10:09:13 mohor
-// thre irq should be cleared only when being source of interrupt.
-//
-// Revision 1.29 2001/12/12 09:05:46 mohor
-// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
-//
-// Revision 1.28 2001/12/10 19:52:41 gorban
-// Scratch register added
-//
-// Revision 1.27 2001/12/06 14:51:04 gorban
-// Bug in LSR[0] is fixed.
-// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
-//
-// Revision 1.26 2001/12/03 21:44:29 gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.25 2001/11/28 19:36:39 gorban
-// Fixed: timeout and break didn't pay attention to current data format when counting time
-//
-// Revision 1.24 2001/11/26 21:38:54 gorban
-// Lots of fixes:
-// Break condition wasn't handled correctly at all.
-// LSR bits could lose their values.
-// LSR value after reset was wrong.
-// Timing of THRE interrupt signal corrected.
-// LSR bit 0 timing corrected.
-//
-// Revision 1.23 2001/11/12 21:57:29 gorban
-// fixed more typo bugs
-//
-// Revision 1.22 2001/11/12 15:02:28 mohor
-// lsr1r error fixed.
-//
-// Revision 1.21 2001/11/12 14:57:27 mohor
-// ti_int_pnd error fixed.
-//
-// Revision 1.20 2001/11/12 14:50:27 mohor
-// ti_int_d error fixed.
-//
-// Revision 1.19 2001/11/10 12:43:21 gorban
-// Logic Synthesis bugs fixed. Some other minor changes
-//
-// Revision 1.18 2001/11/08 14:54:23 mohor
-// Comments in Slovene language deleted, few small fixes for better work of
-// old tools. IRQs need to be fix.
-//
-// Revision 1.17 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.16 2001/11/02 09:55:16 mohor
-// no message
-//
-// Revision 1.15 2001/10/31 15:19:22 gorban
-// Fixes to break and timeout conditions
-//
-// Revision 1.14 2001/10/29 17:00:46 gorban
-// fixed parity sending and tx_fifo resets over- and underrun
-//
-// Revision 1.13 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.12 2001/10/19 16:21:40 gorban
-// Changes data_out to be synchronous again as it should have been.
-//
-// Revision 1.11 2001/10/18 20:35:45 gorban
-// small fix
-//
-// Revision 1.10 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.9 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.10 2001/06/23 11:21:48 gorban
-// DL made 16-bit long. Fixed transmission/reception bugs.
-//
-// Revision 1.9 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.8 2001/05/29 20:05:04 gorban
-// Fixed some bugs and synthesis problems.
-//
-// Revision 1.7 2001/05/27 17:37:49 gorban
-// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
-//
-// Revision 1.6 2001/05/21 19:12:02 gorban
-// Corrected some Linter messages.
-//
-// Revision 1.5 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:11+02 jacob
-// Initial revision
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-`define UART_DL1 7:0
-`define UART_DL2 15:8
-
-module uart_regs (clk,
- wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
-
-// additional signals
- modem_inputs,
- stx_pad_o, srx_pad_i,
-
-`ifdef DATA_BUS_WIDTH_8
-`else
-// debug interface signals enabled
-ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
-`endif
- rts_pad_o, dtr_pad_o, int_o
-`ifdef UART_HAS_BAUDRATE_OUTPUT
- , baud_o
-`endif
-
- );
-
-input clk;
-input wb_rst_i;
-input [`UART_ADDR_WIDTH-1:0] wb_addr_i;
-input [7:0] wb_dat_i;
-output [7:0] wb_dat_o;
-input wb_we_i;
-input wb_re_i;
-
-output stx_pad_o;
-input srx_pad_i;
-
-input [3:0] modem_inputs;
-output rts_pad_o;
-output dtr_pad_o;
-output int_o;
-`ifdef UART_HAS_BAUDRATE_OUTPUT
-output baud_o;
-`endif
-
-`ifdef DATA_BUS_WIDTH_8
-`else
-// if 32-bit databus and debug interface are enabled
-output [3:0] ier;
-output [3:0] iir;
-output [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
-output [4:0] mcr;
-output [7:0] lcr;
-output [7:0] msr;
-output [7:0] lsr;
-output [`UART_FIFO_COUNTER_W-1:0] rf_count;
-output [`UART_FIFO_COUNTER_W-1:0] tf_count;
-output [2:0] tstate;
-output [3:0] rstate;
-
-`endif
-
-wire [3:0] modem_inputs;
-reg enable;
-`ifdef UART_HAS_BAUDRATE_OUTPUT
-assign baud_o = enable; // baud_o is actually the enable signal
-`endif
-
-
-wire stx_pad_o; // received from transmitter module
-wire srx_pad_i;
-wire srx_pad;
-
-reg [7:0] wb_dat_o;
-
-wire [`UART_ADDR_WIDTH-1:0] wb_addr_i;
-wire [7:0] wb_dat_i;
-
-
-reg [3:0] ier;
-reg [3:0] iir;
-reg [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
-reg [4:0] mcr;
-reg [7:0] lcr;
-reg [7:0] msr;
-`ifdef UART_FIX_BAUDRATE
- wire [15:0] dl;
- assign dl = 16'h`UART_DIVISOR;
-`else
-reg [15:0] dl; // 32-bit divisor latch
-`endif
-reg [7:0] scratch; // UART scratch register
-reg start_dlc; // activate dlc on writing to UART_DL1
-reg lsr_mask_d; // delay for lsr_mask condition
-reg msi_reset; // reset MSR 4 lower bits indicator
-//reg threi_clear; // THRE interrupt clear flag
-reg [15:0] dlc; // 32-bit divisor latch counter
-reg int_o;
-
-reg [3:0] trigger_level; // trigger level of the receiver FIFO
-reg rx_reset;
-reg tx_reset;
-
-wire dlab; // divisor latch access bit
-wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
-wire loopback; // loopback bit (MCR bit 4)
-wire cts, dsr, ri, dcd; // effective signals
-wire cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
-wire rts_pad_o, dtr_pad_o; // modem control outputs
-
-// LSR bits wires and regs
-wire [7:0] lsr;
-wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
-reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
-wire lsr_mask; // lsr_mask
-
-//
-// ASSINGS
-//
-
-assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
-
-assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
-assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
-
-assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
- : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
-
-assign dlab = lcr[`UART_LC_DL];
-assign loopback = mcr[4];
-
-// assign modem outputs
-assign rts_pad_o = mcr[`UART_MC_RTS];
-assign dtr_pad_o = mcr[`UART_MC_DTR];
-
-// Interrupt signals
-wire rls_int; // receiver line status interrupt
-wire rda_int; // receiver data available interrupt
-wire ti_int; // timeout indicator interrupt
-wire thre_int; // transmitter holding register empty interrupt
-wire ms_int; // modem status interrupt
-
-// FIFO signals
-reg tf_push;
-reg rf_pop;
-wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
-wire rf_error_bit; // an error (parity or framing) is inside the fifo
-wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
-wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
-wire [2:0] tstate;
-wire [3:0] rstate;
-wire [9:0] counter_t;
-
-wire thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
-reg [7:0] block_cnt; // While counter counts, THRE status is blocked (delayed one character cycle)
-reg [7:0] block_value; // One character length minus stop bit
-
-// Transmitter Instance
-wire serial_out;
-
-uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, serial_out, tstate, tf_count, tx_reset, lsr_mask);
-
- // Synchronizing and sampling serial RX input
- uart_sync_flops i_uart_sync_flops
- (
- .rst_i (wb_rst_i),
- .clk_i (clk),
- .stage1_rst_i (1'b0),
- .stage1_clk_en_i (1'b1),
- .async_dat_i (srx_pad_i),
- .sync_dat_o (srx_pad)
- );
- defparam i_uart_sync_flops.width = 1;
- defparam i_uart_sync_flops.init_value = 1'b1;
-
-// handle loopback
-wire serial_in = loopback ? serial_out : srx_pad;
-assign stx_pad_o = loopback ? 1'b1 : serial_out;
-
-// Receiver Instance
-uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, serial_in, enable,
- counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
-
-
-// Asynchronous reading here because the outputs are sampled in uart_wb.v file
-always @(dl or dlab or ier or iir or scratch
- or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i) // asynchrounous reading
-begin
- case (wb_addr_i)
- `UART_REG_RB : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
- `UART_REG_IE : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
- `UART_REG_II : wb_dat_o = {4'b1100,iir};
- `UART_REG_LC : wb_dat_o = lcr;
- `UART_REG_LS : wb_dat_o = lsr;
- `UART_REG_MS : wb_dat_o = msr;
- `UART_REG_SR : wb_dat_o = scratch;
- default: wb_dat_o = 8'b0; // ??
- endcase // case(wb_addr_i)
-end // always @ (dl or dlab or ier or iir or scratch...
-
-
-// rf_pop signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- rf_pop <= #1 0;
- else
- if (rf_pop) // restore the signal to 0 after one clock cycle
- rf_pop <= #1 0;
- else
- if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
- rf_pop <= #1 1; // advance read pointer
-end
-
-wire lsr_mask_condition;
-wire iir_read;
-wire msr_read;
-wire fifo_read;
-wire fifo_write;
-
-assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
-assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
-assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
-assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
-assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
-
-// lsr_mask_d delayed signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- lsr_mask_d <= #1 0;
- else // reset bits in the Line Status Register
- lsr_mask_d <= #1 lsr_mask_condition;
-end
-
-// lsr_mask is rise detected
-assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
-
-// msi_reset signal handling
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- msi_reset <= #1 1;
- else
- if (msi_reset)
- msi_reset <= #1 0;
- else
- if (msr_read)
- msi_reset <= #1 1; // reset bits in Modem Status Register
-end
-
-
-//
-// WRITES AND RESETS //
-//
-// Line Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- lcr <= #1 8'b00000011; // 8n1 setting
- else
- if (wb_we_i && wb_addr_i==`UART_REG_LC)
- lcr <= #1 wb_dat_i;
-
-// Interrupt Enable Register or UART_DL2
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- begin
- ier <= #1 4'b0000; // no interrupts after reset
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL2] <= #1 8'b0;
-`endif
- end
- else
- if (wb_we_i && wb_addr_i==`UART_REG_IE)
- if (dlab)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL2] <= #1 wb_dat_i;
-`endif
- end
- else
- ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
-
-
-// FIFO Control Register and rx_reset, tx_reset signals
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) begin
- fcr <= #1 2'b11;
- rx_reset <= #1 0;
- tx_reset <= #1 0;
- end else
- if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
- fcr <= #1 wb_dat_i[7:6];
- rx_reset <= #1 wb_dat_i[1];
- tx_reset <= #1 wb_dat_i[2];
- end else begin
- rx_reset <= #1 0;
- tx_reset <= #1 0;
- end
-
-// Modem Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- mcr <= #1 5'b0;
- else
- if (wb_we_i && wb_addr_i==`UART_REG_MC)
- mcr <= #1 wb_dat_i[4:0];
-
-// Scratch register
-// Line Control Register
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- scratch <= #1 0; // 8n1 setting
- else
- if (wb_we_i && wb_addr_i==`UART_REG_SR)
- scratch <= #1 wb_dat_i;
-
-// TX_FIFO or UART_DL1
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL1] <= #1 8'b0;
-`endif
- tf_push <= #1 1'b0;
- start_dlc <= #1 1'b0;
- end
- else
- if (wb_we_i && wb_addr_i==`UART_REG_TR)
- if (dlab)
- begin
-`ifdef UART_FIX_BAUDRATE
-`else
- dl[`UART_DL1] <= #1 wb_dat_i;
-`endif
- start_dlc <= #1 1'b1; // enable DL counter
- tf_push <= #1 1'b0;
- end
- else
- begin
- tf_push <= #1 1'b1;
- start_dlc <= #1 1'b0;
- end // else: !if(dlab)
- else
- begin
- start_dlc <= #1 1'b0;
- tf_push <= #1 1'b0;
- end // else: !if(dlab)
-
-// Receiver FIFO trigger level selection logic (asynchronous mux)
-always @(fcr)
- case (fcr[`UART_FC_TL])
- 2'b00 : trigger_level = 1;
- 2'b01 : trigger_level = 4;
- 2'b10 : trigger_level = 8;
- 2'b11 : trigger_level = 14;
- endcase // case(fcr[`UART_FC_TL])
-
-//
-// STATUS REGISTERS //
-//
-
-// Modem Status Register
-reg [3:0] delayed_modem_signals;
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- begin
- msr <= #1 0;
- delayed_modem_signals[3:0] <= #1 0;
- end
- else begin
- msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
- msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
- msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
- delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
- end
-end
-
-
-// Line Status Register
-
-// activation conditions
-assign lsr0 = (rf_count==0 && rf_push_pulse); // data in receiver fifo available set condition
-assign lsr1 = rf_overrun; // Receiver overrun error
-assign lsr2 = rf_data_out[1]; // parity error bit
-assign lsr3 = rf_data_out[0]; // framing error bit
-assign lsr4 = rf_data_out[2]; // break error in the character
-assign lsr5 = (tf_count==5'b0 && thre_set_en); // transmitter fifo is empty
-assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
-assign lsr7 = rf_error_bit | rf_overrun;
-
-// lsr bit0 (receiver data available)
-reg lsr0_d;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr0_d <= #1 0;
- else lsr0_d <= #1 lsr0;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr0r <= #1 0;
- else lsr0r <= #1 (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 : // deassert condition
- lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted
-
-// lsr bit 1 (receiver overrun)
-reg lsr1_d; // delayed
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr1_d <= #1 0;
- else lsr1_d <= #1 lsr1;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr1r <= #1 0;
- else lsr1r <= #1 lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
-
-// lsr bit 2 (parity error)
-reg lsr2_d; // delayed
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr2_d <= #1 0;
- else lsr2_d <= #1 lsr2;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr2r <= #1 0;
- else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
-
-// lsr bit 3 (framing error)
-reg lsr3_d; // delayed
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr3_d <= #1 0;
- else lsr3_d <= #1 lsr3;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr3r <= #1 0;
- else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
-
-// lsr bit 4 (break indicator)
-reg lsr4_d; // delayed
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr4_d <= #1 0;
- else lsr4_d <= #1 lsr4;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr4r <= #1 0;
- else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
-
-// lsr bit 5 (transmitter fifo is empty)
-reg lsr5_d;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr5_d <= #1 1;
- else lsr5_d <= #1 lsr5;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr5r <= #1 1;
- else lsr5r <= #1 (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
-
-// lsr bit 6 (transmitter empty indicator)
-reg lsr6_d;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr6_d <= #1 1;
- else lsr6_d <= #1 lsr6;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr6r <= #1 1;
- else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
-
-// lsr bit 7 (error in fifo)
-reg lsr7_d;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr7_d <= #1 0;
- else lsr7_d <= #1 lsr7;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) lsr7r <= #1 0;
- else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
-
-// Frequency divider
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- dlc <= #1 0;
- else
- if (start_dlc | ~ (|dlc))
- dlc <= #1 dl - 1; // preset counter
- else
- dlc <= #1 dlc - 1; // decrement counter
-end
-
-// Enable signal generation logic
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- enable <= #1 1'b0;
- else
- if (|dl & ~(|dlc)) // dl>0 & dlc==0
- enable <= #1 1'b1;
- else
- enable <= #1 1'b0;
-end
-
-// Delaying THRE status for one character cycle after a character is written to an empty fifo.
-always @(lcr)
- case (lcr[3:0])
- 4'b0000 : block_value = 95; // 6 bits
- 4'b0100 : block_value = 103; // 6.5 bits
- 4'b0001, 4'b1000 : block_value = 111; // 7 bits
- 4'b1100 : block_value = 119; // 7.5 bits
- 4'b0010, 4'b0101, 4'b1001 : block_value = 127; // 8 bits
- 4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143; // 9 bits
- 4'b0111, 4'b1011, 4'b1110 : block_value = 159; // 10 bits
- 4'b1111 : block_value = 175; // 11 bits
- endcase // case(lcr[3:0])
-
-// Counting time of one character minus stop bit
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- block_cnt <= #1 8'd0;
- else
- if(lsr5r & fifo_write) // THRE bit set & write to fifo occured
- block_cnt <= #1 block_value;
- else
- if (enable & block_cnt != 8'b0) // only work on enable times
- block_cnt <= #1 block_cnt - 1; // decrement break counter
-end // always of break condition detection
-
-// Generating THRE status enable signal
-assign thre_set_en = ~(|block_cnt);
-
-
-//
-// INTERRUPT LOGIC
-//
-
-assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
-assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
-assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
-assign ms_int = ier[`UART_IE_MS] && (| msr[3:0]);
-assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
-
-reg rls_int_d;
-reg thre_int_d;
-reg ms_int_d;
-reg ti_int_d;
-reg rda_int_d;
-
-// delay lines
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rls_int_d <= #1 0;
- else rls_int_d <= #1 rls_int;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rda_int_d <= #1 0;
- else rda_int_d <= #1 rda_int;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) thre_int_d <= #1 0;
- else thre_int_d <= #1 thre_int;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ms_int_d <= #1 0;
- else ms_int_d <= #1 ms_int;
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ti_int_d <= #1 0;
- else ti_int_d <= #1 ti_int;
-
-// rise detection signals
-
-wire rls_int_rise;
-wire thre_int_rise;
-wire ms_int_rise;
-wire ti_int_rise;
-wire rda_int_rise;
-
-assign rda_int_rise = rda_int & ~rda_int_d;
-assign rls_int_rise = rls_int & ~rls_int_d;
-assign thre_int_rise = thre_int & ~thre_int_d;
-assign ms_int_rise = ms_int & ~ms_int_d;
-assign ti_int_rise = ti_int & ~ti_int_d;
-
-// interrupt pending flags
-reg rls_int_pnd;
-reg rda_int_pnd;
-reg thre_int_pnd;
-reg ms_int_pnd;
-reg ti_int_pnd;
-
-// interrupt pending flags assignments
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rls_int_pnd <= #1 0;
- else
- rls_int_pnd <= #1 lsr_mask ? 0 : // reset condition
- rls_int_rise ? 1 : // latch condition
- rls_int_pnd && ier[`UART_IE_RLS]; // default operation: remove if masked
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) rda_int_pnd <= #1 0;
- else
- rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 : // reset condition
- rda_int_rise ? 1 : // latch condition
- rda_int_pnd && ier[`UART_IE_RDA]; // default operation: remove if masked
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) thre_int_pnd <= #1 0;
- else
- thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
- thre_int_rise ? 1 :
- thre_int_pnd && ier[`UART_IE_THRE];
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ms_int_pnd <= #1 0;
- else
- ms_int_pnd <= #1 msr_read ? 0 :
- ms_int_rise ? 1 :
- ms_int_pnd && ier[`UART_IE_MS];
-
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) ti_int_pnd <= #1 0;
- else
- ti_int_pnd <= #1 fifo_read ? 0 :
- ti_int_rise ? 1 :
- ti_int_pnd && ier[`UART_IE_RDA];
-// end of pending flags
-
-// INT_O logic
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- int_o <= #1 1'b0;
- else
- int_o <= #1
- rls_int_pnd ? ~lsr_mask :
- rda_int_pnd ? 1 :
- ti_int_pnd ? ~fifo_read :
- thre_int_pnd ? !(fifo_write & iir_read) :
- ms_int_pnd ? ~msr_read :
- 0; // if no interrupt are pending
-end
-
-
-// Interrupt Identification register
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- iir <= #1 1;
- else
- if (rls_int_pnd) // interrupt is pending
- begin
- iir[`UART_II_II] <= #1 `UART_II_RLS; // set identification register to correct value
- iir[`UART_II_IP] <= #1 1'b0; // and clear the IIR bit 0 (interrupt pending)
- end else // the sequence of conditions determines priority of interrupt identification
- if (rda_int)
- begin
- iir[`UART_II_II] <= #1 `UART_II_RDA;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (ti_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_TI;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (thre_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_THRE;
- iir[`UART_II_IP] <= #1 1'b0;
- end
- else if (ms_int_pnd)
- begin
- iir[`UART_II_II] <= #1 `UART_II_MS;
- iir[`UART_II_IP] <= #1 1'b0;
- end else // no interrupt is pending
- begin
- iir[`UART_II_II] <= #1 0;
- iir[`UART_II_IP] <= #1 1'b1;
- end
-end
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_rfifo.v (Modified from uart_fifo.v) ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core receiver FIFO ////
-//// ////
-//// To Do: ////
-//// Nothing. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2002/07/22 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_rfifo.v,v $
-// Revision 1.4 2003/07/11 18:20:26 gorban
-// added clearing the receiver fifo statuses on resets
-//
-// Revision 1.3 2003/06/11 16:37:47 gorban
-// This fixes errors in some cases when data is being read and put to the FIFO at the same time. Patch is submitted by Scott Furman. Update is very recommended.
-//
-// Revision 1.2 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.1 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.16 2001/12/20 13:25:46 mohor
-// rx push changed to be only one cycle wide.
-//
-// Revision 1.15 2001/12/18 09:01:07 mohor
-// Bug that was entered in the last update fixed (rx state machine).
-//
-// Revision 1.14 2001/12/17 14:46:48 mohor
-// overrun signal was moved to separate block because many sequential lsr
-// reads were preventing data from being written to rx fifo.
-// underrun signal was not used and was removed from the project.
-//
-// Revision 1.13 2001/11/26 21:38:54 gorban
-// Lots of fixes:
-// Break condition wasn't handled correctly at all.
-// LSR bits could lose their values.
-// LSR value after reset was wrong.
-// Timing of THRE interrupt signal corrected.
-// LSR bit 0 timing corrected.
-//
-// Revision 1.12 2001/11/08 14:54:23 mohor
-// Comments in Slovene language deleted, few small fixes for better work of
-// old tools. IRQs need to be fix.
-//
-// Revision 1.11 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.10 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.9 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.8 2001/08/24 08:48:10 mohor
-// FIFO was not cleared after the data was read bug fixed.
-//
-// Revision 1.7 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.3 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/27 17:37:48 gorban
-// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
-//
-// Revision 1.2 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:12+02 jacob
-// Initial revision
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_rfifo (clk,
- wb_rst_i, data_in, data_out,
-// Control signals
- push, // push strobe, active high
- pop, // pop strobe, active high
-// status signals
- overrun,
- count,
- error_bit,
- fifo_reset,
- reset_status
- );
-
-
-// FIFO parameters
-parameter fifo_width = `UART_FIFO_WIDTH;
-parameter fifo_depth = `UART_FIFO_DEPTH;
-parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
-parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
-
-input clk;
-input wb_rst_i;
-input push;
-input pop;
-input [fifo_width-1:0] data_in;
-input fifo_reset;
-input reset_status;
-
-output [fifo_width-1:0] data_out;
-output overrun;
-output [fifo_counter_w-1:0] count;
-output error_bit;
-
-wire [fifo_width-1:0] data_out;
-wire [7:0] data8_out;
-// flags FIFO
-reg [2:0] fifo[fifo_depth-1:0];
-
-// FIFO pointers
-reg [fifo_pointer_w-1:0] top;
-reg [fifo_pointer_w-1:0] bottom;
-
-reg [fifo_counter_w-1:0] count;
-reg overrun;
-
-wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
-
-raminfr #(fifo_pointer_w,8,fifo_depth) rfifo
- (.clk(clk),
- .we(push),
- .a(top),
- .dpra(bottom),
- .di(data_in[fifo_width-1:fifo_width-8]),
- .dpo(data8_out)
- );
-
-always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
-begin
- if (wb_rst_i)
- begin
- top <= #1 0;
- bottom <= #1 1'b0;
- count <= #1 0;
- fifo[0] <= #1 0;
- fifo[1] <= #1 0;
- fifo[2] <= #1 0;
- fifo[3] <= #1 0;
- fifo[4] <= #1 0;
- fifo[5] <= #1 0;
- fifo[6] <= #1 0;
- fifo[7] <= #1 0;
- fifo[8] <= #1 0;
- fifo[9] <= #1 0;
- fifo[10] <= #1 0;
- fifo[11] <= #1 0;
- fifo[12] <= #1 0;
- fifo[13] <= #1 0;
- fifo[14] <= #1 0;
- fifo[15] <= #1 0;
- end
- else
- if (fifo_reset) begin
- top <= #1 0;
- bottom <= #1 1'b0;
- count <= #1 0;
- fifo[0] <= #1 0;
- fifo[1] <= #1 0;
- fifo[2] <= #1 0;
- fifo[3] <= #1 0;
- fifo[4] <= #1 0;
- fifo[5] <= #1 0;
- fifo[6] <= #1 0;
- fifo[7] <= #1 0;
- fifo[8] <= #1 0;
- fifo[9] <= #1 0;
- fifo[10] <= #1 0;
- fifo[11] <= #1 0;
- fifo[12] <= #1 0;
- fifo[13] <= #1 0;
- fifo[14] <= #1 0;
- fifo[15] <= #1 0;
- end
- else
- begin
- case ({push, pop})
- 2'b10 : if (count0)
- begin
- fifo[bottom] <= #1 0;
- bottom <= #1 bottom + 1'b1;
- count <= #1 count - 1'b1;
- end
- 2'b11 : begin
- bottom <= #1 bottom + 1'b1;
- top <= #1 top_plus_1;
- fifo[top] <= #1 data_in[2:0];
- end
- default: ;
- endcase
- end
-end // always
-
-always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
-begin
- if (wb_rst_i)
- overrun <= #1 1'b0;
- else
- if(fifo_reset | reset_status)
- overrun <= #1 1'b0;
- else
- if(push & ~pop & (count==fifo_depth))
- overrun <= #1 1'b1;
-end // always
-
-
-// please note though that data_out is only valid one clock after pop signal
-assign data_out = {data8_out,fifo[bottom]};
-
-// Additional logic for detection of error conditions (parity and framing) inside the FIFO
-// for the Line Status Register bit 7
-
-wire [2:0] word0 = fifo[0];
-wire [2:0] word1 = fifo[1];
-wire [2:0] word2 = fifo[2];
-wire [2:0] word3 = fifo[3];
-wire [2:0] word4 = fifo[4];
-wire [2:0] word5 = fifo[5];
-wire [2:0] word6 = fifo[6];
-wire [2:0] word7 = fifo[7];
-
-wire [2:0] word8 = fifo[8];
-wire [2:0] word9 = fifo[9];
-wire [2:0] word10 = fifo[10];
-wire [2:0] word11 = fifo[11];
-wire [2:0] word12 = fifo[12];
-wire [2:0] word13 = fifo[13];
-wire [2:0] word14 = fifo[14];
-wire [2:0] word15 = fifo[15];
-
-// a 1 is returned if any of the error bits in the fifo is 1
-assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
- word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
- word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
- word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_tfifo.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core transmitter FIFO ////
-//// ////
-//// To Do: ////
-//// Nothing. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2002/07/22 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_tfifo.v,v $
-// Revision 1.2 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.1 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.16 2001/12/20 13:25:46 mohor
-// rx push changed to be only one cycle wide.
-//
-// Revision 1.15 2001/12/18 09:01:07 mohor
-// Bug that was entered in the last update fixed (rx state machine).
-//
-// Revision 1.14 2001/12/17 14:46:48 mohor
-// overrun signal was moved to separate block because many sequential lsr
-// reads were preventing data from being written to rx fifo.
-// underrun signal was not used and was removed from the project.
-//
-// Revision 1.13 2001/11/26 21:38:54 gorban
-// Lots of fixes:
-// Break condition wasn't handled correctly at all.
-// LSR bits could lose their values.
-// LSR value after reset was wrong.
-// Timing of THRE interrupt signal corrected.
-// LSR bit 0 timing corrected.
-//
-// Revision 1.12 2001/11/08 14:54:23 mohor
-// Comments in Slovene language deleted, few small fixes for better work of
-// old tools. IRQs need to be fix.
-//
-// Revision 1.11 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.10 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.9 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.8 2001/08/24 08:48:10 mohor
-// FIFO was not cleared after the data was read bug fixed.
-//
-// Revision 1.7 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.3 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/27 17:37:48 gorban
-// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
-//
-// Revision 1.2 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:12+02 jacob
-// Initial revision
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_tfifo (clk,
- wb_rst_i, data_in, data_out,
-// Control signals
- push, // push strobe, active high
- pop, // pop strobe, active high
-// status signals
- overrun,
- count,
- fifo_reset,
- reset_status
- );
-
-
-// FIFO parameters
-parameter fifo_width = `UART_FIFO_WIDTH;
-parameter fifo_depth = `UART_FIFO_DEPTH;
-parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
-parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
-
-input clk;
-input wb_rst_i;
-input push;
-input pop;
-input [fifo_width-1:0] data_in;
-input fifo_reset;
-input reset_status;
-
-output [fifo_width-1:0] data_out;
-output overrun;
-output [fifo_counter_w-1:0] count;
-
-wire [fifo_width-1:0] data_out;
-
-// FIFO pointers
-reg [fifo_pointer_w-1:0] top;
-reg [fifo_pointer_w-1:0] bottom;
-
-reg [fifo_counter_w-1:0] count;
-reg overrun;
-wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
-
-raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo
- (.clk(clk),
- .we(push),
- .a(top),
- .dpra(bottom),
- .di(data_in),
- .dpo(data_out)
- );
-
-
-always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
-begin
- if (wb_rst_i)
- begin
- top <= #1 0;
- bottom <= #1 1'b0;
- count <= #1 0;
- end
- else
- if (fifo_reset) begin
- top <= #1 0;
- bottom <= #1 1'b0;
- count <= #1 0;
- end
- else
- begin
- case ({push, pop})
- 2'b10 : if (count0)
- begin
- bottom <= #1 bottom + 1'b1;
- count <= #1 count - 1'b1;
- end
- 2'b11 : begin
- bottom <= #1 bottom + 1'b1;
- top <= #1 top_plus_1;
- end
- default: ;
- endcase
- end
-end // always
-
-always @(posedge clk or posedge wb_rst_i) // synchronous FIFO
-begin
- if (wb_rst_i)
- overrun <= #1 1'b0;
- else
- if(fifo_reset | reset_status)
- overrun <= #1 1'b0;
- else
- if(push & (count==fifo_depth))
- overrun <= #1 1'b1;
-end // always
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_receiver.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core receiver logic ////
-//// ////
-//// Known problems (limits): ////
-//// None known ////
-//// ////
-//// To Do: ////
-//// Thourough testing. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2001/05/17 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_receiver.v,v $
-// Revision 1.31 2004/06/18 14:46:15 tadejm
-// Brandl Tobias repaired a bug regarding frame error in receiver when brake is received.
-//
-// Revision 1.29 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.28 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.27 2001/12/30 20:39:13 mohor
-// More than one character was stored in case of break. End of the break
-// was not detected correctly.
-//
-// Revision 1.26 2001/12/20 13:28:27 mohor
-// Missing declaration of rf_push_q fixed.
-//
-// Revision 1.25 2001/12/20 13:25:46 mohor
-// rx push changed to be only one cycle wide.
-//
-// Revision 1.24 2001/12/19 08:03:34 mohor
-// Warnings cleared.
-//
-// Revision 1.23 2001/12/19 07:33:54 mohor
-// Synplicity was having troubles with the comment.
-//
-// Revision 1.22 2001/12/17 14:46:48 mohor
-// overrun signal was moved to separate block because many sequential lsr
-// reads were preventing data from being written to rx fifo.
-// underrun signal was not used and was removed from the project.
-//
-// Revision 1.21 2001/12/13 10:31:16 mohor
-// timeout irq must be set regardless of the rda irq (rda irq does not reset the
-// timeout counter).
-//
-// Revision 1.20 2001/12/10 19:52:05 gorban
-// Igor fixed break condition bugs
-//
-// Revision 1.19 2001/12/06 14:51:04 gorban
-// Bug in LSR[0] is fixed.
-// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
-//
-// Revision 1.18 2001/12/03 21:44:29 gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.17 2001/11/28 19:36:39 gorban
-// Fixed: timeout and break didn't pay attention to current data format when counting time
-//
-// Revision 1.16 2001/11/27 22:17:09 gorban
-// Fixed bug that prevented synthesis in uart_receiver.v
-//
-// Revision 1.15 2001/11/26 21:38:54 gorban
-// Lots of fixes:
-// Break condition wasn't handled correctly at all.
-// LSR bits could lose their values.
-// LSR value after reset was wrong.
-// Timing of THRE interrupt signal corrected.
-// LSR bit 0 timing corrected.
-//
-// Revision 1.14 2001/11/10 12:43:21 gorban
-// Logic Synthesis bugs fixed. Some other minor changes
-//
-// Revision 1.13 2001/11/08 14:54:23 mohor
-// Comments in Slovene language deleted, few small fixes for better work of
-// old tools. IRQs need to be fix.
-//
-// Revision 1.12 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.11 2001/10/31 15:19:22 gorban
-// Fixes to break and timeout conditions
-//
-// Revision 1.10 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.9 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.8 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.6 2001/06/23 11:21:48 gorban
-// DL made 16-bit long. Fixed transmission/reception bugs.
-//
-// Revision 1.5 2001/06/02 14:28:14 gorban
-// Fixed receiver and transmitter. Major bug fixed.
-//
-// Revision 1.4 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/27 17:37:49 gorban
-// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
-//
-// Revision 1.2 2001/05/21 19:12:02 gorban
-// Corrected some Linter messages.
-//
-// Revision 1.1 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:11+02 jacob
-// Initial revision
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
- counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
-
-input clk;
-input wb_rst_i;
-input [7:0] lcr;
-input rf_pop;
-input srx_pad_i;
-input enable;
-input rx_reset;
-input lsr_mask;
-
-output [9:0] counter_t;
-output [`UART_FIFO_COUNTER_W-1:0] rf_count;
-output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
-output rf_overrun;
-output rf_error_bit;
-output [3:0] rstate;
-output rf_push_pulse;
-
-reg [3:0] rstate;
-reg [3:0] rcounter16;
-reg [2:0] rbit_counter;
-reg [7:0] rshift; // receiver shift register
-reg rparity; // received parity
-reg rparity_error;
-reg rframing_error; // framing error flag
-reg rbit_in;
-reg rparity_xor;
-reg [7:0] counter_b; // counts the 0 (low) signals
-reg rf_push_q;
-
-// RX FIFO signals
-reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
-wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
-wire rf_push_pulse;
-reg rf_push;
-wire rf_pop;
-wire rf_overrun;
-wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
-wire rf_error_bit; // an error (parity or framing) is inside the fifo
-wire break_error = (counter_b == 0);
-
-// RX FIFO instance
-uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
- .clk( clk ),
- .wb_rst_i( wb_rst_i ),
- .data_in( rf_data_in ),
- .data_out( rf_data_out ),
- .push( rf_push_pulse ),
- .pop( rf_pop ),
- .overrun( rf_overrun ),
- .count( rf_count ),
- .error_bit( rf_error_bit ),
- .fifo_reset( rx_reset ),
- .reset_status(lsr_mask)
-);
-
-wire rcounter16_eq_7 = (rcounter16 == 4'd7);
-wire rcounter16_eq_0 = (rcounter16 == 4'd0);
-wire rcounter16_eq_1 = (rcounter16 == 4'd1);
-
-wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
-
-parameter sr_idle = 4'd0;
-parameter sr_rec_start = 4'd1;
-parameter sr_rec_bit = 4'd2;
-parameter sr_rec_parity = 4'd3;
-parameter sr_rec_stop = 4'd4;
-parameter sr_check_parity = 4'd5;
-parameter sr_rec_prepare = 4'd6;
-parameter sr_end_bit = 4'd7;
-parameter sr_ca_lc_parity = 4'd8;
-parameter sr_wait1 = 4'd9;
-parameter sr_push = 4'd10;
-
-
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- begin
- rstate <= #1 sr_idle;
- rbit_in <= #1 1'b0;
- rcounter16 <= #1 0;
- rbit_counter <= #1 0;
- rparity_xor <= #1 1'b0;
- rframing_error <= #1 1'b0;
- rparity_error <= #1 1'b0;
- rparity <= #1 1'b0;
- rshift <= #1 0;
- rf_push <= #1 1'b0;
- rf_data_in <= #1 0;
- end
- else
- if (enable)
- begin
- case (rstate)
- sr_idle : begin
- rf_push <= #1 1'b0;
- rf_data_in <= #1 0;
- rcounter16 <= #1 4'b1110;
- if (srx_pad_i==1'b0 & ~break_error) // detected a pulse (start bit?)
- begin
- rstate <= #1 sr_rec_start;
- end
- end
- sr_rec_start : begin
- rf_push <= #1 1'b0;
- if (rcounter16_eq_7) // check the pulse
- if (srx_pad_i==1'b1) // no start bit
- rstate <= #1 sr_idle;
- else // start bit detected
- rstate <= #1 sr_rec_prepare;
- rcounter16 <= #1 rcounter16_minus_1;
- end
- sr_rec_prepare:begin
- case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
- 2'b00 : rbit_counter <= #1 3'b100;
- 2'b01 : rbit_counter <= #1 3'b101;
- 2'b10 : rbit_counter <= #1 3'b110;
- 2'b11 : rbit_counter <= #1 3'b111;
- endcase
- if (rcounter16_eq_0)
- begin
- rstate <= #1 sr_rec_bit;
- rcounter16 <= #1 4'b1110;
- rshift <= #1 0;
- end
- else
- rstate <= #1 sr_rec_prepare;
- rcounter16 <= #1 rcounter16_minus_1;
- end
- sr_rec_bit : begin
- if (rcounter16_eq_0)
- rstate <= #1 sr_end_bit;
- if (rcounter16_eq_7) // read the bit
- case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
- 2'b00 : rshift[4:0] <= #1 {srx_pad_i, rshift[4:1]};
- 2'b01 : rshift[5:0] <= #1 {srx_pad_i, rshift[5:1]};
- 2'b10 : rshift[6:0] <= #1 {srx_pad_i, rshift[6:1]};
- 2'b11 : rshift[7:0] <= #1 {srx_pad_i, rshift[7:1]};
- endcase
- rcounter16 <= #1 rcounter16_minus_1;
- end
- sr_end_bit : begin
- if (rbit_counter==3'b0) // no more bits in word
- if (lcr[`UART_LC_PE]) // choose state based on parity
- rstate <= #1 sr_rec_parity;
- else
- begin
- rstate <= #1 sr_rec_stop;
- rparity_error <= #1 1'b0; // no parity - no error :)
- end
- else // else we have more bits to read
- begin
- rstate <= #1 sr_rec_bit;
- rbit_counter <= #1 rbit_counter - 1'b1;
- end
- rcounter16 <= #1 4'b1110;
- end
- sr_rec_parity: begin
- if (rcounter16_eq_7) // read the parity
- begin
- rparity <= #1 srx_pad_i;
- rstate <= #1 sr_ca_lc_parity;
- end
- rcounter16 <= #1 rcounter16_minus_1;
- end
- sr_ca_lc_parity : begin // rcounter equals 6
- rcounter16 <= #1 rcounter16_minus_1;
- rparity_xor <= #1 ^{rshift,rparity}; // calculate parity on all incoming data
- rstate <= #1 sr_check_parity;
- end
- sr_check_parity: begin // rcounter equals 5
- case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
- 2'b00: rparity_error <= #1 rparity_xor == 0; // no error if parity 1
- 2'b01: rparity_error <= #1 ~rparity; // parity should sticked to 1
- 2'b10: rparity_error <= #1 rparity_xor == 1; // error if parity is odd
- 2'b11: rparity_error <= #1 rparity; // parity should be sticked to 0
- endcase
- rcounter16 <= #1 rcounter16_minus_1;
- rstate <= #1 sr_wait1;
- end
- sr_wait1 : if (rcounter16_eq_0)
- begin
- rstate <= #1 sr_rec_stop;
- rcounter16 <= #1 4'b1110;
- end
- else
- rcounter16 <= #1 rcounter16_minus_1;
- sr_rec_stop : begin
- if (rcounter16_eq_7) // read the parity
- begin
- rframing_error <= #1 !srx_pad_i; // no framing error if input is 1 (stop bit)
- rstate <= #1 sr_push;
- end
- rcounter16 <= #1 rcounter16_minus_1;
- end
- sr_push : begin
-///////////////////////////////////////
-// $display($time, ": received: %b", rf_data_in);
- if(srx_pad_i | break_error)
- begin
- if(break_error)
- rf_data_in <= #1 {8'b0, 3'b100}; // break input (empty character) to receiver FIFO
- else
- rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
- rf_push <= #1 1'b1;
- rstate <= #1 sr_idle;
- end
- else if(~rframing_error) // There's always a framing before break_error -> wait for break or srx_pad_i
- begin
- rf_data_in <= #1 {rshift, 1'b0, rparity_error, rframing_error};
- rf_push <= #1 1'b1;
- rcounter16 <= #1 4'b1110;
- rstate <= #1 sr_rec_start;
- end
-
- end
- default : rstate <= #1 sr_idle;
- endcase
- end // if (enable)
-end // always of receiver
-
-always @ (posedge clk or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- rf_push_q <= 0;
- else
- rf_push_q <= #1 rf_push;
-end
-
-assign rf_push_pulse = rf_push & ~rf_push_q;
-
-
-//
-// Break condition detection.
-// Works in conjuction with the receiver state machine
-
-reg [9:0] toc_value; // value to be set to timeout counter
-
-always @(lcr)
- case (lcr[3:0])
- 4'b0000 : toc_value = 447; // 7 bits
- 4'b0100 : toc_value = 479; // 7.5 bits
- 4'b0001, 4'b1000 : toc_value = 511; // 8 bits
- 4'b1100 : toc_value = 543; // 8.5 bits
- 4'b0010, 4'b0101, 4'b1001 : toc_value = 575; // 9 bits
- 4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639; // 10 bits
- 4'b0111, 4'b1011, 4'b1110 : toc_value = 703; // 11 bits
- 4'b1111 : toc_value = 767; // 12 bits
- endcase // case(lcr[3:0])
-
-wire [7:0] brc_value; // value to be set to break counter
-assign brc_value = toc_value[9:2]; // the same as timeout but 1 insead of 4 character times
-
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- counter_b <= #1 8'd159;
- else
- if (srx_pad_i)
- counter_b <= #1 brc_value; // character time length - 1
- else
- if(enable & counter_b != 8'b0) // only work on enable times break not reached.
- counter_b <= #1 counter_b - 1; // decrement break counter
-end // always of break condition detection
-
-///
-/// Timeout condition detection
-reg [9:0] counter_t; // counts the timeout condition clocks
-
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- counter_t <= #1 10'd639; // 10 bits for the default 8N1
- else
- if(rf_push_pulse || rf_pop || rf_count == 0) // counter is reset when RX FIFO is empty, accessed or above trigger level
- counter_t <= #1 toc_value;
- else
- if (enable && counter_t != 10'b0) // we don't want to underflow
- counter_t <= #1 counter_t - 1;
-end
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_transmitter.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core transmitter logic ////
-//// ////
-//// Known problems (limits): ////
-//// None known ////
-//// ////
-//// To Do: ////
-//// Thourough testing. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2001/05/17 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_transmitter.v,v $
-// Revision 1.19 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.18 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.16 2002/01/08 11:29:40 mohor
-// tf_pop was too wide. Now it is only 1 clk cycle width.
-//
-// Revision 1.15 2001/12/17 14:46:48 mohor
-// overrun signal was moved to separate block because many sequential lsr
-// reads were preventing data from being written to rx fifo.
-// underrun signal was not used and was removed from the project.
-//
-// Revision 1.14 2001/12/03 21:44:29 gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.13 2001/11/08 14:54:23 mohor
-// Comments in Slovene language deleted, few small fixes for better work of
-// old tools. IRQs need to be fix.
-//
-// Revision 1.12 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.11 2001/10/29 17:00:46 gorban
-// fixed parity sending and tx_fifo resets over- and underrun
-//
-// Revision 1.10 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.9 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.8 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.6 2001/06/23 11:21:48 gorban
-// DL made 16-bit long. Fixed transmission/reception bugs.
-//
-// Revision 1.5 2001/06/02 14:28:14 gorban
-// Fixed receiver and transmitter. Major bug fixed.
-//
-// Revision 1.4 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/27 17:37:49 gorban
-// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
-//
-// Revision 1.2 2001/05/21 19:12:02 gorban
-// Corrected some Linter messages.
-//
-// Revision 1.1 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:12+02 jacob
-// Initial revision
-//
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
-
-input clk;
-input wb_rst_i;
-input [7:0] lcr;
-input tf_push;
-input [7:0] wb_dat_i;
-input enable;
-input tx_reset;
-input lsr_mask; //reset of fifo
-output stx_pad_o;
-output [2:0] tstate;
-output [`UART_FIFO_COUNTER_W-1:0] tf_count;
-
-reg [2:0] tstate;
-reg [4:0] counter;
-reg [2:0] bit_counter; // counts the bits to be sent
-reg [6:0] shift_out; // output shift register
-reg stx_o_tmp;
-reg parity_xor; // parity of the word
-reg tf_pop;
-reg bit_out;
-
-// TX FIFO instance
-//
-// Transmitter FIFO signals
-wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
-wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
-wire tf_push;
-wire tf_overrun;
-wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
-
-assign tf_data_in = wb_dat_i;
-
-uart_tfifo fifo_tx( // error bit signal is not used in transmitter FIFO
- .clk( clk ),
- .wb_rst_i( wb_rst_i ),
- .data_in( tf_data_in ),
- .data_out( tf_data_out ),
- .push( tf_push ),
- .pop( tf_pop ),
- .overrun( tf_overrun ),
- .count( tf_count ),
- .fifo_reset( tx_reset ),
- .reset_status(lsr_mask)
-);
-
-`ifdef UART_LOG_TX
- integer file_handler;
-
-initial
- begin
- file_handler = $fopen("uart_tx.txt");
- end
-
-always @(negedge tf_push)
- begin
- $fwrite(file_handler, "%s", tf_data_out);
- $display("UART: %s", tf_data_out);
- end
-`endif
-
-// TRANSMITTER FINAL STATE MACHINE
-
-parameter s_idle = 3'd0;
-parameter s_send_start = 3'd1;
-parameter s_send_byte = 3'd2;
-parameter s_send_parity = 3'd3;
-parameter s_send_stop = 3'd4;
-parameter s_pop_byte = 3'd5;
-
-always @(posedge clk or posedge wb_rst_i)
-begin
- if (wb_rst_i)
- begin
- tstate <= #1 s_idle;
- stx_o_tmp <= #1 1'b1;
- counter <= #1 5'b0;
- shift_out <= #1 7'b0;
- bit_out <= #1 1'b0;
- parity_xor <= #1 1'b0;
- tf_pop <= #1 1'b0;
- bit_counter <= #1 3'b0;
- end
- else
- if (enable)
- begin
- case (tstate)
- s_idle : if (~|tf_count) // if tf_count==0
- begin
- tstate <= #1 s_idle;
- stx_o_tmp <= #1 1'b1;
- end
- else
- begin
- tf_pop <= #1 1'b0;
- stx_o_tmp <= #1 1'b1;
- tstate <= #1 s_pop_byte;
- end
- s_pop_byte : begin
- tf_pop <= #1 1'b1;
- case (lcr[/*`UART_LC_BITS*/1:0]) // number of bits in a word
- 2'b00 : begin
- bit_counter <= #1 3'b100;
- parity_xor <= #1 ^tf_data_out[4:0];
- end
- 2'b01 : begin
- bit_counter <= #1 3'b101;
- parity_xor <= #1 ^tf_data_out[5:0];
- end
- 2'b10 : begin
- bit_counter <= #1 3'b110;
- parity_xor <= #1 ^tf_data_out[6:0];
- end
- 2'b11 : begin
- bit_counter <= #1 3'b111;
- parity_xor <= #1 ^tf_data_out[7:0];
- end
- endcase
- {shift_out[6:0], bit_out} <= #1 tf_data_out;
- tstate <= #1 s_send_start;
- end
- s_send_start : begin
- tf_pop <= #1 1'b0;
- if (~|counter)
- counter <= #1 5'b01111;
- else
- if (counter == 5'b00001)
- begin
- counter <= #1 0;
- tstate <= #1 s_send_byte;
- end
- else
- counter <= #1 counter - 1'b1;
- stx_o_tmp <= #1 1'b0;
- end
- s_send_byte : begin
- if (~|counter)
- counter <= #1 5'b01111;
- else
- if (counter == 5'b00001)
- begin
- if (bit_counter > 3'b0)
- begin
- bit_counter <= #1 bit_counter - 1'b1;
- {shift_out[5:0],bit_out } <= #1 {shift_out[6:1], shift_out[0]};
- tstate <= #1 s_send_byte;
- end
- else // end of byte
- if (~lcr[`UART_LC_PE])
- begin
- tstate <= #1 s_send_stop;
- end
- else
- begin
- case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
- 2'b00: bit_out <= #1 ~parity_xor;
- 2'b01: bit_out <= #1 1'b1;
- 2'b10: bit_out <= #1 parity_xor;
- 2'b11: bit_out <= #1 1'b0;
- endcase
- tstate <= #1 s_send_parity;
- end
- counter <= #1 0;
- end
- else
- counter <= #1 counter - 1'b1;
- stx_o_tmp <= #1 bit_out; // set output pin
- end
- s_send_parity : begin
- if (~|counter)
- counter <= #1 5'b01111;
- else
- if (counter == 5'b00001)
- begin
- counter <= #1 4'b0;
- tstate <= #1 s_send_stop;
- end
- else
- counter <= #1 counter - 1'b1;
- stx_o_tmp <= #1 bit_out;
- end
- s_send_stop : begin
- if (~|counter)
- begin
- casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
- 3'b0xx: counter <= #1 5'b01101; // 1 stop bit ok igor
- 3'b100: counter <= #1 5'b10101; // 1.5 stop bit
- default: counter <= #1 5'b11101; // 2 stop bits
- endcase
- end
- else
- if (counter == 5'b00001)
- begin
- counter <= #1 0;
- tstate <= #1 s_idle;
- end
- else
- counter <= #1 counter - 1'b1;
- stx_o_tmp <= #1 1'b1;
- end
-
- default : // should never get here
- tstate <= #1 s_idle;
- endcase
- end // end if enable
- else
- tf_pop <= #1 1'b0; // tf_pop must be 1 cycle width
-end // transmitter logic
-
-assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp; // Break condition
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_debug_if.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core debug interface. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// ////
-//// Created: 2001/12/02 ////
-//// (See log for the revision history) ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_debug_if.v,v $
-// Revision 1.5 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.4 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.3 2001/12/19 08:40:03 mohor
-// Warnings fixed (unused signals removed).
-//
-// Revision 1.2 2001/12/12 22:17:30 gorban
-// some synthesis bugs fixed
-//
-// Revision 1.1 2001/12/04 21:14:16 gorban
-// committed the debug interface file
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_debug_if (/*AUTOARG*/
-// Outputs
-wb_dat32_o,
-// Inputs
-wb_adr_i, ier, iir, fcr, mcr, lcr, msr,
-lsr, rf_count, tf_count, tstate, rstate
-) ;
-
-input [`UART_ADDR_WIDTH-1:0] wb_adr_i;
-output [31:0] wb_dat32_o;
-input [3:0] ier;
-input [3:0] iir;
-input [1:0] fcr; /// bits 7 and 6 of fcr. Other bits are ignored
-input [4:0] mcr;
-input [7:0] lcr;
-input [7:0] msr;
-input [7:0] lsr;
-input [`UART_FIFO_COUNTER_W-1:0] rf_count;
-input [`UART_FIFO_COUNTER_W-1:0] tf_count;
-input [2:0] tstate;
-input [3:0] rstate;
-
-
-wire [`UART_ADDR_WIDTH-1:0] wb_adr_i;
-reg [31:0] wb_dat32_o;
-
-always @(/*AUTOSENSE*/fcr or ier or iir or lcr or lsr or mcr or msr
- or rf_count or rstate or tf_count or tstate or wb_adr_i)
- case (wb_adr_i)
- // 8 + 8 + 4 + 4 + 8
- 5'b01000: wb_dat32_o = {msr,lcr,iir,ier,lsr};
- // 5 + 2 + 5 + 4 + 5 + 3
- 5'b01100: wb_dat32_o = {8'b0, fcr,mcr, rf_count, rstate, tf_count, tstate};
- default: wb_dat32_o = 0;
- endcase // case(wb_adr_i)
-
-endmodule // uart_debug_if
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_wb.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core WISHBONE interface. ////
-//// ////
-//// Known problems (limits): ////
-//// Inserts one wait state on all transfers. ////
-//// Note affected signals and the way they are affected. ////
-//// ////
-//// To Do: ////
-//// Nothing. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2001/05/17 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_wb.v,v $
-// Revision 1.17 2004/05/21 12:35:15 tadejm
-// Added 2 LSB address generation dependent on select lines and LITLE/BIG endian when UART is in 32-bit mode.
-//
-// Revision 1.16 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.15 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.12 2001/12/19 08:03:34 mohor
-// Warnings cleared.
-//
-// Revision 1.11 2001/12/06 14:51:04 gorban
-// Bug in LSR[0] is fixed.
-// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
-//
-// Revision 1.10 2001/12/03 21:44:29 gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.9 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.8 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.7 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.4 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/21 19:12:01 gorban
-// Corrected some Linter messages.
-//
-// Revision 1.2 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:13+02 jacob
-// Initial revision
-//
-//
-
-// UART core WISHBONE interface
-//
-// Author: Jacob Gorban (jacob.gorban@flextronicssemi.com)
-// Company: Flextronics Semiconductor
-//
-
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-`include "uart_defines.v"
-
-module uart_wb (clk, wb_rst_i,
- wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_adr_i,
- wb_adr_int, wb_dat_i, wb_dat_o, wb_dat8_i, wb_dat8_o, wb_dat32_o, wb_sel_i,
- we_o, re_o // Write and read enable output for the core
-);
-
-input clk;
-
-// WISHBONE interface
-input wb_rst_i;
-input wb_we_i;
-input wb_stb_i;
-input wb_cyc_i;
-input [3:0] wb_sel_i;
-input [`UART_ADDR_WIDTH-1:0] wb_adr_i; //WISHBONE address line
-
-`ifdef DATA_BUS_WIDTH_8
-input [7:0] wb_dat_i; //input WISHBONE bus
-output [7:0] wb_dat_o;
-reg [7:0] wb_dat_o;
-wire [7:0] wb_dat_i;
-reg [7:0] wb_dat_is;
-`else // for 32 data bus mode
-input [31:0] wb_dat_i; //input WISHBONE bus
-output [31:0] wb_dat_o;
-reg [31:0] wb_dat_o;
-wire [31:0] wb_dat_i;
-reg [31:0] wb_dat_is;
-`endif // !`ifdef DATA_BUS_WIDTH_8
-
-output [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
-input [7:0] wb_dat8_o; // internal 8 bit output to be put into wb_dat_o
-output [7:0] wb_dat8_i;
-input [31:0] wb_dat32_o; // 32 bit data output (for debug interface)
-output wb_ack_o;
-output we_o;
-output re_o;
-
-wire we_o;
-reg wb_ack_o;
-reg [7:0] wb_dat8_i;
-wire [7:0] wb_dat8_o;
-wire [`UART_ADDR_WIDTH-1:0] wb_adr_int; // internal signal for address bus
-reg [`UART_ADDR_WIDTH-1:0] wb_adr_is;
-reg wb_we_is;
-reg wb_cyc_is;
-reg wb_stb_is;
-reg [3:0] wb_sel_is;
-wire [3:0] wb_sel_i;
-reg wre ;// timing control signal for write or read enable
-
-// wb_ack_o FSM
-reg [1:0] wbstate;
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) begin
- wb_ack_o <= #1 1'b0;
- wbstate <= #1 0;
- wre <= #1 1'b1;
- end else
- case (wbstate)
- 0: begin
- if (wb_stb_is & wb_cyc_is) begin
- wre <= #1 0;
- wbstate <= #1 1;
- wb_ack_o <= #1 1;
- end else begin
- wre <= #1 1;
- wb_ack_o <= #1 0;
- end
- end
- 1: begin
- wb_ack_o <= #1 0;
- wbstate <= #1 2;
- wre <= #1 0;
- end
- 2,3: begin
- wb_ack_o <= #1 0;
- wbstate <= #1 0;
- wre <= #1 0;
- end
- endcase
-
-assign we_o = wb_we_is & wb_stb_is & wb_cyc_is & wre ; //WE for registers
-assign re_o = ~wb_we_is & wb_stb_is & wb_cyc_is & wre ; //RE for registers
-
-// Sample input signals
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i) begin
- wb_adr_is <= #1 0;
- wb_we_is <= #1 0;
- wb_cyc_is <= #1 0;
- wb_stb_is <= #1 0;
- wb_dat_is <= #1 0;
- wb_sel_is <= #1 0;
- end else begin
- wb_adr_is <= #1 wb_adr_i;
- wb_we_is <= #1 wb_we_i;
- wb_cyc_is <= #1 wb_cyc_i;
- wb_stb_is <= #1 wb_stb_i;
- wb_dat_is <= #1 wb_dat_i;
- wb_sel_is <= #1 wb_sel_i;
- end
-
-`ifdef DATA_BUS_WIDTH_8 // 8-bit data bus
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- wb_dat_o <= #1 0;
- else
- wb_dat_o <= #1 wb_dat8_o;
-
-always @(wb_dat_is)
- wb_dat8_i = wb_dat_is;
-
-assign wb_adr_int = wb_adr_is;
-
-`else // 32-bit bus
-// put output to the correct byte in 32 bits using select line
-always @(posedge clk or posedge wb_rst_i)
- if (wb_rst_i)
- wb_dat_o <= #1 0;
- else if (re_o)
- case (wb_sel_is)
- 4'b0001: wb_dat_o <= #1 {24'b0, wb_dat8_o};
- 4'b0010: wb_dat_o <= #1 {16'b0, wb_dat8_o, 8'b0};
- 4'b0100: wb_dat_o <= #1 {8'b0, wb_dat8_o, 16'b0};
- 4'b1000: wb_dat_o <= #1 {wb_dat8_o, 24'b0};
- 4'b1111: wb_dat_o <= #1 wb_dat32_o; // debug interface output
- default: wb_dat_o <= #1 0;
- endcase // case(wb_sel_i)
-
-reg [1:0] wb_adr_int_lsb;
-
-always @(wb_sel_is or wb_dat_is)
-begin
- case (wb_sel_is)
- 4'b0001 : wb_dat8_i = wb_dat_is[7:0];
- 4'b0010 : wb_dat8_i = wb_dat_is[15:8];
- 4'b0100 : wb_dat8_i = wb_dat_is[23:16];
- 4'b1000 : wb_dat8_i = wb_dat_is[31:24];
- default : wb_dat8_i = wb_dat_is[7:0];
- endcase // case(wb_sel_i)
-
- `ifdef LITLE_ENDIAN
- case (wb_sel_is)
- 4'b0001 : wb_adr_int_lsb = 2'h0;
- 4'b0010 : wb_adr_int_lsb = 2'h1;
- 4'b0100 : wb_adr_int_lsb = 2'h2;
- 4'b1000 : wb_adr_int_lsb = 2'h3;
- default : wb_adr_int_lsb = 2'h0;
- endcase // case(wb_sel_i)
- `else
- case (wb_sel_is)
- 4'b0001 : wb_adr_int_lsb = 2'h3;
- 4'b0010 : wb_adr_int_lsb = 2'h2;
- 4'b0100 : wb_adr_int_lsb = 2'h1;
- 4'b1000 : wb_adr_int_lsb = 2'h0;
- default : wb_adr_int_lsb = 2'h0;
- endcase // case(wb_sel_i)
- `endif
-end
-
-assign wb_adr_int = {wb_adr_is[`UART_ADDR_WIDTH-1:2], wb_adr_int_lsb};
-
-`endif // !`ifdef DATA_BUS_WIDTH_8
-
-endmodule
-
-
-
-
-
-
-
-
-
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// uart_top.v ////
-//// ////
-//// ////
-//// This file is part of the "UART 16550 compatible" project ////
-//// http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Documentation related to this project: ////
-//// - http://www.opencores.org/cores/uart16550/ ////
-//// ////
-//// Projects compatibility: ////
-//// - WISHBONE ////
-//// RS232 Protocol ////
-//// 16550D uart (mostly supported) ////
-//// ////
-//// Overview (main Features): ////
-//// UART core top level. ////
-//// ////
-//// Known problems (limits): ////
-//// Note that transmitter and receiver instances are inside ////
-//// the uart_regs.v file. ////
-//// ////
-//// To Do: ////
-//// Nothing so far. ////
-//// ////
-//// Author(s): ////
-//// - gorban@opencores.org ////
-//// - Jacob Gorban ////
-//// - Igor Mohor (igorm@opencores.org) ////
-//// ////
-//// Created: 2001/05/12 ////
-//// Last Updated: 2001/05/17 ////
-//// (See log for the revision history) ////
-//// ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2000, 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: uart_top.v,v $
-// Revision 1.19 2002/07/29 21:16:18 gorban
-// The uart_defines.v file is included again in sources.
-//
-// Revision 1.18 2002/07/22 23:02:23 gorban
-// Bug Fixes:
-// * Possible loss of sync and bad reception of stop bit on slow baud rates fixed.
-// Problem reported by Kenny.Tung.
-// * Bad (or lack of ) loopback handling fixed. Reported by Cherry Withers.
-//
-// Improvements:
-// * Made FIFO's as general inferrable memory where possible.
-// So on FPGA they should be inferred as RAM (Distributed RAM on Xilinx).
-// This saves about 1/3 of the Slice count and reduces P&R and synthesis times.
-//
-// * Added optional baudrate output (baud_o).
-// This is identical to BAUDOUT* signal on 16550 chip.
-// It outputs 16xbit_clock_rate - the divided clock.
-// It's disabled by default. Define UART_HAS_BAUDRATE_OUTPUT to use.
-//
-// Revision 1.17 2001/12/19 08:40:03 mohor
-// Warnings fixed (unused signals removed).
-//
-// Revision 1.16 2001/12/06 14:51:04 gorban
-// Bug in LSR[0] is fixed.
-// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
-//
-// Revision 1.15 2001/12/03 21:44:29 gorban
-// Updated specification documentation.
-// Added full 32-bit data bus interface, now as default.
-// Address is 5-bit wide in 32-bit data bus mode.
-// Added wb_sel_i input to the core. It's used in the 32-bit mode.
-// Added debug interface with two 32-bit read-only registers in 32-bit mode.
-// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
-// My small test bench is modified to work with 32-bit mode.
-//
-// Revision 1.14 2001/11/07 17:51:52 gorban
-// Heavily rewritten interrupt and LSR subsystems.
-// Many bugs hopefully squashed.
-//
-// Revision 1.13 2001/10/20 09:58:40 gorban
-// Small synopsis fixes
-//
-// Revision 1.12 2001/08/25 15:46:19 gorban
-// Modified port names again
-//
-// Revision 1.11 2001/08/24 21:01:12 mohor
-// Things connected to parity changed.
-// Clock devider changed.
-//
-// Revision 1.10 2001/08/23 16:05:05 mohor
-// Stop bit bug fixed.
-// Parity bug fixed.
-// WISHBONE read cycle bug fixed,
-// OE indicator (Overrun Error) bug fixed.
-// PE indicator (Parity Error) bug fixed.
-// Register read bug fixed.
-//
-// Revision 1.4 2001/05/31 20:08:01 gorban
-// FIFO changes and other corrections.
-//
-// Revision 1.3 2001/05/21 19:12:02 gorban
-// Corrected some Linter messages.
-//
-// Revision 1.2 2001/05/17 18:34:18 gorban
-// First 'stable' release. Should be sythesizable now. Also added new header.
-//
-// Revision 1.0 2001-05-17 21:27:12+02 jacob
-// Initial revision
-//
-//
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
-`include "uart_defines.v"
-
-module uart_top (
- wb_clk_i,
-
- // Wishbone signals
- wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_stb_i, wb_cyc_i, wb_ack_o, wb_sel_i,
- int_o, // interrupt request
-
- // UART signals
- // serial input/output
- stx_pad_o, srx_pad_i,
-
- // modem signals
- rts_pad_o, cts_pad_i, dtr_pad_o, dsr_pad_i, ri_pad_i, dcd_pad_i
-`ifdef UART_HAS_BAUDRATE_OUTPUT
- , baud_o
-`endif
- );
-
-parameter uart_data_width = `UART_DATA_WIDTH;
-parameter uart_addr_width = `UART_ADDR_WIDTH;
-
-input wb_clk_i;
-
-// WISHBONE interface
-input wb_rst_i;
-input [uart_addr_width-1:0] wb_adr_i;
-input [uart_data_width-1:0] wb_dat_i;
-output [uart_data_width-1:0] wb_dat_o;
-input wb_we_i;
-input wb_stb_i;
-input wb_cyc_i;
-input [3:0] wb_sel_i;
-output wb_ack_o;
-output int_o;
-
-// UART signals
-input srx_pad_i;
-output stx_pad_o;
-output rts_pad_o;
-input cts_pad_i;
-output dtr_pad_o;
-input dsr_pad_i;
-input ri_pad_i;
-input dcd_pad_i;
-
-// optional baudrate output
-`ifdef UART_HAS_BAUDRATE_OUTPUT
-output baud_o;
-`endif
-
-
-wire stx_pad_o;
-wire rts_pad_o;
-wire dtr_pad_o;
-
-wire [uart_addr_width-1:0] wb_adr_i;
-wire [uart_data_width-1:0] wb_dat_i;
-wire [uart_data_width-1:0] wb_dat_o;
-
-wire [7:0] wb_dat8_i; // 8-bit internal data input
-wire [7:0] wb_dat8_o; // 8-bit internal data output
-wire [31:0] wb_dat32_o; // debug interface 32-bit output
-wire [3:0] wb_sel_i; // WISHBONE select signal
-wire [uart_addr_width-1:0] wb_adr_int;
-wire we_o; // Write enable for registers
-wire re_o; // Read enable for registers
-//
-// MODULE INSTANCES
-//
-
-`ifdef DATA_BUS_WIDTH_8
-`else
-// debug interface wires
-wire [3:0] ier;
-wire [3:0] iir;
-wire [1:0] fcr;
-wire [4:0] mcr;
-wire [7:0] lcr;
-wire [7:0] msr;
-wire [7:0] lsr;
-wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
-wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
-wire [2:0] tstate;
-wire [3:0] rstate;
-`endif
-
-`ifdef DATA_BUS_WIDTH_8
-//// WISHBONE interface module
-uart_wb wb_interface(
- .clk( wb_clk_i ),
- .wb_rst_i( wb_rst_i ),
- .wb_dat_i(wb_dat_i),
- .wb_dat_o(wb_dat_o),
- .wb_dat8_i(wb_dat8_i),
- .wb_dat8_o(wb_dat8_o),
- .wb_dat32_o(32'b0),
- .wb_sel_i(4'b0),
- .wb_we_i( wb_we_i ),
- .wb_stb_i( wb_stb_i ),
- .wb_cyc_i( wb_cyc_i ),
- .wb_ack_o( wb_ack_o ),
- .wb_adr_i(wb_adr_i),
- .wb_adr_int(wb_adr_int),
- .we_o( we_o ),
- .re_o(re_o)
- );
-`else
-uart_wb wb_interface(
- .clk( wb_clk_i ),
- .wb_rst_i( wb_rst_i ),
- .wb_dat_i(wb_dat_i),
- .wb_dat_o(wb_dat_o),
- .wb_dat8_i(wb_dat8_i),
- .wb_dat8_o(wb_dat8_o),
- .wb_sel_i(wb_sel_i),
- .wb_dat32_o(wb_dat32_o),
- .wb_we_i( wb_we_i ),
- .wb_stb_i( wb_stb_i ),
- .wb_cyc_i( wb_cyc_i ),
- .wb_ack_o( wb_ack_o ),
- .wb_adr_i(wb_adr_i),
- .wb_adr_int(wb_adr_int),
- .we_o( we_o ),
- .re_o(re_o)
- );
-`endif
-
-// Registers
-uart_regs regs(
- .clk( wb_clk_i ),
- .wb_rst_i( wb_rst_i ),
- .wb_addr_i( wb_adr_int ),
- .wb_dat_i( wb_dat8_i ),
- .wb_dat_o( wb_dat8_o ),
- .wb_we_i( we_o ),
- .wb_re_i(re_o),
- .modem_inputs( {cts_pad_i, dsr_pad_i,
- ri_pad_i, dcd_pad_i} ),
- .stx_pad_o( stx_pad_o ),
- .srx_pad_i( srx_pad_i ),
-`ifdef DATA_BUS_WIDTH_8
-`else
-// debug interface signals enabled
-.ier(ier),
-.iir(iir),
-.fcr(fcr),
-.mcr(mcr),
-.lcr(lcr),
-.msr(msr),
-.lsr(lsr),
-.rf_count(rf_count),
-.tf_count(tf_count),
-.tstate(tstate),
-.rstate(rstate),
-`endif
- .rts_pad_o( rts_pad_o ),
- .dtr_pad_o( dtr_pad_o ),
- .int_o( int_o )
-`ifdef UART_HAS_BAUDRATE_OUTPUT
- , .baud_o(baud_o)
-`endif
-
-);
-
-`ifdef DATA_BUS_WIDTH_8
-`else
-uart_debug_if dbg(/*AUTOINST*/
- // Outputs
- .wb_dat32_o (wb_dat32_o[31:0]),
- // Inputs
- .wb_adr_i (wb_adr_int[`UART_ADDR_WIDTH-1:0]),
- .ier (ier[3:0]),
- .iir (iir[3:0]),
- .fcr (fcr[1:0]),
- .mcr (mcr[4:0]),
- .lcr (lcr[7:0]),
- .msr (msr[7:0]),
- .lsr (lsr[7:0]),
- .rf_count (rf_count[`UART_FIFO_COUNTER_W-1:0]),
- .tf_count (tf_count[`UART_FIFO_COUNTER_W-1:0]),
- .tstate (tstate[2:0]),
- .rstate (rstate[3:0]));
-`endif
-
-initial
-begin
- `ifdef DATA_BUS_WIDTH_8
- $display("(%m) UART INFO: Data bus width is 8. No Debug interface.\n");
- `else
- $display("(%m) UART INFO: Data bus width is 32. Debug Interface present.\n");
- `endif
- `ifdef UART_HAS_BAUDRATE_OUTPUT
- $display("(%m) UART INFO: Has baudrate output\n");
- `else
- $display("(%m) UART INFO: Doesn't have baudrate output\n");
- `endif
-end
-
-endmodule
-
-
orpsocv2/rtl/verilog/components/uart16550/uart_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v
===================================================================
--- orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v (revision 54)
+++ orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v (nonexistent)
@@ -1,10026 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_clockgen.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_clockgen.v,v $
-// Revision 1.4 2005/02/21 12:48:05 igorm
-// Warning fixes.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:55 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-module eth_clockgen(Clk, Reset, Divider, MdcEn, MdcEn_n, Mdc);
-
-parameter Tp=1;
-
-input Clk; // Input clock (Host clock)
-input Reset; // Reset signal
-input [7:0] Divider; // Divider (input clock will be divided by the Divider[7:0])
-
-output Mdc; // Output clock
-output MdcEn; // Enable signal is asserted for one Clk period before Mdc rises.
-output MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
-
-reg Mdc;
-reg [7:0] Counter;
-
-wire CountEq0;
-wire [7:0] CounterPreset;
-wire [7:0] TempDivider;
-
-
-assign TempDivider[7:0] = (Divider[7:0]<2)? 8'h02 : Divider[7:0]; // If smaller than 2
-assign CounterPreset[7:0] = (TempDivider[7:0]>>1) - 1'b1; // We are counting half of period
-
-
-// Counter counts half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Counter[7:0] <= #Tp 8'h1;
- else
- begin
- if(CountEq0)
- begin
- Counter[7:0] <= #Tp CounterPreset[7:0];
- end
- else
- Counter[7:0] <= #Tp Counter - 8'h1;
- end
-end
-
-
-// Mdc is asserted every other half period
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Mdc <= #Tp 1'b0;
- else
- begin
- if(CountEq0)
- Mdc <= #Tp ~Mdc;
- end
-end
-
-
-assign CountEq0 = Counter == 8'h0;
-assign MdcEn = CountEq0 & ~Mdc;
-assign MdcEn_n = CountEq0 & Mdc;
-
-endmodule
-
-
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_crc.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_crc.v,v $
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-
-`include "timescale.v"
-
-module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);
-
-
-parameter Tp = 1;
-
-input Clk;
-input Reset;
-input [3:0] Data;
-input Enable;
-input Initialize;
-
-output [31:0] Crc;
-output CrcError;
-
-reg [31:0] Crc;
-
-wire [31:0] CrcNext;
-
-
-assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);
-assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);
-assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);
-assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);
-assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];
-assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];
-assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];
-assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];
-assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];
-assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];
-assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];
-assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];
-assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];
-assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];
-assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];
-assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];
-assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];
-assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];
-assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];
-assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];
-assign CrcNext[20] = Crc[16];
-assign CrcNext[21] = Crc[17];
-assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];
-assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];
-assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];
-assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];
-assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];
-assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];
-assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];
-assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];
-assign CrcNext[30] = Crc[26];
-assign CrcNext[31] = Crc[27];
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if (Reset)
- Crc <= #1 32'hffffffff;
- else
- if(Initialize)
- Crc <= #Tp 32'hffffffff;
- else
- Crc <= #Tp CrcNext;
-end
-
-assign CrcError = Crc[31:0] != 32'hc704dd7b; // CRC not equal to magic number
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_fifo.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_fifo.v,v $
-// Revision 1.4 2005/02/21 12:48:07 igorm
-// Warning fixes.
-//
-// Revision 1.3 2002/04/22 13:45:52 mohor
-// Generic ram or Xilinx ram can be used in fifo (selectable by setting
-// ETH_FIFO_XILINX in eth_defines.v).
-//
-// Revision 1.2 2002/03/25 13:33:04 mohor
-// When clear and read/write are active at the same time, cnt and pointers are
-// set to 1.
-//
-// Revision 1.1 2002/02/05 16:44:39 mohor
-// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
-// MHz. Statuses, overrun, control frame transmission and reception still need
-// to be fixed.
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-module eth_fifo (data_in, data_out, clk, reset, write, read, clear, almost_full, full, almost_empty, empty, cnt);
-
-parameter DATA_WIDTH = 32;
-parameter DEPTH = 8;
-parameter CNT_WIDTH = 4;
-
-parameter Tp = 1;
-
-input clk;
-input reset;
-input write;
-input read;
-input clear;
-input [DATA_WIDTH-1:0] data_in;
-
-output [DATA_WIDTH-1:0] data_out;
-output almost_full;
-output full;
-output almost_empty;
-output empty;
-output [CNT_WIDTH-1:0] cnt;
-
-`ifdef ETH_FIFO_XILINX
-`else
- `ifdef ETH_ALTERA_ALTSYNCRAM
- `else
- reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1];
-// reg [DATA_WIDTH-1:0] data_out;
- `endif
-`endif
-
-reg [CNT_WIDTH-1:0] cnt;
-reg [CNT_WIDTH-2:0] read_pointer;
-reg [CNT_WIDTH-2:0] write_pointer;
-
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- cnt <=#Tp 0;
- else
- if(clear)
- cnt <=#Tp { {(CNT_WIDTH-1){1'b0}}, read^write};
- else
- if(read ^ write)
- if(read)
- cnt <=#Tp cnt - 1'b1;
- else
- cnt <=#Tp cnt + 1'b1;
-end
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- read_pointer <=#Tp 0;
- else
- if(clear)
- read_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, read};
- else
- if(read & ~empty)
- read_pointer <=#Tp read_pointer + 1'b1;
-end
-
-always @ (posedge clk or posedge reset)
-begin
- if(reset)
- write_pointer <=#Tp 0;
- else
- if(clear)
- write_pointer <=#Tp { {(CNT_WIDTH-2){1'b0}}, write};
- else
- if(write & ~full)
- write_pointer <=#Tp write_pointer + 1'b1;
-end
-
-assign empty = ~(|cnt);
-assign almost_empty = cnt == 1;
-assign full = cnt == DEPTH;
-assign almost_full = &cnt[CNT_WIDTH-2:0];
-
-
-
-`ifdef ETH_FIFO_XILINX
- xilinx_dist_ram_16x32 fifo
- ( .data_out(data_out),
- .we(write & ~full),
- .data_in(data_in),
- .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer),
- .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
- .wclk(clk)
- );
-`else // !ETH_FIFO_XILINX
-`ifdef ETH_ALTERA_ALTSYNCRAM
- altera_dpram_16x32 altera_dpram_16x32_inst
- (
- .data (data_in),
- .wren (write & ~full),
- .wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
- .rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
- .clock (clk),
- .q (data_out)
- ); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
-`else // !ETH_ALTERA_ALTSYNCRAM
-
- wire [CNT_WIDTH-2:0] waddr, raddr;
- reg [CNT_WIDTH-2:0] raddr_reg;
- wire we;
-
- assign waddr = clear ? {CNT_WIDTH-1{1'b0}} : write_pointer;
- assign raddr = clear ? {CNT_WIDTH-1{1'b0}} : read_pointer;
-
- assign we = (write & clear) | (write & ~full);
-
- always @ (posedge clk)
- if (we)
- fifo[waddr] <= #Tp data_in;
-
- always @ (posedge clk)
- raddr_reg <= raddr;
-
- assign #Tp data_out = fifo[raddr_reg];
-
-
- /*
- always @ (posedge clk)
- begin
- if(write & clear)
- fifo[0] <=#Tp data_in;
- else
- if(write & ~full)
- fifo[write_pointer] <=#Tp data_in;
- end
-
-
- always @ (posedge clk)
- begin
- if(clear)
- data_out <=#Tp fifo[0];
- else
- data_out <=#Tp fifo[read_pointer];
- end
- */
-`endif // !ETH_ALTERA_ALTSYNCRAM
-`endif // !ETH_FIFO_XILINX
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_maccontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_maccontrol.v,v $
-// Revision 1.7 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.6 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.5 2002/11/21 00:14:39 mohor
-// TxDone and TxAbort changed so they're not propagated to the wishbone
-// module when control frame is transmitted.
-//
-// Revision 1.4 2002/11/19 17:37:32 mohor
-// When control frame (PAUSE) was sent, status was written in the
-// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
-// Only TXC interrupt is set.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_maccontrol (MTxClk, MRxClk, TxReset, RxReset, TPauseRq, TxDataIn, TxStartFrmIn, TxUsedDataIn,
- TxEndFrmIn, TxDoneIn, TxAbortIn, RxData, RxValid, RxStartFrm, RxEndFrm, ReceiveEnd,
- ReceivedPacketGood, ReceivedLengthOK, TxFlow, RxFlow, DlyCrcEn, TxPauseTV,
- MAC, PadIn, PadOut, CrcEnIn, CrcEnOut, TxDataOut, TxStartFrmOut, TxEndFrmOut,
- TxDoneOut, TxAbortOut, TxUsedDataOut, WillSendControlFrame, TxCtrlEndFrm,
- ReceivedPauseFrm, ControlFrmAddressOK, SetPauseTimer, r_PassAll, RxStatusWriteLatched_sync2
- );
-
-
-parameter Tp = 1;
-
-
-input MTxClk; // Transmit clock (from PHY)
-input MRxClk; // Receive clock (from PHY)
-input TxReset; // Transmit reset
-input RxReset; // Receive reset
-input TPauseRq; // Transmit control frame (from host)
-input [7:0] TxDataIn; // Transmit packet data byte (from host)
-input TxStartFrmIn; // Transmit packet start frame input (from host)
-input TxUsedDataIn; // Transmit packet used data (from TxEthMAC)
-input TxEndFrmIn; // Transmit packet end frame input (from host)
-input TxDoneIn; // Transmit packet done (from TxEthMAC)
-input TxAbortIn; // Transmit packet abort (input from TxEthMAC)
-input PadIn; // Padding (input from registers)
-input CrcEnIn; // Crc append (input from registers)
-input [7:0] RxData; // Receive Packet Data (from RxEthMAC)
-input RxValid; // Received a valid packet
-input RxStartFrm; // Receive packet start frame (input from RxEthMAC)
-input RxEndFrm; // Receive packet end frame (input from RxEthMAC)
-input ReceiveEnd; // End of receiving of the current packet (input from RxEthMAC)
-input ReceivedPacketGood; // Received packet is good
-input ReceivedLengthOK; // Length of the received packet is OK
-input TxFlow; // Tx flow control (from registers)
-input RxFlow; // Rx flow control (from registers)
-input DlyCrcEn; // Delayed CRC enabled (from registers)
-input [15:0] TxPauseTV; // Transmit Pause Timer Value (from registers)
-input [47:0] MAC; // MAC address (from registers)
-input RxStatusWriteLatched_sync2;
-input r_PassAll;
-
-output [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
-output TxStartFrmOut; // Transmit packet start frame (output to TxEthMAC)
-output TxEndFrmOut; // Transmit packet end frame (output to TxEthMAC)
-output TxDoneOut; // Transmit packet done (to host)
-output TxAbortOut; // Transmit packet aborted (to host)
-output TxUsedDataOut; // Transmit packet used data (to host)
-output PadOut; // Padding (output to TxEthMAC)
-output CrcEnOut; // Crc append (output to TxEthMAC)
-output WillSendControlFrame;
-output TxCtrlEndFrm;
-output ReceivedPauseFrm;
-output ControlFrmAddressOK;
-output SetPauseTimer;
-
-reg TxUsedDataOutDetected;
-reg TxAbortInLatched;
-reg TxDoneInLatched;
-reg MuxedDone;
-reg MuxedAbort;
-
-wire Pause;
-wire TxCtrlStartFrm;
-wire [7:0] ControlData;
-wire CtrlMux;
-wire SendingCtrlFrm; // Sending Control Frame (enables padding and CRC)
-wire BlockTxDone;
-
-
-// Signal TxUsedDataOut was detected (a transfer is already in progress)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxUsedDataOutDetected <= #Tp 1'b0;
- else
- if(TxDoneIn | TxAbortIn)
- TxUsedDataOutDetected <= #Tp 1'b0;
- else
- if(TxUsedDataOut)
- TxUsedDataOutDetected <= #Tp 1'b1;
-end
-
-
-// Latching variables
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- begin
- TxAbortInLatched <= #Tp 1'b0;
- TxDoneInLatched <= #Tp 1'b0;
- end
- else
- begin
- TxAbortInLatched <= #Tp TxAbortIn;
- TxDoneInLatched <= #Tp TxDoneIn;
- end
-end
-
-
-
-// Generating muxed abort signal
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- MuxedAbort <= #Tp 1'b0;
- else
- if(TxStartFrmIn)
- MuxedAbort <= #Tp 1'b0;
- else
- if(TxAbortIn & ~TxAbortInLatched & TxUsedDataOutDetected)
- MuxedAbort <= #Tp 1'b1;
-end
-
-
-// Generating muxed done signal
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- MuxedDone <= #Tp 1'b0;
- else
- if(TxStartFrmIn)
- MuxedDone <= #Tp 1'b0;
- else
- if(TxDoneIn & (~TxDoneInLatched) & TxUsedDataOutDetected)
- MuxedDone <= #Tp 1'b1;
-end
-
-
-// TxDoneOut
-assign TxDoneOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedDone) :
- ((~TxStartFrmIn) & (~BlockTxDone) & TxDoneIn);
-
-// TxAbortOut
-assign TxAbortOut = CtrlMux? ((~TxStartFrmIn) & (~BlockTxDone) & MuxedAbort) :
- ((~TxStartFrmIn) & (~BlockTxDone) & TxAbortIn);
-
-// TxUsedDataOut
-assign TxUsedDataOut = ~CtrlMux & TxUsedDataIn;
-
-// TxStartFrmOut
-assign TxStartFrmOut = CtrlMux? TxCtrlStartFrm : (TxStartFrmIn & ~Pause);
-
-
-// TxEndFrmOut
-assign TxEndFrmOut = CtrlMux? TxCtrlEndFrm : TxEndFrmIn;
-
-
-// TxDataOut[7:0]
-assign TxDataOut[7:0] = CtrlMux? ControlData[7:0] : TxDataIn[7:0];
-
-
-// PadOut
-assign PadOut = PadIn | SendingCtrlFrm;
-
-
-// CrcEnOut
-assign CrcEnOut = CrcEnIn | SendingCtrlFrm;
-
-
-
-// Connecting receivecontrol module
-eth_receivecontrol receivecontrol1
-(
- .MTxClk(MTxClk), .MRxClk(MRxClk), .TxReset(TxReset), .RxReset(RxReset), .RxData(RxData),
- .RxValid(RxValid), .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm), .RxFlow(RxFlow),
- .ReceiveEnd(ReceiveEnd), .MAC(MAC), .DlyCrcEn(DlyCrcEn), .TxDoneIn(TxDoneIn),
- .TxAbortIn(TxAbortIn), .TxStartFrmOut(TxStartFrmOut), .ReceivedLengthOK(ReceivedLengthOK),
- .ReceivedPacketGood(ReceivedPacketGood), .TxUsedDataOutDetected(TxUsedDataOutDetected),
- .Pause(Pause), .ReceivedPauseFrm(ReceivedPauseFrm), .AddressOK(ControlFrmAddressOK),
- .r_PassAll(r_PassAll), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .SetPauseTimer(SetPauseTimer)
-);
-
-
-eth_transmitcontrol transmitcontrol1
-(
- .MTxClk(MTxClk), .TxReset(TxReset), .TxUsedDataIn(TxUsedDataIn), .TxUsedDataOut(TxUsedDataOut),
- .TxDoneIn(TxDoneIn), .TxAbortIn(TxAbortIn), .TxStartFrmIn(TxStartFrmIn), .TPauseRq(TPauseRq),
- .TxUsedDataOutDetected(TxUsedDataOutDetected), .TxFlow(TxFlow), .DlyCrcEn(DlyCrcEn), .TxPauseTV(TxPauseTV),
- .MAC(MAC), .TxCtrlStartFrm(TxCtrlStartFrm), .TxCtrlEndFrm(TxCtrlEndFrm), .SendingCtrlFrm(SendingCtrlFrm),
- .CtrlMux(CtrlMux), .ControlData(ControlData), .WillSendControlFrame(WillSendControlFrame), .BlockTxDone(BlockTxDone)
-);
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_macstatus.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_macstatus.v,v $
-// Revision 1.17 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.16 2005/02/21 10:42:11 igorm
-// Defer indication fixed.
-//
-// Revision 1.15 2003/01/30 13:28:19 tadejm
-// Defer indication changed.
-//
-// Revision 1.14 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.13 2002/11/13 22:30:58 tadejm
-// Late collision is reported only when not in the full duplex.
-// Sample is taken (for status) as soon as MRxDV is not valid (regardless
-// of the received byte cnt).
-//
-// Revision 1.12 2002/09/12 14:50:16 mohor
-// CarrierSenseLost bug fixed when operating in full duplex mode.
-//
-// Revision 1.11 2002/09/04 18:38:03 mohor
-// CarrierSenseLost status is not set when working in loopback mode.
-//
-// Revision 1.10 2002/07/25 18:17:46 mohor
-// InvalidSymbol generation changed.
-//
-// Revision 1.9 2002/04/22 13:51:44 mohor
-// Short frame and ReceivedLengthOK were not detected correctly.
-//
-// Revision 1.8 2002/02/18 10:40:17 mohor
-// Small fixes.
-//
-// Revision 1.7 2002/02/15 17:07:39 mohor
-// Status was not written correctly when frames were discarted because of
-// address mismatch.
-//
-// Revision 1.6 2002/02/11 09:18:21 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.5 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_macstatus(
- MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
- MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
- RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
- InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
- r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
- LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
- RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
- StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
- r_FullD
- );
-
-
-
-parameter Tp = 1;
-
-
-input MRxClk;
-input Reset;
-input RxCrcError;
-input MRxErr;
-input MRxDV;
-
-input RxStateSFD;
-input [1:0] RxStateData;
-input RxStatePreamble;
-input RxStateIdle;
-input Transmitting;
-input [15:0] RxByteCnt;
-input RxByteCntEq0;
-input RxByteCntGreat2;
-input RxByteCntMaxFrame;
-input [3:0] MRxD;
-input Collision;
-input [5:0] CollValid;
-input r_RecSmall;
-input [15:0] r_MinFL;
-input [15:0] r_MaxFL;
-input r_HugEn;
-input StartTxDone;
-input StartTxAbort;
-input [3:0] RetryCnt;
-input MTxClk;
-input MaxCollisionOccured;
-input LateCollision;
-input DeferIndication;
-input TxStartFrm;
-input StatePreamble;
-input [1:0] StateData;
-input CarrierSense;
-input TxUsedData;
-input Loopback;
-input r_FullD;
-
-
-output ReceivedLengthOK;
-output ReceiveEnd;
-output ReceivedPacketGood;
-output InvalidSymbol;
-output LatchedCrcError;
-output RxLateCollision;
-output ShortFrame;
-output DribbleNibble;
-output ReceivedPacketTooBig;
-output LoadRxStatus;
-output [3:0] RetryCntLatched;
-output RetryLimit;
-output LateCollLatched;
-output DeferLatched;
-input RstDeferLatched;
-output CarrierSenseLost;
-output LatchedMRxErr;
-
-
-reg ReceiveEnd;
-
-reg LatchedCrcError;
-reg LatchedMRxErr;
-reg LoadRxStatus;
-reg InvalidSymbol;
-reg [3:0] RetryCntLatched;
-reg RetryLimit;
-reg LateCollLatched;
-reg DeferLatched;
-reg CarrierSenseLost;
-
-wire TakeSample;
-wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps
-
-// Crc error
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedCrcError <=#Tp 1'b0;
- else
- if(RxStateSFD)
- LatchedCrcError <=#Tp 1'b0;
- else
- if(RxStateData[0])
- LatchedCrcError <=#Tp RxCrcError & ~RxByteCntEq0;
-end
-
-
-// LatchedMRxErr
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedMRxErr <=#Tp 1'b0;
- else
- if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
- LatchedMRxErr <=#Tp 1'b1;
- else
- LatchedMRxErr <=#Tp 1'b0;
-end
-
-
-// ReceivedPacketGood
-assign ReceivedPacketGood = ~LatchedCrcError;
-
-
-// ReceivedLengthOK
-assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
-
-
-
-
-
-// Time to take a sample
-//assign TakeSample = |RxStateData & ~MRxDV & RxByteCntGreat2 |
-assign TakeSample = (|RxStateData) & (~MRxDV) |
- RxStateData[0] & MRxDV & RxByteCntMaxFrame;
-
-
-// LoadRxStatus
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LoadRxStatus <=#Tp 1'b0;
- else
- LoadRxStatus <=#Tp TakeSample;
-end
-
-
-
-// ReceiveEnd
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ReceiveEnd <=#Tp 1'b0;
- else
- ReceiveEnd <=#Tp LoadRxStatus;
-end
-
-
-// Invalid Symbol received during 100Mbps mode
-assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
-
-
-// InvalidSymbol
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- InvalidSymbol <=#Tp 1'b0;
- else
- if(LoadRxStatus & ~SetInvalidSymbol)
- InvalidSymbol <=#Tp 1'b0;
- else
- if(SetInvalidSymbol)
- InvalidSymbol <=#Tp 1'b1;
-end
-
-
-// Late Collision
-
-reg RxLateCollision;
-reg RxColWindow;
-// Collision Window
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxLateCollision <=#Tp 1'b0;
- else
- if(LoadRxStatus)
- RxLateCollision <=#Tp 1'b0;
- else
- if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
- RxLateCollision <=#Tp 1'b1;
-end
-
-// Collision Window
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxColWindow <=#Tp 1'b1;
- else
- if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
- RxColWindow <=#Tp 1'b0;
- else
- if(RxStateIdle)
- RxColWindow <=#Tp 1'b1;
-end
-
-
-// ShortFrame
-reg ShortFrame;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShortFrame <=#Tp 1'b0;
- else
- if(LoadRxStatus)
- ShortFrame <=#Tp 1'b0;
- else
- if(TakeSample)
- ShortFrame <=#Tp RxByteCnt[15:0] < r_MinFL[15:0];
-end
-
-
-// DribbleNibble
-reg DribbleNibble;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- DribbleNibble <=#Tp 1'b0;
- else
- if(RxStateSFD)
- DribbleNibble <=#Tp 1'b0;
- else
- if(~MRxDV & RxStateData[1])
- DribbleNibble <=#Tp 1'b1;
-end
-
-
-reg ReceivedPacketTooBig;
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ReceivedPacketTooBig <=#Tp 1'b0;
- else
- if(LoadRxStatus)
- ReceivedPacketTooBig <=#Tp 1'b0;
- else
- if(TakeSample)
- ReceivedPacketTooBig <=#Tp ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
-end
-
-
-
-// Latched Retry counter for tx status
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryCntLatched <=#Tp 4'h0;
- else
- if(StartTxDone | StartTxAbort)
- RetryCntLatched <=#Tp RetryCnt;
-end
-
-
-// Latched Retransmission limit
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryLimit <=#Tp 1'h0;
- else
- if(StartTxDone | StartTxAbort)
- RetryLimit <=#Tp MaxCollisionOccured;
-end
-
-
-// Latched Late Collision
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- LateCollLatched <=#Tp 1'b0;
- else
- if(StartTxDone | StartTxAbort)
- LateCollLatched <=#Tp LateCollision;
-end
-
-
-
-// Latched Defer state
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- DeferLatched <=#Tp 1'b0;
- else
- if(DeferIndication)
- DeferLatched <=#Tp 1'b1;
- else
- if(RstDeferLatched)
- DeferLatched <=#Tp 1'b0;
-end
-
-
-// CarrierSenseLost
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- CarrierSenseLost <=#Tp 1'b0;
- else
- if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
- CarrierSenseLost <=#Tp 1'b1;
- else
- if(TxStartFrm)
- CarrierSenseLost <=#Tp 1'b0;
-end
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_miim.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_miim.v,v $
-// Revision 1.7 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.6 2005/02/21 12:48:07 igorm
-// Warning fixes.
-//
-// Revision 1.5 2003/05/16 10:08:27 mohor
-// Busy was set 2 cycles too late. Reported by Dennis Scott.
-//
-// Revision 1.4 2002/08/14 18:32:10 mohor
-// - Busy signal was not set on time when scan status operation was performed
-// and clock was divided with more than 2.
-// - Nvalid remains valid two more clocks (was previously cleared too soon).
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-
-module eth_miim
-(
- Clk,
- Reset,
- Divider,
- NoPre,
- CtrlData,
- Rgad,
- Fiad,
- WCtrlData,
- RStat,
- ScanStat,
- Mdi,
- Mdo,
- MdoEn,
- Mdc,
- Busy,
- Prsd,
- LinkFail,
- Nvalid,
- WCtrlDataStart,
- RStatStart,
- UpdateMIIRX_DATAReg
-);
-
-
-
-input Clk; // Host Clock
-input Reset; // General Reset
-input [7:0] Divider; // Divider for the host clock
-input [15:0] CtrlData; // Control Data (to be written to the PHY reg.)
-input [4:0] Rgad; // Register Address (within the PHY)
-input [4:0] Fiad; // PHY Address
-input NoPre; // No Preamble (no 32-bit preamble)
-input WCtrlData; // Write Control Data operation
-input RStat; // Read Status operation
-input ScanStat; // Scan Status operation
-input Mdi; // MII Management Data In
-
-output Mdc; // MII Management Data Clock
-output Mdo; // MII Management Data Output
-output MdoEn; // MII Management Data Output Enable
-output Busy; // Busy Signal
-output LinkFail; // Link Integrity Signal
-output Nvalid; // Invalid Status (qualifier for the valid scan result)
-
-output [15:0] Prsd; // Read Status Data (data read from the PHY)
-
-output WCtrlDataStart; // This signals resets the WCTRLDATA bit in the MIIM Command register
-output RStatStart; // This signal resets the RSTAT BIT in the MIIM Command register
-output UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
-
-parameter Tp = 1;
-
-
-reg Nvalid;
-reg EndBusy_d; // Pre-end Busy signal
-reg EndBusy; // End Busy signal (stops the operation in progress)
-
-reg WCtrlData_q1; // Write Control Data operation delayed 1 Clk cycle
-reg WCtrlData_q2; // Write Control Data operation delayed 2 Clk cycles
-reg WCtrlData_q3; // Write Control Data operation delayed 3 Clk cycles
-reg WCtrlDataStart; // Start Write Control Data Command (positive edge detected)
-reg WCtrlDataStart_q;
-reg WCtrlDataStart_q1; // Start Write Control Data Command delayed 1 Mdc cycle
-reg WCtrlDataStart_q2; // Start Write Control Data Command delayed 2 Mdc cycles
-
-reg RStat_q1; // Read Status operation delayed 1 Clk cycle
-reg RStat_q2; // Read Status operation delayed 2 Clk cycles
-reg RStat_q3; // Read Status operation delayed 3 Clk cycles
-reg RStatStart; // Start Read Status Command (positive edge detected)
-reg RStatStart_q1; // Start Read Status Command delayed 1 Mdc cycle
-reg RStatStart_q2; // Start Read Status Command delayed 2 Mdc cycles
-
-reg ScanStat_q1; // Scan Status operation delayed 1 cycle
-reg ScanStat_q2; // Scan Status operation delayed 2 cycles
-reg SyncStatMdcEn; // Scan Status operation delayed at least cycles and synchronized to MdcEn
-
-wire WriteDataOp; // Write Data Operation (positive edge detected)
-wire ReadStatusOp; // Read Status Operation (positive edge detected)
-wire ScanStatusOp; // Scan Status Operation (positive edge detected)
-wire StartOp; // Start Operation (start of any of the preceding operations)
-wire EndOp; // End of Operation
-
-reg InProgress; // Operation in progress
-reg InProgress_q1; // Operation in progress delayed 1 Mdc cycle
-reg InProgress_q2; // Operation in progress delayed 2 Mdc cycles
-reg InProgress_q3; // Operation in progress delayed 3 Mdc cycles
-
-reg WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
-reg [6:0] BitCounter; // Bit Counter
-
-
-wire [3:0] ByteSelect; // Byte Select defines which byte (preamble, data, operation, etc.) is loaded and shifted through the shift register.
-wire MdcEn; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc rises.
-wire ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
-wire MdcEn_n;
-
-wire LatchByte1_d2;
-wire LatchByte0_d2;
-reg LatchByte1_d;
-reg LatchByte0_d;
-reg [1:0] LatchByte; // Latch Byte selects which part of Read Status Data is updated from the shift register
-
-reg UpdateMIIRX_DATAReg;// Updates MII RX_DATA register with read data
-
-
-
-
-
-// Generation of the EndBusy signal. It is used for ending the MII Management operation.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- EndBusy_d <= #Tp 1'b0;
- EndBusy <= #Tp 1'b0;
- end
- else
- begin
- EndBusy_d <= #Tp ~InProgress_q2 & InProgress_q3;
- EndBusy <= #Tp EndBusy_d;
- end
-end
-
-
-// Update MII RX_DATA register
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- UpdateMIIRX_DATAReg <= #Tp 0;
- else
- if(EndBusy & ~WCtrlDataStart_q)
- UpdateMIIRX_DATAReg <= #Tp 1;
- else
- UpdateMIIRX_DATAReg <= #Tp 0;
-end
-
-
-
-// Generation of the delayed signals used for positive edge triggering.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlData_q1 <= #Tp 1'b0;
- WCtrlData_q2 <= #Tp 1'b0;
- WCtrlData_q3 <= #Tp 1'b0;
-
- RStat_q1 <= #Tp 1'b0;
- RStat_q2 <= #Tp 1'b0;
- RStat_q3 <= #Tp 1'b0;
-
- ScanStat_q1 <= #Tp 1'b0;
- ScanStat_q2 <= #Tp 1'b0;
- SyncStatMdcEn <= #Tp 1'b0;
- end
- else
- begin
- WCtrlData_q1 <= #Tp WCtrlData;
- WCtrlData_q2 <= #Tp WCtrlData_q1;
- WCtrlData_q3 <= #Tp WCtrlData_q2;
-
- RStat_q1 <= #Tp RStat;
- RStat_q2 <= #Tp RStat_q1;
- RStat_q3 <= #Tp RStat_q2;
-
- ScanStat_q1 <= #Tp ScanStat;
- ScanStat_q2 <= #Tp ScanStat_q1;
- if(MdcEn)
- SyncStatMdcEn <= #Tp ScanStat_q2;
- end
-end
-
-
-// Generation of the Start Commands (Write Control Data or Read Status)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlDataStart <= #Tp 1'b0;
- WCtrlDataStart_q <= #Tp 1'b0;
- RStatStart <= #Tp 1'b0;
- end
- else
- begin
- if(EndBusy)
- begin
- WCtrlDataStart <= #Tp 1'b0;
- RStatStart <= #Tp 1'b0;
- end
- else
- begin
- if(WCtrlData_q2 & ~WCtrlData_q3)
- WCtrlDataStart <= #Tp 1'b1;
- if(RStat_q2 & ~RStat_q3)
- RStatStart <= #Tp 1'b1;
- WCtrlDataStart_q <= #Tp WCtrlDataStart;
- end
- end
-end
-
-
-// Generation of the Nvalid signal (indicates when the status is invalid)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- Nvalid <= #Tp 1'b0;
- else
- begin
- if(~InProgress_q2 & InProgress_q3)
- begin
- Nvalid <= #Tp 1'b0;
- end
- else
- begin
- if(ScanStat_q2 & ~SyncStatMdcEn)
- Nvalid <= #Tp 1'b1;
- end
- end
-end
-
-// Signals used for the generation of the Operation signals (positive edge)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- WCtrlDataStart_q1 <= #Tp 1'b0;
- WCtrlDataStart_q2 <= #Tp 1'b0;
-
- RStatStart_q1 <= #Tp 1'b0;
- RStatStart_q2 <= #Tp 1'b0;
-
- InProgress_q1 <= #Tp 1'b0;
- InProgress_q2 <= #Tp 1'b0;
- InProgress_q3 <= #Tp 1'b0;
-
- LatchByte0_d <= #Tp 1'b0;
- LatchByte1_d <= #Tp 1'b0;
-
- LatchByte <= #Tp 2'b00;
- end
- else
- begin
- if(MdcEn)
- begin
- WCtrlDataStart_q1 <= #Tp WCtrlDataStart;
- WCtrlDataStart_q2 <= #Tp WCtrlDataStart_q1;
-
- RStatStart_q1 <= #Tp RStatStart;
- RStatStart_q2 <= #Tp RStatStart_q1;
-
- LatchByte[0] <= #Tp LatchByte0_d;
- LatchByte[1] <= #Tp LatchByte1_d;
-
- LatchByte0_d <= #Tp LatchByte0_d2;
- LatchByte1_d <= #Tp LatchByte1_d2;
-
- InProgress_q1 <= #Tp InProgress;
- InProgress_q2 <= #Tp InProgress_q1;
- InProgress_q3 <= #Tp InProgress_q2;
- end
- end
-end
-
-
-// Generation of the Operation signals
-assign WriteDataOp = WCtrlDataStart_q1 & ~WCtrlDataStart_q2;
-assign ReadStatusOp = RStatStart_q1 & ~RStatStart_q2;
-assign ScanStatusOp = SyncStatMdcEn & ~InProgress & ~InProgress_q1 & ~InProgress_q2;
-assign StartOp = WriteDataOp | ReadStatusOp | ScanStatusOp;
-
-// Busy
-assign Busy = WCtrlData | WCtrlDataStart | RStat | RStatStart | SyncStatMdcEn | EndBusy | InProgress | InProgress_q3 | Nvalid;
-
-
-// Generation of the InProgress signal (indicates when an operation is in progress)
-// Generation of the WriteOp signal (indicates when a write is in progress)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- InProgress <= #Tp 1'b0;
- WriteOp <= #Tp 1'b0;
- end
- else
- begin
- if(MdcEn)
- begin
- if(StartOp)
- begin
- if(~InProgress)
- WriteOp <= #Tp WriteDataOp;
- InProgress <= #Tp 1'b1;
- end
- else
- begin
- if(EndOp)
- begin
- InProgress <= #Tp 1'b0;
- WriteOp <= #Tp 1'b0;
- end
- end
- end
- end
-end
-
-
-
-// Bit Counter counts from 0 to 63 (from 32 to 63 when NoPre is asserted)
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- BitCounter[6:0] <= #Tp 7'h0;
- else
- begin
- if(MdcEn)
- begin
- if(InProgress)
- begin
- if(NoPre & ( BitCounter == 7'h0 ))
- BitCounter[6:0] <= #Tp 7'h21;
- else
- BitCounter[6:0] <= #Tp BitCounter[6:0] + 1'b1;
- end
- else
- BitCounter[6:0] <= #Tp 7'h0;
- end
- end
-end
-
-
-// Operation ends when the Bit Counter reaches 63
-assign EndOp = BitCounter==63;
-
-assign ByteSelect[0] = InProgress & ((NoPre & (BitCounter == 7'h0)) | (~NoPre & (BitCounter == 7'h20)));
-assign ByteSelect[1] = InProgress & (BitCounter == 7'h28);
-assign ByteSelect[2] = InProgress & WriteOp & (BitCounter == 7'h30);
-assign ByteSelect[3] = InProgress & WriteOp & (BitCounter == 7'h38);
-
-
-// Latch Byte selects which part of Read Status Data is updated from the shift register
-assign LatchByte1_d2 = InProgress & ~WriteOp & BitCounter == 7'h37;
-assign LatchByte0_d2 = InProgress & ~WriteOp & BitCounter == 7'h3F;
-
-
-// Connecting the Clock Generator Module
-eth_clockgen clkgen(.Clk(Clk), .Reset(Reset), .Divider(Divider[7:0]), .MdcEn(MdcEn), .MdcEn_n(MdcEn_n), .Mdc(Mdc)
- );
-
-// Connecting the Shift Register Module
-eth_shiftreg shftrg(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .Mdi(Mdi), .Fiad(Fiad), .Rgad(Rgad),
- .CtrlData(CtrlData), .WriteOp(WriteOp), .ByteSelect(ByteSelect), .LatchByte(LatchByte),
- .ShiftedBit(ShiftedBit), .Prsd(Prsd), .LinkFail(LinkFail)
- );
-
-// Connecting the Output Control Module
-eth_outputcontrol outctrl(.Clk(Clk), .Reset(Reset), .MdcEn_n(MdcEn_n), .InProgress(InProgress),
- .ShiftedBit(ShiftedBit), .BitCounter(BitCounter), .WriteOp(WriteOp), .NoPre(NoPre),
- .Mdo(Mdo), .MdoEn(MdoEn)
- );
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_outputcontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_outputcontrol.v,v $
-// Revision 1.4 2002/07/09 20:11:59 mohor
-// Comment removed.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-module eth_outputcontrol(Clk, Reset, InProgress, ShiftedBit, BitCounter, WriteOp, NoPre, MdcEn_n, Mdo, MdoEn);
-
-parameter Tp = 1;
-
-input Clk; // Host Clock
-input Reset; // General Reset
-input WriteOp; // Write Operation Latch (When asserted, write operation is in progress)
-input NoPre; // No Preamble (no 32-bit preamble)
-input InProgress; // Operation in progress
-input ShiftedBit; // This bit is output of the shift register and is connected to the Mdo signal
-input [6:0] BitCounter; // Bit Counter
-input MdcEn_n; // MII Management Data Clock Enable signal is asserted for one Clk period before Mdc falls.
-
-output Mdo; // MII Management Data Output
-output MdoEn; // MII Management Data Output Enable
-
-wire SerialEn;
-
-reg MdoEn_2d;
-reg MdoEn_d;
-reg MdoEn;
-
-reg Mdo_2d;
-reg Mdo_d;
-reg Mdo; // MII Management Data Output
-
-
-
-// Generation of the Serial Enable signal (enables the serialization of the data)
-assign SerialEn = WriteOp & InProgress & ( BitCounter>31 | ( ( BitCounter == 0 ) & NoPre ) )
- | ~WriteOp & InProgress & (( BitCounter>31 & BitCounter<46 ) | ( ( BitCounter == 0 ) & NoPre ));
-
-
-// Generation of the MdoEn signal
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- MdoEn_2d <= #Tp 1'b0;
- MdoEn_d <= #Tp 1'b0;
- MdoEn <= #Tp 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- MdoEn_2d <= #Tp SerialEn | InProgress & BitCounter<32;
- MdoEn_d <= #Tp MdoEn_2d;
- MdoEn <= #Tp MdoEn_d;
- end
- end
-end
-
-
-// Generation of the Mdo signal.
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- Mdo_2d <= #Tp 1'b0;
- Mdo_d <= #Tp 1'b0;
- Mdo <= #Tp 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- Mdo_2d <= #Tp ~SerialEn & BitCounter<32;
- Mdo_d <= #Tp ShiftedBit | Mdo_2d;
- Mdo <= #Tp Mdo_d;
- end
- end
-end
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_random.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_random.v,v $
-// Revision 1.4 2003/06/13 11:26:08 mohor
-// Binary operator used instead of unary (xnor).
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-//
-
-`include "timescale.v"
-
-module eth_random (MTxClk, Reset, StateJam, StateJam_q, RetryCnt, NibCnt, ByteCnt,
- RandomEq0, RandomEqByteCnt);
-
-parameter Tp = 1;
-
-input MTxClk;
-input Reset;
-input StateJam;
-input StateJam_q;
-input [3:0] RetryCnt;
-input [15:0] NibCnt;
-input [9:0] ByteCnt;
-output RandomEq0;
-output RandomEqByteCnt;
-
-wire Feedback;
-reg [9:0] x;
-wire [9:0] Random;
-reg [9:0] RandomLatched;
-
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- x[9:0] <= #Tp 0;
- else
- x[9:0] <= #Tp {x[8:0], Feedback};
-end
-
-assign Feedback = ~(x[2] ^ x[9]);
-
-assign Random [0] = x[0];
-assign Random [1] = (RetryCnt > 1) ? x[1] : 1'b0;
-assign Random [2] = (RetryCnt > 2) ? x[2] : 1'b0;
-assign Random [3] = (RetryCnt > 3) ? x[3] : 1'b0;
-assign Random [4] = (RetryCnt > 4) ? x[4] : 1'b0;
-assign Random [5] = (RetryCnt > 5) ? x[5] : 1'b0;
-assign Random [6] = (RetryCnt > 6) ? x[6] : 1'b0;
-assign Random [7] = (RetryCnt > 7) ? x[7] : 1'b0;
-assign Random [8] = (RetryCnt > 8) ? x[8] : 1'b0;
-assign Random [9] = (RetryCnt > 9) ? x[9] : 1'b0;
-
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RandomLatched <= #Tp 10'h000;
- else
- begin
- if(StateJam & StateJam_q)
- RandomLatched <= #Tp Random;
- end
-end
-
-// Random Number == 0 IEEE 802.3 page 68. If 0 we go to defer and not to backoff.
-assign RandomEq0 = RandomLatched == 10'h0;
-
-assign RandomEqByteCnt = ByteCnt[9:0] == RandomLatched & (&NibCnt[6:0]);
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_receivecontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_receivecontrol.v,v $
-// Revision 1.5 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.4 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_receivecontrol (MTxClk, MRxClk, TxReset, RxReset, RxData, RxValid, RxStartFrm,
- RxEndFrm, RxFlow, ReceiveEnd, MAC, DlyCrcEn, TxDoneIn,
- TxAbortIn, TxStartFrmOut, ReceivedLengthOK, ReceivedPacketGood,
- TxUsedDataOutDetected, Pause, ReceivedPauseFrm, AddressOK,
- RxStatusWriteLatched_sync2, r_PassAll, SetPauseTimer
- );
-
-parameter Tp = 1;
-
-
-input MTxClk;
-input MRxClk;
-input TxReset;
-input RxReset;
-input [7:0] RxData;
-input RxValid;
-input RxStartFrm;
-input RxEndFrm;
-input RxFlow;
-input ReceiveEnd;
-input [47:0]MAC;
-input DlyCrcEn;
-input TxDoneIn;
-input TxAbortIn;
-input TxStartFrmOut;
-input ReceivedLengthOK;
-input ReceivedPacketGood;
-input TxUsedDataOutDetected;
-input RxStatusWriteLatched_sync2;
-input r_PassAll;
-
-output Pause;
-output ReceivedPauseFrm;
-output AddressOK;
-output SetPauseTimer;
-
-
-reg Pause;
-reg AddressOK; // Multicast or unicast address detected
-reg TypeLengthOK; // Type/Length field contains 0x8808
-reg DetectionWindow; // Detection of the PAUSE frame is possible within this window
-reg OpCodeOK; // PAUSE opcode detected (0x0001)
-reg [2:0] DlyCrcCnt;
-reg [4:0] ByteCnt;
-reg [15:0] AssembledTimerValue;
-reg [15:0] LatchedTimerValue;
-reg ReceivedPauseFrm;
-reg ReceivedPauseFrmWAddr;
-reg PauseTimerEq0_sync1;
-reg PauseTimerEq0_sync2;
-reg [15:0] PauseTimer;
-reg Divider2;
-reg [5:0] SlotTimer;
-
-wire [47:0] ReservedMulticast; // 0x0180C2000001
-wire [15:0] TypeLength; // 0x8808
-wire ResetByteCnt; //
-wire IncrementByteCnt; //
-wire ByteCntEq0; // ByteCnt = 0
-wire ByteCntEq1; // ByteCnt = 1
-wire ByteCntEq2; // ByteCnt = 2
-wire ByteCntEq3; // ByteCnt = 3
-wire ByteCntEq4; // ByteCnt = 4
-wire ByteCntEq5; // ByteCnt = 5
-wire ByteCntEq12; // ByteCnt = 12
-wire ByteCntEq13; // ByteCnt = 13
-wire ByteCntEq14; // ByteCnt = 14
-wire ByteCntEq15; // ByteCnt = 15
-wire ByteCntEq16; // ByteCnt = 16
-wire ByteCntEq17; // ByteCnt = 17
-wire ByteCntEq18; // ByteCnt = 18
-wire DecrementPauseTimer; //
-wire PauseTimerEq0; //
-wire ResetSlotTimer; //
-wire IncrementSlotTimer; //
-wire SlotFinished; //
-
-
-
-// Reserved multicast address and Type/Length for PAUSE control
-assign ReservedMulticast = 48'h0180C2000001;
-assign TypeLength = 16'h8808;
-
-
-// Address Detection (Multicast or unicast)
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- AddressOK <= #Tp 1'b0;
- else
- if(DetectionWindow & ByteCntEq0)
- AddressOK <= #Tp RxData[7:0] == ReservedMulticast[47:40] | RxData[7:0] == MAC[47:40];
- else
- if(DetectionWindow & ByteCntEq1)
- AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[39:32] | RxData[7:0] == MAC[39:32]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq2)
- AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[31:24] | RxData[7:0] == MAC[31:24]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq3)
- AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[23:16] | RxData[7:0] == MAC[23:16]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq4)
- AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[15:8] | RxData[7:0] == MAC[15:8]) & AddressOK;
- else
- if(DetectionWindow & ByteCntEq5)
- AddressOK <= #Tp (RxData[7:0] == ReservedMulticast[7:0] | RxData[7:0] == MAC[7:0]) & AddressOK;
- else
- if(ReceiveEnd)
- AddressOK <= #Tp 1'b0;
-end
-
-
-
-// TypeLengthOK (Type/Length Control frame detected)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- TypeLengthOK <= #Tp 1'b0;
- else
- if(DetectionWindow & ByteCntEq12)
- TypeLengthOK <= #Tp ByteCntEq12 & (RxData[7:0] == TypeLength[15:8]);
- else
- if(DetectionWindow & ByteCntEq13)
- TypeLengthOK <= #Tp ByteCntEq13 & (RxData[7:0] == TypeLength[7:0]) & TypeLengthOK;
- else
- if(ReceiveEnd)
- TypeLengthOK <= #Tp 1'b0;
-end
-
-
-
-// Latch Control Frame Opcode
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- OpCodeOK <= #Tp 1'b0;
- else
- if(ByteCntEq16)
- OpCodeOK <= #Tp 1'b0;
- else
- begin
- if(DetectionWindow & ByteCntEq14)
- OpCodeOK <= #Tp ByteCntEq14 & RxData[7:0] == 8'h00;
-
- if(DetectionWindow & ByteCntEq15)
- OpCodeOK <= #Tp ByteCntEq15 & RxData[7:0] == 8'h01 & OpCodeOK;
- end
-end
-
-
-// ReceivedPauseFrmWAddr (+Address Check)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- ReceivedPauseFrmWAddr <= #Tp 1'b0;
- else
- if(ReceiveEnd)
- ReceivedPauseFrmWAddr <= #Tp 1'b0;
- else
- if(ByteCntEq16 & TypeLengthOK & OpCodeOK & AddressOK)
- ReceivedPauseFrmWAddr <= #Tp 1'b1;
-end
-
-
-
-// Assembling 16-bit timer value from two 8-bit data
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- AssembledTimerValue[15:0] <= #Tp 16'h0;
- else
- if(RxStartFrm)
- AssembledTimerValue[15:0] <= #Tp 16'h0;
- else
- begin
- if(DetectionWindow & ByteCntEq16)
- AssembledTimerValue[15:8] <= #Tp RxData[7:0];
- if(DetectionWindow & ByteCntEq17)
- AssembledTimerValue[7:0] <= #Tp RxData[7:0];
- end
-end
-
-
-// Detection window (while PAUSE detection is possible)
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- DetectionWindow <= #Tp 1'b1;
- else
- if(ByteCntEq18)
- DetectionWindow <= #Tp 1'b0;
- else
- if(ReceiveEnd)
- DetectionWindow <= #Tp 1'b1;
-end
-
-
-
-// Latching Timer Value
-always @ (posedge MRxClk or posedge RxReset )
-begin
- if(RxReset)
- LatchedTimerValue[15:0] <= #Tp 16'h0;
- else
- if(DetectionWindow & ReceivedPauseFrmWAddr & ByteCntEq18)
- LatchedTimerValue[15:0] <= #Tp AssembledTimerValue[15:0];
- else
- if(ReceiveEnd)
- LatchedTimerValue[15:0] <= #Tp 16'h0;
-end
-
-
-
-// Delayed CEC counter
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- DlyCrcCnt <= #Tp 3'h0;
- else
- if(RxValid & RxEndFrm)
- DlyCrcCnt <= #Tp 3'h0;
- else
- if(RxValid & ~RxEndFrm & ~DlyCrcCnt[2])
- DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
-end
-
-
-assign ResetByteCnt = RxEndFrm;
-assign IncrementByteCnt = RxValid & DetectionWindow & ~ByteCntEq18 & (~DlyCrcEn | DlyCrcEn & DlyCrcCnt[2]);
-
-
-// Byte counter
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- ByteCnt[4:0] <= #Tp 5'h0;
- else
- if(ResetByteCnt)
- ByteCnt[4:0] <= #Tp 5'h0;
- else
- if(IncrementByteCnt)
- ByteCnt[4:0] <= #Tp ByteCnt[4:0] + 1'b1;
-end
-
-
-assign ByteCntEq0 = RxValid & ByteCnt[4:0] == 5'h0;
-assign ByteCntEq1 = RxValid & ByteCnt[4:0] == 5'h1;
-assign ByteCntEq2 = RxValid & ByteCnt[4:0] == 5'h2;
-assign ByteCntEq3 = RxValid & ByteCnt[4:0] == 5'h3;
-assign ByteCntEq4 = RxValid & ByteCnt[4:0] == 5'h4;
-assign ByteCntEq5 = RxValid & ByteCnt[4:0] == 5'h5;
-assign ByteCntEq12 = RxValid & ByteCnt[4:0] == 5'h0C;
-assign ByteCntEq13 = RxValid & ByteCnt[4:0] == 5'h0D;
-assign ByteCntEq14 = RxValid & ByteCnt[4:0] == 5'h0E;
-assign ByteCntEq15 = RxValid & ByteCnt[4:0] == 5'h0F;
-assign ByteCntEq16 = RxValid & ByteCnt[4:0] == 5'h10;
-assign ByteCntEq17 = RxValid & ByteCnt[4:0] == 5'h11;
-assign ByteCntEq18 = RxValid & ByteCnt[4:0] == 5'h12 & DetectionWindow;
-
-
-assign SetPauseTimer = ReceiveEnd & ReceivedPauseFrmWAddr & ReceivedPacketGood & ReceivedLengthOK & RxFlow;
-assign DecrementPauseTimer = SlotFinished & |PauseTimer;
-
-
-// PauseTimer[15:0]
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- PauseTimer[15:0] <= #Tp 16'h0;
- else
- if(SetPauseTimer)
- PauseTimer[15:0] <= #Tp LatchedTimerValue[15:0];
- else
- if(DecrementPauseTimer)
- PauseTimer[15:0] <= #Tp PauseTimer[15:0] - 1'b1;
-end
-
-assign PauseTimerEq0 = ~(|PauseTimer[15:0]);
-
-
-
-// Synchronization of the pause timer
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- begin
- PauseTimerEq0_sync1 <= #Tp 1'b1;
- PauseTimerEq0_sync2 <= #Tp 1'b1;
- end
- else
- begin
- PauseTimerEq0_sync1 <= #Tp PauseTimerEq0;
- PauseTimerEq0_sync2 <= #Tp PauseTimerEq0_sync1;
- end
-end
-
-
-// Pause signal generation
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- Pause <= #Tp 1'b0;
- else
- if((TxDoneIn | TxAbortIn | ~TxUsedDataOutDetected) & ~TxStartFrmOut)
- Pause <= #Tp RxFlow & ~PauseTimerEq0_sync2;
-end
-
-
-// Divider2 is used for incrementing the Slot timer every other clock
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- Divider2 <= #Tp 1'b0;
- else
- if(|PauseTimer[15:0] & RxFlow)
- Divider2 <= #Tp ~Divider2;
- else
- Divider2 <= #Tp 1'b0;
-end
-
-
-assign ResetSlotTimer = RxReset;
-assign IncrementSlotTimer = Pause & RxFlow & Divider2;
-
-
-// SlotTimer
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- SlotTimer[5:0] <= #Tp 6'h0;
- else
- if(ResetSlotTimer)
- SlotTimer[5:0] <= #Tp 6'h0;
- else
- if(IncrementSlotTimer)
- SlotTimer[5:0] <= #Tp SlotTimer[5:0] + 1'b1;
-end
-
-
-assign SlotFinished = &SlotTimer[5:0] & IncrementSlotTimer; // Slot is 512 bits (64 bytes)
-
-
-
-// Pause Frame received
-always @ (posedge MRxClk or posedge RxReset)
-begin
- if(RxReset)
- ReceivedPauseFrm <=#Tp 1'b0;
- else
- if(RxStatusWriteLatched_sync2 & r_PassAll | ReceivedPauseFrm & (~r_PassAll))
- ReceivedPauseFrm <=#Tp 1'b0;
- else
- if(ByteCntEq16 & TypeLengthOK & OpCodeOK)
- ReceivedPauseFrm <=#Tp 1'b1;
-end
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_register.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_register.v,v $
-// Revision 1.6 2002/08/16 22:10:12 mohor
-// Synchronous reset added.
-//
-// Revision 1.5 2002/08/16 12:33:27 mohor
-// Parameter ResetValue changed to capital letters.
-//
-// Revision 1.4 2002/02/26 16:18:08 mohor
-// Reset values are passed to registers through parameters
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-//
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_register(DataIn, DataOut, Write, Clk, Reset);
-
-parameter WIDTH = 8; // default parameter of the register width
-parameter RESET_VALUE = 0;
-
-input [WIDTH-1:0] DataIn;
-
-input Write;
-input Clk;
-input Reset;
-
-output [WIDTH-1:0] DataOut;
-reg [WIDTH-1:0] DataOut;
-
-
-
- always @ (posedge Clk or posedge Reset)
- if(Reset)
- DataOut<=#1 RESET_VALUE;
- else
- if(Write) // write
- DataOut<=#1 DataIn;
-
-endmodule // Register
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_registers.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_registers.v,v $
-// Revision 1.29 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.28 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.27 2004/04/26 11:42:17 igorm
-// TX_BD_NUM_Wr error fixed. Error was entered with the last check-in.
-//
-// Revision 1.26 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.25 2003/04/18 16:26:25 mohor
-// RxBDAddress was updated also when value to r_TxBDNum was written with
-// greater value than allowed.
-//
-// Revision 1.24 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.23 2002/11/19 18:13:49 mohor
-// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
-//
-// Revision 1.22 2002/11/14 18:37:20 mohor
-// r_Rst signal does not reset any module any more and is removed from the design.
-//
-// Revision 1.21 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.20 2002/09/04 18:40:25 mohor
-// ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
-// the control frames connected.
-//
-// Revision 1.19 2002/08/19 16:01:40 mohor
-// Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
-// r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
-//
-// Revision 1.18 2002/08/16 22:28:23 mohor
-// Syntax error fixed.
-//
-// Revision 1.17 2002/08/16 22:23:03 mohor
-// Syntax error fixed.
-//
-// Revision 1.16 2002/08/16 22:14:22 mohor
-// Synchronous reset added to all registers. Defines used for width. r_MiiMRst
-// changed from bit position 10 to 9.
-//
-// Revision 1.15 2002/08/14 18:26:37 mohor
-// LinkFailRegister is reflecting the status of the PHY's link fail status bit.
-//
-// Revision 1.14 2002/04/22 14:03:44 mohor
-// Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
-// or not.
-//
-// Revision 1.13 2002/02/26 16:18:09 mohor
-// Reset values are passed to registers through parameters
-//
-// Revision 1.12 2002/02/17 13:23:42 mohor
-// Define missmatch fixed.
-//
-// Revision 1.11 2002/02/16 14:03:44 mohor
-// Registered trimmed. Unused registers removed.
-//
-// Revision 1.10 2002/02/15 11:08:25 mohor
-// File format fixed a bit.
-//
-// Revision 1.9 2002/02/14 20:19:41 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.8 2002/02/12 17:01:19 mohor
-// HASH0 and HASH1 registers added.
-
-// Revision 1.7 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.6 2001/12/05 15:00:16 mohor
-// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
-// instead of the number of RX descriptors).
-//
-// Revision 1.5 2001/12/05 10:22:19 mohor
-// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
-//
-// Revision 1.4 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.3 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.2 2001/09/24 15:02:56 mohor
-// Defines changed (All precede with ETH_). Small changes because some
-// tools generate warnings when two operands are together. Synchronization
-// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
-// demands).
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
- r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
- r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
- r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
- TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
- r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
- r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
- r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
- r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
- LinkFail, r_MAC, WCtrlDataStart, RStatStart,
- UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, int_o,
- r_HASH0, r_HASH1, r_TxPauseTV, r_TxPauseRq, RstTxPauseRq, TxCtrlEndFrm,
- StartTxDone, TxClk, RxClk, SetPauseTimer
- );
-
-parameter Tp = 1;
-
-input [31:0] DataIn;
-input [7:0] Address;
-
-input Rw;
-input [3:0] Cs;
-input Clk;
-input Reset;
-
-input WCtrlDataStart;
-input RStatStart;
-
-input UpdateMIIRX_DATAReg;
-input [15:0] Prsd;
-
-output [31:0] DataOut;
-reg [31:0] DataOut;
-
-output r_RecSmall;
-output r_Pad;
-output r_HugEn;
-output r_CrcEn;
-output r_DlyCrcEn;
-output r_FullD;
-output r_ExDfrEn;
-output r_NoBckof;
-output r_LoopBck;
-output r_IFG;
-output r_Pro;
-output r_Iam;
-output r_Bro;
-output r_NoPre;
-output r_TxEn;
-output r_RxEn;
-output [31:0] r_HASH0;
-output [31:0] r_HASH1;
-
-input TxB_IRQ;
-input TxE_IRQ;
-input RxB_IRQ;
-input RxE_IRQ;
-input Busy_IRQ;
-
-output [6:0] r_IPGT;
-
-output [6:0] r_IPGR1;
-
-output [6:0] r_IPGR2;
-
-output [15:0] r_MinFL;
-output [15:0] r_MaxFL;
-
-output [3:0] r_MaxRet;
-output [5:0] r_CollValid;
-
-output r_TxFlow;
-output r_RxFlow;
-output r_PassAll;
-
-output r_MiiNoPre;
-output [7:0] r_ClkDiv;
-
-output r_WCtrlData;
-output r_RStat;
-output r_ScanStat;
-
-output [4:0] r_RGAD;
-output [4:0] r_FIAD;
-
-output [15:0]r_CtrlData;
-
-
-input NValid_stat;
-input Busy_stat;
-input LinkFail;
-
-output [47:0]r_MAC;
-output [7:0] r_TxBDNum;
-output int_o;
-output [15:0]r_TxPauseTV;
-output r_TxPauseRq;
-input RstTxPauseRq;
-input TxCtrlEndFrm;
-input StartTxDone;
-input TxClk;
-input RxClk;
-input SetPauseTimer;
-
-reg irq_txb;
-reg irq_txe;
-reg irq_rxb;
-reg irq_rxe;
-reg irq_busy;
-reg irq_txc;
-reg irq_rxc;
-
-reg SetTxCIrq_txclk;
-reg SetTxCIrq_sync1, SetTxCIrq_sync2, SetTxCIrq_sync3;
-reg SetTxCIrq;
-reg ResetTxCIrq_sync1, ResetTxCIrq_sync2;
-
-reg SetRxCIrq_rxclk;
-reg SetRxCIrq_sync1, SetRxCIrq_sync2, SetRxCIrq_sync3;
-reg SetRxCIrq;
-reg ResetRxCIrq_sync1;
-reg ResetRxCIrq_sync2;
-reg ResetRxCIrq_sync3;
-
-wire [3:0] Write = Cs & {4{Rw}};
-wire Read = (|Cs) & ~Rw;
-
-wire MODER_Sel = (Address == `ETH_MODER_ADR );
-wire INT_SOURCE_Sel = (Address == `ETH_INT_SOURCE_ADR );
-wire INT_MASK_Sel = (Address == `ETH_INT_MASK_ADR );
-wire IPGT_Sel = (Address == `ETH_IPGT_ADR );
-wire IPGR1_Sel = (Address == `ETH_IPGR1_ADR );
-wire IPGR2_Sel = (Address == `ETH_IPGR2_ADR );
-wire PACKETLEN_Sel = (Address == `ETH_PACKETLEN_ADR );
-wire COLLCONF_Sel = (Address == `ETH_COLLCONF_ADR );
-
-wire CTRLMODER_Sel = (Address == `ETH_CTRLMODER_ADR );
-wire MIIMODER_Sel = (Address == `ETH_MIIMODER_ADR );
-wire MIICOMMAND_Sel = (Address == `ETH_MIICOMMAND_ADR );
-wire MIIADDRESS_Sel = (Address == `ETH_MIIADDRESS_ADR );
-wire MIITX_DATA_Sel = (Address == `ETH_MIITX_DATA_ADR );
-wire MAC_ADDR0_Sel = (Address == `ETH_MAC_ADDR0_ADR );
-wire MAC_ADDR1_Sel = (Address == `ETH_MAC_ADDR1_ADR );
-wire HASH0_Sel = (Address == `ETH_HASH0_ADR );
-wire HASH1_Sel = (Address == `ETH_HASH1_ADR );
-wire TXCTRL_Sel = (Address == `ETH_TX_CTRL_ADR );
-wire RXCTRL_Sel = (Address == `ETH_RX_CTRL_ADR );
-wire TX_BD_NUM_Sel = (Address == `ETH_TX_BD_NUM_ADR );
-
-
-wire [2:0] MODER_Wr;
-wire [0:0] INT_SOURCE_Wr;
-wire [0:0] INT_MASK_Wr;
-wire [0:0] IPGT_Wr;
-wire [0:0] IPGR1_Wr;
-wire [0:0] IPGR2_Wr;
-wire [3:0] PACKETLEN_Wr;
-wire [2:0] COLLCONF_Wr;
-wire [0:0] CTRLMODER_Wr;
-wire [1:0] MIIMODER_Wr;
-wire [0:0] MIICOMMAND_Wr;
-wire [1:0] MIIADDRESS_Wr;
-wire [1:0] MIITX_DATA_Wr;
-wire MIIRX_DATA_Wr;
-wire [3:0] MAC_ADDR0_Wr;
-wire [1:0] MAC_ADDR1_Wr;
-wire [3:0] HASH0_Wr;
-wire [3:0] HASH1_Wr;
-wire [2:0] TXCTRL_Wr;
-wire [0:0] TX_BD_NUM_Wr;
-
-assign MODER_Wr[0] = Write[0] & MODER_Sel;
-assign MODER_Wr[1] = Write[1] & MODER_Sel;
-assign MODER_Wr[2] = Write[2] & MODER_Sel;
-assign INT_SOURCE_Wr[0] = Write[0] & INT_SOURCE_Sel;
-assign INT_MASK_Wr[0] = Write[0] & INT_MASK_Sel;
-assign IPGT_Wr[0] = Write[0] & IPGT_Sel;
-assign IPGR1_Wr[0] = Write[0] & IPGR1_Sel;
-assign IPGR2_Wr[0] = Write[0] & IPGR2_Sel;
-assign PACKETLEN_Wr[0] = Write[0] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[1] = Write[1] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[2] = Write[2] & PACKETLEN_Sel;
-assign PACKETLEN_Wr[3] = Write[3] & PACKETLEN_Sel;
-assign COLLCONF_Wr[0] = Write[0] & COLLCONF_Sel;
-assign COLLCONF_Wr[1] = 1'b0; // Not used
-assign COLLCONF_Wr[2] = Write[2] & COLLCONF_Sel;
-
-assign CTRLMODER_Wr[0] = Write[0] & CTRLMODER_Sel;
-assign MIIMODER_Wr[0] = Write[0] & MIIMODER_Sel;
-assign MIIMODER_Wr[1] = Write[1] & MIIMODER_Sel;
-assign MIICOMMAND_Wr[0] = Write[0] & MIICOMMAND_Sel;
-assign MIIADDRESS_Wr[0] = Write[0] & MIIADDRESS_Sel;
-assign MIIADDRESS_Wr[1] = Write[1] & MIIADDRESS_Sel;
-assign MIITX_DATA_Wr[0] = Write[0] & MIITX_DATA_Sel;
-assign MIITX_DATA_Wr[1] = Write[1] & MIITX_DATA_Sel;
-assign MIIRX_DATA_Wr = UpdateMIIRX_DATAReg;
-assign MAC_ADDR0_Wr[0] = Write[0] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[1] = Write[1] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[2] = Write[2] & MAC_ADDR0_Sel;
-assign MAC_ADDR0_Wr[3] = Write[3] & MAC_ADDR0_Sel;
-assign MAC_ADDR1_Wr[0] = Write[0] & MAC_ADDR1_Sel;
-assign MAC_ADDR1_Wr[1] = Write[1] & MAC_ADDR1_Sel;
-assign HASH0_Wr[0] = Write[0] & HASH0_Sel;
-assign HASH0_Wr[1] = Write[1] & HASH0_Sel;
-assign HASH0_Wr[2] = Write[2] & HASH0_Sel;
-assign HASH0_Wr[3] = Write[3] & HASH0_Sel;
-assign HASH1_Wr[0] = Write[0] & HASH1_Sel;
-assign HASH1_Wr[1] = Write[1] & HASH1_Sel;
-assign HASH1_Wr[2] = Write[2] & HASH1_Sel;
-assign HASH1_Wr[3] = Write[3] & HASH1_Sel;
-assign TXCTRL_Wr[0] = Write[0] & TXCTRL_Sel;
-assign TXCTRL_Wr[1] = Write[1] & TXCTRL_Sel;
-assign TXCTRL_Wr[2] = Write[2] & TXCTRL_Sel;
-assign TX_BD_NUM_Wr[0] = Write[0] & TX_BD_NUM_Sel & (DataIn<='h80);
-
-
-
-wire [31:0] MODEROut;
-wire [31:0] INT_SOURCEOut;
-wire [31:0] INT_MASKOut;
-wire [31:0] IPGTOut;
-wire [31:0] IPGR1Out;
-wire [31:0] IPGR2Out;
-wire [31:0] PACKETLENOut;
-wire [31:0] COLLCONFOut;
-wire [31:0] CTRLMODEROut;
-wire [31:0] MIIMODEROut;
-wire [31:0] MIICOMMANDOut;
-wire [31:0] MIIADDRESSOut;
-wire [31:0] MIITX_DATAOut;
-wire [31:0] MIIRX_DATAOut;
-wire [31:0] MIISTATUSOut;
-wire [31:0] MAC_ADDR0Out;
-wire [31:0] MAC_ADDR1Out;
-wire [31:0] TX_BD_NUMOut;
-wire [31:0] HASH0Out;
-wire [31:0] HASH1Out;
-wire [31:0] TXCTRLOut;
-
-// MODER Register
-eth_register #(`ETH_MODER_WIDTH_0, `ETH_MODER_DEF_0) MODER_0
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_0 - 1:0]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_0 - 1:0]),
- .Write (MODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MODER_WIDTH_1, `ETH_MODER_DEF_1) MODER_1
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_1 + 7:8]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_1 + 7:8]),
- .Write (MODER_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MODER_WIDTH_2, `ETH_MODER_DEF_2) MODER_2
- (
- .DataIn (DataIn[`ETH_MODER_WIDTH_2 + 15:16]),
- .DataOut (MODEROut[`ETH_MODER_WIDTH_2 + 15:16]),
- .Write (MODER_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MODEROut[31:`ETH_MODER_WIDTH_2 + 16] = 0;
-
-// INT_MASK Register
-eth_register #(`ETH_INT_MASK_WIDTH_0, `ETH_INT_MASK_DEF_0) INT_MASK_0
- (
- .DataIn (DataIn[`ETH_INT_MASK_WIDTH_0 - 1:0]),
- .DataOut (INT_MASKOut[`ETH_INT_MASK_WIDTH_0 - 1:0]),
- .Write (INT_MASK_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign INT_MASKOut[31:`ETH_INT_MASK_WIDTH_0] = 0;
-`ifdef ETH_IPGT
- assign IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0] = `ETH_IPGT_DEF_0;
-`else
-// IPGT Register
-eth_register #(`ETH_IPGT_WIDTH_0, `ETH_IPGT_DEF_0) IPGT_0
- (
- .DataIn (DataIn[`ETH_IPGT_WIDTH_0 - 1:0]),
- .DataOut (IPGTOut[`ETH_IPGT_WIDTH_0 - 1:0]),
- .Write (IPGT_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif
-assign IPGTOut[31:`ETH_IPGT_WIDTH_0] = 0;
-`ifdef ETH_IPGR1
- assign IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0] = `ETH_IPGR1_DEF_0;
-`else
-// IPGR1 Register
-eth_register #(`ETH_IPGR1_WIDTH_0, `ETH_IPGR1_DEF_0) IPGR1_0
- (
- .DataIn (DataIn[`ETH_IPGR1_WIDTH_0 - 1:0]),
- .DataOut (IPGR1Out[`ETH_IPGR1_WIDTH_0 - 1:0]),
- .Write (IPGR1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif
-assign IPGR1Out[31:`ETH_IPGR1_WIDTH_0] = 0;
-
-`ifdef ETH_IPGR2
- assign IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0] = `ETH_IPGR2_DEF_0;
-`else
-// IPGR2 Register
-eth_register #(`ETH_IPGR2_WIDTH_0, `ETH_IPGR2_DEF_0) IPGR2_0
- (
- .DataIn (DataIn[`ETH_IPGR2_WIDTH_0 - 1:0]),
- .DataOut (IPGR2Out[`ETH_IPGR2_WIDTH_0 - 1:0]),
- .Write (IPGR2_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif
-assign IPGR2Out[31:`ETH_IPGR2_WIDTH_0] = 0;
-
-`ifdef ETH_PACKETLEN
- assign PACKETLENOut = {`ETH_PACKETLEN_DEF_3,`ETH_PACKETLEN_DEF_2,`ETH_PACKETLEN_DEF_1,`ETH_PACKETLEN_DEF_0};
-`else
-// PACKETLEN Register
-eth_register #(`ETH_PACKETLEN_WIDTH_0, `ETH_PACKETLEN_DEF_0) PACKETLEN_0
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_0 - 1:0]),
- .Write (PACKETLEN_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_1, `ETH_PACKETLEN_DEF_1) PACKETLEN_1
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_1 + 7:8]),
- .Write (PACKETLEN_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_2, `ETH_PACKETLEN_DEF_2) PACKETLEN_2
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_2 + 15:16]),
- .Write (PACKETLEN_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_PACKETLEN_WIDTH_3, `ETH_PACKETLEN_DEF_3) PACKETLEN_3
- (
- .DataIn (DataIn[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
- .DataOut (PACKETLENOut[`ETH_PACKETLEN_WIDTH_3 + 23:24]),
- .Write (PACKETLEN_Wr[3]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif // !`ifdef
-
-`ifdef ETH_COLLCONF
- assign COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0] = `ETH_COLLCONF_DEF_0;
- assign COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16] = `ETH_COLLCONF_DEF_2;
-`else
-// COLLCONF Register
-eth_register #(`ETH_COLLCONF_WIDTH_0, `ETH_COLLCONF_DEF_0) COLLCONF_0
- (
- .DataIn (DataIn[`ETH_COLLCONF_WIDTH_0 - 1:0]),
- .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_0 - 1:0]),
- .Write (COLLCONF_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_COLLCONF_WIDTH_2, `ETH_COLLCONF_DEF_2) COLLCONF_2
- (
- .DataIn (DataIn[`ETH_COLLCONF_WIDTH_2 + 15:16]),
- .DataOut (COLLCONFOut[`ETH_COLLCONF_WIDTH_2 + 15:16]),
- .Write (COLLCONF_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif
-assign COLLCONFOut[15:`ETH_COLLCONF_WIDTH_0] = 0;
-assign COLLCONFOut[31:`ETH_COLLCONF_WIDTH_2 + 16] = 0;
-
-// TX_BD_NUM Register
-eth_register #(`ETH_TX_BD_NUM_WIDTH_0, `ETH_TX_BD_NUM_DEF_0) TX_BD_NUM_0
- (
- .DataIn (DataIn[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
- .DataOut (TX_BD_NUMOut[`ETH_TX_BD_NUM_WIDTH_0 - 1:0]),
- .Write (TX_BD_NUM_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign TX_BD_NUMOut[31:`ETH_TX_BD_NUM_WIDTH_0] = 0;
-
-// CTRLMODER Register
-eth_register #(`ETH_CTRLMODER_WIDTH_0, `ETH_CTRLMODER_DEF_0) CTRLMODER_0
- (
- .DataIn (DataIn[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
- .DataOut (CTRLMODEROut[`ETH_CTRLMODER_WIDTH_0 - 1:0]),
- .Write (CTRLMODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign CTRLMODEROut[31:`ETH_CTRLMODER_WIDTH_0] = 0;
-
-// MIIMODER Register
-eth_register #(`ETH_MIIMODER_WIDTH_0, `ETH_MIIMODER_DEF_0) MIIMODER_0
- (
- .DataIn (DataIn[`ETH_MIIMODER_WIDTH_0 - 1:0]),
- .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_0 - 1:0]),
- .Write (MIIMODER_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MIIMODER_WIDTH_1, `ETH_MIIMODER_DEF_1) MIIMODER_1
- (
- .DataIn (DataIn[`ETH_MIIMODER_WIDTH_1 + 7:8]),
- .DataOut (MIIMODEROut[`ETH_MIIMODER_WIDTH_1 + 7:8]),
- .Write (MIIMODER_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MIIMODEROut[31:`ETH_MIIMODER_WIDTH_1 + 8] = 0;
-
-// MIICOMMAND Register
-eth_register #(1, 0) MIICOMMAND0
- (
- .DataIn (DataIn[0]),
- .DataOut (MIICOMMANDOut[0]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(1, 0) MIICOMMAND1
- (
- .DataIn (DataIn[1]),
- .DataOut (MIICOMMANDOut[1]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(1, 0) MIICOMMAND2
- (
- .DataIn (DataIn[2]),
- .DataOut (MIICOMMANDOut[2]),
- .Write (MIICOMMAND_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MIICOMMANDOut[31:`ETH_MIICOMMAND_WIDTH_0] = 29'h0;
-
-// MIIADDRESSRegister
-eth_register #(`ETH_MIIADDRESS_WIDTH_0, `ETH_MIIADDRESS_DEF_0) MIIADDRESS_0
- (
- .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
- .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_0 - 1:0]),
- .Write (MIIADDRESS_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MIIADDRESS_WIDTH_1, `ETH_MIIADDRESS_DEF_1) MIIADDRESS_1
- (
- .DataIn (DataIn[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
- .DataOut (MIIADDRESSOut[`ETH_MIIADDRESS_WIDTH_1 + 7:8]),
- .Write (MIIADDRESS_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MIIADDRESSOut[7:`ETH_MIIADDRESS_WIDTH_0] = 0;
-assign MIIADDRESSOut[31:`ETH_MIIADDRESS_WIDTH_1 + 8] = 0;
-
-// MIITX_DATA Register
-eth_register #(`ETH_MIITX_DATA_WIDTH_0, `ETH_MIITX_DATA_DEF_0) MIITX_DATA_0
- (
- .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
- .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_0 - 1:0]),
- .Write (MIITX_DATA_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MIITX_DATA_WIDTH_1, `ETH_MIITX_DATA_DEF_1) MIITX_DATA_1
- (
- .DataIn (DataIn[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
- .DataOut (MIITX_DATAOut[`ETH_MIITX_DATA_WIDTH_1 + 7:8]),
- .Write (MIITX_DATA_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MIITX_DATAOut[31:`ETH_MIITX_DATA_WIDTH_1 + 8] = 0;
-
-// MIIRX_DATA Register
-eth_register #(`ETH_MIIRX_DATA_WIDTH, `ETH_MIIRX_DATA_DEF) MIIRX_DATA
- (
- .DataIn (Prsd[`ETH_MIIRX_DATA_WIDTH-1:0]),
- .DataOut (MIIRX_DATAOut[`ETH_MIIRX_DATA_WIDTH-1:0]),
- .Write (MIIRX_DATA_Wr), // not written from WB
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MIIRX_DATAOut[31:`ETH_MIIRX_DATA_WIDTH] = 0;
-
-`ifdef ETH_MAC_ADDR
- assign MAC_ADDR0Out = {`ETH_MAC_ADDR0_DEF_3,`ETH_MAC_ADDR0_DEF_2,`ETH_MAC_ADDR0_DEF_1,`ETH_MAC_ADDR0_DEF_0};
- assign MAC_ADDR1Out = {16'h0,`ETH_MAC_ADDR1_DEF_1,`ETH_MAC_ADDR1_DEF_0};
-`else
-// MAC_ADDR0 Register
-eth_register #(`ETH_MAC_ADDR0_WIDTH_0, `ETH_MAC_ADDR0_DEF_0) MAC_ADDR0_0
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_0 - 1:0]),
- .Write (MAC_ADDR0_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_1, `ETH_MAC_ADDR0_DEF_1) MAC_ADDR0_1
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_1 + 7:8]),
- .Write (MAC_ADDR0_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_2, `ETH_MAC_ADDR0_DEF_2) MAC_ADDR0_2
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_2 + 15:16]),
- .Write (MAC_ADDR0_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MAC_ADDR0_WIDTH_3, `ETH_MAC_ADDR0_DEF_3) MAC_ADDR0_3
- (
- .DataIn (DataIn[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
- .DataOut (MAC_ADDR0Out[`ETH_MAC_ADDR0_WIDTH_3 + 23:24]),
- .Write (MAC_ADDR0_Wr[3]),
- .Clk (Clk),
- .Reset (Reset)
- );
-
-// MAC_ADDR1 Register
-eth_register #(`ETH_MAC_ADDR1_WIDTH_0, `ETH_MAC_ADDR1_DEF_0) MAC_ADDR1_0
- (
- .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
- .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_0 - 1:0]),
- .Write (MAC_ADDR1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_MAC_ADDR1_WIDTH_1, `ETH_MAC_ADDR1_DEF_1) MAC_ADDR1_1
- (
- .DataIn (DataIn[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
- .DataOut (MAC_ADDR1Out[`ETH_MAC_ADDR1_WIDTH_1 + 7:8]),
- .Write (MAC_ADDR1_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign MAC_ADDR1Out[31:`ETH_MAC_ADDR1_WIDTH_1 + 8] = 0;
-`endif // !`ifdef ETH_MAC_ADDR
-`ifdef ETH_HASH0
- assign HASH0Out = {`ETH_HASH0_DEF_3,`ETH_HASH0_DEF_2,`ETH_HASH0_DEF_1,`ETH_HASH0_DEF_0};
-`else
-// RXHASH0 Register
-eth_register #(`ETH_HASH0_WIDTH_0, `ETH_HASH0_DEF_0) RXHASH0_0
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_0 - 1:0]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_0 - 1:0]),
- .Write (HASH0_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH0_WIDTH_1, `ETH_HASH0_DEF_1) RXHASH0_1
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_1 + 7:8]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_1 + 7:8]),
- .Write (HASH0_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH0_WIDTH_2, `ETH_HASH0_DEF_2) RXHASH0_2
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_2 + 15:16]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_2 + 15:16]),
- .Write (HASH0_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH0_WIDTH_3, `ETH_HASH0_DEF_3) RXHASH0_3
- (
- .DataIn (DataIn[`ETH_HASH0_WIDTH_3 + 23:24]),
- .DataOut (HASH0Out[`ETH_HASH0_WIDTH_3 + 23:24]),
- .Write (HASH0_Wr[3]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif // !`ifdef ETH_HASH0
-`ifdef ETH_HASH1
- assign HASH1Out = {`ETH_HASH1_DEF_3,`ETH_HASH1_DEF_2,`ETH_HASH1_DEF_1,`ETH_HASH1_DEF_0};
-`else
-// RXHASH1 Register
-eth_register #(`ETH_HASH1_WIDTH_0, `ETH_HASH1_DEF_0) RXHASH1_0
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_0 - 1:0]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_0 - 1:0]),
- .Write (HASH1_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH1_WIDTH_1, `ETH_HASH1_DEF_1) RXHASH1_1
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_1 + 7:8]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_1 + 7:8]),
- .Write (HASH1_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH1_WIDTH_2, `ETH_HASH1_DEF_2) RXHASH1_2
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_2 + 15:16]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_2 + 15:16]),
- .Write (HASH1_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_HASH1_WIDTH_3, `ETH_HASH1_DEF_3) RXHASH1_3
- (
- .DataIn (DataIn[`ETH_HASH1_WIDTH_3 + 23:24]),
- .DataOut (HASH1Out[`ETH_HASH1_WIDTH_3 + 23:24]),
- .Write (HASH1_Wr[3]),
- .Clk (Clk),
- .Reset (Reset)
- );
-`endif
-// TXCTRL Register
-eth_register #(`ETH_TX_CTRL_WIDTH_0, `ETH_TX_CTRL_DEF_0) TXCTRL_0
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_0 - 1:0]),
- .Write (TXCTRL_Wr[0]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_TX_CTRL_WIDTH_1, `ETH_TX_CTRL_DEF_1) TXCTRL_1
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_1 + 7:8]),
- .Write (TXCTRL_Wr[1]),
- .Clk (Clk),
- .Reset (Reset)
- );
-eth_register #(`ETH_TX_CTRL_WIDTH_2, `ETH_TX_CTRL_DEF_2) TXCTRL_2 // Request bit is synchronously reset
- (
- .DataIn (DataIn[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
- .DataOut (TXCTRLOut[`ETH_TX_CTRL_WIDTH_2 + 15:16]),
- .Write (TXCTRL_Wr[2]),
- .Clk (Clk),
- .Reset (Reset)
- );
-assign TXCTRLOut[31:`ETH_TX_CTRL_WIDTH_2 + 16] = 0;
-
-
-
-// Reading data from registers
-always @ (Address or Read or MODEROut or INT_SOURCEOut or
- INT_MASKOut or IPGTOut or IPGR1Out or IPGR2Out or
- PACKETLENOut or COLLCONFOut or CTRLMODEROut or MIIMODEROut or
- MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or MIIRX_DATAOut or
- MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or TX_BD_NUMOut or
- HASH0Out or HASH1Out or TXCTRLOut
- )
-begin
- if(Read) // read
- begin
- case(Address)
- `ETH_MODER_ADR : DataOut<=MODEROut;
- `ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
- `ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
- `ETH_IPGT_ADR : DataOut<=IPGTOut;
- `ETH_IPGR1_ADR : DataOut<=IPGR1Out;
- `ETH_IPGR2_ADR : DataOut<=IPGR2Out;
- `ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
- `ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
- `ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
- `ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
- `ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
- `ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
- `ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
- `ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
- `ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
- `ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
- `ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
- `ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
- `ETH_HASH0_ADR : DataOut<=HASH0Out;
- `ETH_HASH1_ADR : DataOut<=HASH1Out;
- `ETH_TX_CTRL_ADR : DataOut<=TXCTRLOut;
-
- default: DataOut<=32'h0;
- endcase
- end
- else
- DataOut<=32'h0;
-end
-
-
-assign r_RecSmall = MODEROut[16];
-assign r_Pad = MODEROut[15];
-assign r_HugEn = MODEROut[14];
-assign r_CrcEn = MODEROut[13];
-assign r_DlyCrcEn = MODEROut[12];
-// assign r_Rst = MODEROut[11]; This signal is not used any more
-assign r_FullD = MODEROut[10];
-assign r_ExDfrEn = MODEROut[9];
-assign r_NoBckof = MODEROut[8];
-assign r_LoopBck = MODEROut[7];
-assign r_IFG = MODEROut[6];
-assign r_Pro = MODEROut[5];
-assign r_Iam = MODEROut[4];
-assign r_Bro = MODEROut[3];
-assign r_NoPre = MODEROut[2];
-assign r_TxEn = MODEROut[1] & (TX_BD_NUMOut>0); // Transmission is enabled when there is at least one TxBD.
-assign r_RxEn = MODEROut[0] & (TX_BD_NUMOut<'h80); // Reception is enabled when there is at least one RxBD.
-
-assign r_IPGT[6:0] = IPGTOut[6:0];
-
-assign r_IPGR1[6:0] = IPGR1Out[6:0];
-
-assign r_IPGR2[6:0] = IPGR2Out[6:0];
-
-assign r_MinFL[15:0] = PACKETLENOut[31:16];
-assign r_MaxFL[15:0] = PACKETLENOut[15:0];
-
-assign r_MaxRet[3:0] = COLLCONFOut[19:16];
-assign r_CollValid[5:0] = COLLCONFOut[5:0];
-
-assign r_TxFlow = CTRLMODEROut[2];
-assign r_RxFlow = CTRLMODEROut[1];
-assign r_PassAll = CTRLMODEROut[0];
-
-assign r_MiiNoPre = MIIMODEROut[8];
-assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
-
-assign r_WCtrlData = MIICOMMANDOut[2];
-assign r_RStat = MIICOMMANDOut[1];
-assign r_ScanStat = MIICOMMANDOut[0];
-
-assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
-assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
-
-assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
-
-assign MIISTATUSOut[31:`ETH_MIISTATUS_WIDTH] = 0;
-assign MIISTATUSOut[2] = NValid_stat ;
-assign MIISTATUSOut[1] = Busy_stat ;
-assign MIISTATUSOut[0] = LinkFail ;
-
-assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
-assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
-assign r_HASH1[31:0] = HASH1Out;
-assign r_HASH0[31:0] = HASH0Out;
-
-assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
-
-assign r_TxPauseTV[15:0] = TXCTRLOut[15:0];
-assign r_TxPauseRq = TXCTRLOut[16];
-
-
-// Synchronizing TxC Interrupt
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_txclk <=#Tp 1'b0;
- else
- if(TxCtrlEndFrm & StartTxDone & r_TxFlow)
- SetTxCIrq_txclk <=#Tp 1'b1;
- else
- if(ResetTxCIrq_sync2)
- SetTxCIrq_txclk <=#Tp 1'b0;
-end
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync1 <=#Tp 1'b0;
- else
- SetTxCIrq_sync1 <=#Tp SetTxCIrq_txclk;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync2 <=#Tp 1'b0;
- else
- SetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq_sync3 <=#Tp 1'b0;
- else
- SetTxCIrq_sync3 <=#Tp SetTxCIrq_sync2;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetTxCIrq <=#Tp 1'b0;
- else
- SetTxCIrq <=#Tp SetTxCIrq_sync2 & ~SetTxCIrq_sync3;
-end
-
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- ResetTxCIrq_sync1 <=#Tp 1'b0;
- else
- ResetTxCIrq_sync1 <=#Tp SetTxCIrq_sync2;
-end
-
-always @ (posedge TxClk or posedge Reset)
-begin
- if(Reset)
- ResetTxCIrq_sync2 <=#Tp 1'b0;
- else
- ResetTxCIrq_sync2 <=#Tp SetTxCIrq_sync1;
-end
-
-
-// Synchronizing RxC Interrupt
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_rxclk <=#Tp 1'b0;
- else
- if(SetPauseTimer & r_RxFlow)
- SetRxCIrq_rxclk <=#Tp 1'b1;
- else
- if(ResetRxCIrq_sync2 & (~ResetRxCIrq_sync3))
- SetRxCIrq_rxclk <=#Tp 1'b0;
-end
-
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync1 <=#Tp 1'b0;
- else
- SetRxCIrq_sync1 <=#Tp SetRxCIrq_rxclk;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync2 <=#Tp 1'b0;
- else
- SetRxCIrq_sync2 <=#Tp SetRxCIrq_sync1;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq_sync3 <=#Tp 1'b0;
- else
- SetRxCIrq_sync3 <=#Tp SetRxCIrq_sync2;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- SetRxCIrq <=#Tp 1'b0;
- else
- SetRxCIrq <=#Tp SetRxCIrq_sync2 & ~SetRxCIrq_sync3;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync1 <=#Tp 1'b0;
- else
- ResetRxCIrq_sync1 <=#Tp SetRxCIrq_sync2;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync2 <=#Tp 1'b0;
- else
- ResetRxCIrq_sync2 <=#Tp ResetRxCIrq_sync1;
-end
-
-always @ (posedge RxClk or posedge Reset)
-begin
- if(Reset)
- ResetRxCIrq_sync3 <=#Tp 1'b0;
- else
- ResetRxCIrq_sync3 <=#Tp ResetRxCIrq_sync2;
-end
-
-
-
-// Interrupt generation
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txb <= 1'b0;
- else
- if(TxB_IRQ)
- irq_txb <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[0])
- irq_txb <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txe <= 1'b0;
- else
- if(TxE_IRQ)
- irq_txe <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[1])
- irq_txe <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxb <= 1'b0;
- else
- if(RxB_IRQ)
- irq_rxb <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[2])
- irq_rxb <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxe <= 1'b0;
- else
- if(RxE_IRQ)
- irq_rxe <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[3])
- irq_rxe <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_busy <= 1'b0;
- else
- if(Busy_IRQ)
- irq_busy <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[4])
- irq_busy <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_txc <= 1'b0;
- else
- if(SetTxCIrq)
- irq_txc <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[5])
- irq_txc <= #Tp 1'b0;
-end
-
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- irq_rxc <= 1'b0;
- else
- if(SetRxCIrq)
- irq_rxc <= #Tp 1'b1;
- else
- if(INT_SOURCE_Wr[0] & DataIn[6])
- irq_rxc <= #Tp 1'b0;
-end
-
-// Generating interrupt signal
-assign int_o = irq_txb & INT_MASKOut[0] |
- irq_txe & INT_MASKOut[1] |
- irq_rxb & INT_MASKOut[2] |
- irq_rxe & INT_MASKOut[3] |
- irq_busy & INT_MASKOut[4] |
- irq_txc & INT_MASKOut[5] |
- irq_rxc & INT_MASKOut[6] ;
-
-// For reading interrupt status
-assign INT_SOURCEOut = {{(32-`ETH_INT_SOURCE_WIDTH_0){1'b0}}, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxaddrcheck.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/cores/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Bill Dittenhofer (billditt@aol.com) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_rxaddrcheck.v,v $
-// Revision 1.9 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.8 2002/11/19 17:34:52 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.7 2002/09/04 18:41:06 mohor
-// Bug when last byte of destination address was not checked fixed.
-//
-// Revision 1.6 2002/03/20 15:14:11 mohor
-// When in promiscous mode some frames were not received correctly. Fixed.
-//
-// Revision 1.5 2002/03/02 21:06:32 mohor
-// Log info was missing.
-//
-//
-// Revision 1.1 2002/02/08 12:51:54 ditt
-// Initial release of the ethernet addresscheck module.
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxaddrcheck(MRxClk, Reset, RxData, Broadcast ,r_Bro ,r_Pro,
- ByteCntEq2, ByteCntEq3, ByteCntEq4, ByteCntEq5,
- ByteCntEq6, ByteCntEq7, HASH0, HASH1,
- CrcHash, CrcHashGood, StateData, RxEndFrm,
- Multicast, MAC, RxAbort, AddressMiss, PassAll,
- ControlFrmAddressOK
- );
-
-parameter Tp = 1;
-
- input MRxClk;
- input Reset;
- input [7:0] RxData;
- input Broadcast;
- input r_Bro;
- input r_Pro;
- input ByteCntEq2;
- input ByteCntEq3;
- input ByteCntEq4;
- input ByteCntEq5;
- input ByteCntEq6;
- input ByteCntEq7;
- input [31:0] HASH0;
- input [31:0] HASH1;
- input [5:0] CrcHash;
- input CrcHashGood;
- input Multicast;
- input [47:0] MAC;
- input [1:0] StateData;
- input RxEndFrm;
- input PassAll;
- input ControlFrmAddressOK;
-
- output RxAbort;
- output AddressMiss;
-
- wire BroadcastOK;
- wire ByteCntEq2;
- wire ByteCntEq3;
- wire ByteCntEq4;
- wire ByteCntEq5;
- wire RxAddressInvalid;
- wire RxCheckEn;
- wire HashBit;
- wire [31:0] IntHash;
- reg [7:0] ByteHash;
- reg MulticastOK;
- reg UnicastOK;
- reg RxAbort;
- reg AddressMiss;
-
-assign RxAddressInvalid = ~(UnicastOK | BroadcastOK | MulticastOK | r_Pro);
-
-assign BroadcastOK = Broadcast & ~r_Bro;
-
-assign RxCheckEn = | StateData;
-
- // Address Error Reported at end of address cycle
- // RxAbort clears after one cycle
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxAbort <= #Tp 1'b0;
- else if(RxAddressInvalid & ByteCntEq7 & RxCheckEn)
- RxAbort <= #Tp 1'b1;
- else
- RxAbort <= #Tp 1'b0;
-end
-
-
-// This ff holds the "Address Miss" information that is written to the RX BD status.
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- AddressMiss <= #Tp 1'b0;
- else if(ByteCntEq7 & RxCheckEn)
- AddressMiss <= #Tp (~(UnicastOK | BroadcastOK | MulticastOK | (PassAll & ControlFrmAddressOK)));
-end
-
-
-// Hash Address Check, Multicast
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- MulticastOK <= #Tp 1'b0;
- else if(RxEndFrm | RxAbort)
- MulticastOK <= #Tp 1'b0;
- else if(CrcHashGood & Multicast)
- MulticastOK <= #Tp HashBit;
-end
-
-
-// Address Detection (unicast)
-// start with ByteCntEq2 due to delay of addres from RxData
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- UnicastOK <= #Tp 1'b0;
- else
- if(RxCheckEn & ByteCntEq2)
- UnicastOK <= #Tp RxData[7:0] == MAC[47:40];
- else
- if(RxCheckEn & ByteCntEq3)
- UnicastOK <= #Tp ( RxData[7:0] == MAC[39:32]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq4)
- UnicastOK <= #Tp ( RxData[7:0] == MAC[31:24]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq5)
- UnicastOK <= #Tp ( RxData[7:0] == MAC[23:16]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq6)
- UnicastOK <= #Tp ( RxData[7:0] == MAC[15:8]) & UnicastOK;
- else
- if(RxCheckEn & ByteCntEq7)
- UnicastOK <= #Tp ( RxData[7:0] == MAC[7:0]) & UnicastOK;
- else
- if(RxEndFrm | RxAbort)
- UnicastOK <= #Tp 1'b0;
-end
-
-assign IntHash = (CrcHash[5])? HASH1 : HASH0;
-
-always@(CrcHash or IntHash)
-begin
- case(CrcHash[4:3])
- 2'b00: ByteHash = IntHash[7:0];
- 2'b01: ByteHash = IntHash[15:8];
- 2'b10: ByteHash = IntHash[23:16];
- 2'b11: ByteHash = IntHash[31:24];
- endcase
-end
-
-assign HashBit = ByteHash[CrcHash[2:0]];
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxcounters.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_rxcounters.v,v $
-// Revision 1.6 2005/02/21 11:00:57 igorm
-// Delayed CRC fixed.
-//
-// Revision 1.5 2002/02/15 11:13:29 mohor
-// Format of the file changed a bit.
-//
-// Revision 1.4 2002/02/14 20:19:41 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxcounters (MRxClk, Reset, MRxDV, StateIdle, StateSFD, StateData, StateDrop, StatePreamble,
- MRxDEqD, DlyCrcEn, DlyCrcCnt, Transmitting, MaxFL, r_IFG, HugEn, IFGCounterEq24,
- ByteCntEq0, ByteCntEq1, ByteCntEq2,ByteCntEq3,ByteCntEq4,ByteCntEq5, ByteCntEq6,
- ByteCntEq7, ByteCntGreat2, ByteCntSmall7, ByteCntMaxFrame, ByteCntOut
- );
-
-parameter Tp = 1;
-
-input MRxClk;
-input Reset;
-input MRxDV;
-input StateSFD;
-input [1:0] StateData;
-input MRxDEqD;
-input StateIdle;
-input StateDrop;
-input DlyCrcEn;
-input StatePreamble;
-input Transmitting;
-input HugEn;
-input [15:0] MaxFL;
-input r_IFG;
-
-output IFGCounterEq24; // IFG counter reaches 9600 ns (960 ns)
-output [3:0] DlyCrcCnt; // Delayed CRC counter
-output ByteCntEq0; // Byte counter = 0
-output ByteCntEq1; // Byte counter = 1
-output ByteCntEq2; // Byte counter = 2
-output ByteCntEq3; // Byte counter = 3
-output ByteCntEq4; // Byte counter = 4
-output ByteCntEq5; // Byte counter = 5
-output ByteCntEq6; // Byte counter = 6
-output ByteCntEq7; // Byte counter = 7
-output ByteCntGreat2; // Byte counter > 2
-output ByteCntSmall7; // Byte counter < 7
-output ByteCntMaxFrame; // Byte counter = MaxFL
-output [15:0] ByteCntOut; // Byte counter
-
-wire ResetByteCounter;
-wire IncrementByteCounter;
-wire ResetIFGCounter;
-wire IncrementIFGCounter;
-wire ByteCntMax;
-
-reg [15:0] ByteCnt;
-reg [3:0] DlyCrcCnt;
-reg [4:0] IFGCounter;
-
-wire [15:0] ByteCntDelayed;
-
-
-
-assign ResetByteCounter = MRxDV & (StateSFD & MRxDEqD | StateData[0] & ByteCntMaxFrame);
-
-assign IncrementByteCounter = ~ResetByteCounter & MRxDV &
- (StatePreamble | StateSFD | StateIdle & ~Transmitting |
- StateData[1] & ~ByteCntMax & ~(DlyCrcEn & |DlyCrcCnt)
- );
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ByteCnt[15:0] <= #Tp 16'h0;
- else
- begin
- if(ResetByteCounter)
- ByteCnt[15:0] <= #Tp 16'h0;
- else
- if(IncrementByteCounter)
- ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
- end
-end
-
-assign ByteCntDelayed = ByteCnt + 3'h4;
-assign ByteCntOut = DlyCrcEn? ByteCntDelayed : ByteCnt;
-
-assign ByteCntEq0 = ByteCnt == 16'h0;
-assign ByteCntEq1 = ByteCnt == 16'h1;
-assign ByteCntEq2 = ByteCnt == 16'h2;
-assign ByteCntEq3 = ByteCnt == 16'h3;
-assign ByteCntEq4 = ByteCnt == 16'h4;
-assign ByteCntEq5 = ByteCnt == 16'h5;
-assign ByteCntEq6 = ByteCnt == 16'h6;
-assign ByteCntEq7 = ByteCnt == 16'h7;
-assign ByteCntGreat2 = ByteCnt > 16'h2;
-assign ByteCntSmall7 = ByteCnt < 16'h7;
-assign ByteCntMax = ByteCnt == 16'hffff;
-assign ByteCntMaxFrame = ByteCnt == MaxFL[15:0] & ~HugEn;
-
-
-assign ResetIFGCounter = StateSFD & MRxDV & MRxDEqD | StateDrop;
-
-assign IncrementIFGCounter = ~ResetIFGCounter & (StateDrop | StateIdle | StatePreamble | StateSFD) & ~IFGCounterEq24;
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- IFGCounter[4:0] <= #Tp 5'h0;
- else
- begin
- if(ResetIFGCounter)
- IFGCounter[4:0] <= #Tp 5'h0;
- else
- if(IncrementIFGCounter)
- IFGCounter[4:0] <= #Tp IFGCounter[4:0] + 1'b1;
- end
-end
-
-
-
-assign IFGCounterEq24 = (IFGCounter[4:0] == 5'h18) | r_IFG; // 24*400 = 9600 ns or r_IFG is set to 1
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- DlyCrcCnt[3:0] <= #Tp 4'h0;
- else
- begin
- if(DlyCrcCnt[3:0] == 4'h9)
- DlyCrcCnt[3:0] <= #Tp 4'h0;
- else
- if(DlyCrcEn & StateSFD)
- DlyCrcCnt[3:0] <= #Tp 4'h1;
- else
- if(DlyCrcEn & (|DlyCrcCnt[3:0]))
- DlyCrcCnt[3:0] <= #Tp DlyCrcCnt[3:0] + 1'b1;
- end
-end
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxethmac.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_rxethmac.v,v $
-// Revision 1.13 2005/02/21 12:48:07 igorm
-// Warning fixes.
-//
-// Revision 1.12 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.11 2004/03/17 09:32:15 igorm
-// Multicast detection fixed. Only the LSB of the first byte is checked.
-//
-// Revision 1.10 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.9 2002/11/19 17:35:35 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.8 2002/02/16 07:15:27 mohor
-// Testbench fixed, code simplified, unused signals removed.
-//
-// Revision 1.7 2002/02/15 13:44:28 mohor
-// RxAbort is an output. No need to have is declared as wire.
-//
-// Revision 1.6 2002/02/15 11:17:48 mohor
-// File format changed.
-//
-// Revision 1.5 2002/02/14 20:48:43 billditt
-// Addition of new module eth_addrcheck.v
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG, HugEn, DlyCrcEn,
- RxData, RxValid, RxStartFrm, RxEndFrm, ByteCnt, ByteCntEq0, ByteCntGreat2,
- ByteCntMaxFrame, CrcError, StateIdle, StatePreamble, StateSFD, StateData,
- MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss, PassAll, ControlFrmAddressOK
- );
-
-parameter Tp = 1;
-
-
-
-input MRxClk;
-input MRxDV;
-input [3:0] MRxD;
-input Transmitting;
-input HugEn;
-input DlyCrcEn;
-input [15:0] MaxFL;
-input r_IFG;
-input Reset;
-input [47:0] MAC; // Station Address
-input r_Bro; // broadcast disable
-input r_Pro; // promiscuous enable
-input [31:0] r_HASH0; // lower 4 bytes Hash Table
-input [31:0] r_HASH1; // upper 4 bytes Hash Table
-input PassAll;
-input ControlFrmAddressOK;
-
-output [7:0] RxData;
-output RxValid;
-output RxStartFrm;
-output RxEndFrm;
-output [15:0] ByteCnt;
-output ByteCntEq0;
-output ByteCntGreat2;
-output ByteCntMaxFrame;
-output CrcError;
-output StateIdle;
-output StatePreamble;
-output StateSFD;
-output [1:0] StateData;
-output RxAbort;
-output AddressMiss;
-
-reg [7:0] RxData;
-reg RxValid;
-reg RxStartFrm;
-reg RxEndFrm;
-reg Broadcast;
-reg Multicast;
-reg [5:0] CrcHash;
-reg CrcHashGood;
-reg DelayData;
-reg [7:0] LatchedByte;
-reg [7:0] RxData_d;
-reg RxValid_d;
-reg RxStartFrm_d;
-reg RxEndFrm_d;
-
-wire MRxDEqD;
-wire MRxDEq5;
-wire StateDrop;
-wire ByteCntEq1;
-wire ByteCntEq2;
-wire ByteCntEq3;
-wire ByteCntEq4;
-wire ByteCntEq5;
-wire ByteCntEq6;
-wire ByteCntEq7;
-wire ByteCntSmall7;
-wire [31:0] Crc;
-wire Enable_Crc;
-wire Initialize_Crc;
-wire [3:0] Data_Crc;
-wire GenerateRxValid;
-wire GenerateRxStartFrm;
-wire GenerateRxEndFrm;
-wire DribbleRxEndFrm;
-wire [3:0] DlyCrcCnt;
-wire IFGCounterEq24;
-
-assign MRxDEqD = MRxD == 4'hd;
-assign MRxDEq5 = MRxD == 4'h5;
-
-
-// Rx State Machine module
-eth_rxstatem rxstatem1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .ByteCntEq0(ByteCntEq0),
- .ByteCntGreat2(ByteCntGreat2), .Transmitting(Transmitting), .MRxDEq5(MRxDEq5),
- .MRxDEqD(MRxDEqD), .IFGCounterEq24(IFGCounterEq24), .ByteCntMaxFrame(ByteCntMaxFrame),
- .StateData(StateData), .StateIdle(StateIdle), .StatePreamble(StatePreamble),
- .StateSFD(StateSFD), .StateDrop(StateDrop)
- );
-
-
-// Rx Counters module
-eth_rxcounters rxcounters1 (.MRxClk(MRxClk), .Reset(Reset), .MRxDV(MRxDV), .StateIdle(StateIdle),
- .StateSFD(StateSFD), .StateData(StateData), .StateDrop(StateDrop),
- .StatePreamble(StatePreamble), .MRxDEqD(MRxDEqD), .DlyCrcEn(DlyCrcEn),
- .DlyCrcCnt(DlyCrcCnt), .Transmitting(Transmitting), .MaxFL(MaxFL), .r_IFG(r_IFG),
- .HugEn(HugEn), .IFGCounterEq24(IFGCounterEq24), .ByteCntEq0(ByteCntEq0),
- .ByteCntEq1(ByteCntEq1), .ByteCntEq2(ByteCntEq2), .ByteCntEq3(ByteCntEq3),
- .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5), .ByteCntEq6(ByteCntEq6),
- .ByteCntEq7(ByteCntEq7), .ByteCntGreat2(ByteCntGreat2),
- .ByteCntSmall7(ByteCntSmall7), .ByteCntMaxFrame(ByteCntMaxFrame),
- .ByteCntOut(ByteCnt)
- );
-
-// Rx Address Check
-
-eth_rxaddrcheck rxaddrcheck1
- (.MRxClk(MRxClk), .Reset( Reset), .RxData(RxData),
- .Broadcast (Broadcast), .r_Bro (r_Bro), .r_Pro(r_Pro),
- .ByteCntEq6(ByteCntEq6), .ByteCntEq7(ByteCntEq7), .ByteCntEq2(ByteCntEq2),
- .ByteCntEq3(ByteCntEq3), .ByteCntEq4(ByteCntEq4), .ByteCntEq5(ByteCntEq5),
- .HASH0(r_HASH0), .HASH1(r_HASH1),
- .CrcHash(CrcHash), .CrcHashGood(CrcHashGood), .StateData(StateData),
- .Multicast(Multicast), .MAC(MAC), .RxAbort(RxAbort),
- .RxEndFrm(RxEndFrm), .AddressMiss(AddressMiss), .PassAll(PassAll),
- .ControlFrmAddressOK(ControlFrmAddressOK)
- );
-
-
-assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
-assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) & DlyCrcCnt[3:0] < 4'h9;
-
-assign Data_Crc[0] = MRxD[3];
-assign Data_Crc[1] = MRxD[2];
-assign Data_Crc[2] = MRxD[1];
-assign Data_Crc[3] = MRxD[0];
-
-
-// Connecting module Crc
-eth_crc crcrx (.Clk(MRxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
- .Crc(Crc), .CrcError(CrcError)
- );
-
-
-
-// Latching CRC for use in the hash table
-
-always @ (posedge MRxClk)
-begin
- CrcHashGood <= #Tp StateData[0] & ByteCntEq6;
-end
-
-always @ (posedge MRxClk)
-begin
- if(Reset | StateIdle)
- CrcHash[5:0] <= #Tp 6'h0;
- else
- if(StateData[0] & ByteCntEq6)
- CrcHash[5:0] <= #Tp Crc[31:26];
-end
-
-
-// Output byte stream
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxData_d[7:0] <= #Tp 8'h0;
- DelayData <= #Tp 1'b0;
- LatchedByte[7:0] <= #Tp 8'h0;
- RxData[7:0] <= #Tp 8'h0;
- end
- else
- begin
- LatchedByte[7:0] <= #Tp {MRxD[3:0], LatchedByte[7:4]}; // Latched byte
- DelayData <= #Tp StateData[0];
-
- if(GenerateRxValid)
- RxData_d[7:0] <= #Tp LatchedByte[7:0] & {8{|StateData}}; // Data goes through only in data state
- else
- if(~DelayData)
- RxData_d[7:0] <= #Tp 8'h0; // Delaying data to be valid for two cycles. Zero when not active.
-
- RxData[7:0] <= #Tp RxData_d[7:0]; // Output data byte
- end
-end
-
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- Broadcast <= #Tp 1'b0;
- else
- begin
- if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
- Broadcast <= #Tp 1'b0;
- else
- if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
- Broadcast <= #Tp 1'b1;
- else
- if(RxAbort | RxEndFrm)
- Broadcast <= #Tp 1'b0;
- end
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- Multicast <= #Tp 1'b0;
- else
- begin
- if(StateData[0] & ByteCntEq1 & LatchedByte[0])
- Multicast <= #Tp 1'b1;
- else if(RxAbort | RxEndFrm)
- Multicast <= #Tp 1'b0;
- end
-end
-
-
-assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxValid_d <= #Tp 1'b0;
- RxValid <= #Tp 1'b0;
- end
- else
- begin
- RxValid_d <= #Tp GenerateRxValid;
- RxValid <= #Tp RxValid_d;
- end
-end
-
-
-assign GenerateRxStartFrm = StateData[0] & (ByteCntEq1 & ~DlyCrcEn | DlyCrcCnt == 4'h3 & DlyCrcEn);
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxStartFrm_d <= #Tp 1'b0;
- RxStartFrm <= #Tp 1'b0;
- end
- else
- begin
- RxStartFrm_d <= #Tp GenerateRxStartFrm;
- RxStartFrm <= #Tp RxStartFrm_d;
- end
-end
-
-
-assign GenerateRxEndFrm = StateData[0] & (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
-assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxEndFrm_d <= #Tp 1'b0;
- RxEndFrm <= #Tp 1'b0;
- end
- else
- begin
- RxEndFrm_d <= #Tp GenerateRxEndFrm;
- RxEndFrm <= #Tp RxEndFrm_d | DribbleRxEndFrm;
- end
-end
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_rxstatem.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_rxstatem.v,v $
-// Revision 1.6 2002/11/13 22:28:26 tadejm
-// StartIdle state changed (not important the size of the packet).
-// StartData1 activates only while ByteCnt is smaller than the MaxFrame.
-//
-// Revision 1.5 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.4 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.3 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.2 2001/07/03 12:55:41 mohor
-// Minor changes because of the synthesys warnings.
-//
-//
-// Revision 1.1 2001/06/27 21:26:19 mohor
-// Initial release of the RxEthMAC module.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_rxstatem (MRxClk, Reset, MRxDV, ByteCntEq0, ByteCntGreat2, Transmitting, MRxDEq5, MRxDEqD,
- IFGCounterEq24, ByteCntMaxFrame, StateData, StateIdle, StatePreamble, StateSFD,
- StateDrop
- );
-
-parameter Tp = 1;
-
-input MRxClk;
-input Reset;
-input MRxDV;
-input ByteCntEq0;
-input ByteCntGreat2;
-input MRxDEq5;
-input Transmitting;
-input MRxDEqD;
-input IFGCounterEq24;
-input ByteCntMaxFrame;
-
-output [1:0] StateData;
-output StateIdle;
-output StateDrop;
-output StatePreamble;
-output StateSFD;
-
-reg StateData0;
-reg StateData1;
-reg StateIdle;
-reg StateDrop;
-reg StatePreamble;
-reg StateSFD;
-
-wire StartIdle;
-wire StartDrop;
-wire StartData0;
-wire StartData1;
-wire StartPreamble;
-wire StartSFD;
-
-
-// Defining the next state
-assign StartIdle = ~MRxDV & (StateDrop | StatePreamble | StateSFD | (|StateData));
-
-assign StartPreamble = MRxDV & ~MRxDEq5 & (StateIdle & ~Transmitting);
-
-assign StartSFD = MRxDV & MRxDEq5 & (StateIdle & ~Transmitting | StatePreamble);
-
-assign StartData0 = MRxDV & (StateSFD & MRxDEqD & IFGCounterEq24 | StateData1);
-
-assign StartData1 = MRxDV & StateData0 & (~ByteCntMaxFrame);
-
-assign StartDrop = MRxDV & (StateIdle & Transmitting | StateSFD & ~IFGCounterEq24 & MRxDEqD
- | StateData0 & ByteCntMaxFrame
- );
-
-// Rx State Machine
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- StateIdle <= #Tp 1'b0;
- StateDrop <= #Tp 1'b1;
- StatePreamble <= #Tp 1'b0;
- StateSFD <= #Tp 1'b0;
- StateData0 <= #Tp 1'b0;
- StateData1 <= #Tp 1'b0;
- end
- else
- begin
- if(StartPreamble | StartSFD | StartDrop)
- StateIdle <= #Tp 1'b0;
- else
- if(StartIdle)
- StateIdle <= #Tp 1'b1;
-
- if(StartIdle)
- StateDrop <= #Tp 1'b0;
- else
- if(StartDrop)
- StateDrop <= #Tp 1'b1;
-
- if(StartSFD | StartIdle | StartDrop)
- StatePreamble <= #Tp 1'b0;
- else
- if(StartPreamble)
- StatePreamble <= #Tp 1'b1;
-
- if(StartPreamble | StartIdle | StartData0 | StartDrop)
- StateSFD <= #Tp 1'b0;
- else
- if(StartSFD)
- StateSFD <= #Tp 1'b1;
-
- if(StartIdle | StartData1 | StartDrop)
- StateData0 <= #Tp 1'b0;
- else
- if(StartData0)
- StateData0 <= #Tp 1'b1;
-
- if(StartIdle | StartData0 | StartDrop)
- StateData1 <= #Tp 1'b0;
- else
- if(StartData1)
- StateData1 <= #Tp 1'b1;
- end
-end
-
-assign StateData[1:0] = {StateData1, StateData0};
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_shiftreg.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_shiftreg.v,v $
-// Revision 1.6 2005/03/08 14:45:09 igorm
-// Case statement improved for synthesys.
-//
-// Revision 1.5 2002/08/14 18:16:59 mohor
-// LinkFail signal was not latching appropriate bit.
-//
-// Revision 1.4 2002/03/02 21:06:01 mohor
-// LinkFail signal was not latching appropriate bit.
-//
-// Revision 1.3 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.2 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/01 22:28:56 mohor
-// This files (MIIM) are fully working. They were thoroughly tested. The testbench is not updated.
-//
-//
-
-`include "timescale.v"
-
-
-module eth_shiftreg(Clk, Reset, MdcEn_n, Mdi, Fiad, Rgad, CtrlData, WriteOp, ByteSelect,
- LatchByte, ShiftedBit, Prsd, LinkFail);
-
-
-parameter Tp=1;
-
-input Clk; // Input clock (Host clock)
-input Reset; // Reset signal
-input MdcEn_n; // Enable signal is asserted for one Clk period before Mdc falls.
-input Mdi; // MII input data
-input [4:0] Fiad; // PHY address
-input [4:0] Rgad; // Register address (within the selected PHY)
-input [15:0]CtrlData; // Control data (data to be written to the PHY)
-input WriteOp; // The current operation is a PHY register write operation
-input [3:0] ByteSelect; // Byte select
-input [1:0] LatchByte; // Byte select for latching (read operation)
-
-output ShiftedBit; // Bit shifted out of the shift register
-output[15:0]Prsd; // Read Status Data (data read from the PHY)
-output LinkFail; // Link Integrity Signal
-
-reg [7:0] ShiftReg; // Shift register for shifting the data in and out
-reg [15:0]Prsd;
-reg LinkFail;
-
-
-
-
-// ShiftReg[7:0] :: Shift Register Data
-always @ (posedge Clk or posedge Reset)
-begin
- if(Reset)
- begin
- ShiftReg[7:0] <= #Tp 8'h0;
- Prsd[15:0] <= #Tp 16'h0;
- LinkFail <= #Tp 1'b0;
- end
- else
- begin
- if(MdcEn_n)
- begin
- if(|ByteSelect)
- begin
- case (ByteSelect[3:0]) // synopsys parallel_case full_case
- 4'h1 : ShiftReg[7:0] <= #Tp {2'b01, ~WriteOp, WriteOp, Fiad[4:1]};
- 4'h2 : ShiftReg[7:0] <= #Tp {Fiad[0], Rgad[4:0], 2'b10};
- 4'h4 : ShiftReg[7:0] <= #Tp CtrlData[15:8];
- 4'h8 : ShiftReg[7:0] <= #Tp CtrlData[7:0];
- endcase
- end
- else
- begin
- ShiftReg[7:0] <= #Tp {ShiftReg[6:0], Mdi};
- if(LatchByte[0])
- begin
- Prsd[7:0] <= #Tp {ShiftReg[6:0], Mdi};
- if(Rgad == 5'h01)
- LinkFail <= #Tp ~ShiftReg[1]; // this is bit [2], because it is not shifted yet
- end
- else
- begin
- if(LatchByte[1])
- Prsd[15:8] <= #Tp {ShiftReg[6:0], Mdi};
- end
- end
- end
- end
-end
-
-
-assign ShiftedBit = ShiftReg[7];
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_spram_256x32.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_spram_256x32.v,v $
-// Revision 1.10 2005/02/21 12:48:07 igorm
-// Warning fixes.
-//
-// Revision 1.9 2003/12/05 12:43:06 tadejm
-// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
-//
-// Revision 1.8 2003/12/04 14:59:13 simons
-// Lapsus fixed (!we -> ~we).
-//
-// Revision 1.7 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.6 2003/10/17 07:46:15 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.5 2003/08/14 16:42:58 simons
-// Artisan ram instance added.
-//
-// Revision 1.4 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.3 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.2 2002/09/23 18:24:31 mohor
-// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
-//
-// Revision 1.1 2002/07/23 16:36:09 mohor
-// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
-//
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-module eth_spram_256x32(
- // Generic synchronous single-port RAM interface
- clk, rst, ce, we, oe, addr, di, do
-
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-
-
-);
-
- //
- // Generic synchronous single-port RAM interface
- //
- input clk; // Clock, rising edge
- input rst; // Reset, active high
- input ce; // Chip enable input, active high
- input [3:0] we; // Write enable input, active high
- input oe; // Output enable input, active high
- input [7:0] addr; // address bus inputs
- input [31:0] di; // input data bus
- output [31:0] do; // output data bus
-
-
-`ifdef ETH_BIST
- input mbist_si_i; // bist scan serial in
- output mbist_so_o; // bist scan serial out
- input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-`ifdef ETH_XILINX_RAMB4
-
- /*RAMB4_S16 ram0
- (
- .DO (do[15:0]),
- .ADDR (addr),
- .DI (di[15:0]),
- .EN (ce),
- .CLK (clk),
- .WE (we),
- .RST (rst)
- );
-
- RAMB4_S16 ram1
- (
- .DO (do[31:16]),
- .ADDR (addr),
- .DI (di[31:16]),
- .EN (ce),
- .CLK (clk),
- .WE (we),
- .RST (rst)
- );*/
-
- RAMB4_S8 ram0
- (
- .DO (do[7:0]),
- .ADDR ({1'b0, addr}),
- .DI (di[7:0]),
- .EN (ce),
- .CLK (clk),
- .WE (we[0]),
- .RST (rst)
- );
-
- RAMB4_S8 ram1
- (
- .DO (do[15:8]),
- .ADDR ({1'b0, addr}),
- .DI (di[15:8]),
- .EN (ce),
- .CLK (clk),
- .WE (we[1]),
- .RST (rst)
- );
-
- RAMB4_S8 ram2
- (
- .DO (do[23:16]),
- .ADDR ({1'b0, addr}),
- .DI (di[23:16]),
- .EN (ce),
- .CLK (clk),
- .WE (we[2]),
- .RST (rst)
- );
-
- RAMB4_S8 ram3
- (
- .DO (do[31:24]),
- .ADDR ({1'b0, addr}),
- .DI (di[31:24]),
- .EN (ce),
- .CLK (clk),
- .WE (we[3]),
- .RST (rst)
- );
-
-`else // !ETH_XILINX_RAMB4
-`ifdef ETH_VIRTUAL_SILICON_RAM
- `ifdef ETH_BIST
- //vs_hdsp_256x32_bist ram0_bist
- vs_hdsp_256x32_bw_bist ram0_bist
- `else
- //vs_hdsp_256x32 ram0
- vs_hdsp_256x32_bw ram0
- `endif
- (
- .CK (clk),
- .CEN (!ce),
- .WEN (~we),
- .OEN (!oe),
- .ADR (addr),
- .DI (di),
- .DOUT (do)
-
- `ifdef ETH_BIST
- ,
- // debug chain signals
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
- `endif
- );
-
-`else // !ETH_VIRTUAL_SILICON_RAM
-
-`ifdef ETH_ARTISAN_RAM
- `ifdef ETH_BIST
- //art_hssp_256x32_bist ram0_bist
- art_hssp_256x32_bw_bist ram0_bist
- `else
- //art_hssp_256x32 ram0
- art_hssp_256x32_bw ram0
- `endif
- (
- .CLK (clk),
- .CEN (!ce),
- .WEN (~we),
- .OEN (!oe),
- .A (addr),
- .D (di),
- .Q (do)
-
- `ifdef ETH_BIST
- ,
- // debug chain signals
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
- `endif
- );
-
-`else // !ETH_ARTISAN_RAM
-`ifdef ETH_ALTERA_ALTSYNCRAM
-
- altera_spram_256x32 altera_spram_256x32_inst
- (
- .address (addr),
- .wren (ce & we),
- .clock (clk),
- .data (di),
- .q (do)
- ); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
-
-`else // !ETH_ALTERA_ALTSYNCRAM
-
-
- //
- // Generic single-port synchronous RAM model
- //
-
- //
- // Generic RAM's registers and wires
- //
-`ifdef ETH_SPRAM_BYTE_ENABLE
- reg [ 7: 0] mem0 [255:0]; // RAM content
- reg [15: 8] mem1 [255:0]; // RAM content
- reg [23:16] mem2 [255:0]; // RAM content
- reg [31:24] mem3 [255:0]; // RAM content
-// wire [31:0] q; // RAM output
- reg [7:0] raddr; // RAM read address
- //
- // Data output drivers
- //
- //assign do = (oe & ce) ? q : {32{1'bz}};
-
- //
- // RAM read and write
- //
-
- // read operation
- always@(posedge clk)
- if (ce) // && !we)
- raddr <= #1 addr; // read address needs to be registered to read clock
-
-// assign #1 q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
- assign #1 do = {mem3[raddr], mem2[raddr], mem1[raddr], mem0[raddr]};
-
- // write operation
- always@(posedge clk)
- begin
- if (ce && we[3])
- mem3[addr] <= #1 di[31:24];
- if (ce && we[2])
- mem2[addr] <= #1 di[23:16];
- if (ce && we[1])
- mem1[addr] <= #1 di[15: 8];
- if (ce && we[0])
- mem0[addr] <= #1 di[ 7: 0];
- end
-
- // Task prints range of memory
- // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
- task print_ram;
- input [7:0] start;
- input [7:0] finish;
- integer rnum;
- begin
- for (rnum=start;rnum<=finish;rnum=rnum+1)
- $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
- end
- endtask
-`else // !`ifdef ETH_SPRAM_BYTE_ENABLE
- reg [31:0] mem [255:0]; // RAM content
- reg [7:0] raddr;
- always @ (posedge clk)
- if (ce)
- raddr <= #1 addr;
-
- assign #1 do = mem[raddr];
-
- always @ (posedge clk)
- if (ce && we[0])
- mem[addr] <= #1 di;
-
- // Task prints range of memory
- // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.
- task print_ram;
- input [7:0] start;
- input [7:0] finish;
- integer rnum;
- begin
- for (rnum=start;rnum<=finish;rnum=rnum+1)
- $display("Addr %h = %0h",rnum,mem[rnum]);
- end
- endtask
-
-`endif
-`endif // !ETH_ALTERA_ALTSYNCRAM
-`endif // !ETH_ARTISAN_RAM
-`endif // !ETH_VIRTUAL_SILICON_RAM
-`endif // !ETH_XILINX_RAMB4
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_transmitcontrol.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_transmitcontrol.v,v $
-// Revision 1.6 2002/11/21 00:16:14 mohor
-// When TxUsedData and CtrlMux occur at the same time, byte counter needs
-// to be incremented by 2. Signal IncrementByteCntBy2 added for that reason.
-//
-// Revision 1.5 2002/11/19 17:37:32 mohor
-// When control frame (PAUSE) was sent, status was written in the
-// eth_wishbone module and both TXB and TXC interrupts were set. Fixed.
-// Only TXC interrupt is set.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.1 2001/07/03 12:51:54 mohor
-// Initial release of the MAC Control module.
-//
-//
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_transmitcontrol (MTxClk, TxReset, TxUsedDataIn, TxUsedDataOut, TxDoneIn, TxAbortIn,
- TxStartFrmIn, TPauseRq, TxUsedDataOutDetected, TxFlow, DlyCrcEn,
- TxPauseTV, MAC, TxCtrlStartFrm, TxCtrlEndFrm, SendingCtrlFrm, CtrlMux,
- ControlData, WillSendControlFrame, BlockTxDone
- );
-
-parameter Tp = 1;
-
-
-input MTxClk;
-input TxReset;
-input TxUsedDataIn;
-input TxUsedDataOut;
-input TxDoneIn;
-input TxAbortIn;
-input TxStartFrmIn;
-input TPauseRq;
-input TxUsedDataOutDetected;
-input TxFlow;
-input DlyCrcEn;
-input [15:0] TxPauseTV;
-input [47:0] MAC;
-
-output TxCtrlStartFrm;
-output TxCtrlEndFrm;
-output SendingCtrlFrm;
-output CtrlMux;
-output [7:0] ControlData;
-output WillSendControlFrame;
-output BlockTxDone;
-
-reg SendingCtrlFrm;
-reg CtrlMux;
-reg WillSendControlFrame;
-reg [3:0] DlyCrcCnt;
-reg [5:0] ByteCnt;
-reg ControlEnd_q;
-reg [7:0] MuxedCtrlData;
-reg TxCtrlStartFrm;
-reg TxCtrlStartFrm_q;
-reg TxCtrlEndFrm;
-reg [7:0] ControlData;
-reg TxUsedDataIn_q;
-reg BlockTxDone;
-
-wire IncrementDlyCrcCnt;
-wire ResetByteCnt;
-wire IncrementByteCnt;
-wire ControlEnd;
-wire IncrementByteCntBy2;
-wire EnableCnt;
-
-
-// A command for Sending the control frame is active (latched)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- WillSendControlFrame <= #Tp 1'b0;
- else
- if(TxCtrlEndFrm & CtrlMux)
- WillSendControlFrame <= #Tp 1'b0;
- else
- if(TPauseRq & TxFlow)
- WillSendControlFrame <= #Tp 1'b1;
-end
-
-
-// Generation of the transmit control packet start frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxCtrlStartFrm <= #Tp 1'b0;
- else
- if(TxUsedDataIn_q & CtrlMux)
- TxCtrlStartFrm <= #Tp 1'b0;
- else
- if(WillSendControlFrame & ~TxUsedDataOut & (TxDoneIn | TxAbortIn | TxStartFrmIn | (~TxUsedDataOutDetected)))
- TxCtrlStartFrm <= #Tp 1'b1;
-end
-
-
-
-// Generation of the transmit control packet end frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxCtrlEndFrm <= #Tp 1'b0;
- else
- if(ControlEnd | ControlEnd_q)
- TxCtrlEndFrm <= #Tp 1'b1;
- else
- TxCtrlEndFrm <= #Tp 1'b0;
-end
-
-
-// Generation of the multiplexer signal (controls muxes for switching between
-// normal and control packets)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- CtrlMux <= #Tp 1'b0;
- else
- if(WillSendControlFrame & ~TxUsedDataOut)
- CtrlMux <= #Tp 1'b1;
- else
- if(TxDoneIn)
- CtrlMux <= #Tp 1'b0;
-end
-
-
-
-// Generation of the Sending Control Frame signal (enables padding and CRC)
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- SendingCtrlFrm <= #Tp 1'b0;
- else
- if(WillSendControlFrame & TxCtrlStartFrm)
- SendingCtrlFrm <= #Tp 1'b1;
- else
- if(TxDoneIn)
- SendingCtrlFrm <= #Tp 1'b0;
-end
-
-
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- TxUsedDataIn_q <= #Tp 1'b0;
- else
- TxUsedDataIn_q <= #Tp TxUsedDataIn;
-end
-
-
-
-// Generation of the signal that will block sending the Done signal to the eth_wishbone module
-// While sending the control frame
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- BlockTxDone <= #Tp 1'b0;
- else
- if(TxCtrlStartFrm)
- BlockTxDone <= #Tp 1'b1;
- else
- if(TxStartFrmIn)
- BlockTxDone <= #Tp 1'b0;
-end
-
-
-always @ (posedge MTxClk)
-begin
- ControlEnd_q <= #Tp ControlEnd;
- TxCtrlStartFrm_q <= #Tp TxCtrlStartFrm;
-end
-
-
-assign IncrementDlyCrcCnt = CtrlMux & TxUsedDataIn & ~DlyCrcCnt[2];
-
-
-// Delayed CRC counter
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- DlyCrcCnt <= #Tp 4'h0;
- else
- if(ResetByteCnt)
- DlyCrcCnt <= #Tp 4'h0;
- else
- if(IncrementDlyCrcCnt)
- DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
-end
-
-
-assign ResetByteCnt = TxReset | (~TxCtrlStartFrm & (TxDoneIn | TxAbortIn));
-assign IncrementByteCnt = CtrlMux & (TxCtrlStartFrm & ~TxCtrlStartFrm_q & ~TxUsedDataIn | TxUsedDataIn & ~ControlEnd);
-assign IncrementByteCntBy2 = CtrlMux & TxCtrlStartFrm & (~TxCtrlStartFrm_q) & TxUsedDataIn; // When TxUsedDataIn and CtrlMux are set at the same time
-
-assign EnableCnt = (~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]));
-// Byte counter
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- ByteCnt <= #Tp 6'h0;
- else
- if(ResetByteCnt)
- ByteCnt <= #Tp 6'h0;
- else
- if(IncrementByteCntBy2 & EnableCnt)
- ByteCnt <= #Tp (ByteCnt[5:0] ) + 2'h2;
- else
- if(IncrementByteCnt & EnableCnt)
- ByteCnt <= #Tp (ByteCnt[5:0] ) + 1'b1;
-end
-
-
-assign ControlEnd = ByteCnt[5:0] == 6'h22;
-
-
-// Control data generation (goes to the TxEthMAC module)
-always @ (ByteCnt or DlyCrcEn or MAC or TxPauseTV or DlyCrcCnt)
-begin
- case(ByteCnt)
- 6'h0: if(~DlyCrcEn | DlyCrcEn & (&DlyCrcCnt[1:0]))
- MuxedCtrlData[7:0] = 8'h01; // Reserved Multicast Address
- else
- MuxedCtrlData[7:0] = 8'h0;
- 6'h2: MuxedCtrlData[7:0] = 8'h80;
- 6'h4: MuxedCtrlData[7:0] = 8'hC2;
- 6'h6: MuxedCtrlData[7:0] = 8'h00;
- 6'h8: MuxedCtrlData[7:0] = 8'h00;
- 6'hA: MuxedCtrlData[7:0] = 8'h01;
- 6'hC: MuxedCtrlData[7:0] = MAC[47:40];
- 6'hE: MuxedCtrlData[7:0] = MAC[39:32];
- 6'h10: MuxedCtrlData[7:0] = MAC[31:24];
- 6'h12: MuxedCtrlData[7:0] = MAC[23:16];
- 6'h14: MuxedCtrlData[7:0] = MAC[15:8];
- 6'h16: MuxedCtrlData[7:0] = MAC[7:0];
- 6'h18: MuxedCtrlData[7:0] = 8'h88; // Type/Length
- 6'h1A: MuxedCtrlData[7:0] = 8'h08;
- 6'h1C: MuxedCtrlData[7:0] = 8'h00; // Opcode
- 6'h1E: MuxedCtrlData[7:0] = 8'h01;
- 6'h20: MuxedCtrlData[7:0] = TxPauseTV[15:8]; // Pause timer value
- 6'h22: MuxedCtrlData[7:0] = TxPauseTV[7:0];
- default: MuxedCtrlData[7:0] = 8'h0;
- endcase
-end
-
-
-// Latched Control data
-always @ (posedge MTxClk or posedge TxReset)
-begin
- if(TxReset)
- ControlData[7:0] <= #Tp 8'h0;
- else
- if(~ByteCnt[0])
- ControlData[7:0] <= #Tp MuxedCtrlData[7:0];
-end
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txcounters.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_txcounters.v,v $
-// Revision 1.6 2005/02/21 11:25:27 igorm
-// Delayed CRC fixed.
-//
-// Revision 1.5 2002/04/22 14:54:14 mohor
-// FCS should not be included in NibbleMinFl.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.4 2001/06/27 21:27:45 mohor
-// Few typos fixed.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
- StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
- StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
- ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
- ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
- );
-
-parameter Tp = 1;
-
-input MTxClk; // Tx clock
-input Reset; // Reset
-input StatePreamble; // Preamble state
-input StateIPG; // IPG state
-input [1:0] StateData; // Data state
-input StatePAD; // PAD state
-input StateFCS; // FCS state
-input StateJam; // Jam state
-input StateBackOff; // Backoff state
-input StateDefer; // Defer state
-input StateIdle; // Idle state
-input StateSFD; // SFD state
-input StartDefer; // Defer state will be activated in next clock
-input StartIPG; // IPG state will be activated in next clock
-input StartFCS; // FCS state will be activated in next clock
-input StartJam; // Jam state will be activated in next clock
-input StartBackoff; // Backoff state will be activated in next clock
-input TxStartFrm; // Tx start frame
-input [15:0] MinFL; // Minimum frame length (in bytes)
-input [15:0] MaxFL; // Miximum frame length (in bytes)
-input HugEn; // Pakets bigger then MaxFL enabled
-input ExDfrEn; // Excessive deferral enabled
-input PacketFinished_q;
-input DlyCrcEn; // Delayed CRC enabled
-
-output [15:0] ByteCnt; // Byte counter
-output [15:0] NibCnt; // Nibble counter
-output ExcessiveDefer; // Excessive Deferral occuring
-output NibCntEq7; // Nibble counter is equal to 7
-output NibCntEq15; // Nibble counter is equal to 15
-output MaxFrame; // Maximum frame occured
-output NibbleMinFl; // Nibble counter is greater than the minimum frame length
-output [2:0] DlyCrcCnt; // Delayed CRC Count
-
-wire ExcessiveDeferCnt;
-wire ResetNibCnt;
-wire IncrementNibCnt;
-wire ResetByteCnt;
-wire IncrementByteCnt;
-wire ByteCntMax;
-
-reg [15:0] NibCnt;
-reg [15:0] ByteCnt;
-reg [2:0] DlyCrcCnt;
-
-
-
-assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
- | StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
-
-
-assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
- | StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
-
-// Nibble Counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- NibCnt <= #Tp 16'h0;
- else
- begin
- if(ResetNibCnt)
- NibCnt <= #Tp 16'h0;
- else
- if(IncrementNibCnt)
- NibCnt <= #Tp NibCnt + 1'b1;
- end
-end
-
-
-assign NibCntEq7 = &NibCnt[2:0];
-assign NibCntEq15 = &NibCnt[3:0];
-
-assign NibbleMinFl = NibCnt >= (((MinFL-3'h4)<<1) -1); // FCS should not be included in NibbleMinFl
-
-assign ExcessiveDeferCnt = NibCnt[13:0] == 16'h17b7;
-
-assign ExcessiveDefer = NibCnt[13:0] == 16'h17b7 & ~ExDfrEn; // 6071 nibbles
-
-assign IncrementByteCnt = StateData[1] & ~ByteCntMax
- | StateBackOff & (&NibCnt[6:0])
- | (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
-
-assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
-
-
-// Transmit Byte Counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ByteCnt[15:0] <= #Tp 16'h0;
- else
- begin
- if(ResetByteCnt)
- ByteCnt[15:0] <= #Tp 16'h0;
- else
- if(IncrementByteCnt)
- ByteCnt[15:0] <= #Tp ByteCnt[15:0] + 1'b1;
- end
-end
-
-
-assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
-
-assign ByteCntMax = &ByteCnt[15:0];
-
-
-// Delayed CRC counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- DlyCrcCnt <= #Tp 3'h0;
- else
- begin
- if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
- DlyCrcCnt <= #Tp 3'h0;
- else
- if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
- DlyCrcCnt <= #Tp DlyCrcCnt + 1'b1;
- end
-end
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txethmac.v ////
-/// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_txethmac.v,v $
-// Revision 1.9 2005/02/21 11:25:28 igorm
-// Delayed CRC fixed.
-//
-// Revision 1.8 2003/01/30 13:33:24 mohor
-// When padding was enabled and crc disabled, frame was not ended correctly.
-//
-// Revision 1.7 2002/02/26 16:24:01 mohor
-// RetryCntLatched was unused and removed from design
-//
-// Revision 1.6 2002/02/22 12:56:35 mohor
-// Retry is not activated when a Tx Underrun occured
-//
-// Revision 1.5 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:08 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:58 mohor
-// TxEthMAC initial release.
-//
-//
-//
-
-`include "timescale.v"
-
-
-module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
- Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
- IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
- MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
- ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
- LateCollision, DeferIndication, StatePreamble, StateData
-
- );
-
-parameter Tp = 1;
-
-
-input MTxClk; // Transmit clock (from PHY)
-input Reset; // Reset
-input TxStartFrm; // Transmit packet start frame
-input TxEndFrm; // Transmit packet end frame
-input TxUnderRun; // Transmit packet under-run
-input [7:0] TxData; // Transmit packet data byte
-input CarrierSense; // Carrier sense (synchronized)
-input Collision; // Collision (synchronized)
-input Pad; // Pad enable (from register)
-input CrcEn; // Crc enable (from register)
-input FullD; // Full duplex (from register)
-input HugEn; // Huge packets enable (from register)
-input DlyCrcEn; // Delayed Crc enabled (from register)
-input [15:0] MinFL; // Minimum frame length (from register)
-input [15:0] MaxFL; // Maximum frame length (from register)
-input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
-input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
-input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
-input [5:0] CollValid; // Valid collision window (from register)
-input [3:0] MaxRet; // Maximum retry number (from register)
-input NoBckof; // No backoff (from register)
-input ExDfrEn; // Excessive defferal enable (from register)
-
-output [3:0] MTxD; // Transmit nibble (to PHY)
-output MTxEn; // Transmit enable (to PHY)
-output MTxErr; // Transmit error (to PHY)
-output TxDone; // Transmit packet done (to RISC)
-output TxRetry; // Transmit packet retry (to RISC)
-output TxAbort; // Transmit packet abort (to RISC)
-output TxUsedData; // Transmit packet used data (to RISC)
-output WillTransmit; // Will transmit (to RxEthMAC)
-output ResetCollision; // Reset Collision (for synchronizing collision)
-output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
-output StartTxDone;
-output StartTxAbort;
-output MaxCollisionOccured;
-output LateCollision;
-output DeferIndication;
-output StatePreamble;
-output [1:0] StateData;
-
-reg [3:0] MTxD;
-reg MTxEn;
-reg MTxErr;
-reg TxDone;
-reg TxRetry;
-reg TxAbort;
-reg TxUsedData;
-reg WillTransmit;
-reg ColWindow;
-reg StopExcessiveDeferOccured;
-reg [3:0] RetryCnt;
-reg [3:0] MTxD_d;
-reg StatusLatch;
-reg PacketFinished_q;
-reg PacketFinished;
-
-
-wire ExcessiveDeferOccured;
-wire StartIPG;
-wire StartPreamble;
-wire [1:0] StartData;
-wire StartFCS;
-wire StartJam;
-wire StartDefer;
-wire StartBackoff;
-wire StateDefer;
-wire StateIPG;
-wire StateIdle;
-wire StatePAD;
-wire StateFCS;
-wire StateJam;
-wire StateJam_q;
-wire StateBackOff;
-wire StateSFD;
-wire StartTxRetry;
-wire UnderRun;
-wire TooBig;
-wire [31:0] Crc;
-wire CrcError;
-wire [2:0] DlyCrcCnt;
-wire [15:0] NibCnt;
-wire NibCntEq7;
-wire NibCntEq15;
-wire NibbleMinFl;
-wire ExcessiveDefer;
-wire [15:0] ByteCnt;
-wire MaxFrame;
-wire RetryMax;
-wire RandomEq0;
-wire RandomEqByteCnt;
-wire PacketFinished_d;
-
-
-
-assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
-
-assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
-
-assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
-
-assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
-
-assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
-
-// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
-assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
-
-assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
-
-assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
-
-assign StateSFD = StatePreamble & NibCntEq15;
-
-assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
-
-
-// StopExcessiveDeferOccured
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- StopExcessiveDeferOccured <= #Tp 1'b0;
- else
- begin
- if(~TxStartFrm)
- StopExcessiveDeferOccured <= #Tp 1'b0;
- else
- if(ExcessiveDeferOccured)
- StopExcessiveDeferOccured <= #Tp 1'b1;
- end
-end
-
-
-// Collision Window
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ColWindow <= #Tp 1'b1;
- else
- begin
- if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
- ColWindow <= #Tp 1'b0;
- else
- if(StateIdle | StateIPG)
- ColWindow <= #Tp 1'b1;
- end
-end
-
-
-// Start Window
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- StatusLatch <= #Tp 1'b0;
- else
- begin
- if(~TxStartFrm)
- StatusLatch <= #Tp 1'b0;
- else
- if(ExcessiveDeferOccured | StateIdle)
- StatusLatch <= #Tp 1'b1;
- end
-end
-
-
-// Transmit packet used data
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxUsedData <= #Tp 1'b0;
- else
- TxUsedData <= #Tp |StartData;
-end
-
-
-// Transmit packet done
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxDone <= #Tp 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch)
- TxDone <= #Tp 1'b0;
- else
- if(StartTxDone)
- TxDone <= #Tp 1'b1;
- end
-end
-
-
-// Transmit packet retry
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxRetry <= #Tp 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch)
- TxRetry <= #Tp 1'b0;
- else
- if(StartTxRetry)
- TxRetry <= #Tp 1'b1;
- end
-end
-
-
-// Transmit packet abort
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxAbort <= #Tp 1'b0;
- else
- begin
- if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
- TxAbort <= #Tp 1'b0;
- else
- if(StartTxAbort)
- TxAbort <= #Tp 1'b1;
- end
-end
-
-
-// Retry counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- RetryCnt[3:0] <= #Tp 4'h0;
- else
- begin
- if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
- | StateJam & NibCntEq7 & (~ColWindow | RetryMax))
- RetryCnt[3:0] <= #Tp 4'h0;
- else
- if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
- RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
- end
-end
-
-
-assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
-
-
-// Transmit nibble
-always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
- Crc or NibCntEq15)
-begin
- if(StateData[0])
- MTxD_d[3:0] = TxData[3:0]; // Lower nibble
- else
- if(StateData[1])
- MTxD_d[3:0] = TxData[7:4]; // Higher nibble
- else
- if(StateFCS)
- MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
- else
- if(StateJam)
- MTxD_d[3:0] = 4'h9; // Jam pattern
- else
- if(StatePreamble)
- if(NibCntEq15)
- MTxD_d[3:0] = 4'hd; // SFD
- else
- MTxD_d[3:0] = 4'h5; // Preamble
- else
- MTxD_d[3:0] = 4'h0;
-end
-
-
-// Transmit Enable
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxEn <= #Tp 1'b0;
- else
- MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
-end
-
-
-// Transmit nibble
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxD[3:0] <= #Tp 4'h0;
- else
- MTxD[3:0] <= #Tp MTxD_d[3:0];
-end
-
-
-// Transmit error
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- MTxErr <= #Tp 1'b0;
- else
- MTxErr <= #Tp TooBig | UnderRun;
-end
-
-
-// WillTransmit
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- WillTransmit <= #Tp 1'b0;
- else
- WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
-end
-
-
-assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
-
-
-// Packet finished
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- begin
- PacketFinished <= #Tp 1'b0;
- PacketFinished_q <= #Tp 1'b0;
- end
- else
- begin
- PacketFinished <= #Tp PacketFinished_d;
- PacketFinished_q <= #Tp PacketFinished;
- end
-end
-
-
-// Connecting module Counters
-eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
- .StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
- .StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
- .StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
- .Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
- .PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
- .StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
- .NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
- .DlyCrcCnt(DlyCrcCnt)
- );
-
-
-// Connecting module StateM
-eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
- .NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
- .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
- .UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
- .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
- .NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
- .NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
- .StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
- .StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
- .StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
- .StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
- );
-
-
-wire Enable_Crc;
-wire [3:0] Data_Crc;
-wire Initialize_Crc;
-
-assign Enable_Crc = ~StateFCS;
-
-assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
-assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
-assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
-assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
-
-assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
-
-
-// Connecting module Crc
-eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
- .Crc(Crc), .CrcError(CrcError)
- );
-
-
-// Connecting module Random
-eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
- .NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
-
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_txstatem.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////
-//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_txstatem.v,v $
-// Revision 1.6 2003/01/30 13:29:08 tadejm
-// Defer indication changed.
-//
-// Revision 1.5 2002/10/30 12:54:50 mohor
-// State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.
-//
-// Revision 1.4 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.3 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.2 2001/09/11 14:17:00 mohor
-// Few little NCSIM warnings fixed.
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-// Revision 1.3 2001/06/19 18:16:40 mohor
-// TxClk changed to MTxClk (as discribed in the documentation).
-// Crc changed so only one file can be used instead of two.
-//
-// Revision 1.2 2001/06/19 10:38:07 mohor
-// Minor changes in header.
-//
-// Revision 1.1 2001/06/19 10:27:57 mohor
-// TxEthMAC initial release.
-//
-//
-//
-//
-
-
-`include "timescale.v"
-
-
-module eth_txstatem (MTxClk, Reset, ExcessiveDefer, CarrierSense, NibCnt, IPGT, IPGR1,
- IPGR2, FullD, TxStartFrm, TxEndFrm, TxUnderRun, Collision, UnderRun,
- StartTxDone, TooBig, NibCntEq7, NibCntEq15, MaxFrame, Pad, CrcEn,
- NibbleMinFl, RandomEq0, ColWindow, RetryMax, NoBckof, RandomEqByteCnt,
- StateIdle, StateIPG, StatePreamble, StateData, StatePAD, StateFCS,
- StateJam, StateJam_q, StateBackOff, StateDefer, StartFCS, StartJam,
- StartBackoff, StartDefer, DeferIndication, StartPreamble, StartData, StartIPG
- );
-
-parameter Tp = 1;
-
-input MTxClk;
-input Reset;
-input ExcessiveDefer;
-input CarrierSense;
-input [6:0] NibCnt;
-input [6:0] IPGT;
-input [6:0] IPGR1;
-input [6:0] IPGR2;
-input FullD;
-input TxStartFrm;
-input TxEndFrm;
-input TxUnderRun;
-input Collision;
-input UnderRun;
-input StartTxDone;
-input TooBig;
-input NibCntEq7;
-input NibCntEq15;
-input MaxFrame;
-input Pad;
-input CrcEn;
-input NibbleMinFl;
-input RandomEq0;
-input ColWindow;
-input RetryMax;
-input NoBckof;
-input RandomEqByteCnt;
-
-
-output StateIdle; // Idle state
-output StateIPG; // IPG state
-output StatePreamble; // Preamble state
-output [1:0] StateData; // Data state
-output StatePAD; // PAD state
-output StateFCS; // FCS state
-output StateJam; // Jam state
-output StateJam_q; // Delayed Jam state
-output StateBackOff; // Backoff state
-output StateDefer; // Defer state
-
-output StartFCS; // FCS state will be activated in next clock
-output StartJam; // Jam state will be activated in next clock
-output StartBackoff; // Backoff state will be activated in next clock
-output StartDefer; // Defer state will be activated in next clock
-output DeferIndication;
-output StartPreamble; // Preamble state will be activated in next clock
-output [1:0] StartData; // Data state will be activated in next clock
-output StartIPG; // IPG state will be activated in next clock
-
-wire StartIdle; // Idle state will be activated in next clock
-wire StartPAD; // PAD state will be activated in next clock
-
-
-reg StateIdle;
-reg StateIPG;
-reg StatePreamble;
-reg [1:0] StateData;
-reg StatePAD;
-reg StateFCS;
-reg StateJam;
-reg StateJam_q;
-reg StateBackOff;
-reg StateDefer;
-reg Rule1;
-
-
-// Defining the next state
-assign StartIPG = StateDefer & ~ExcessiveDefer & ~CarrierSense;
-
-assign StartIdle = StateIPG & (Rule1 & NibCnt[6:0] >= IPGT | ~Rule1 & NibCnt[6:0] >= IPGR2);
-
-assign StartPreamble = StateIdle & TxStartFrm & ~CarrierSense;
-
-assign StartData[0] = ~Collision & (StatePreamble & NibCntEq15 | StateData[1] & ~TxEndFrm);
-
-assign StartData[1] = ~Collision & StateData[0] & ~TxUnderRun & ~MaxFrame;
-
-assign StartPAD = ~Collision & StateData[1] & TxEndFrm & Pad & ~NibbleMinFl;
-
-assign StartFCS = ~Collision & StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & CrcEn
- | ~Collision & StatePAD & NibbleMinFl & CrcEn;
-
-assign StartJam = (Collision | UnderRun) & ((StatePreamble & NibCntEq15) | (|StateData[1:0]) | StatePAD | StateFCS);
-
-assign StartBackoff = StateJam & ~RandomEq0 & ColWindow & ~RetryMax & NibCntEq7 & ~NoBckof;
-
-assign StartDefer = StateIPG & ~Rule1 & CarrierSense & NibCnt[6:0] <= IPGR1 & NibCnt[6:0] != IPGR2
- | StateIdle & CarrierSense
- | StateJam & NibCntEq7 & (NoBckof | RandomEq0 | ~ColWindow | RetryMax)
- | StateBackOff & (TxUnderRun | RandomEqByteCnt)
- | StartTxDone | TooBig;
-
-assign DeferIndication = StateIdle & CarrierSense;
-
-// Tx State Machine
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- begin
- StateIPG <= #Tp 1'b0;
- StateIdle <= #Tp 1'b0;
- StatePreamble <= #Tp 1'b0;
- StateData[1:0] <= #Tp 2'b0;
- StatePAD <= #Tp 1'b0;
- StateFCS <= #Tp 1'b0;
- StateJam <= #Tp 1'b0;
- StateJam_q <= #Tp 1'b0;
- StateBackOff <= #Tp 1'b0;
- StateDefer <= #Tp 1'b1;
- end
- else
- begin
- StateData[1:0] <= #Tp StartData[1:0];
- StateJam_q <= #Tp StateJam;
-
- if(StartDefer | StartIdle)
- StateIPG <= #Tp 1'b0;
- else
- if(StartIPG)
- StateIPG <= #Tp 1'b1;
-
- if(StartDefer | StartPreamble)
- StateIdle <= #Tp 1'b0;
- else
- if(StartIdle)
- StateIdle <= #Tp 1'b1;
-
- if(StartData[0] | StartJam)
- StatePreamble <= #Tp 1'b0;
- else
- if(StartPreamble)
- StatePreamble <= #Tp 1'b1;
-
- if(StartFCS | StartJam)
- StatePAD <= #Tp 1'b0;
- else
- if(StartPAD)
- StatePAD <= #Tp 1'b1;
-
- if(StartJam | StartDefer)
- StateFCS <= #Tp 1'b0;
- else
- if(StartFCS)
- StateFCS <= #Tp 1'b1;
-
- if(StartBackoff | StartDefer)
- StateJam <= #Tp 1'b0;
- else
- if(StartJam)
- StateJam <= #Tp 1'b1;
-
- if(StartDefer)
- StateBackOff <= #Tp 1'b0;
- else
- if(StartBackoff)
- StateBackOff <= #Tp 1'b1;
-
- if(StartIPG)
- StateDefer <= #Tp 1'b0;
- else
- if(StartDefer)
- StateDefer <= #Tp 1'b1;
- end
-end
-
-
-// This sections defines which interpack gap rule to use
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- Rule1 <= #Tp 1'b0;
- else
- begin
- if(StateIdle | StateBackOff)
- Rule1 <= #Tp 1'b0;
- else
- if(StatePreamble | FullD)
- Rule1 <= #Tp 1'b1;
- end
-end
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_wishbone.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_wishbone.v,v $
-// Revision 1.58 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.57 2005/02/21 11:35:33 igorm
-// Defer indication fixed.
-//
-// Revision 1.56 2004/04/30 10:30:00 igorm
-// Accidently deleted line put back.
-//
-// Revision 1.55 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.54 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.53 2003/10/17 07:46:17 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.52 2003/01/30 14:51:31 mohor
-// Reset has priority in some flipflops.
-//
-// Revision 1.51 2003/01/30 13:36:22 mohor
-// A new bug (entered with previous update) fixed. When abort occured sometimes
-// data transmission was blocked.
-//
-// Revision 1.50 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.49 2003/01/21 12:09:40 mohor
-// When receiving normal data frame and RxFlow control was switched on, RXB
-// interrupt was not set.
-//
-// Revision 1.48 2003/01/20 12:05:26 mohor
-// When in full duplex, transmit was sometimes blocked. Fixed.
-//
-// Revision 1.47 2002/11/22 13:26:21 mohor
-// Registers RxStatusWrite_rck and RxStatusWriteLatched were not used
-// anywhere. Removed.
-//
-// Revision 1.46 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.45 2002/11/19 17:33:34 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.44 2002/11/13 22:21:40 tadejm
-// RxError is not generated when small frame reception is enabled and small
-// frames are received.
-//
-// Revision 1.43 2002/10/18 20:53:34 mohor
-// case changed to casex.
-//
-// Revision 1.42 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.41 2002/10/18 15:42:09 tadejm
-// Igor added WB burst support and repaired BUG when handling TX under-run and retry.
-//
-// Revision 1.40 2002/10/14 16:07:02 mohor
-// TxStatus is written after last access to the TX fifo is finished (in case of abort
-// or retry). TxDone is fixed.
-//
-// Revision 1.39 2002/10/11 15:35:20 mohor
-// txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
-// TxDone and TxRetry are generated after the current WISHBONE access is
-// finished.
-//
-// Revision 1.38 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.37 2002/09/11 14:18:46 mohor
-// Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.
-//
-// Revision 1.36 2002/09/10 13:48:46 mohor
-// Reception is possible after RxPointer is read and not after BD is read. For
-// that reason RxBDReady is changed to RxReady.
-// Busy_IRQ interrupt connected. When there is no RxBD ready and frame
-// comes, interrupt is generated.
-//
-// Revision 1.35 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.34 2002/09/08 16:31:49 mohor
-// Async reset for WB_ACK_O removed (when core was in reset, it was
-// impossible to access BDs).
-// RxPointers and TxPointers names changed to be more descriptive.
-// TxUnderRun synchronized.
-//
-// Revision 1.33 2002/09/04 18:47:57 mohor
-// Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
-// changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
-// was not used OK.
-//
-// Revision 1.32 2002/08/14 19:31:48 mohor
-// Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
-// need to multiply or devide any more.
-//
-// Revision 1.31 2002/07/25 18:29:01 mohor
-// WriteRxDataToMemory signal changed so end of frame (when last word is
-// written to fifo) is changed.
-//
-// Revision 1.30 2002/07/23 15:28:31 mohor
-// Ram , used for BDs changed from generic_spram to eth_spram_256x32.
-//
-// Revision 1.29 2002/07/20 00:41:32 mohor
-// ShiftEnded synchronization changed.
-//
-// Revision 1.28 2002/07/18 16:11:46 mohor
-// RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.
-//
-// Revision 1.27 2002/07/11 02:53:20 mohor
-// RxPointer bug fixed.
-//
-// Revision 1.26 2002/07/10 13:12:38 mohor
-// Previous bug wasn't succesfully removed. Now fixed.
-//
-// Revision 1.25 2002/07/09 23:53:24 mohor
-// Master state machine had a bug when switching from master write to
-// master read.
-//
-// Revision 1.24 2002/07/09 20:44:41 mohor
-// m_wb_cyc_o signal released after every single transfer.
-//
-// Revision 1.23 2002/05/03 10:15:50 mohor
-// Outputs registered. Reset changed for eth_wishbone module.
-//
-// Revision 1.22 2002/04/24 08:52:19 mohor
-// Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
-// bug fixed.
-//
-// Revision 1.21 2002/03/29 16:18:11 lampret
-// Small typo fixed.
-//
-// Revision 1.20 2002/03/25 16:19:12 mohor
-// Any address can be used for Tx and Rx BD pointers. Address does not need
-// to be aligned.
-//
-// Revision 1.19 2002/03/19 12:51:50 mohor
-// Comments in Slovene language removed.
-//
-// Revision 1.18 2002/03/19 12:46:52 mohor
-// casex changed with case, fifo reset changed.
-//
-// Revision 1.17 2002/03/09 16:08:45 mohor
-// rx_fifo was not always cleared ok. Fixed.
-//
-// Revision 1.16 2002/03/09 13:51:20 mohor
-// Status was not latched correctly sometimes. Fixed.
-//
-// Revision 1.15 2002/03/08 06:56:46 mohor
-// Big Endian problem when sending frames fixed.
-//
-// Revision 1.14 2002/03/02 19:12:40 mohor
-// Byte ordering changed (Big Endian used). casex changed with case because
-// Xilinx Foundation had problems. Tested in HW. It WORKS.
-//
-// Revision 1.13 2002/02/26 16:59:55 mohor
-// Small fixes for external/internal DMA missmatches.
-//
-// Revision 1.12 2002/02/26 16:22:07 mohor
-// Interrupts changed
-//
-// Revision 1.11 2002/02/15 17:07:39 mohor
-// Status was not written correctly when frames were discarted because of
-// address mismatch.
-//
-// Revision 1.10 2002/02/15 12:17:39 mohor
-// RxStartFrm cleared when abort or retry comes.
-//
-// Revision 1.9 2002/02/15 11:59:10 mohor
-// Changes that were lost when updating from 1.5 to 1.8 fixed.
-//
-// Revision 1.8 2002/02/14 20:54:33 billditt
-// Addition of new module eth_addrcheck.v
-//
-// Revision 1.7 2002/02/12 17:03:47 mohor
-// RxOverRun added to statuses.
-//
-// Revision 1.6 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.5 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.4 2002/02/06 14:10:21 mohor
-// non-DMA host interface added. Select the right configutation in eth_defines.
-//
-// Revision 1.3 2002/02/05 16:44:39 mohor
-// Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
-// MHz. Statuses, overrun, control frame transmission and reception still need
-// to be fixed.
-//
-// Revision 1.2 2002/02/01 12:46:51 mohor
-// Tx part finished. TxStatus needs to be fixed. Pause request needs to be
-// added.
-//
-// Revision 1.1 2002/01/23 10:47:59 mohor
-// Initial version. Equals to eth_wishbonedma.v at this moment.
-//
-//
-//
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_wishbone
- (
-
- // WISHBONE common
- WB_CLK_I, WB_DAT_I, WB_DAT_O,
-
- // WISHBONE slave
- WB_ADR_I, WB_WE_I, WB_ACK_O,
- BDCs,
-
- Reset,
-
- // WISHBONE master
- m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
- m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
- m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
-
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o, m_wb_bte_o,
-`endif
-
- //TX
- MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData,
- TxRetry, TxAbort, TxUnderRun, TxDone, PerPacketCrcEn,
- PerPacketPad,
-
- //RX
- MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, RxAbort, RxStatusWriteLatched_sync2,
-
- // Register
- r_TxEn, r_RxEn, r_TxBDNum, r_RxFlow, r_PassAll,
-
- // Interrupts
- TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ,
-
- // Rx Status
- InvalidSymbol, LatchedCrcError, RxLateCollision, ShortFrame, DribbleNibble,
- ReceivedPacketTooBig, RxLength, LoadRxStatus, ReceivedPacketGood, AddressMiss,
- ReceivedPauseFrm,
-
- // Tx Status
- RetryCntLatched, RetryLimit, LateCollLatched, DeferLatched, RstDeferLatched, CarrierSenseLost
-
- // Bist
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-
-
- );
-
-
-parameter Tp = 1;
-
-
-// WISHBONE common
-input WB_CLK_I; // WISHBONE clock
-input [31:0] WB_DAT_I; // WISHBONE data input
-output [31:0] WB_DAT_O; // WISHBONE data output
-
-// WISHBONE slave
-input [9:2] WB_ADR_I; // WISHBONE address input
-input WB_WE_I; // WISHBONE write enable input
-input [3:0] BDCs; // Buffer descriptors are selected
-output WB_ACK_O; // WISHBONE acknowledge output
-
-// WISHBONE master
-output [29:0] m_wb_adr_o; //
-output [3:0] m_wb_sel_o; //
-output m_wb_we_o; //
-output [31:0] m_wb_dat_o; //
-output m_wb_cyc_o; //
-output m_wb_stb_o; //
-input [31:0] m_wb_dat_i; //
-input m_wb_ack_i; //
-input m_wb_err_i; //
-
-`ifdef ETH_WISHBONE_B3
-output [2:0] m_wb_cti_o; // Cycle Type Identifier
-output [1:0] m_wb_bte_o; // Burst Type Extension
-reg [2:0] m_wb_cti_o; // Cycle Type Identifier
-`endif
-
-input Reset; // Reset signal
-
-// Rx Status signals
-input InvalidSymbol; // Invalid symbol was received during reception in 100 Mbps mode
-input LatchedCrcError; // CRC error
-input RxLateCollision; // Late collision occured while receiving frame
-input ShortFrame; // Frame shorter then the minimum size (r_MinFL) was received while small packets are enabled (r_RecSmall)
-input DribbleNibble; // Extra nibble received
-input ReceivedPacketTooBig;// Received packet is bigger than r_MaxFL
-input [15:0] RxLength; // Length of the incoming frame
-input LoadRxStatus; // Rx status was loaded
-input ReceivedPacketGood;// Received packet's length and CRC are good
-input AddressMiss; // When a packet is received AddressMiss status is written to the Rx BD
-input r_RxFlow;
-input r_PassAll;
-input ReceivedPauseFrm;
-
-// Tx Status signals
-input [3:0] RetryCntLatched; // Latched Retry Counter
-input RetryLimit; // Retry limit reached (Retry Max value + 1 attempts were made)
-input LateCollLatched; // Late collision occured
-input DeferLatched; // Defer indication (Frame was defered before sucessfully sent)
-output RstDeferLatched;
-input CarrierSenseLost; // Carrier Sense was lost during the frame transmission
-
-// Tx
-input MTxClk; // Transmit clock (from PHY)
-input TxUsedData; // Transmit packet used data
-input TxRetry; // Transmit packet retry
-input TxAbort; // Transmit packet abort
-input TxDone; // Transmission ended
-output TxStartFrm; // Transmit packet start frame
-output TxEndFrm; // Transmit packet end frame
-output [7:0] TxData; // Transmit packet data byte
-output TxUnderRun; // Transmit packet under-run
-output PerPacketCrcEn; // Per packet crc enable
-output PerPacketPad; // Per packet pading
-
-// Rx
-input MRxClk; // Receive clock (from PHY)
-input [7:0] RxData; // Received data byte (from PHY)
-input RxValid; //
-input RxStartFrm; //
-input RxEndFrm; //
-input RxAbort; // This signal is set when address doesn't match.
-output RxStatusWriteLatched_sync2;
-
-//Register
-input r_TxEn; // Transmit enable
-input r_RxEn; // Receive enable
-input [7:0] r_TxBDNum; // Receive buffer descriptor number
-
-// Interrupts
-output TxB_IRQ;
-output TxE_IRQ;
-output RxB_IRQ;
-output RxE_IRQ;
-output Busy_IRQ;
-
-
-// Bist
-`ifdef ETH_BIST
-input mbist_si_i; // bist scan serial in
-output mbist_so_o; // bist scan serial out
-input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-reg TxB_IRQ;
-reg TxE_IRQ;
-reg RxB_IRQ;
-reg RxE_IRQ;
-
-reg TxStartFrm;
-reg TxEndFrm;
-reg [7:0] TxData;
-
-reg TxUnderRun;
-reg TxUnderRun_wb;
-
-reg TxBDRead;
-wire TxStatusWrite;
-
-reg [1:0] TxValidBytesLatched;
-
-reg [15:0] TxLength;
-reg [15:0] LatchedTxLength;
-reg [14:11] TxStatus;
-
-reg [14:13] RxStatus;
-
-reg TxStartFrm_wb;
-reg TxRetry_wb;
-reg TxAbort_wb;
-reg TxDone_wb;
-
-reg TxDone_wb_q;
-reg TxAbort_wb_q;
-reg TxRetry_wb_q;
-reg TxRetryPacket;
-reg TxRetryPacket_NotCleared;
-reg TxDonePacket;
-reg TxDonePacket_NotCleared;
-reg TxAbortPacket;
-reg TxAbortPacket_NotCleared;
-reg RxBDReady;
-reg RxReady;
-reg TxBDReady;
-
-reg RxBDRead;
-
-reg [31:0] TxDataLatched;
-reg [1:0] TxByteCnt;
-reg LastWord;
-reg ReadTxDataFromFifo_tck;
-
-reg BlockingTxStatusWrite;
-reg BlockingTxBDRead;
-
-reg Flop;
-
-reg [7:1] TxBDAddress;
-reg [7:1] RxBDAddress;
-
-reg TxRetrySync1;
-reg TxAbortSync1;
-reg TxDoneSync1;
-
-reg TxAbort_q;
-reg TxRetry_q;
-reg TxUsedData_q;
-
-reg [31:0] RxDataLatched2;
-
-reg [31:8] RxDataLatched1; // Big Endian Byte Ordering
-
-reg [1:0] RxValidBytes;
-reg [1:0] RxByteCnt;
-reg LastByteIn;
-reg ShiftWillEnd;
-
-reg WriteRxDataToFifo;
-reg [15:0] LatchedRxLength;
-reg RxAbortLatched;
-
-reg ShiftEnded;
-reg RxOverrun;
-
-reg [3:0] BDWrite; // BD Write Enable for access from WISHBONE side
-reg BDRead; // BD Read access from WISHBONE side
-wire [31:0] RxBDDataIn; // Rx BD data in
-wire [31:0] TxBDDataIn; // Tx BD data in
-
-reg TxEndFrm_wb;
-
-wire TxRetryPulse;
-wire TxDonePulse;
-wire TxAbortPulse;
-
-wire StartRxBDRead;
-
-wire StartTxBDRead;
-
-wire TxIRQEn;
-wire WrapTxStatusBit;
-
-wire RxIRQEn;
-wire WrapRxStatusBit;
-
-wire [1:0] TxValidBytes;
-
-wire [7:1] TempTxBDAddress;
-wire [7:1] TempRxBDAddress;
-
-wire RxStatusWrite;
-wire RxBufferFull;
-wire RxBufferAlmostEmpty;
-wire RxBufferEmpty;
-
-reg WB_ACK_O;
-
-wire [8:0] RxStatusIn;
-reg [8:0] RxStatusInLatched;
-
-reg WbEn, WbEn_q;
-reg RxEn, RxEn_q;
-reg TxEn, TxEn_q;
-reg r_TxEn_q;
-reg r_RxEn_q;
-
-wire ram_ce;
-wire [3:0] ram_we;
-wire ram_oe;
-reg [7:0] ram_addr;
-reg [31:0] ram_di;
-wire [31:0] ram_do;
-
-wire StartTxPointerRead;
-reg TxPointerRead;
-reg TxEn_needed;
-reg RxEn_needed;
-
-wire StartRxPointerRead;
-reg RxPointerRead;
-
-`ifdef ETH_WISHBONE_B3
-assign m_wb_bte_o = 2'b00; // Linear burst
-`endif
-
-assign m_wb_stb_o = m_wb_cyc_o;
-
-always @ (posedge WB_CLK_I)
-begin
- WB_ACK_O <=#Tp (|BDWrite) & WbEn & WbEn_q | BDRead & WbEn & ~WbEn_q;
-end
-
-assign WB_DAT_O = ram_do;
-
-// Generic synchronous single-port RAM interface
-eth_spram_256x32 bd_ram (
- .clk(WB_CLK_I), .rst(Reset), .ce(ram_ce), .we(ram_we), .oe(ram_oe), .addr(ram_addr), .di(ram_di), .do(ram_do)
-`ifdef ETH_BIST
- ,
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
-`endif
-);
-
-assign ram_ce = 1'b1;
-assign ram_we = (BDWrite & {4{(WbEn & WbEn_q)}}) | {4{(TxStatusWrite | RxStatusWrite)}};
-assign ram_oe = BDRead & WbEn & WbEn_q | TxEn & TxEn_q & (TxBDRead | TxPointerRead) | RxEn & RxEn_q & (RxBDRead | RxPointerRead);
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxEn_needed <=#Tp 1'b0;
- else
- if(~TxBDReady & r_TxEn & WbEn & ~WbEn_q)
- TxEn_needed <=#Tp 1'b1;
- else
- if(TxPointerRead & TxEn & TxEn_q)
- TxEn_needed <=#Tp 1'b0;
-end
-
-// Enabling access to the RAM for three devices.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- begin
- WbEn <=#Tp 1'b1;
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b0;
- ram_addr <=#Tp 8'h0;
- ram_di <=#Tp 32'h0;
- BDRead <=#Tp 1'b0;
- BDWrite <=#Tp 1'b0;
- end
- else
- begin
- // Switching between three stages depends on enable signals
- case ({WbEn_q, RxEn_q, TxEn_q, RxEn_needed, TxEn_needed}) // synopsys parallel_case
- 5'b100_10, 5'b100_11 :
- begin
- WbEn <=#Tp 1'b0;
- RxEn <=#Tp 1'b1; // wb access stage and r_RxEn is enabled
- TxEn <=#Tp 1'b0;
- ram_addr <=#Tp {RxBDAddress, RxPointerRead};
- ram_di <=#Tp RxBDDataIn;
- end
- 5'b100_01 :
- begin
- WbEn <=#Tp 1'b0;
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b1; // wb access stage, r_RxEn is disabled but r_TxEn is enabled
- ram_addr <=#Tp {TxBDAddress, TxPointerRead};
- ram_di <=#Tp TxBDDataIn;
- end
- 5'b010_00, 5'b010_10 :
- begin
- WbEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is disabled
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b0;
- ram_addr <=#Tp WB_ADR_I[9:2];
- ram_di <=#Tp WB_DAT_I;
- BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
- BDRead <=#Tp (|BDCs) & ~WB_WE_I;
- end
- 5'b010_01, 5'b010_11 :
- begin
- WbEn <=#Tp 1'b0;
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b1; // RxEn access stage and r_TxEn is enabled
- ram_addr <=#Tp {TxBDAddress, TxPointerRead};
- ram_di <=#Tp TxBDDataIn;
- end
- 5'b001_00, 5'b001_01, 5'b001_10, 5'b001_11 :
- begin
- WbEn <=#Tp 1'b1; // TxEn access stage (we always go to wb access stage)
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b0;
- ram_addr <=#Tp WB_ADR_I[9:2];
- ram_di <=#Tp WB_DAT_I;
- BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
- BDRead <=#Tp (|BDCs) & ~WB_WE_I;
- end
- 5'b100_00 :
- begin
- WbEn <=#Tp 1'b0; // WbEn access stage and there is no need for other stages. WbEn needs to be switched off for a bit
- end
- 5'b000_00 :
- begin
- WbEn <=#Tp 1'b1; // Idle state. We go to WbEn access stage.
- RxEn <=#Tp 1'b0;
- TxEn <=#Tp 1'b0;
- ram_addr <=#Tp WB_ADR_I[9:2];
- ram_di <=#Tp WB_DAT_I;
- BDWrite <=#Tp BDCs[3:0] & {4{WB_WE_I}};
- BDRead <=#Tp (|BDCs) & ~WB_WE_I;
- end
- endcase
- end
-end
-
-
-// Delayed stage signals
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- begin
- WbEn_q <=#Tp 1'b0;
- RxEn_q <=#Tp 1'b0;
- TxEn_q <=#Tp 1'b0;
- r_TxEn_q <=#Tp 1'b0;
- r_RxEn_q <=#Tp 1'b0;
- end
- else
- begin
- WbEn_q <=#Tp WbEn;
- RxEn_q <=#Tp RxEn;
- TxEn_q <=#Tp TxEn;
- r_TxEn_q <=#Tp r_TxEn;
- r_RxEn_q <=#Tp r_RxEn;
- end
-end
-
-// Changes for tx occur every second clock. Flop is used for this manner.
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- Flop <=#Tp 1'b0;
- else
- if(TxDone | TxAbort | TxRetry_q)
- Flop <=#Tp 1'b0;
- else
- if(TxUsedData)
- Flop <=#Tp ~Flop;
-end
-
-wire ResetTxBDReady;
-assign ResetTxBDReady = TxDonePulse | TxAbortPulse | TxRetryPulse;
-
-// Latching READY status of the Tx buffer descriptor
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxBDReady <=#Tp 1'b0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- TxBDReady <=#Tp ram_do[15] & (ram_do[31:16] > 4); // TxBDReady is sampled only once at the beginning.
- else // Only packets larger then 4 bytes are transmitted.
- if(ResetTxBDReady)
- TxBDReady <=#Tp 1'b0;
-end
-
-
-// Reading the Tx buffer descriptor
-assign StartTxBDRead = (TxRetryPacket_NotCleared | TxStatusWrite) & ~BlockingTxBDRead & ~TxBDReady;
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxBDRead <=#Tp 1'b1;
- else
- if(StartTxBDRead)
- TxBDRead <=#Tp 1'b1;
- else
- if(TxBDReady)
- TxBDRead <=#Tp 1'b0;
-end
-
-
-// Reading Tx BD pointer
-assign StartTxPointerRead = TxBDRead & TxBDReady;
-
-// Reading Tx BD Pointer
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxPointerRead <=#Tp 1'b0;
- else
- if(StartTxPointerRead)
- TxPointerRead <=#Tp 1'b1;
- else
- if(TxEn_q)
- TxPointerRead <=#Tp 1'b0;
-end
-
-
-// Writing status back to the Tx buffer descriptor
-assign TxStatusWrite = (TxDonePacket_NotCleared | TxAbortPacket_NotCleared) & TxEn & TxEn_q & ~BlockingTxStatusWrite;
-
-
-
-// Status writing must occur only once. Meanwhile it is blocked.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- BlockingTxStatusWrite <=#Tp 1'b0;
- else
- if(~TxDone_wb & ~TxAbort_wb)
- BlockingTxStatusWrite <=#Tp 1'b0;
- else
- if(TxStatusWrite)
- BlockingTxStatusWrite <=#Tp 1'b1;
-end
-
-
-reg BlockingTxStatusWrite_sync1;
-reg BlockingTxStatusWrite_sync2;
-reg BlockingTxStatusWrite_sync3;
-
-// Synchronizing BlockingTxStatusWrite to MTxClk
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- BlockingTxStatusWrite_sync1 <=#Tp 1'b0;
- else
- BlockingTxStatusWrite_sync1 <=#Tp BlockingTxStatusWrite;
-end
-
-// Synchronizing BlockingTxStatusWrite to MTxClk
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- BlockingTxStatusWrite_sync2 <=#Tp 1'b0;
- else
- BlockingTxStatusWrite_sync2 <=#Tp BlockingTxStatusWrite_sync1;
-end
-
-// Synchronizing BlockingTxStatusWrite to MTxClk
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- BlockingTxStatusWrite_sync3 <=#Tp 1'b0;
- else
- BlockingTxStatusWrite_sync3 <=#Tp BlockingTxStatusWrite_sync2;
-end
-
-assign RstDeferLatched = BlockingTxStatusWrite_sync2 & ~BlockingTxStatusWrite_sync3;
-
-// TxBDRead state is activated only once.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- BlockingTxBDRead <=#Tp 1'b0;
- else
- if(StartTxBDRead)
- BlockingTxBDRead <=#Tp 1'b1;
- else
- if(~StartTxBDRead & ~TxBDReady)
- BlockingTxBDRead <=#Tp 1'b0;
-end
-
-
-// Latching status from the tx buffer descriptor
-// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxStatus <=#Tp 4'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- TxStatus <=#Tp ram_do[14:11];
-end
-
-reg ReadTxDataFromMemory;
-wire WriteRxDataToMemory;
-
-reg MasterWbTX;
-reg MasterWbRX;
-
-reg [29:0] m_wb_adr_o;
-reg m_wb_cyc_o;
-reg [3:0] m_wb_sel_o;
-reg m_wb_we_o;
-
-wire TxLengthEq0;
-wire TxLengthLt4;
-
-reg BlockingIncrementTxPointer;
-reg [31:2] TxPointerMSB;
-reg [1:0] TxPointerLSB;
-reg [1:0] TxPointerLSB_rst;
-reg [31:2] RxPointerMSB;
-reg [1:0] RxPointerLSB_rst;
-
-wire RxBurstAcc;
-wire RxWordAcc;
-wire RxHalfAcc;
-wire RxByteAcc;
-
-//Latching length from the buffer descriptor;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxLength <=#Tp 16'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- TxLength <=#Tp ram_do[31:16];
- else
- if(MasterWbTX & m_wb_ack_i)
- begin
- if(TxLengthLt4)
- TxLength <=#Tp 16'h0;
- else
- if(TxPointerLSB_rst==2'h0)
- TxLength <=#Tp TxLength - 3'h4; // Length is subtracted at the data request
- else
- if(TxPointerLSB_rst==2'h1)
- TxLength <=#Tp TxLength - 3'h3; // Length is subtracted at the data request
- else
- if(TxPointerLSB_rst==2'h2)
- TxLength <=#Tp TxLength - 3'h2; // Length is subtracted at the data request
- else
- if(TxPointerLSB_rst==2'h3)
- TxLength <=#Tp TxLength - 3'h1; // Length is subtracted at the data request
- end
-end
-
-
-
-//Latching length from the buffer descriptor;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- LatchedTxLength <=#Tp 16'h0;
- else
- if(TxEn & TxEn_q & TxBDRead)
- LatchedTxLength <=#Tp ram_do[31:16];
-end
-
-assign TxLengthEq0 = TxLength == 0;
-assign TxLengthLt4 = TxLength < 4;
-
-reg cyc_cleared;
-reg IncrTxPointer;
-
-
-// Latching Tx buffer pointer from buffer descriptor. Only 30 MSB bits are latched
-// because TxPointerMSB is only used for word-aligned accesses.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxPointerMSB <=#Tp 30'h0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerMSB <=#Tp ram_do[31:2];
- else
- if(IncrTxPointer & ~BlockingIncrementTxPointer)
- TxPointerMSB <=#Tp TxPointerMSB + 1'b1; // TxPointer is word-aligned
-end
-
-
-// Latching 2 MSB bits of the buffer descriptor. Since word accesses are performed,
-// valid data does not necesserly start at byte 0 (could be byte 0, 1, 2 or 3). This
-// signals are used for proper selection of the start byte (TxData and TxByteCnt) are
-// set by this two bits.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxPointerLSB[1:0] <=#Tp 0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerLSB[1:0] <=#Tp ram_do[1:0];
-end
-
-
-// Latching 2 MSB bits of the buffer descriptor.
-// After the read access, TxLength needs to be decremented for the number of the valid
-// bytes (1 to 4 bytes are valid in the first word). After the first read all bytes are
-// valid so this two bits are reset to zero.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxPointerLSB_rst[1:0] <=#Tp 0;
- else
- if(TxEn & TxEn_q & TxPointerRead)
- TxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
- else
- if(MasterWbTX & m_wb_ack_i) // After first access pointer is word alligned
- TxPointerLSB_rst[1:0] <=#Tp 0;
-end
-
-
-reg [3:0] RxByteSel;
-wire MasterAccessFinished;
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- BlockingIncrementTxPointer <=#Tp 0;
- else
- if(MasterAccessFinished)
- BlockingIncrementTxPointer <=#Tp 0;
- else
- if(IncrTxPointer)
- BlockingIncrementTxPointer <=#Tp 1'b1;
-end
-
-
-wire TxBufferAlmostFull;
-wire TxBufferFull;
-wire TxBufferEmpty;
-wire TxBufferAlmostEmpty;
-wire SetReadTxDataFromMemory;
-
-reg BlockReadTxDataFromMemory;
-
-assign SetReadTxDataFromMemory = TxEn & TxEn_q & TxPointerRead;
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromMemory <=#Tp 1'b0;
- else
- if(TxLengthEq0 | TxAbortPulse | TxRetryPulse)
- ReadTxDataFromMemory <=#Tp 1'b0;
- else
- if(SetReadTxDataFromMemory)
- ReadTxDataFromMemory <=#Tp 1'b1;
-end
-
-reg tx_burst_en;
-reg rx_burst_en;
-
-wire ReadTxDataFromMemory_2 = ReadTxDataFromMemory & ~BlockReadTxDataFromMemory;
-wire tx_burst = ReadTxDataFromMemory_2 & tx_burst_en;
-
-wire [31:0] TxData_wb;
-wire ReadTxDataFromFifo_wb;
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- BlockReadTxDataFromMemory <=#Tp 1'b0;
- else
- if((TxBufferAlmostFull | TxLength <= 4)& MasterWbTX & (~cyc_cleared) & (!(TxAbortPacket_NotCleared | TxRetryPacket_NotCleared)))
- BlockReadTxDataFromMemory <=#Tp 1'b1;
- else
- if(ReadTxDataFromFifo_wb | TxDonePacket | TxAbortPacket | TxRetryPacket)
- BlockReadTxDataFromMemory <=#Tp 1'b0;
-end
-
-
-assign MasterAccessFinished = m_wb_ack_i | m_wb_err_i;
-wire [`ETH_TX_FIFO_CNT_WIDTH-1:0] txfifo_cnt;
-wire [`ETH_RX_FIFO_CNT_WIDTH-1:0] rxfifo_cnt;
-reg [`ETH_BURST_CNT_WIDTH-1:0] tx_burst_cnt;
-reg [`ETH_BURST_CNT_WIDTH-1:0] rx_burst_cnt;
-
-wire rx_burst;
-wire enough_data_in_rxfifo_for_burst;
-wire enough_data_in_rxfifo_for_burst_plus1;
-
-// Enabling master wishbone access to the memory for two devices TX and RX.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- begin
- MasterWbTX <=#Tp 1'b0;
- MasterWbRX <=#Tp 1'b0;
- m_wb_adr_o <=#Tp 30'h0;
- m_wb_cyc_o <=#Tp 1'b0;
- m_wb_we_o <=#Tp 1'b0;
- m_wb_sel_o <=#Tp 4'h0;
- cyc_cleared<=#Tp 1'b0;
- tx_burst_cnt<=#Tp 0;
- rx_burst_cnt<=#Tp 0;
- IncrTxPointer<=#Tp 1'b0;
- tx_burst_en<=#Tp 1'b1;
- rx_burst_en<=#Tp 1'b0;
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b0;
- `endif
- end
- else
- begin
- // Switching between two stages depends on enable signals
- casex ({MasterWbTX, MasterWbRX, ReadTxDataFromMemory_2, WriteRxDataToMemory, MasterAccessFinished, cyc_cleared, tx_burst, rx_burst}) // synopsys parallel_case
- 8'b00_10_00_10, // Idle and MRB needed
- 8'b10_1x_10_1x, // MRB continues
- 8'b10_10_01_10, // Clear (previously MR) and MRB needed
- 8'b01_1x_01_1x : // Clear (previously MW) and MRB needed
- begin
- MasterWbTX <=#Tp 1'b1; // tx burst
- MasterWbRX <=#Tp 1'b0;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b0;
- m_wb_sel_o <=#Tp 4'hf;
- cyc_cleared<=#Tp 1'b0;
- IncrTxPointer<=#Tp 1'b1;
- tx_burst_cnt <=#Tp tx_burst_cnt+3'h1;
- if(tx_burst_cnt==0)
- m_wb_adr_o <=#Tp TxPointerMSB;
- else
- m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
-
- if(tx_burst_cnt==(`ETH_BURST_LENGTH-1))
- begin
- tx_burst_en<=#Tp 1'b0;
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b111;
- `endif
- end
- else
- begin
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b010;
- `endif
- end
- end
- 8'b00_x1_00_x1, // Idle and MWB needed
- 8'b01_x1_10_x1, // MWB continues
- 8'b01_01_01_01, // Clear (previously MW) and MWB needed
- 8'b10_x1_01_x1 : // Clear (previously MR) and MWB needed
- begin
- MasterWbTX <=#Tp 1'b0; // rx burst
- MasterWbRX <=#Tp 1'b1;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b1;
- m_wb_sel_o <=#Tp RxByteSel;
- IncrTxPointer<=#Tp 1'b0;
- cyc_cleared<=#Tp 1'b0;
- rx_burst_cnt <=#Tp rx_burst_cnt+3'h1;
-
- if(rx_burst_cnt==0)
- m_wb_adr_o <=#Tp RxPointerMSB;
- else
- m_wb_adr_o <=#Tp m_wb_adr_o+1'b1;
-
- if(rx_burst_cnt==(`ETH_BURST_LENGTH-1))
- begin
- rx_burst_en<=#Tp 1'b0;
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b111;
- `endif
- end
- else
- begin
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b010;
- `endif
- end
- end
- 8'b00_x1_00_x0 : // idle and MW is needed (data write to rx buffer)
- begin
- MasterWbTX <=#Tp 1'b0;
- MasterWbRX <=#Tp 1'b1;
- m_wb_adr_o <=#Tp RxPointerMSB;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b1;
- m_wb_sel_o <=#Tp RxByteSel;
- IncrTxPointer<=#Tp 1'b0;
- end
- 8'b00_10_00_00 : // idle and MR is needed (data read from tx buffer)
- begin
- MasterWbTX <=#Tp 1'b1;
- MasterWbRX <=#Tp 1'b0;
- m_wb_adr_o <=#Tp TxPointerMSB;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b0;
- m_wb_sel_o <=#Tp 4'hf;
- IncrTxPointer<=#Tp 1'b1;
- end
- 8'b10_10_01_00, // MR and MR is needed (data read from tx buffer)
- 8'b01_1x_01_0x : // MW and MR is needed (data read from tx buffer)
- begin
- MasterWbTX <=#Tp 1'b1;
- MasterWbRX <=#Tp 1'b0;
- m_wb_adr_o <=#Tp TxPointerMSB;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b0;
- m_wb_sel_o <=#Tp 4'hf;
- cyc_cleared<=#Tp 1'b0;
- IncrTxPointer<=#Tp 1'b1;
- end
- 8'b01_01_01_00, // MW and MW needed (data write to rx buffer)
- 8'b10_x1_01_x0 : // MR and MW is needed (data write to rx buffer)
- begin
- MasterWbTX <=#Tp 1'b0;
- MasterWbRX <=#Tp 1'b1;
- m_wb_adr_o <=#Tp RxPointerMSB;
- m_wb_cyc_o <=#Tp 1'b1;
- m_wb_we_o <=#Tp 1'b1;
- m_wb_sel_o <=#Tp RxByteSel;
- cyc_cleared<=#Tp 1'b0;
- IncrTxPointer<=#Tp 1'b0;
- end
- 8'b01_01_10_00, // MW and MW needed (cycle is cleared between previous and next access)
- 8'b01_1x_10_x0, // MW and MW or MR or MRB needed (cycle is cleared between previous and next access)
- 8'b10_10_10_00, // MR and MR needed (cycle is cleared between previous and next access)
- 8'b10_x1_10_0x : // MR and MR or MW or MWB (cycle is cleared between previous and next access)
- begin
- m_wb_cyc_o <=#Tp 1'b0; // whatever and master read or write is needed. We need to clear m_wb_cyc_o before next access is started
- cyc_cleared<=#Tp 1'b1;
- IncrTxPointer<=#Tp 1'b0;
- tx_burst_cnt<=#Tp 0;
- tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
- rx_burst_cnt<=#Tp 0;
- rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b0;
- `endif
- end
- 8'bxx_00_10_00, // whatever and no master read or write is needed (ack or err comes finishing previous access)
- 8'bxx_00_01_00 : // Between cyc_cleared request was cleared
- begin
- MasterWbTX <=#Tp 1'b0;
- MasterWbRX <=#Tp 1'b0;
- m_wb_cyc_o <=#Tp 1'b0;
- cyc_cleared<=#Tp 1'b0;
- IncrTxPointer<=#Tp 1'b0;
- rx_burst_cnt<=#Tp 0;
- rx_burst_en<=#Tp MasterWbRX ? enough_data_in_rxfifo_for_burst_plus1 : enough_data_in_rxfifo_for_burst; // Counter is not decremented, yet, so plus1 is used.
- `ifdef ETH_WISHBONE_B3
- m_wb_cti_o <=#Tp 3'b0;
- `endif
- end
- 8'b00_00_00_00: // whatever and no master read or write is needed (ack or err comes finishing previous access)
- begin
- tx_burst_cnt<=#Tp 0;
- tx_burst_en<=#Tp txfifo_cnt<(`ETH_TX_FIFO_DEPTH-`ETH_BURST_LENGTH) & (TxLength>(`ETH_BURST_LENGTH*4+4));
- end
- default: // Don't touch
- begin
- MasterWbTX <=#Tp MasterWbTX;
- MasterWbRX <=#Tp MasterWbRX;
- m_wb_cyc_o <=#Tp m_wb_cyc_o;
- m_wb_sel_o <=#Tp m_wb_sel_o;
- IncrTxPointer<=#Tp IncrTxPointer;
- end
- endcase
- end
-end
-
-
-wire TxFifoClear;
-
-assign TxFifoClear = (TxAbortPacket | TxRetryPacket);
-
-eth_fifo #(`ETH_TX_FIFO_DATA_WIDTH, `ETH_TX_FIFO_DEPTH, `ETH_TX_FIFO_CNT_WIDTH)
-tx_fifo ( .data_in(m_wb_dat_i), .data_out(TxData_wb),
- .clk(WB_CLK_I), .reset(Reset),
- .write(MasterWbTX & m_wb_ack_i), .read(ReadTxDataFromFifo_wb & ~TxBufferEmpty),
- .clear(TxFifoClear), .full(TxBufferFull),
- .almost_full(TxBufferAlmostFull), .almost_empty(TxBufferAlmostEmpty),
- .empty(TxBufferEmpty), .cnt(txfifo_cnt)
- );
-
-
-reg StartOccured;
-reg TxStartFrm_sync1;
-reg TxStartFrm_sync2;
-reg TxStartFrm_syncb1;
-reg TxStartFrm_syncb2;
-
-
-
-// Start: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxStartFrm_wb <=#Tp 1'b0;
- else
- if(TxBDReady & ~StartOccured & (TxBufferFull | TxLengthEq0))
- TxStartFrm_wb <=#Tp 1'b1;
- else
- if(TxStartFrm_syncb2)
- TxStartFrm_wb <=#Tp 1'b0;
-end
-
-// StartOccured: TxStartFrm_wb occurs only ones at the beginning. Then it's blocked.
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- StartOccured <=#Tp 1'b0;
- else
- if(TxStartFrm_wb)
- StartOccured <=#Tp 1'b1;
- else
- if(ResetTxBDReady)
- StartOccured <=#Tp 1'b0;
-end
-
-// Synchronizing TxStartFrm_wb to MTxClk
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxStartFrm_sync1 <=#Tp 1'b0;
- else
- TxStartFrm_sync1 <=#Tp TxStartFrm_wb;
-end
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxStartFrm_sync2 <=#Tp 1'b0;
- else
- TxStartFrm_sync2 <=#Tp TxStartFrm_sync1;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxStartFrm_syncb1 <=#Tp 1'b0;
- else
- TxStartFrm_syncb1 <=#Tp TxStartFrm_sync2;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxStartFrm_syncb2 <=#Tp 1'b0;
- else
- TxStartFrm_syncb2 <=#Tp TxStartFrm_syncb1;
-end
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxStartFrm <=#Tp 1'b0;
- else
- if(TxStartFrm_sync2)
- TxStartFrm <=#Tp 1'b1;
- else
- if(TxUsedData_q | ~TxStartFrm_sync2 & (TxRetry & (~TxRetry_q) | TxAbort & (~TxAbort_q)))
- TxStartFrm <=#Tp 1'b0;
-end
-// End: Generation of the TxStartFrm_wb which is then synchronized to the MTxClk
-
-
-// TxEndFrm_wb: indicator of the end of frame
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxEndFrm_wb <=#Tp 1'b0;
- else
- if(TxLengthEq0 & TxBufferAlmostEmpty & TxUsedData)
- TxEndFrm_wb <=#Tp 1'b1;
- else
- if(TxRetryPulse | TxDonePulse | TxAbortPulse)
- TxEndFrm_wb <=#Tp 1'b0;
-end
-
-
-// Marks which bytes are valid within the word.
-assign TxValidBytes = TxLengthLt4 ? TxLength[1:0] : 2'b0;
-
-reg LatchValidBytes;
-reg LatchValidBytes_q;
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- LatchValidBytes <=#Tp 1'b0;
- else
- if(TxLengthLt4 & TxBDReady)
- LatchValidBytes <=#Tp 1'b1;
- else
- LatchValidBytes <=#Tp 1'b0;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- LatchValidBytes_q <=#Tp 1'b0;
- else
- LatchValidBytes_q <=#Tp LatchValidBytes;
-end
-
-
-// Latching valid bytes
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxValidBytesLatched <=#Tp 2'h0;
- else
- if(LatchValidBytes & ~LatchValidBytes_q)
- TxValidBytesLatched <=#Tp TxValidBytes;
- else
- if(TxRetryPulse | TxDonePulse | TxAbortPulse)
- TxValidBytesLatched <=#Tp 2'h0;
-end
-
-
-assign TxIRQEn = TxStatus[14];
-assign WrapTxStatusBit = TxStatus[13];
-assign PerPacketPad = TxStatus[12];
-assign PerPacketCrcEn = TxStatus[11];
-
-
-assign RxIRQEn = RxStatus[14];
-assign WrapRxStatusBit = RxStatus[13];
-
-
-// Temporary Tx and Rx buffer descriptor address
-assign TempTxBDAddress[7:1] = {7{ TxStatusWrite & ~WrapTxStatusBit}} & (TxBDAddress + 1'b1) ; // Tx BD increment or wrap (last BD)
-assign TempRxBDAddress[7:1] = {7{ WrapRxStatusBit}} & (r_TxBDNum[6:0]) | // Using first Rx BD
- {7{~WrapRxStatusBit}} & (RxBDAddress + 1'b1) ; // Using next Rx BD (incremenrement address)
-
-
-// Latching Tx buffer descriptor address
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxBDAddress <=#Tp 7'h0;
- else if (r_TxEn & (~r_TxEn_q))
- TxBDAddress <=#Tp 7'h0;
- else if (TxStatusWrite)
- TxBDAddress <=#Tp TempTxBDAddress;
-end
-
-
-// Latching Rx buffer descriptor address
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxBDAddress <=#Tp 7'h0;
- else if(r_RxEn & (~r_RxEn_q))
- RxBDAddress <=#Tp r_TxBDNum[6:0];
- else if(RxStatusWrite)
- RxBDAddress <=#Tp TempRxBDAddress;
-end
-
-wire [8:0] TxStatusInLatched = {TxUnderRun, RetryCntLatched[3:0], RetryLimit, LateCollLatched, DeferLatched, CarrierSenseLost};
-
-assign RxBDDataIn = {LatchedRxLength, 1'b0, RxStatus, 4'h0, RxStatusInLatched};
-assign TxBDDataIn = {LatchedTxLength, 1'b0, TxStatus, 2'h0, TxStatusInLatched};
-
-
-// Signals used for various purposes
-assign TxRetryPulse = TxRetry_wb & ~TxRetry_wb_q;
-assign TxDonePulse = TxDone_wb & ~TxDone_wb_q;
-assign TxAbortPulse = TxAbort_wb & ~TxAbort_wb_q;
-
-
-
-// Generating delayed signals
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- begin
- TxAbort_q <=#Tp 1'b0;
- TxRetry_q <=#Tp 1'b0;
- TxUsedData_q <=#Tp 1'b0;
- end
- else
- begin
- TxAbort_q <=#Tp TxAbort;
- TxRetry_q <=#Tp TxRetry;
- TxUsedData_q <=#Tp TxUsedData;
- end
-end
-
-// Generating delayed signals
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- begin
- TxDone_wb_q <=#Tp 1'b0;
- TxAbort_wb_q <=#Tp 1'b0;
- TxRetry_wb_q <=#Tp 1'b0;
- end
- else
- begin
- TxDone_wb_q <=#Tp TxDone_wb;
- TxAbort_wb_q <=#Tp TxAbort_wb;
- TxRetry_wb_q <=#Tp TxRetry_wb;
- end
-end
-
-
-reg TxAbortPacketBlocked;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxAbortPacket <=#Tp 1'b0;
- else
- if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
- TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
- TxAbortPacket <=#Tp 1'b1;
- else
- TxAbortPacket <=#Tp 1'b0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxAbortPacket_NotCleared <=#Tp 1'b0;
- else
- if(TxEn & TxEn_q & TxAbortPacket_NotCleared)
- TxAbortPacket_NotCleared <=#Tp 1'b0;
- else
- if(TxAbort_wb & (~tx_burst_en) & MasterWbTX & MasterAccessFinished & (~TxAbortPacketBlocked) |
- TxAbort_wb & (~MasterWbTX) & (~TxAbortPacketBlocked))
- TxAbortPacket_NotCleared <=#Tp 1'b1;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxAbortPacketBlocked <=#Tp 1'b0;
- else
- if(!TxAbort_wb & TxAbort_wb_q)
- TxAbortPacketBlocked <=#Tp 1'b0;
- else
- if(TxAbortPacket)
- TxAbortPacketBlocked <=#Tp 1'b1;
-end
-
-
-reg TxRetryPacketBlocked;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxRetryPacket <=#Tp 1'b0;
- else
- if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
- TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
- TxRetryPacket <=#Tp 1'b1;
- else
- TxRetryPacket <=#Tp 1'b0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxRetryPacket_NotCleared <=#Tp 1'b0;
- else
- if(StartTxBDRead)
- TxRetryPacket_NotCleared <=#Tp 1'b0;
- else
- if(TxRetry_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxRetryPacketBlocked |
- TxRetry_wb & !MasterWbTX & !TxRetryPacketBlocked)
- TxRetryPacket_NotCleared <=#Tp 1'b1;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxRetryPacketBlocked <=#Tp 1'b0;
- else
- if(!TxRetry_wb & TxRetry_wb_q)
- TxRetryPacketBlocked <=#Tp 1'b0;
- else
- if(TxRetryPacket)
- TxRetryPacketBlocked <=#Tp 1'b1;
-end
-
-
-reg TxDonePacketBlocked;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxDonePacket <=#Tp 1'b0;
- else
- if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & !TxDonePacketBlocked |
- TxDone_wb & !MasterWbTX & !TxDonePacketBlocked)
- TxDonePacket <=#Tp 1'b1;
- else
- TxDonePacket <=#Tp 1'b0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxDonePacket_NotCleared <=#Tp 1'b0;
- else
- if(TxEn & TxEn_q & TxDonePacket_NotCleared)
- TxDonePacket_NotCleared <=#Tp 1'b0;
- else
- if(TxDone_wb & !tx_burst_en & MasterWbTX & MasterAccessFinished & (~TxDonePacketBlocked) |
- TxDone_wb & !MasterWbTX & (~TxDonePacketBlocked))
- TxDonePacket_NotCleared <=#Tp 1'b1;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxDonePacketBlocked <=#Tp 1'b0;
- else
- if(!TxDone_wb & TxDone_wb_q)
- TxDonePacketBlocked <=#Tp 1'b0;
- else
- if(TxDonePacket)
- TxDonePacketBlocked <=#Tp 1'b1;
-end
-
-
-// Indication of the last word
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- LastWord <=#Tp 1'b0;
- else
- if((TxEndFrm | TxAbort | TxRetry) & Flop)
- LastWord <=#Tp 1'b0;
- else
- if(TxUsedData & Flop & TxByteCnt == 2'h3)
- LastWord <=#Tp TxEndFrm_wb;
-end
-
-
-// Tx end frame generation
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxEndFrm <=#Tp 1'b0;
- else
- if(Flop & TxEndFrm | TxAbort | TxRetry_q)
- TxEndFrm <=#Tp 1'b0;
- else
- if(Flop & LastWord)
- begin
- case (TxValidBytesLatched) // synopsys parallel_case
- 1 : TxEndFrm <=#Tp TxByteCnt == 2'h0;
- 2 : TxEndFrm <=#Tp TxByteCnt == 2'h1;
- 3 : TxEndFrm <=#Tp TxByteCnt == 2'h2;
- 0 : TxEndFrm <=#Tp TxByteCnt == 2'h3;
- default : TxEndFrm <=#Tp 1'b0;
- endcase
- end
-end
-
-
-// Tx data selection (latching)
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxData <=#Tp 0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm)
- case(TxPointerLSB) // synopsys parallel_case
- 2'h0 : TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
- 2'h1 : TxData <=#Tp TxData_wb[23:16]; // Big Endian Byte Ordering
- 2'h2 : TxData <=#Tp TxData_wb[15:08]; // Big Endian Byte Ordering
- 2'h3 : TxData <=#Tp TxData_wb[07:00]; // Big Endian Byte Ordering
- endcase
- else
- if(TxStartFrm & TxUsedData & TxPointerLSB==2'h3)
- TxData <=#Tp TxData_wb[31:24]; // Big Endian Byte Ordering
- else
- if(TxUsedData & Flop)
- begin
- case(TxByteCnt) // synopsys parallel_case
- 0 : TxData <=#Tp TxDataLatched[31:24]; // Big Endian Byte Ordering
- 1 : TxData <=#Tp TxDataLatched[23:16];
- 2 : TxData <=#Tp TxDataLatched[15:8];
- 3 : TxData <=#Tp TxDataLatched[7:0];
- endcase
- end
-end
-
-
-// Latching tx data
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxDataLatched[31:0] <=#Tp 32'h0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
- TxDataLatched[31:0] <=#Tp TxData_wb[31:0];
-end
-
-
-// Tx under run
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxUnderRun_wb <=#Tp 1'b0;
- else
- if(TxAbortPulse)
- TxUnderRun_wb <=#Tp 1'b0;
- else
- if(TxBufferEmpty & ReadTxDataFromFifo_wb)
- TxUnderRun_wb <=#Tp 1'b1;
-end
-
-
-reg TxUnderRun_sync1;
-
-// Tx under run
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxUnderRun_sync1 <=#Tp 1'b0;
- else
- if(TxUnderRun_wb)
- TxUnderRun_sync1 <=#Tp 1'b1;
- else
- if(BlockingTxStatusWrite_sync2)
- TxUnderRun_sync1 <=#Tp 1'b0;
-end
-
-// Tx under run
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxUnderRun <=#Tp 1'b0;
- else
- if(BlockingTxStatusWrite_sync2)
- TxUnderRun <=#Tp 1'b0;
- else
- if(TxUnderRun_sync1)
- TxUnderRun <=#Tp 1'b1;
-end
-
-
-// Tx Byte counter
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- TxByteCnt <=#Tp 2'h0;
- else
- if(TxAbort_q | TxRetry_q)
- TxByteCnt <=#Tp 2'h0;
- else
- if(TxStartFrm & ~TxUsedData)
- case(TxPointerLSB) // synopsys parallel_case
- 2'h0 : TxByteCnt <=#Tp 2'h1;
- 2'h1 : TxByteCnt <=#Tp 2'h2;
- 2'h2 : TxByteCnt <=#Tp 2'h3;
- 2'h3 : TxByteCnt <=#Tp 2'h0;
- endcase
- else
- if(TxUsedData & Flop)
- TxByteCnt <=#Tp TxByteCnt + 1'b1;
-end
-
-
-// Start: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
-reg ReadTxDataFromFifo_sync1;
-reg ReadTxDataFromFifo_sync2;
-reg ReadTxDataFromFifo_sync3;
-reg ReadTxDataFromFifo_syncb1;
-reg ReadTxDataFromFifo_syncb2;
-reg ReadTxDataFromFifo_syncb3;
-
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_tck <=#Tp 1'b0;
- else
- if(TxStartFrm_sync2 & ~TxStartFrm | TxUsedData & Flop & TxByteCnt == 2'h3 & ~LastWord | TxStartFrm & TxUsedData & Flop & TxByteCnt == 2'h0)
- ReadTxDataFromFifo_tck <=#Tp 1'b1;
- else
- if(ReadTxDataFromFifo_syncb2 & ~ReadTxDataFromFifo_syncb3)
- ReadTxDataFromFifo_tck <=#Tp 1'b0;
-end
-
-// Synchronizing TxStartFrm_wb to MTxClk
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_sync1 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_sync1 <=#Tp ReadTxDataFromFifo_tck;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_sync2 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_sync2 <=#Tp ReadTxDataFromFifo_sync1;
-end
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_syncb1 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_syncb1 <=#Tp ReadTxDataFromFifo_sync2;
-end
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_syncb2 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_syncb2 <=#Tp ReadTxDataFromFifo_syncb1;
-end
-
-always @ (posedge MTxClk or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_syncb3 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_syncb3 <=#Tp ReadTxDataFromFifo_syncb2;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ReadTxDataFromFifo_sync3 <=#Tp 1'b0;
- else
- ReadTxDataFromFifo_sync3 <=#Tp ReadTxDataFromFifo_sync2;
-end
-
-assign ReadTxDataFromFifo_wb = ReadTxDataFromFifo_sync2 & ~ReadTxDataFromFifo_sync3;
-// End: Generation of the ReadTxDataFromFifo_tck signal and synchronization to the WB_CLK_I
-
-
-// Synchronizing TxRetry signal (synchronized to WISHBONE clock)
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxRetrySync1 <=#Tp 1'b0;
- else
- TxRetrySync1 <=#Tp TxRetry;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxRetry_wb <=#Tp 1'b0;
- else
- TxRetry_wb <=#Tp TxRetrySync1;
-end
-
-
-// Synchronized TxDone_wb signal (synchronized to WISHBONE clock)
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxDoneSync1 <=#Tp 1'b0;
- else
- TxDoneSync1 <=#Tp TxDone;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxDone_wb <=#Tp 1'b0;
- else
- TxDone_wb <=#Tp TxDoneSync1;
-end
-
-// Synchronizing TxAbort signal (synchronized to WISHBONE clock)
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxAbortSync1 <=#Tp 1'b0;
- else
- TxAbortSync1 <=#Tp TxAbort;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxAbort_wb <=#Tp 1'b0;
- else
- TxAbort_wb <=#Tp TxAbortSync1;
-end
-
-
-reg RxAbortSync1;
-reg RxAbortSync2;
-reg RxAbortSync3;
-reg RxAbortSync4;
-reg RxAbortSyncb1;
-reg RxAbortSyncb2;
-
-assign StartRxBDRead = RxStatusWrite | RxAbortSync3 & ~RxAbortSync4 | r_RxEn & ~r_RxEn_q;
-
-// Reading the Rx buffer descriptor
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxBDRead <=#Tp 1'b0;
- else
- if(StartRxBDRead & ~RxReady)
- RxBDRead <=#Tp 1'b1;
- else
- if(RxBDReady)
- RxBDRead <=#Tp 1'b0;
-end
-
-
-// Reading of the next receive buffer descriptor starts after reception status is
-// written to the previous one.
-
-// Latching READY status of the Rx buffer descriptor
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxBDReady <=#Tp 1'b0;
- else
- if(RxPointerRead)
- RxBDReady <=#Tp 1'b0;
- else
- if(RxEn & RxEn_q & RxBDRead)
- RxBDReady <=#Tp ram_do[15]; // RxBDReady is sampled only once at the beginning
-end
-
-// Latching Rx buffer descriptor status
-// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxStatus <=#Tp 2'h0;
- else
- if(RxEn & RxEn_q & RxBDRead)
- RxStatus <=#Tp ram_do[14:13];
-end
-
-
-// RxReady generation
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxReady <=#Tp 1'b0;
- else
- if(ShiftEnded | RxAbortSync2 & ~RxAbortSync3 | ~r_RxEn & r_RxEn_q)
- RxReady <=#Tp 1'b0;
- else
- if(RxEn & RxEn_q & RxPointerRead)
- RxReady <=#Tp 1'b1;
-end
-
-
-// Reading Rx BD pointer
-
-
-assign StartRxPointerRead = RxBDRead & RxBDReady;
-
-// Reading Tx BD Pointer
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxPointerRead <=#Tp 1'b0;
- else
- if(StartRxPointerRead)
- RxPointerRead <=#Tp 1'b1;
- else
- if(RxEn & RxEn_q)
- RxPointerRead <=#Tp 1'b0;
-end
-
-
-//Latching Rx buffer pointer from buffer descriptor;
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxPointerMSB <=#Tp 30'h0;
- else
- if(RxEn & RxEn_q & RxPointerRead)
- RxPointerMSB <=#Tp ram_do[31:2];
- else
- if(MasterWbRX & m_wb_ack_i)
- RxPointerMSB <=#Tp RxPointerMSB + 1'b1; // Word access (always word access. m_wb_sel_o are used for selecting bytes)
-end
-
-
-//Latching last addresses from buffer descriptor (used as byte-half-word indicator);
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxPointerLSB_rst[1:0] <=#Tp 0;
- else
- if(MasterWbRX & m_wb_ack_i) // After first write all RxByteSel are active
- RxPointerLSB_rst[1:0] <=#Tp 0;
- else
- if(RxEn & RxEn_q & RxPointerRead)
- RxPointerLSB_rst[1:0] <=#Tp ram_do[1:0];
-end
-
-
-always @ (RxPointerLSB_rst)
-begin
- case(RxPointerLSB_rst[1:0]) // synopsys parallel_case
- 2'h0 : RxByteSel[3:0] = 4'hf;
- 2'h1 : RxByteSel[3:0] = 4'h7;
- 2'h2 : RxByteSel[3:0] = 4'h3;
- 2'h3 : RxByteSel[3:0] = 4'h1;
- endcase
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxEn_needed <=#Tp 1'b0;
- else
- if(~RxReady & r_RxEn & WbEn & ~WbEn_q)
- RxEn_needed <=#Tp 1'b1;
- else
- if(RxPointerRead & RxEn & RxEn_q)
- RxEn_needed <=#Tp 1'b0;
-end
-
-
-// Reception status is written back to the buffer descriptor after the end of frame is detected.
-assign RxStatusWrite = ShiftEnded & RxEn & RxEn_q;
-
-reg RxEnableWindow;
-
-// Indicating that last byte is being reveived
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LastByteIn <=#Tp 1'b0;
- else
- if(ShiftWillEnd & (&RxByteCnt) | RxAbort)
- LastByteIn <=#Tp 1'b0;
- else
- if(RxValid & RxReady & RxEndFrm & ~(&RxByteCnt) & RxEnableWindow)
- LastByteIn <=#Tp 1'b1;
-end
-
-reg ShiftEnded_rck;
-reg ShiftEndedSync1;
-reg ShiftEndedSync2;
-reg ShiftEndedSync3;
-reg ShiftEndedSync_c1;
-reg ShiftEndedSync_c2;
-
-wire StartShiftWillEnd;
-assign StartShiftWillEnd = LastByteIn | RxValid & RxEndFrm & (&RxByteCnt) & RxEnableWindow;
-
-// Indicating that data reception will end
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShiftWillEnd <=#Tp 1'b0;
- else
- if(ShiftEnded_rck | RxAbort)
- ShiftWillEnd <=#Tp 1'b0;
- else
- if(StartShiftWillEnd)
- ShiftWillEnd <=#Tp 1'b1;
-end
-
-
-
-// Receive byte counter
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxByteCnt <=#Tp 2'h0;
- else
- if(ShiftEnded_rck | RxAbort)
- RxByteCnt <=#Tp 2'h0;
- else
- if(RxValid & RxStartFrm & RxReady)
- case(RxPointerLSB_rst) // synopsys parallel_case
- 2'h0 : RxByteCnt <=#Tp 2'h1;
- 2'h1 : RxByteCnt <=#Tp 2'h2;
- 2'h2 : RxByteCnt <=#Tp 2'h3;
- 2'h3 : RxByteCnt <=#Tp 2'h0;
- endcase
- else
- if(RxValid & RxEnableWindow & RxReady | LastByteIn)
- RxByteCnt <=#Tp RxByteCnt + 1'b1;
-end
-
-
-// Indicates how many bytes are valid within the last word
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxValidBytes <=#Tp 2'h1;
- else
- if(RxValid & RxStartFrm)
- case(RxPointerLSB_rst) // synopsys parallel_case
- 2'h0 : RxValidBytes <=#Tp 2'h1;
- 2'h1 : RxValidBytes <=#Tp 2'h2;
- 2'h2 : RxValidBytes <=#Tp 2'h3;
- 2'h3 : RxValidBytes <=#Tp 2'h0;
- endcase
- else
- if(RxValid & ~LastByteIn & ~RxStartFrm & RxEnableWindow)
- RxValidBytes <=#Tp RxValidBytes + 1'b1;
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxDataLatched1 <=#Tp 24'h0;
- else
- if(RxValid & RxReady & ~LastByteIn)
- if(RxStartFrm)
- begin
- case(RxPointerLSB_rst) // synopsys parallel_case
- 2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
- 2'h1: RxDataLatched1[23:16] <=#Tp RxData;
- 2'h2: RxDataLatched1[15:8] <=#Tp RxData;
- 2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
- endcase
- end
- else if (RxEnableWindow)
- begin
- case(RxByteCnt) // synopsys parallel_case
- 2'h0: RxDataLatched1[31:24] <=#Tp RxData; // Big Endian Byte Ordering
- 2'h1: RxDataLatched1[23:16] <=#Tp RxData;
- 2'h2: RxDataLatched1[15:8] <=#Tp RxData;
- 2'h3: RxDataLatched1 <=#Tp RxDataLatched1;
- endcase
- end
-end
-
-wire SetWriteRxDataToFifo;
-
-// Assembling data that will be written to the rx_fifo
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxDataLatched2 <=#Tp 32'h0;
- else
- if(SetWriteRxDataToFifo & ~ShiftWillEnd)
- RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
- else
- if(SetWriteRxDataToFifo & ShiftWillEnd)
- case(RxValidBytes) // synopsys parallel_case
- 0 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], RxData}; // Big Endian Byte Ordering
- 1 : RxDataLatched2 <=#Tp {RxDataLatched1[31:24], 24'h0};
- 2 : RxDataLatched2 <=#Tp {RxDataLatched1[31:16], 16'h0};
- 3 : RxDataLatched2 <=#Tp {RxDataLatched1[31:8], 8'h0};
- endcase
-end
-
-
-reg WriteRxDataToFifoSync1;
-reg WriteRxDataToFifoSync2;
-reg WriteRxDataToFifoSync3;
-
-
-// Indicating start of the reception process
-assign SetWriteRxDataToFifo = (RxValid & RxReady & ~RxStartFrm & RxEnableWindow & (&RxByteCnt)) |
- (RxValid & RxReady & RxStartFrm & (&RxPointerLSB_rst)) |
- (ShiftWillEnd & LastByteIn & (&RxByteCnt));
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- WriteRxDataToFifo <=#Tp 1'b0;
- else
- if(SetWriteRxDataToFifo & ~RxAbort)
- WriteRxDataToFifo <=#Tp 1'b1;
- else
- if(WriteRxDataToFifoSync2 | RxAbort)
- WriteRxDataToFifo <=#Tp 1'b0;
-end
-
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- WriteRxDataToFifoSync1 <=#Tp 1'b0;
- else
- if(WriteRxDataToFifo)
- WriteRxDataToFifoSync1 <=#Tp 1'b1;
- else
- WriteRxDataToFifoSync1 <=#Tp 1'b0;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- WriteRxDataToFifoSync2 <=#Tp 1'b0;
- else
- WriteRxDataToFifoSync2 <=#Tp WriteRxDataToFifoSync1;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- WriteRxDataToFifoSync3 <=#Tp 1'b0;
- else
- WriteRxDataToFifoSync3 <=#Tp WriteRxDataToFifoSync2;
-end
-
-wire WriteRxDataToFifo_wb;
-assign WriteRxDataToFifo_wb = WriteRxDataToFifoSync2 & ~WriteRxDataToFifoSync3;
-
-
-reg LatchedRxStartFrm;
-reg SyncRxStartFrm;
-reg SyncRxStartFrm_q;
-reg SyncRxStartFrm_q2;
-wire RxFifoReset;
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedRxStartFrm <=#Tp 0;
- else
- if(RxStartFrm & ~SyncRxStartFrm_q)
- LatchedRxStartFrm <=#Tp 1;
- else
- if(SyncRxStartFrm_q)
- LatchedRxStartFrm <=#Tp 0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- SyncRxStartFrm <=#Tp 0;
- else
- if(LatchedRxStartFrm)
- SyncRxStartFrm <=#Tp 1;
- else
- SyncRxStartFrm <=#Tp 0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- SyncRxStartFrm_q <=#Tp 0;
- else
- SyncRxStartFrm_q <=#Tp SyncRxStartFrm;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- SyncRxStartFrm_q2 <=#Tp 0;
- else
- SyncRxStartFrm_q2 <=#Tp SyncRxStartFrm_q;
-end
-
-
-assign RxFifoReset = SyncRxStartFrm_q & ~SyncRxStartFrm_q2;
-
-
-eth_fifo #(`ETH_RX_FIFO_DATA_WIDTH, `ETH_RX_FIFO_DEPTH, `ETH_RX_FIFO_CNT_WIDTH)
-rx_fifo (.data_in(RxDataLatched2), .data_out(m_wb_dat_o),
- .clk(WB_CLK_I), .reset(Reset),
- .write(WriteRxDataToFifo_wb & ~RxBufferFull), .read(MasterWbRX & m_wb_ack_i),
- .clear(RxFifoReset), .full(RxBufferFull),
- .almost_full(), .almost_empty(RxBufferAlmostEmpty),
- .empty(RxBufferEmpty), .cnt(rxfifo_cnt)
- );
-
-assign enough_data_in_rxfifo_for_burst = rxfifo_cnt>=`ETH_BURST_LENGTH;
-assign enough_data_in_rxfifo_for_burst_plus1 = rxfifo_cnt>`ETH_BURST_LENGTH;
-assign WriteRxDataToMemory = ~RxBufferEmpty;
-assign rx_burst = rx_burst_en & WriteRxDataToMemory;
-
-
-// Generation of the end-of-frame signal
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShiftEnded_rck <=#Tp 1'b0;
- else
- if(~RxAbort & SetWriteRxDataToFifo & StartShiftWillEnd)
- ShiftEnded_rck <=#Tp 1'b1;
- else
- if(RxAbort | ShiftEndedSync_c1 & ShiftEndedSync_c2)
- ShiftEnded_rck <=#Tp 1'b0;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ShiftEndedSync1 <=#Tp 1'b0;
- else
- ShiftEndedSync1 <=#Tp ShiftEnded_rck;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ShiftEndedSync2 <=#Tp 1'b0;
- else
- ShiftEndedSync2 <=#Tp ShiftEndedSync1;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ShiftEndedSync3 <=#Tp 1'b0;
- else
- if(ShiftEndedSync1 & ~ShiftEndedSync2)
- ShiftEndedSync3 <=#Tp 1'b1;
- else
- if(ShiftEnded)
- ShiftEndedSync3 <=#Tp 1'b0;
-end
-
-// Generation of the end-of-frame signal
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- ShiftEnded <=#Tp 1'b0;
- else
- if(ShiftEndedSync3 & MasterWbRX & m_wb_ack_i & RxBufferAlmostEmpty & ~ShiftEnded)
- ShiftEnded <=#Tp 1'b1;
- else
- if(RxStatusWrite)
- ShiftEnded <=#Tp 1'b0;
-end
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShiftEndedSync_c1 <=#Tp 1'b0;
- else
- ShiftEndedSync_c1 <=#Tp ShiftEndedSync2;
-end
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- ShiftEndedSync_c2 <=#Tp 1'b0;
- else
- ShiftEndedSync_c2 <=#Tp ShiftEndedSync_c1;
-end
-
-// Generation of the end-of-frame signal
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxEnableWindow <=#Tp 1'b0;
- else
- if(RxStartFrm)
- RxEnableWindow <=#Tp 1'b1;
- else
- if(RxEndFrm | RxAbort)
- RxEnableWindow <=#Tp 1'b0;
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxAbortSync1 <=#Tp 1'b0;
- else
- RxAbortSync1 <=#Tp RxAbortLatched;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxAbortSync2 <=#Tp 1'b0;
- else
- RxAbortSync2 <=#Tp RxAbortSync1;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxAbortSync3 <=#Tp 1'b0;
- else
- RxAbortSync3 <=#Tp RxAbortSync2;
-end
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxAbortSync4 <=#Tp 1'b0;
- else
- RxAbortSync4 <=#Tp RxAbortSync3;
-end
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxAbortSyncb1 <=#Tp 1'b0;
- else
- RxAbortSyncb1 <=#Tp RxAbortSync2;
-end
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxAbortSyncb2 <=#Tp 1'b0;
- else
- RxAbortSyncb2 <=#Tp RxAbortSyncb1;
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxAbortLatched <=#Tp 1'b0;
- else
- if(RxAbortSyncb2)
- RxAbortLatched <=#Tp 1'b0;
- else
- if(RxAbort)
- RxAbortLatched <=#Tp 1'b1;
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- LatchedRxLength[15:0] <=#Tp 16'h0;
- else
- if(LoadRxStatus)
- LatchedRxLength[15:0] <=#Tp RxLength[15:0];
-end
-
-
-assign RxStatusIn = {ReceivedPauseFrm, AddressMiss, RxOverrun, InvalidSymbol, DribbleNibble, ReceivedPacketTooBig, ShortFrame, LatchedCrcError, RxLateCollision};
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- RxStatusInLatched <=#Tp 'h0;
- else
- if(LoadRxStatus)
- RxStatusInLatched <=#Tp RxStatusIn;
-end
-
-
-// Rx overrun
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxOverrun <=#Tp 1'b0;
- else
- if(RxStatusWrite)
- RxOverrun <=#Tp 1'b0;
- else
- if(RxBufferFull & WriteRxDataToFifo_wb)
- RxOverrun <=#Tp 1'b1;
-end
-
-
-
-wire TxError;
-assign TxError = TxUnderRun | RetryLimit | LateCollLatched | CarrierSenseLost;
-
-wire RxError;
-
-// ShortFrame (RxStatusInLatched[2]) can not set an error because short frames
-// are aborted when signal r_RecSmall is set to 0 in MODER register.
-// AddressMiss is identifying that a frame was received because of the promiscous
-// mode and is not an error
-assign RxError = (|RxStatusInLatched[6:3]) | (|RxStatusInLatched[1:0]);
-
-
-
-reg RxStatusWriteLatched;
-reg RxStatusWriteLatched_sync1;
-reg RxStatusWriteLatched_sync2;
-reg RxStatusWriteLatched_syncb1;
-reg RxStatusWriteLatched_syncb2;
-
-
-// Latching and synchronizing RxStatusWrite signal. This signal is used for clearing the ReceivedPauseFrm signal
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxStatusWriteLatched <=#Tp 1'b0;
- else
- if(RxStatusWriteLatched_syncb2)
- RxStatusWriteLatched <=#Tp 1'b0;
- else
- if(RxStatusWrite)
- RxStatusWriteLatched <=#Tp 1'b1;
-end
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- begin
- RxStatusWriteLatched_sync1 <=#Tp 1'b0;
- RxStatusWriteLatched_sync2 <=#Tp 1'b0;
- end
- else
- begin
- RxStatusWriteLatched_sync1 <=#Tp RxStatusWriteLatched;
- RxStatusWriteLatched_sync2 <=#Tp RxStatusWriteLatched_sync1;
- end
-end
-
-
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- begin
- RxStatusWriteLatched_syncb1 <=#Tp 1'b0;
- RxStatusWriteLatched_syncb2 <=#Tp 1'b0;
- end
- else
- begin
- RxStatusWriteLatched_syncb1 <=#Tp RxStatusWriteLatched_sync2;
- RxStatusWriteLatched_syncb2 <=#Tp RxStatusWriteLatched_syncb1;
- end
-end
-
-
-
-// Tx Done Interrupt
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxB_IRQ <=#Tp 1'b0;
- else
- if(TxStatusWrite & TxIRQEn)
- TxB_IRQ <=#Tp ~TxError;
- else
- TxB_IRQ <=#Tp 1'b0;
-end
-
-
-// Tx Error Interrupt
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- TxE_IRQ <=#Tp 1'b0;
- else
- if(TxStatusWrite & TxIRQEn)
- TxE_IRQ <=#Tp TxError;
- else
- TxE_IRQ <=#Tp 1'b0;
-end
-
-
-// Rx Done Interrupt
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxB_IRQ <=#Tp 1'b0;
- else
- if(RxStatusWrite & RxIRQEn & ReceivedPacketGood & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
- RxB_IRQ <=#Tp (~RxError);
- else
- RxB_IRQ <=#Tp 1'b0;
-end
-
-
-// Rx Error Interrupt
-always @ (posedge WB_CLK_I or posedge Reset)
-begin
- if(Reset)
- RxE_IRQ <=#Tp 1'b0;
- else
- if(RxStatusWrite & RxIRQEn & (~ReceivedPauseFrm | ReceivedPauseFrm & r_PassAll & (~r_RxFlow)))
- RxE_IRQ <=#Tp RxError;
- else
- RxE_IRQ <=#Tp 1'b0;
-end
-
-
-// Busy Interrupt
-
-reg Busy_IRQ_rck;
-reg Busy_IRQ_sync1;
-reg Busy_IRQ_sync2;
-reg Busy_IRQ_sync3;
-reg Busy_IRQ_syncb1;
-reg Busy_IRQ_syncb2;
-
-
-always @ (posedge MRxClk or posedge Reset)
-begin
- if(Reset)
- Busy_IRQ_rck <=#Tp 1'b0;
- else
- if(RxValid & RxStartFrm & ~RxReady)
- Busy_IRQ_rck <=#Tp 1'b1;
- else
- if(Busy_IRQ_syncb2)
- Busy_IRQ_rck <=#Tp 1'b0;
-end
-
-always @ (posedge WB_CLK_I)
-begin
- Busy_IRQ_sync1 <=#Tp Busy_IRQ_rck;
- Busy_IRQ_sync2 <=#Tp Busy_IRQ_sync1;
- Busy_IRQ_sync3 <=#Tp Busy_IRQ_sync2;
-end
-
-always @ (posedge MRxClk)
-begin
- Busy_IRQ_syncb1 <=#Tp Busy_IRQ_sync2;
- Busy_IRQ_syncb2 <=#Tp Busy_IRQ_syncb1;
-end
-
-assign Busy_IRQ = Busy_IRQ_sync2 & ~Busy_IRQ_sync3;
-
-
-
-
-
-endmodule
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// eth_top.v ////
-//// ////
-//// This file is part of the Ethernet IP core project ////
-//// http://www.opencores.org/projects/ethmac/ ////
-//// ////
-//// Author(s): ////
-//// - Igor Mohor (igorM@opencores.org) ////
-//// ////
-//// All additional information is available in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2001, 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//
-// CVS Revision History
-//
-// $Log: eth_top.v,v $
-// Revision 1.52 2005/03/21 20:07:18 igorm
-// Some small fixes + some troubles fixed.
-//
-// Revision 1.51 2005/02/21 11:13:17 igorm
-// Defer indication fixed.
-//
-// Revision 1.50 2004/04/26 15:26:23 igorm
-// - Bug connected to the TX_BD_NUM_Wr signal fixed (bug came in with the
-// previous update of the core.
-// - TxBDAddress is set to 0 after the TX is enabled in the MODER register.
-// - RxBDAddress is set to r_TxBDNum<<1 after the RX is enabled in the MODER
-// register. (thanks to Mathias and Torbjorn)
-// - Multicast reception was fixed. Thanks to Ulrich Gries
-//
-// Revision 1.49 2003/11/12 18:24:59 tadejm
-// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
-//
-// Revision 1.48 2003/10/17 07:46:16 markom
-// mbist signals updated according to newest convention
-//
-// Revision 1.47 2003/10/06 15:43:45 knguyen
-// Update RxEnSync only when mrxdv_pad_i is inactive (LOW).
-//
-// Revision 1.46 2003/01/30 13:30:22 tadejm
-// Defer indication changed.
-//
-// Revision 1.45 2003/01/22 13:49:26 tadejm
-// When control packets were received, they were ignored in some cases.
-//
-// Revision 1.44 2003/01/21 12:09:40 mohor
-// When receiving normal data frame and RxFlow control was switched on, RXB
-// interrupt was not set.
-//
-// Revision 1.43 2002/11/22 01:57:06 mohor
-// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
-// synchronized.
-//
-// Revision 1.42 2002/11/21 00:09:19 mohor
-// TPauseRq synchronized to tx_clk.
-//
-// Revision 1.41 2002/11/19 18:13:49 mohor
-// r_MiiMRst is not used for resetting the MIIM module. wb_rst used instead.
-//
-// Revision 1.40 2002/11/19 17:34:25 mohor
-// AddressMiss status is connecting to the Rx BD. AddressMiss is identifying
-// that a frame was received because of the promiscous mode.
-//
-// Revision 1.39 2002/11/18 17:31:55 mohor
-// wb_rst_i is used for MIIM reset.
-//
-// Revision 1.38 2002/11/14 18:37:20 mohor
-// r_Rst signal does not reset any module any more and is removed from the design.
-//
-// Revision 1.37 2002/11/13 22:25:36 tadejm
-// All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.
-//
-// Revision 1.36 2002/10/18 17:04:20 tadejm
-// Changed BIST scan signals.
-//
-// Revision 1.35 2002/10/11 13:36:58 mohor
-// Typo error fixed. (When using Bist)
-//
-// Revision 1.34 2002/10/10 16:49:50 mohor
-// Signals for WISHBONE B3 compliant interface added.
-//
-// Revision 1.33 2002/10/10 16:29:30 mohor
-// BIST added.
-//
-// Revision 1.32 2002/09/20 17:12:58 mohor
-// CsMiss added. When address between 0x800 and 0xfff is accessed within
-// Ethernet Core, error acknowledge is generated.
-//
-// Revision 1.31 2002/09/12 14:50:17 mohor
-// CarrierSenseLost bug fixed when operating in full duplex mode.
-//
-// Revision 1.30 2002/09/10 10:35:23 mohor
-// Ethernet debug registers removed.
-//
-// Revision 1.29 2002/09/09 13:03:13 mohor
-// Error acknowledge is generated when accessing BDs and RST bit in the
-// MODER register (r_Rst) is set.
-//
-// Revision 1.28 2002/09/04 18:44:10 mohor
-// Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
-// connected.
-//
-// Revision 1.27 2002/07/25 18:15:37 mohor
-// RxAbort changed. Packets received with MRxErr (from PHY) are also
-// aborted.
-//
-// Revision 1.26 2002/07/17 18:51:50 mohor
-// EXTERNAL_DMA removed. External DMA not supported.
-//
-// Revision 1.25 2002/05/03 10:15:50 mohor
-// Outputs registered. Reset changed for eth_wishbone module.
-//
-// Revision 1.24 2002/04/22 14:15:42 mohor
-// Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
-// selected in eth_defines.v
-//
-// Revision 1.23 2002/03/25 13:33:53 mohor
-// md_padoen_o changed to md_padoe_o. Signal was always active high, just
-// name was incorrect.
-//
-// Revision 1.22 2002/02/26 16:59:54 mohor
-// Small fixes for external/internal DMA missmatches.
-//
-// Revision 1.21 2002/02/26 16:21:00 mohor
-// Interrupts changed in the top file
-//
-// Revision 1.20 2002/02/18 10:40:17 mohor
-// Small fixes.
-//
-// Revision 1.19 2002/02/16 14:03:44 mohor
-// Registered trimmed. Unused registers removed.
-//
-// Revision 1.18 2002/02/16 13:06:33 mohor
-// EXTERNAL_DMA used instead of WISHBONE_DMA.
-//
-// Revision 1.17 2002/02/16 07:15:27 mohor
-// Testbench fixed, code simplified, unused signals removed.
-//
-// Revision 1.16 2002/02/15 13:49:39 mohor
-// RxAbort is connected differently.
-//
-// Revision 1.15 2002/02/15 11:38:26 mohor
-// Changes that were lost when updating from 1.11 to 1.14 fixed.
-//
-// Revision 1.14 2002/02/14 20:19:11 billditt
-// Modified for Address Checking,
-// addition of eth_addrcheck.v
-//
-// Revision 1.13 2002/02/12 17:03:03 mohor
-// HASH0 and HASH1 registers added. Registers address width was
-// changed to 8 bits.
-//
-// Revision 1.12 2002/02/11 09:18:22 mohor
-// Tx status is written back to the BD.
-//
-// Revision 1.11 2002/02/08 16:21:54 mohor
-// Rx status is written back to the BD.
-//
-// Revision 1.10 2002/02/06 14:10:21 mohor
-// non-DMA host interface added. Select the right configutation in eth_defines.
-//
-// Revision 1.9 2002/01/23 10:28:16 mohor
-// Link in the header changed.
-//
-// Revision 1.8 2001/12/05 15:00:16 mohor
-// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
-// instead of the number of RX descriptors).
-//
-// Revision 1.7 2001/12/05 10:45:59 mohor
-// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
-//
-// Revision 1.6 2001/10/19 11:24:29 mohor
-// Number of addresses (wb_adr_i) minimized.
-//
-// Revision 1.5 2001/10/19 08:43:51 mohor
-// eth_timescale.v changed to timescale.v This is done because of the
-// simulation of the few cores in a one joined project.
-//
-// Revision 1.4 2001/10/18 12:07:11 mohor
-// Status signals changed, Adress decoding changed, interrupt controller
-// added.
-//
-// Revision 1.3 2001/09/24 15:02:56 mohor
-// Defines changed (All precede with ETH_). Small changes because some
-// tools generate warnings when two operands are together. Synchronization
-// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
-// demands).
-//
-// Revision 1.2 2001/08/15 14:03:59 mohor
-// Signal names changed on the top level for easier pad insertion (ASIC).
-//
-// Revision 1.1 2001/08/06 14:44:29 mohor
-// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
-// Include files fixed to contain no path.
-// File names and module names changed ta have a eth_ prologue in the name.
-// File eth_timescale.v is used to define timescale
-// All pin names on the top module are changed to contain _I, _O or _OE at the end.
-// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
-// and Mdo_OE. The bidirectional signal must be created on the top level. This
-// is done due to the ASIC tools.
-//
-// Revision 1.2 2001/08/02 09:25:31 mohor
-// Unconnected signals are now connected.
-//
-// Revision 1.1 2001/07/30 21:23:42 mohor
-// Directory structure changed. Files checked and joind together.
-//
-//
-//
-//
-
-
-`include "eth_defines.v"
-`include "timescale.v"
-
-
-module eth_top
-(
- // WISHBONE common
- wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
-
- // WISHBONE slave
- wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
-
- // WISHBONE master
- m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
- m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
- m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
-
-`ifdef ETH_WISHBONE_B3
- m_wb_cti_o, m_wb_bte_o,
-`endif
-
- //TX
- mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
-
- //RX
- mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i, mcrs_pad_i,
-
- // MIIM
- mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
-
- int_o
-
- // Bist
-`ifdef ETH_BIST
- ,
- // debug chain signals
- mbist_si_i, // bist scan serial in
- mbist_so_o, // bist scan serial out
- mbist_ctrl_i // bist chain shift control
-`endif
-
-);
-
-
-parameter Tp = 1;
-
-
-// WISHBONE common
-input wb_clk_i; // WISHBONE clock
-input wb_rst_i; // WISHBONE reset
-input [31:0] wb_dat_i; // WISHBONE data input
-output [31:0] wb_dat_o; // WISHBONE data output
-output wb_err_o; // WISHBONE error output
-
-// WISHBONE slave
-input [11:2] wb_adr_i; // WISHBONE address input
-input [3:0] wb_sel_i; // WISHBONE byte select input
-input wb_we_i; // WISHBONE write enable input
-input wb_cyc_i; // WISHBONE cycle input
-input wb_stb_i; // WISHBONE strobe input
-output wb_ack_o; // WISHBONE acknowledge output
-
-// WISHBONE master
-output [31:0] m_wb_adr_o;
-output [3:0] m_wb_sel_o;
-output m_wb_we_o;
-input [31:0] m_wb_dat_i;
-output [31:0] m_wb_dat_o;
-output m_wb_cyc_o;
-output m_wb_stb_o;
-input m_wb_ack_i;
-input m_wb_err_i;
-
-wire [29:0] m_wb_adr_tmp;
-
-`ifdef ETH_WISHBONE_B3
-output [2:0] m_wb_cti_o; // Cycle Type Identifier
-output [1:0] m_wb_bte_o; // Burst Type Extension
-`endif
-
-// Tx
-input mtx_clk_pad_i; // Transmit clock (from PHY)
-output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)
-output mtxen_pad_o; // Transmit enable (to PHY)
-output mtxerr_pad_o; // Transmit error (to PHY)
-
-// Rx
-input mrx_clk_pad_i; // Receive clock (from PHY)
-input [3:0] mrxd_pad_i; // Receive nibble (from PHY)
-input mrxdv_pad_i; // Receive data valid (from PHY)
-input mrxerr_pad_i; // Receive data error (from PHY)
-
-// Common Tx and Rx
-input mcoll_pad_i; // Collision (from PHY)
-input mcrs_pad_i; // Carrier sense (from PHY)
-
-// MII Management interface
-input md_pad_i; // MII data input (from I/O cell)
-output mdc_pad_o; // MII Management data clock (to PHY)
-output md_pad_o; // MII data output (to I/O cell)
-output md_padoe_o; // MII data output enable (to I/O cell)
-
-output int_o; // Interrupt output
-
-// Bist
-`ifdef ETH_BIST
-input mbist_si_i; // bist scan serial in
-output mbist_so_o; // bist scan serial out
-input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
-`endif
-
-wire [7:0] r_ClkDiv;
-wire r_MiiNoPre;
-wire [15:0] r_CtrlData;
-wire [4:0] r_FIAD;
-wire [4:0] r_RGAD;
-wire r_WCtrlData;
-wire r_RStat;
-wire r_ScanStat;
-wire NValid_stat;
-wire Busy_stat;
-wire LinkFail;
-wire [15:0] Prsd; // Read Status Data (data read from the PHY)
-wire WCtrlDataStart;
-wire RStatStart;
-wire UpdateMIIRX_DATAReg;
-
-wire TxStartFrm;
-wire TxEndFrm;
-wire TxUsedData;
-wire [7:0] TxData;
-wire TxRetry;
-wire TxAbort;
-wire TxUnderRun;
-wire TxDone;
-
-
-reg WillSendControlFrame_sync1;
-reg WillSendControlFrame_sync2;
-reg WillSendControlFrame_sync3;
-reg RstTxPauseRq;
-
-reg TxPauseRq_sync1;
-reg TxPauseRq_sync2;
-reg TxPauseRq_sync3;
-reg TPauseRq;
-
-
-// Connecting Miim module
-eth_miim miim1
-(
- .Clk(wb_clk_i), .Reset(wb_rst_i), .Divider(r_ClkDiv),
- .NoPre(r_MiiNoPre), .CtrlData(r_CtrlData), .Rgad(r_RGAD),
- .Fiad(r_FIAD), .WCtrlData(r_WCtrlData), .RStat(r_RStat),
- .ScanStat(r_ScanStat), .Mdi(md_pad_i), .Mdo(md_pad_o),
- .MdoEn(md_padoe_o), .Mdc(mdc_pad_o), .Busy(Busy_stat),
- .Prsd(Prsd), .LinkFail(LinkFail), .Nvalid(NValid_stat),
- .WCtrlDataStart(WCtrlDataStart), .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
-);
-
-
-
-
-wire [3:0] RegCs; // Connected to registers
-wire [31:0] RegDataOut; // Multiplexed to wb_dat_o
-wire r_RecSmall; // Receive small frames
-wire r_LoopBck; // Loopback
-wire r_TxEn; // Tx Enable
-wire r_RxEn; // Rx Enable
-
-wire MRxDV_Lb; // Muxed MII receive data valid
-wire MRxErr_Lb; // Muxed MII Receive Error
-wire [3:0] MRxD_Lb; // Muxed MII Receive Data
-wire Transmitting; // Indication that TxEthMAC is transmitting
-wire r_HugEn; // Huge packet enable
-wire r_DlyCrcEn; // Delayed CRC enabled
-wire [15:0] r_MaxFL; // Maximum frame length
-
-wire [15:0] r_MinFL; // Minimum frame length
-wire ShortFrame;
-wire DribbleNibble; // Extra nibble received
-wire ReceivedPacketTooBig; // Received packet is too big
-wire [47:0] r_MAC; // MAC address
-wire LoadRxStatus; // Rx status was loaded
-wire [31:0] r_HASH0; // HASH table, lower 4 bytes
-wire [31:0] r_HASH1; // HASH table, upper 4 bytes
-wire [7:0] r_TxBDNum; // Receive buffer descriptor number
-wire [6:0] r_IPGT; //
-wire [6:0] r_IPGR1; //
-wire [6:0] r_IPGR2; //
-wire [5:0] r_CollValid; //
-wire [15:0] r_TxPauseTV; // Transmit PAUSE value
-wire r_TxPauseRq; // Transmit PAUSE request
-
-wire [3:0] r_MaxRet; //
-wire r_NoBckof; //
-wire r_ExDfrEn; //
-wire r_TxFlow; // Tx flow control enable
-wire r_IFG; // Minimum interframe gap for incoming packets
-
-wire TxB_IRQ; // Interrupt Tx Buffer
-wire TxE_IRQ; // Interrupt Tx Error
-wire RxB_IRQ; // Interrupt Rx Buffer
-wire RxE_IRQ; // Interrupt Rx Error
-wire Busy_IRQ; // Interrupt Busy (lack of buffers)
-
-//wire DWord;
-wire ByteSelected;
-wire BDAck;
-wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
-wire [3:0] BDCs; // Buffer descriptor CS
-wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
- // but data is not valid.
-wire r_Pad;
-wire r_CrcEn;
-wire r_FullD;
-wire r_Pro;
-wire r_Bro;
-wire r_NoPre;
-wire r_RxFlow;
-wire r_PassAll;
-wire TxCtrlEndFrm;
-wire StartTxDone;
-wire SetPauseTimer;
-wire TxUsedDataIn;
-wire TxDoneIn;
-wire TxAbortIn;
-wire PerPacketPad;
-wire PadOut;
-wire PerPacketCrcEn;
-wire CrcEnOut;
-wire TxStartFrmOut;
-wire TxEndFrmOut;
-wire ReceivedPauseFrm;
-wire ControlFrmAddressOK;
-wire RxStatusWriteLatched_sync2;
-wire LateCollision;
-wire DeferIndication;
-wire LateCollLatched;
-wire DeferLatched;
-wire RstDeferLatched;
-wire CarrierSenseLost;
-
-wire temp_wb_ack_o;
-wire [31:0] temp_wb_dat_o;
-wire temp_wb_err_o;
-
-`ifdef ETH_REGISTERED_OUTPUTS
- reg temp_wb_ack_o_reg;
- reg [31:0] temp_wb_dat_o_reg;
- reg temp_wb_err_o_reg;
-`endif
-
-//assign DWord = &wb_sel_i;
-assign ByteSelected = |wb_sel_i;
-assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF
-assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF
-assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF
-assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF
-assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF
-assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF
-assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF
-assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF
-assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF
-assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
-assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
-
-`ifdef ETH_REGISTERED_OUTPUTS
- assign wb_ack_o = temp_wb_ack_o_reg;
- assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
- assign wb_err_o = temp_wb_err_o_reg;
-`else
- assign wb_ack_o = temp_wb_ack_o;
- assign wb_dat_o[31:0] = temp_wb_dat_o;
- assign wb_err_o = temp_wb_err_o;
-`endif
-
-`ifdef ETH_AVALON_BUS
- // As Avalon has no corresponding "error" signal, I (erroneously) will
- // send an ack to Avalon, even when accessing undefined memory. This
- // is a grey area in Avalon vs. Wishbone specs: My understanding
- // is that Avalon expects all memory addressable by the addr bus feeding
- // a slave to be, at the very minimum, readable.
- assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
-`else // WISHBONE
- assign temp_wb_ack_o = (|RegCs) | BDAck;
-`endif
-
-`ifdef ETH_REGISTERED_OUTPUTS
- always @ (posedge wb_clk_i or posedge wb_rst_i)
- begin
- if(wb_rst_i)
- begin
- temp_wb_ack_o_reg <=#Tp 1'b0;
- temp_wb_dat_o_reg <=#Tp 32'h0;
- temp_wb_err_o_reg <=#Tp 1'b0;
- end
- else
- begin
- temp_wb_ack_o_reg <=#Tp temp_wb_ack_o & ~temp_wb_ack_o_reg;
- temp_wb_dat_o_reg <=#Tp temp_wb_dat_o;
- temp_wb_err_o_reg <=#Tp temp_wb_err_o & ~temp_wb_err_o_reg;
- end
- end
-`endif
-
-
-// Connecting Ethernet registers
-eth_registers ethreg1
-(
- .DataIn(wb_dat_i), .Address(wb_adr_i[9:2]), .Rw(wb_we_i),
- .Cs(RegCs), .Clk(wb_clk_i), .Reset(wb_rst_i),
- .DataOut(RegDataOut), .r_RecSmall(r_RecSmall),
- .r_Pad(r_Pad), .r_HugEn(r_HugEn), .r_CrcEn(r_CrcEn),
- .r_DlyCrcEn(r_DlyCrcEn), .r_FullD(r_FullD),
- .r_ExDfrEn(r_ExDfrEn), .r_NoBckof(r_NoBckof), .r_LoopBck(r_LoopBck),
- .r_IFG(r_IFG), .r_Pro(r_Pro), .r_Iam(),
- .r_Bro(r_Bro), .r_NoPre(r_NoPre), .r_TxEn(r_TxEn),
- .r_RxEn(r_RxEn), .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ),
- .RxB_IRQ(RxB_IRQ), .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
- .r_IPGT(r_IPGT),
- .r_IPGR1(r_IPGR1), .r_IPGR2(r_IPGR2), .r_MinFL(r_MinFL),
- .r_MaxFL(r_MaxFL), .r_MaxRet(r_MaxRet), .r_CollValid(r_CollValid),
- .r_TxFlow(r_TxFlow), .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
- .r_MiiNoPre(r_MiiNoPre), .r_ClkDiv(r_ClkDiv),
- .r_WCtrlData(r_WCtrlData), .r_RStat(r_RStat), .r_ScanStat(r_ScanStat),
- .r_RGAD(r_RGAD), .r_FIAD(r_FIAD), .r_CtrlData(r_CtrlData),
- .NValid_stat(NValid_stat), .Busy_stat(Busy_stat),
- .LinkFail(LinkFail), .r_MAC(r_MAC), .WCtrlDataStart(WCtrlDataStart),
- .RStatStart(RStatStart), .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg), .Prsd(Prsd),
- .r_TxBDNum(r_TxBDNum), .int_o(int_o),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .r_TxPauseRq(r_TxPauseRq),
- .r_TxPauseTV(r_TxPauseTV), .RstTxPauseRq(RstTxPauseRq), .TxCtrlEndFrm(TxCtrlEndFrm),
- .StartTxDone(StartTxDone), .TxClk(mtx_clk_pad_i), .RxClk(mrx_clk_pad_i),
- .SetPauseTimer(SetPauseTimer)
-
-);
-
-
-
-wire [7:0] RxData;
-wire RxValid;
-wire RxStartFrm;
-wire RxEndFrm;
-wire RxAbort;
-
-wire WillTransmit; // Will transmit (to RxEthMAC)
-wire ResetCollision; // Reset Collision (for synchronizing collision)
-wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)
-wire WillSendControlFrame;
-wire ReceiveEnd;
-wire ReceivedPacketGood;
-wire ReceivedLengthOK;
-wire InvalidSymbol;
-wire LatchedCrcError;
-wire RxLateCollision;
-wire [3:0] RetryCntLatched;
-wire [3:0] RetryCnt;
-wire StartTxAbort;
-wire MaxCollisionOccured;
-wire RetryLimit;
-wire StatePreamble;
-wire [1:0] StateData;
-
-// Connecting MACControl
-eth_maccontrol maccontrol1
-(
- .MTxClk(mtx_clk_pad_i), .TPauseRq(TPauseRq),
- .TxPauseTV(r_TxPauseTV), .TxDataIn(TxData),
- .TxStartFrmIn(TxStartFrm), .TxEndFrmIn(TxEndFrm),
- .TxUsedDataIn(TxUsedDataIn), .TxDoneIn(TxDoneIn),
- .TxAbortIn(TxAbortIn), .MRxClk(mrx_clk_pad_i),
- .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood),
- .TxFlow(r_TxFlow),
- .RxFlow(r_RxFlow), .DlyCrcEn(r_DlyCrcEn),
- .MAC(r_MAC), .PadIn(r_Pad | PerPacketPad),
- .PadOut(PadOut), .CrcEnIn(r_CrcEn | PerPacketCrcEn),
- .CrcEnOut(CrcEnOut), .TxReset(wb_rst_i),
- .RxReset(wb_rst_i), .ReceivedLengthOK(ReceivedLengthOK),
- .TxDataOut(TxDataOut), .TxStartFrmOut(TxStartFrmOut),
- .TxEndFrmOut(TxEndFrmOut), .TxUsedDataOut(TxUsedData),
- .TxDoneOut(TxDone), .TxAbortOut(TxAbort),
- .WillSendControlFrame(WillSendControlFrame), .TxCtrlEndFrm(TxCtrlEndFrm),
- .ReceivedPauseFrm(ReceivedPauseFrm), .ControlFrmAddressOK(ControlFrmAddressOK),
- .SetPauseTimer(SetPauseTimer),
- .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2), .r_PassAll(r_PassAll)
-);
-
-
-
-wire TxCarrierSense; // Synchronized CarrierSense (to Tx clock)
-wire Collision; // Synchronized Collision
-
-reg CarrierSense_Tx1;
-reg CarrierSense_Tx2;
-reg Collision_Tx1;
-reg Collision_Tx2;
-
-reg RxEnSync; // Synchronized Receive Enable
-reg WillTransmit_q;
-reg WillTransmit_q2;
-
-
-
-// Muxed MII receive data valid
-assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
-
-// Muxed MII Receive Error
-assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
-
-// Muxed MII Receive Data
-assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
-
-
-
-// Connecting TxEthMAC
-eth_txethmac txethmac1
-(
- .MTxClk(mtx_clk_pad_i), .Reset(wb_rst_i), .CarrierSense(TxCarrierSense),
- .Collision(Collision), .TxData(TxDataOut), .TxStartFrm(TxStartFrmOut),
- .TxUnderRun(TxUnderRun), .TxEndFrm(TxEndFrmOut), .Pad(PadOut),
- .MinFL(r_MinFL), .CrcEn(CrcEnOut), .FullD(r_FullD),
- .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn), .IPGT(r_IPGT),
- .IPGR1(r_IPGR1), .IPGR2(r_IPGR2), .CollValid(r_CollValid),
- .MaxRet(r_MaxRet), .NoBckof(r_NoBckof), .ExDfrEn(r_ExDfrEn),
- .MaxFL(r_MaxFL), .MTxEn(mtxen_pad_o), .MTxD(mtxd_pad_o),
- .MTxErr(mtxerr_pad_o), .TxUsedData(TxUsedDataIn), .TxDone(TxDoneIn),
- .TxRetry(TxRetry), .TxAbort(TxAbortIn), .WillTransmit(WillTransmit),
- .ResetCollision(ResetCollision), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .MaxCollisionOccured(MaxCollisionOccured), .LateCollision(LateCollision),
- .DeferIndication(DeferIndication), .StatePreamble(StatePreamble), .StateData(StateData)
-);
-
-
-
-
-wire [15:0] RxByteCnt;
-wire RxByteCntEq0;
-wire RxByteCntGreat2;
-wire RxByteCntMaxFrame;
-wire RxCrcError;
-wire RxStateIdle;
-wire RxStatePreamble;
-wire RxStateSFD;
-wire [1:0] RxStateData;
-wire AddressMiss;
-
-
-
-// Connecting RxEthMAC
-eth_rxethmac rxethmac1
-(
- .MRxClk(mrx_clk_pad_i), .MRxDV(MRxDV_Lb), .MRxD(MRxD_Lb),
- .Transmitting(Transmitting), .HugEn(r_HugEn), .DlyCrcEn(r_DlyCrcEn),
- .MaxFL(r_MaxFL), .r_IFG(r_IFG), .Reset(wb_rst_i),
- .RxData(RxData), .RxValid(RxValid), .RxStartFrm(RxStartFrm),
- .RxEndFrm(RxEndFrm), .ByteCnt(RxByteCnt),
- .ByteCntEq0(RxByteCntEq0), .ByteCntGreat2(RxByteCntGreat2), .ByteCntMaxFrame(RxByteCntMaxFrame),
- .CrcError(RxCrcError), .StateIdle(RxStateIdle), .StatePreamble(RxStatePreamble),
- .StateSFD(RxStateSFD), .StateData(RxStateData),
- .MAC(r_MAC), .r_Pro(r_Pro), .r_Bro(r_Bro),
- .r_HASH0(r_HASH0), .r_HASH1(r_HASH1), .RxAbort(RxAbort),
- .AddressMiss(AddressMiss), .PassAll(r_PassAll), .ControlFrmAddressOK(ControlFrmAddressOK)
-);
-
-
-// MII Carrier Sense Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- CarrierSense_Tx1 <= #Tp 1'b0;
- CarrierSense_Tx2 <= #Tp 1'b0;
- end
- else
- begin
- CarrierSense_Tx1 <= #Tp mcrs_pad_i;
- CarrierSense_Tx2 <= #Tp CarrierSense_Tx1;
- end
-end
-
-assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
-
-
-// MII Collision Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- Collision_Tx1 <= #Tp 1'b0;
- Collision_Tx2 <= #Tp 1'b0;
- end
- else
- begin
- Collision_Tx1 <= #Tp mcoll_pad_i;
- if(ResetCollision)
- Collision_Tx2 <= #Tp 1'b0;
- else
- if(Collision_Tx1)
- Collision_Tx2 <= #Tp 1'b1;
- end
-end
-
-
-// Synchronized Collision
-assign Collision = ~r_FullD & Collision_Tx2;
-
-
-
-// Delayed WillTransmit
-always @ (posedge mrx_clk_pad_i)
-begin
- WillTransmit_q <= #Tp WillTransmit;
- WillTransmit_q2 <= #Tp WillTransmit_q;
-end
-
-
-assign Transmitting = ~r_FullD & WillTransmit_q2;
-
-
-
-// Synchronized Receive Enable
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxEnSync <= #Tp 1'b0;
- else
- if(~mrxdv_pad_i)
- RxEnSync <= #Tp r_RxEn;
-end
-
-
-
-// Synchronizing WillSendControlFrame to WB_CLK;
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync1 <= 1'b0;
- else
- WillSendControlFrame_sync1 <=#Tp WillSendControlFrame;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync2 <= 1'b0;
- else
- WillSendControlFrame_sync2 <=#Tp WillSendControlFrame_sync1;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- WillSendControlFrame_sync3 <= 1'b0;
- else
- WillSendControlFrame_sync3 <=#Tp WillSendControlFrame_sync2;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RstTxPauseRq <= 1'b0;
- else
- RstTxPauseRq <=#Tp WillSendControlFrame_sync2 & ~WillSendControlFrame_sync3;
-end
-
-
-
-
-// TX Pause request Synchronization
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- TxPauseRq_sync1 <= #Tp 1'b0;
- TxPauseRq_sync2 <= #Tp 1'b0;
- TxPauseRq_sync3 <= #Tp 1'b0;
- end
- else
- begin
- TxPauseRq_sync1 <= #Tp (r_TxPauseRq & r_TxFlow);
- TxPauseRq_sync2 <= #Tp TxPauseRq_sync1;
- TxPauseRq_sync3 <= #Tp TxPauseRq_sync2;
- end
-end
-
-
-always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- TPauseRq <= #Tp 1'b0;
- else
- TPauseRq <= #Tp TxPauseRq_sync2 & (~TxPauseRq_sync3);
-end
-
-
-wire LatchedMRxErr;
-reg RxAbort_latch;
-reg RxAbort_sync1;
-reg RxAbort_wb;
-reg RxAbortRst_sync1;
-reg RxAbortRst;
-
-// Synchronizing RxAbort to the WISHBONE clock
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- RxAbort_latch <= #Tp 1'b0;
- else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr & ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
- RxAbort_latch <= #Tp 1'b1;
- else if(RxAbortRst)
- RxAbort_latch <= #Tp 1'b0;
-end
-
-always @ (posedge wb_clk_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbort_sync1 <= #Tp 1'b0;
- RxAbort_wb <= #Tp 1'b0;
- RxAbort_wb <= #Tp 1'b0;
- end
- else
- begin
- RxAbort_sync1 <= #Tp RxAbort_latch;
- RxAbort_wb <= #Tp RxAbort_sync1;
- end
-end
-
-always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
-begin
- if(wb_rst_i)
- begin
- RxAbortRst_sync1 <= #Tp 1'b0;
- RxAbortRst <= #Tp 1'b0;
- end
- else
- begin
- RxAbortRst_sync1 <= #Tp RxAbort_wb;
- RxAbortRst <= #Tp RxAbortRst_sync1;
- end
-end
-
-
-
-// Connecting Wishbone module
-eth_wishbone wishbone
-(
- .WB_CLK_I(wb_clk_i), .WB_DAT_I(wb_dat_i),
- .WB_DAT_O(BD_WB_DAT_O),
-
- // WISHBONE slave
- .WB_ADR_I(wb_adr_i[9:2]), .WB_WE_I(wb_we_i),
- .BDCs(BDCs), .WB_ACK_O(BDAck),
-
- .Reset(wb_rst_i),
-
- // WISHBONE master
- .m_wb_adr_o(m_wb_adr_tmp), .m_wb_sel_o(m_wb_sel_o), .m_wb_we_o(m_wb_we_o),
- .m_wb_dat_i(m_wb_dat_i), .m_wb_dat_o(m_wb_dat_o), .m_wb_cyc_o(m_wb_cyc_o),
- .m_wb_stb_o(m_wb_stb_o), .m_wb_ack_i(m_wb_ack_i), .m_wb_err_i(m_wb_err_i),
-
-`ifdef ETH_WISHBONE_B3
- .m_wb_cti_o(m_wb_cti_o), .m_wb_bte_o(m_wb_bte_o),
-`endif
-
-
- //TX
- .MTxClk(mtx_clk_pad_i), .TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm),
- .TxUsedData(TxUsedData), .TxData(TxData),
- .TxRetry(TxRetry), .TxAbort(TxAbort), .TxUnderRun(TxUnderRun),
- .TxDone(TxDone),
- .PerPacketCrcEn(PerPacketCrcEn), .PerPacketPad(PerPacketPad),
-
- // Register
- .r_TxEn(r_TxEn), .r_RxEn(r_RxEn), .r_TxBDNum(r_TxBDNum),
- .r_RxFlow(r_RxFlow), .r_PassAll(r_PassAll),
-
- //RX
- .MRxClk(mrx_clk_pad_i), .RxData(RxData), .RxValid(RxValid),
- .RxStartFrm(RxStartFrm), .RxEndFrm(RxEndFrm),
- .Busy_IRQ(Busy_IRQ), .RxE_IRQ(RxE_IRQ), .RxB_IRQ(RxB_IRQ),
- .TxE_IRQ(TxE_IRQ), .TxB_IRQ(TxB_IRQ),
-
- .RxAbort(RxAbort_wb), .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
-
- .InvalidSymbol(InvalidSymbol), .LatchedCrcError(LatchedCrcError), .RxLength(RxByteCnt),
- .RxLateCollision(RxLateCollision), .ShortFrame(ShortFrame), .DribbleNibble(DribbleNibble),
- .ReceivedPacketTooBig(ReceivedPacketTooBig), .LoadRxStatus(LoadRxStatus), .RetryCntLatched(RetryCntLatched),
- .RetryLimit(RetryLimit), .LateCollLatched(LateCollLatched), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .CarrierSenseLost(CarrierSenseLost),.ReceivedPacketGood(ReceivedPacketGood), .AddressMiss(AddressMiss),
- .ReceivedPauseFrm(ReceivedPauseFrm)
-
-`ifdef ETH_BIST
- ,
- .mbist_si_i (mbist_si_i),
- .mbist_so_o (mbist_so_o),
- .mbist_ctrl_i (mbist_ctrl_i)
-`endif
-);
-
-assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
-
-// Connecting MacStatus module
-eth_macstatus macstatus1
-(
- .MRxClk(mrx_clk_pad_i), .Reset(wb_rst_i),
- .ReceiveEnd(ReceiveEnd), .ReceivedPacketGood(ReceivedPacketGood), .ReceivedLengthOK(ReceivedLengthOK),
- .RxCrcError(RxCrcError), .MRxErr(MRxErr_Lb), .MRxDV(MRxDV_Lb),
- .RxStateSFD(RxStateSFD), .RxStateData(RxStateData), .RxStatePreamble(RxStatePreamble),
- .RxStateIdle(RxStateIdle), .Transmitting(Transmitting), .RxByteCnt(RxByteCnt),
- .RxByteCntEq0(RxByteCntEq0), .RxByteCntGreat2(RxByteCntGreat2), .RxByteCntMaxFrame(RxByteCntMaxFrame),
- .InvalidSymbol(InvalidSymbol),
- .MRxD(MRxD_Lb), .LatchedCrcError(LatchedCrcError), .Collision(mcoll_pad_i),
- .CollValid(r_CollValid), .RxLateCollision(RxLateCollision), .r_RecSmall(r_RecSmall),
- .r_MinFL(r_MinFL), .r_MaxFL(r_MaxFL), .ShortFrame(ShortFrame),
- .DribbleNibble(DribbleNibble), .ReceivedPacketTooBig(ReceivedPacketTooBig), .r_HugEn(r_HugEn),
- .LoadRxStatus(LoadRxStatus), .RetryCnt(RetryCnt), .StartTxDone(StartTxDone),
- .StartTxAbort(StartTxAbort), .RetryCntLatched(RetryCntLatched), .MTxClk(mtx_clk_pad_i),
- .MaxCollisionOccured(MaxCollisionOccured), .RetryLimit(RetryLimit), .LateCollision(LateCollision),
- .LateCollLatched(LateCollLatched), .DeferIndication(DeferIndication), .DeferLatched(DeferLatched),
- .RstDeferLatched(RstDeferLatched),
- .TxStartFrm(TxStartFrmOut), .StatePreamble(StatePreamble), .StateData(StateData),
- .CarrierSense(CarrierSense_Tx2), .CarrierSenseLost(CarrierSenseLost), .TxUsedData(TxUsedDataIn),
- .LatchedMRxErr(LatchedMRxErr), .Loopback(r_LoopBck), .r_FullD(r_FullD)
-);
-
-
-endmodule
orpsocv2/rtl/verilog/components/ethernet/eth_top_ip.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v (nonexistent)
@@ -1,82 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1K_startup ////
-//// ////
-//// This file is part of the OR1K startup IP core project ////
-//// http://www.opencores.org/ ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback (unneback@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-module OR1K_startup
- (
- input [6:2] wb_adr_i,
- input wb_stb_i,
- input wb_cyc_i,
- output reg [31:0] wb_dat_o,
- output reg wb_ack_o,
- input wb_clk,
- input wb_rst
- );
- reg [3:0] counter;
- wire [7:0] do;
- parameter [31:0] NOP = 32'h15000000;
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- counter <= 4'd0;
- else
- if (!wb_cyc_i)
- counter <= 4'd0;
- else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
- counter <= counter + 4'd1;
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_ack_o <= 1'b0;
- else
- wb_ack_o <= (counter == 4'd15);
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_dat_o <= NOP;
- else
- case (counter)
- 4'd15: wb_dat_o[31:24] <= do;
- 4'd11: wb_dat_o[23:16] <= do;
- 4'd7 : wb_dat_o[15: 8] <= do;
- 4'd3 : wb_dat_o[ 7: 0] <= do;
- endcase
- flash flash0
- (
- .CLK (counter[1] ^ counter[0]),
- .ADDR ({wb_adr_i,counter[3:2]}),
- .DOUT (do)
- );
-endmodule
orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL_IP.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v (nonexistent)
@@ -1,39 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// OR1K_startup ////
-//// ////
-//// This file is part of the OR1K startup IP core project ////
-//// http://www.opencores.org/ ////
-//// ////
-//// Author(s): ////
-//// - Michael Unneback (unneback@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2009 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
orpsocv2/rtl/verilog/components/or1k_startup/copyright_OR1K_startup.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v (nonexistent)
@@ -1,60 +0,0 @@
-module OR1K_startup_rom
- (
- input [6:0] addr,
- output [31:0] dout,
- input clk
- );
-
- wire [31:0] rom [0:31];
-
- assign rom[ 0] = 32'h18000000;
- assign rom[ 1] = 32'hA8200000;
- assign rom[ 2] = 32'h1880B000;
- assign rom[ 3] = 32'hA8A00520;
- assign rom[ 4] = 32'hA8600001;
- assign rom[ 5] = 32'h04000014;
- assign rom[ 6] = 32'hD4041818;
- assign rom[ 7] = 32'h04000012;
- assign rom[ 8] = 32'hD4040000;
- assign rom[ 9] = 32'hE0431804;
- assign rom[10] = 32'h0400000F;
- assign rom[11] = 32'h9C210008;
- assign rom[12] = 32'h0400000D;
- assign rom[13] = 32'hE1031804;
- assign rom[14] = 32'hE4080000;
- assign rom[15] = 32'h0FFFFFFB;
- assign rom[16] = 32'hD4081800;
- assign rom[17] = 32'h04000008;
- assign rom[18] = 32'h9C210004;
- assign rom[19] = 32'hD4011800;
- assign rom[20] = 32'hE4011000;
- assign rom[21] = 32'h0FFFFFFC;
- assign rom[22] = 32'hA8C00100;
- assign rom[23] = 32'h44003000;
- assign rom[24] = 32'hD4040018;
- assign rom[25] = 32'hD4042810;
- assign rom[26] = 32'h84640010;
- assign rom[27] = 32'hBC030520;
- assign rom[28] = 32'h13FFFFFE;
- assign rom[29] = 32'h15000000;
- assign rom[30] = 32'h44004800;
- assign rom[31] = 32'h84640000;
-
- reg [6:0] addr_reg;
-
- always @ (posedge clk)
- addr_reg <= addr;
-
- /*
- always @ (*)
- case (addr_reg[1:0])
- 2'b00 : dout <= rom[addr_reg[6:2]][31:24];
- 2'b01 : dout <= rom[addr_reg[6:2]][23:16];
- 2'b10 : dout <= rom[addr_reg[6:2]][15: 8];
- 2'b11 : dout <= rom[addr_reg[6:2]][ 7: 0];
- endcase
- */
-
- assign dout = rom[addr_reg];
-
-endmodule // OR1K_startup_rom
orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_rom.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v (nonexistent)
@@ -1,50 +0,0 @@
-module OR1K_startup
- (
- input [6:2] wb_adr_i,
- input wb_stb_i,
- input wb_cyc_i,
- output reg [31:0] wb_dat_o,
- output reg wb_ack_o,
- input wb_clk,
- input wb_rst
- );
-
- reg [3:0] counter;
- wire [7:0] do;
-
- parameter [31:0] NOP = 32'h15000000;
-
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- counter <= 4'd0;
- else
- if (!wb_cyc_i)
- counter <= 4'd0;
- else if (wb_cyc_i & wb_stb_i & !wb_ack_o)
- counter <= counter + 4'd1;
-
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_ack_o <= 1'b0;
- else
- wb_ack_o <= (counter == 4'd15);
-
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_dat_o <= NOP;
- else
- case (counter)
- 4'd15: wb_dat_o[31:24] <= do;
- 4'd11: wb_dat_o[23:16] <= do;
- 4'd7 : wb_dat_o[15: 8] <= do;
- 4'd3 : wb_dat_o[ 7: 0] <= do;
- endcase
-
- flash flash0
- (
- .CLK (counter[1] ^ counter[0]),
- .ADDR ({wb_adr_i,counter[3:2]}),
- .DOUT (do)
- );
-
-endmodule // OR1K_startup
orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_ACTEL.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v (nonexistent)
@@ -1,60 +0,0 @@
-`ifndef SPI_BASE_MSB
- `define SPI_BASE_MSB B000
-`endif
-module OR1K_startup
- (
- input [6:2] wb_adr_i,
- input wb_stb_i,
- input wb_cyc_i,
- output reg [31:0] wb_dat_o,
- output reg wb_ack_o,
- input wb_clk,
- input wb_rst
- );
-
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_dat_o <= 32'h15000000;
- else
- case (wb_adr_i)
- 0 : wb_dat_o <= 32'h18000000;
- 1 : wb_dat_o <= 32'hA8200000;
- 2 : wb_dat_o <= { 16'h1880, 16'h`SPI_BASE_MSB } ;
- 3 : wb_dat_o <= 32'hA8A00520;
- 4 : wb_dat_o <= 32'hA8600001;
- 5 : wb_dat_o <= 32'h04000014;
- 6 : wb_dat_o <= 32'hD4041818;
- 7 : wb_dat_o <= 32'h04000012;
- 8 : wb_dat_o <= 32'hD4040000;
- 9 : wb_dat_o <= 32'hE0431804;
- 10 : wb_dat_o <= 32'h0400000F;
- 11 : wb_dat_o <= 32'h9C210008;
- 12 : wb_dat_o <= 32'h0400000D;
- 13 : wb_dat_o <= 32'hE1031804;
- 14 : wb_dat_o <= 32'hE4080000;
- 15 : wb_dat_o <= 32'h0FFFFFFB;
- 16 : wb_dat_o <= 32'hD4081800;
- 17 : wb_dat_o <= 32'h04000008;
- 18 : wb_dat_o <= 32'h9C210004;
- 19 : wb_dat_o <= 32'hD4011800;
- 20 : wb_dat_o <= 32'hE4011000;
- 21 : wb_dat_o <= 32'h0FFFFFFC;
- 22 : wb_dat_o <= 32'hA8C00100;
- 23 : wb_dat_o <= 32'h44003000;
- 24 : wb_dat_o <= 32'hD4040018;
- 25 : wb_dat_o <= 32'hD4042810;
- 26 : wb_dat_o <= 32'h84640010;
- 27 : wb_dat_o <= 32'hBC030520;
- 28 : wb_dat_o <= 32'h13FFFFFE;
- 29 : wb_dat_o <= 32'h15000000;
- 30 : wb_dat_o <= 32'h44004800;
- 31 : wb_dat_o <= 32'h84640000;
- endcase
-
- always @ (posedge wb_clk or posedge wb_rst)
- if (wb_rst)
- wb_ack_o <= 1'b0;
- else
- wb_ack_o <= wb_stb_i & wb_cyc_i & !wb_ack_o;
-
-endmodule // OR1K_startup
orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_generic.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v (nonexistent)
@@ -1,39 +0,0 @@
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// spi_shift.v ////
-//// ////
-//// This file is part of the SPI IP core project ////
-//// http://www.opencores.org/projects/spi/ ////
-//// ////
-//// Author(s): ////
-//// - Simon Srot (simons@opencores.org) ////
-//// ////
-//// All additional information is avaliable in the Readme.txt ////
-//// file. ////
-//// ////
-//////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2002 Authors ////
-//// ////
-//// This source file may be used and distributed without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and that any derivative work contains ////
-//// the original copyright notice and the associated disclaimer. ////
-//// ////
-//// This source file is free software; you can redistribute it ////
-//// and/or modify it under the terms of the GNU Lesser General ////
-//// Public License as published by the Free Software Foundation; ////
-//// either version 2.1 of the License, or (at your option) any ////
-//// later version. ////
-//// ////
-//// This source is distributed in the hope that it will be ////
-//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
-//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
-//// PURPOSE. See the GNU Lesser General Public License for more ////
-//// details. ////
-//// ////
-//// You should have received a copy of the GNU Lesser General ////
-//// Public License along with this source; if not, download it ////
-//// from http://www.opencores.org/lgpl.shtml ////
-//// ////
-//////////////////////////////////////////////////////////////////////
orpsocv2/rtl/verilog/components/or1k_startup/copyright_spi.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v (nonexistent)
@@ -1,49 +0,0 @@
-module flash_wb_1k (
- wb_adr_i, wb_cyc_i, wb_stb_i, wb_dat_o, wb_ack_o, clk, rst );
-
-input [4:0] wb_adr_i;
-input wb_cyc_i;
-input wb_stb_i;
-output [31:0] wb_dat_o;
-reg [31:0] wb_dat_o;
-output wb_ack_o;
-reg wb_ack_o;
-input clk;
-input rst;
-
-reg [3:0] counter;
-wire [7:0] do;
-
-parameter [31:0] NOP = 32'h15000000;
-
-always @ (posedge rst or posedge clk)
-if (rst)
- counter <= 4'd0;
-else
- if (wb_cyc_i & wb_stb_i & !wb_ack_o)
- counter <= counter + 4'd1;
-
-always @ (posedge rst or posedge clk)
-if (rst)
- wb_ack_o <= 1'b0;
-else
- wb_ack_o <= (counter == 4'd15);
-
-always @ (posedge rst or posedge clk)
-if (rst)
- wb_dat_o <= NOP;
-else
- case (counter)
- 4'd15: wb_dat_o[31:24] <= do;
- 4'd11: wb_dat_o[23:16] <= do;
- 4'd7: wb_dat_o[15: 8] <= do;
- 4'd3: wb_dat_o[ 7: 0] <= do;
- endcase
-
-
-flash flash0 (
- .CLK (counter[1] ^ counter[0]),
- .ADDR ({wb_adr_i,counter[3:2]}),
- .DOUT (do));
-
-endmodule
\ No newline at end of file
orpsocv2/rtl/verilog/components/or1k_startup/flash_wb_32x32.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/Makefile
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/Makefile (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/Makefile (nonexistent)
@@ -1,11 +0,0 @@
-spi:
- vppp --simple spi_clgen.v spi_shift.v spi_top.v | cat copyright_spi.v - > spi_flash.v
-
-OR1K_startup:
- vppp --simple +define+SPI_BASE_MSB+B000 OR1K_startup_generic.v | cat copyright_OR1K_startup.v - > OR1K_startup.v
-
-OR1K_startup_ACTEL:
- vppp --simple OR1K_startup_ACTEL.v | cat copyright_OR1K_startup.v - > OR1K_startup_ACTEL_IP.v
-
-all: spi OR1K_startup OR1K_startup_ACTEL
-
orpsocv2/rtl/verilog/components/or1k_startup/Makefile
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v
===================================================================
--- orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v (revision 54)
+++ orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v (nonexistent)
@@ -1,55 +0,0 @@
-OR1K_startup OR1K_startup0
- (
- .wb_adr_i(wbs_rom_adr_i[6:2]),
- .wb_stb_i(wbs_rom_stb_i),
- .wb_cyc_i(wbs_rom_cyc_i),
- .wb_dat_o(wbs_rom_dat_o),
- .wb_ack_o(wbs_rom_ack_o),
- .wb_clk(wb_clk),
- .wb_rst(wb_rst)
- );
-
-wire spi_flash_mosi, spi_flash_miso, spi_flash_sclk;
-wire [1:0] spi_flash_ss;
-
-spi_flash_top #
- (
- .divider(`SPI_FLASH_DIVIDER),
- .divider_len(`SPI_FLASH_DIVIDER_LEN)
- )
-spi_flash_top0
- (
- // Wishbone signals
- .wb_clk_i(wb_clk),
- .wb_rst_i(wb_rst),
- .wb_adr_i(wbs_spi_flash_adr_i[4:2]),
- .wb_dat_i(wbs_spi_flash_dat_i),
- .wb_dat_o(wbs_spi_flash_dat_o),
- .wb_sel_i(wbs_spi_flash_sel_i),
- .wb_we_i(wbs_spi_flash_we_i),
- .wb_stb_i(wbs_spi_flash_stb_i),
- .wb_cyc_i(wbs_spi_flash_cyc_i),
- .wb_ack_o(wbs_spi_flash_ack_o),
- // SPI signals
- .mosi_pad_o(spi_flash_mosi),
- .miso_pad_i(spi_flash_miso),
- .sclk_pad_o(spi_flash_sclk),
- .ss_pad_o(spi_flash_ss)
- );
-
-// external SPI FLASH
-assign spi_flash_mosi_pad_o = !spi_flash_ss[0] ? spi_flash_mosi : 1'b1;
-assign spi_flash_sclk_pad_o = !spi_flash_ss[0] ? spi_flash_sclk : 1'b1;
-assign spi_flash_ss_pad_o = spi_flash_ss[0];
-assign spi_flash_w_n_pad_o = 1'b1;
-assign spi_flash_hold_n_pad_o = 1'b1;
-
-// external SD FLASH in SPI mode
-assign spi_sd_mosi_pad_o = !spi_flash_ss[1] ? spi_flash_mosi : 1'b1;
-assign spi_sd_sclk_pad_o = !spi_flash_ss[1] ? spi_flash_sclk : 1'b1;
-assign spi_sd_ss_pad_o = spi_flash_ss[1];
-
-// input mux
-assign spi_flash_miso = !spi_flash_ss[0] ? spi_flash_miso_pad_i :
- !spi_flash_ss[1] ? spi_sd_miso_pad_i :
- 1'b0;
orpsocv2/rtl/verilog/components/or1k_startup/OR1K_startup_module_inst.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/rtl/verilog/orpsoc_top.v
===================================================================
--- orpsocv2/rtl/verilog/orpsoc_top.v (revision 54)
+++ orpsocv2/rtl/verilog/orpsoc_top.v (revision 55)
@@ -95,7 +95,7 @@
)
;
wire wb_rst;
- wire wb_clk, clk50, clk100, usbClk, dbg_tck;
+ wire wb_clk, clk50, clk100, dbg_tck;
wire pll_lock;
wire mem_io_req, mem_io_gnt, mem_io_busy;
wire [15:0] mem_dat_pad_i, mem_dat_pad_o;
@@ -318,11 +318,11 @@
// Inputs
.m4_dat_i (0),
.m4_adr_i (0),
- .m4_sel_i (0),
- .m4_we_i (0),
- .m4_cyc_i (0),
- .m4_stb_i (0),
- .m4_cab_i (0),
+ .m4_sel_i (4'h0),
+ .m4_we_i (1'b0),
+ .m4_cyc_i (1'b0),
+ .m4_stb_i (1'b0),
+ .m4_cab_i (1'b0),
// Outputs
//.m4_dat_o (),
//.m4_ack_o (),
@@ -333,11 +333,11 @@
// Inputs
.m5_dat_i (0),
.m5_adr_i (0),
- .m5_sel_i (0),
- .m5_we_i (0),
- .m5_cyc_i (0),
- .m5_stb_i (0),
- .m5_cab_i (0),
+ .m5_sel_i (4'h0),
+ .m5_we_i (1'b0),
+ .m5_cyc_i (1'b0),
+ .m5_stb_i (1'b0),
+ .m5_cab_i (1'b0),
// Outputs
//.m5_dat_o (),
//.m5_ack_o (),
@@ -348,11 +348,11 @@
// Inputs
.m6_dat_i (0),
.m6_adr_i (0),
- .m6_sel_i (0),
- .m6_we_i (0),
- .m6_cyc_i (0),
- .m6_stb_i (0),
- .m6_cab_i (0),
+ .m6_sel_i (4'h0),
+ .m6_we_i (1'b0),
+ .m6_cyc_i (1'b0),
+ .m6_stb_i (1'b0),
+ .m6_cab_i (1'b0),
// Outputs
//.m6_dat_o (),
//.m6_ack_o (),
@@ -363,11 +363,11 @@
// Inputs
.m7_dat_i (0),
.m7_adr_i (0),
- .m7_sel_i (0),
- .m7_we_i (0),
- .m7_cyc_i (0),
- .m7_stb_i (0),
- .m7_cab_i (0),
+ .m7_sel_i (4'h0),
+ .m7_we_i (1'b0),
+ .m7_cyc_i (1'b0),
+ .m7_stb_i (1'b0),
+ .m7_cab_i (1'b0),
// Outputs
//.m7_dat_o (),
//.m7_ack_o (),
@@ -454,8 +454,8 @@
// Inputs
.s5_dat_i (wbs_ds1_dat_o),
.s5_ack_i (wbs_ds1_ack_o),
- .s5_err_i (0),
- .s5_rty_i (0),
+ .s5_err_i (1'b0),
+ .s5_rty_i (1'b0),
// Outputs
.s5_dat_o (wbs_ds1_dat_i),
.s5_adr_o (wbs_ds1_adr_i),
@@ -469,8 +469,8 @@
// Inputs
.s6_dat_i (wbs_ds2_dat_o),
.s6_ack_i (wbs_ds2_ack_o),
- .s6_err_i (0),
- .s6_rty_i (0),
+ .s6_err_i (1'b0),
+ .s6_rty_i (1'b0),
// Outputs
.s6_dat_o (wbs_ds2_dat_i),
.s6_adr_o (wbs_ds2_adr_i),
@@ -484,8 +484,8 @@
// Inputs
.s7_dat_i (wbs_ds3_dat_o),
.s7_ack_i (wbs_ds3_ack_o),
- .s7_err_i (0),
- .s7_rty_i (0),
+ .s7_err_i (1'b0),
+ .s7_rty_i (1'b0),
// Outputs
.s7_dat_o (wbs_ds3_dat_i),
.s7_adr_o (wbs_ds3_adr_i),
@@ -909,7 +909,7 @@
.clk(wb_clk),
.rst(wb_rst)
);
-
+ /*
clk_gen iclk_gen
(
.POWERDOWN (1'b1),
@@ -916,28 +916,30 @@
.CLKA (clk_pad_i),
.LOCK (pll_lock),
.GLA(wb_clk),
- .GLB(usbClk_pll),
+ .GLB(),
.GLC()
);
+ */
+ generic_pll iclk_gen
+ (
+ // Outputs
+ .clk1x(wb_clk),
+ .clk2x(),
+ .clkdiv(),
+ .locked(pll_lock),
+ // Inputs
+ .clk_in(clk_pad_i),
+ .rst_in(~rst_pad_i)
+ );
+
assign rst_pad_o = pll_lock;
+ assign wb_rst = ~(pll_lock & rst_pad_i);
+ assign dbg_tck = dbg_tck_pad_i;
+`ifdef USE_ETHERNET_IO
+ assign eth_clk = eth_clk_pad_i;
+`else
+ assign eth_clk = 0;
+`endif
- gbuf gbufi1
- (
- .CLK(~(pll_lock & rst_pad_i)),
- .GL(wb_rst));
- gbuf gbufi2
- (
- .CLK(dbg_tck_pad_i),
- .GL(dbg_tck));
- gbuf gbufi3
- (
- .CLK(usbClk_pll),
- .GL(usbClk));
- gbuf gbufi4
- (
- .CLK(eth_clk_pad_i),
- .GL(eth_clk));
-
-
endmodule
/orpsocv2/backend/gbuf.v
File deleted
orpsocv2/backend/gbuf.v
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: orpsocv2/backend/generic_gbuf.v
===================================================================
--- orpsocv2/backend/generic_gbuf.v (nonexistent)
+++ orpsocv2/backend/generic_gbuf.v (revision 55)
@@ -0,0 +1,50 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SMII ////
+//// ////
+//// Description ////
+//// Low pin count serial MII ethernet interface ////
+//// ////
+//// To Do: ////
+//// - ////
+//// ////
+//// Author(s): ////
+//// - Michael Unneback, unneback@opencores.org ////
+//// ORSoC AB michael.unneback@orsoc.se ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+`timescale 1 ns/100 ps
+module gbuf
+ (
+ output GL,
+ input CLK
+ );
+
+ assign GL = CLK;
+
+endmodule
orpsocv2/backend/generic_gbuf.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: orpsocv2/backend/generic_buffers.v
===================================================================
--- orpsocv2/backend/generic_buffers.v (nonexistent)
+++ orpsocv2/backend/generic_buffers.v (revision 55)
@@ -0,0 +1,94 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// SMII ////
+//// ////
+//// Description ////
+//// Low pin count serial MII ethernet interface ////
+//// ////
+//// To Do: ////
+//// - ////
+//// ////
+//// Author(s): ////
+//// - Michael Unneback, unneback@opencores.org ////
+//// ORSoC AB michael.unneback@orsoc.se ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+module obufdff
+ (
+ input d,
+ output reg pad,
+ input clk,
+ input rst
+ );
+
+ always @ (posedge clk or posedge rst)
+ if (rst)
+ pad <= #1 1'b0;
+ else
+ pad <= #1 d;
+
+endmodule // obufdff
+
+module ibufdff
+ (
+ input pad,
+ output reg q,
+ input clk,
+ input rst
+ );
+
+ always @ (posedge clk or posedge rst)
+ if (rst)
+ q <= #1 1'b0;
+ else
+ q <= #1 pad;
+
+endmodule // ibufdff
+
+module iobuftri
+ (
+ input i,
+ input oe,
+ output o,
+ inout pad
+ );
+
+ assign #1 pad = oe ? i : 1'bz;
+ assign #1 o = pad;
+
+endmodule // iobuftri
+
+module obuf
+ (
+ input i,
+ inout pad
+ );
+
+ assign #1 pad = i;
+
+endmodule // iobuftri
orpsocv2/backend/generic_buffers.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mergeinfo
## -0,0 +0,0 ##
Index: orpsocv2/sim/bin/modelsim.scr
===================================================================
--- orpsocv2/sim/bin/modelsim.scr (nonexistent)
+++ orpsocv2/sim/bin/modelsim.scr (revision 55)
@@ -0,0 +1,164 @@
+// This file should be processed by the Makefile before being used
++incdir+$BENCH_DIR
++incdir+$BENCH_DIR/vpi/verilog
++incdir+$BACKEND_DIR
++incdir+$RTL_DIR
++incdir+$RTL_DIR/components/uart16550
++incdir+$RTL_DIR/components/ethernet
++incdir+$RTL_DIR/components/or1k_startup
++incdir+$RTL_DIR/components/or1k_top
++incdir+$RTL_DIR/components/or1200r2
++incdir+$RTL_DIR/components/tap
++incdir+$RTL_DIR/components/smii
++incdir+$RTL_DIR/components/debug_if
++incdir+$RTL_DIR/components/wb_sdram_ctrl
++incdir+$RTL_DIR/components/wb_conbus
+
+-y $BENCH_DIR
+-y $BENCH_DIR/vpi/verilog
+-y $BACKEND_DIR
+-y $RTL_DIR
+-y $RTL_DIR/components/uart16550
+-y $RTL_DIR/components/ethernet
+-y $RTL_DIR/components/or1k_startup
+-y $RTL_DIR/components/or1k_top
+-y $RTL_DIR/components/or1200r2
+-y $RTL_DIR/components/tap
+-y $RTL_DIR/components/smii
+-y $RTL_DIR/components/debug_if
+-y $RTL_DIR/components/wb_sdram_ctrl
+-y $RTL_DIR/components/ram_wb
+-y $RTL_DIR/components/wb_conbus
+
+// Couple of library files
+$BACKEND_DIR/sim_lib.v
+$BACKEND_DIR/generic_pll.v
+$BACKEND_DIR/generic_buffers.v
+
+// Verilog component files
+$RTL_DIR/components/uart16550/uart_rfifo.v
+$RTL_DIR/components/uart16550/uart_debug_if.v
+$RTL_DIR/components/uart16550/raminfr.v
+$RTL_DIR/components/uart16550/uart_transmitter.v
+$RTL_DIR/components/uart16550/uart_sync_flops.v
+$RTL_DIR/components/uart16550/uart_receiver.v
+$RTL_DIR/components/uart16550/uart_top.v
+$RTL_DIR/components/uart16550/uart_regs.v
+$RTL_DIR/components/uart16550/uart_tfifo.v
+$RTL_DIR/components/uart16550/uart_wb.v
+$RTL_DIR/components/wb_conbus/wb_conbus_top.v
+$RTL_DIR/components/wb_conbus/wb_conbus_arb.v
+$RTL_DIR/components/wb_sdram_ctrl/delay.v
+$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl.v
+$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
+$RTL_DIR/components/wb_sdram_ctrl/wb_sdram_ctrl_fifo.v
+$RTL_DIR/components/ethernet/eth_top.v
+$RTL_DIR/components/ethernet/eth_maccontrol.v
+$RTL_DIR/components/ethernet/eth_crc.v
+$RTL_DIR/components/ethernet/eth_rxethmac.v
+//$RTL_DIR/components/ethernet/eth_cop.v
+$RTL_DIR/components/ethernet/eth_spram_256x32.v
+$RTL_DIR/components/ethernet/eth_outputcontrol.v
+$RTL_DIR/components/ethernet/eth_rxstatem.v
+$RTL_DIR/components/ethernet/eth_register.v
+$RTL_DIR/components/ethernet/eth_registers.v
+$RTL_DIR/components/ethernet/eth_transmitcontrol.v
+$RTL_DIR/components/ethernet/eth_clockgen.v
+$RTL_DIR/components/ethernet/eth_random.v
+$RTL_DIR/components/ethernet/eth_macstatus.v
+//$RTL_DIR/components/ethernet/xilinx_dist_ram_16x32.v
+$RTL_DIR/components/ethernet/eth_txcounters.v
+$RTL_DIR/components/ethernet/eth_shiftreg.v
+$RTL_DIR/components/ethernet/eth_txethmac.v
+$RTL_DIR/components/ethernet/eth_wishbone.v
+$RTL_DIR/components/ethernet/eth_rxaddrcheck.v
+$RTL_DIR/components/ethernet/eth_miim.v
+$RTL_DIR/components/ethernet/eth_rxcounters.v
+$RTL_DIR/components/ethernet/eth_fifo.v
+$RTL_DIR/components/ethernet/eth_receivecontrol.v
+$RTL_DIR/components/ethernet/eth_txstatem.v
+$RTL_DIR/components/or1200r2/or1200_immu_top.v
+$RTL_DIR/components/or1200r2/or1200_sb_fifo.v
+$RTL_DIR/components/or1200r2/or1200_freeze.v
+$RTL_DIR/components/or1200r2/or1200_dpram_256x32.v
+$RTL_DIR/components/or1200r2/or1200_ic_fsm.v
+$RTL_DIR/components/or1200r2/or1200_spram_2048x32_bw.v
+$RTL_DIR/components/or1200r2/or1200_dc_fsm.v
+$RTL_DIR/components/or1200r2/or1200_spram_1024x32.v
+$RTL_DIR/components/or1200r2/or1200_spram_64x24.v
+$RTL_DIR/components/or1200r2/or1200_xcv_ram32x8d.v
+$RTL_DIR/components/or1200r2/or1200_wb_biu.v
+$RTL_DIR/components/or1200r2/or1200_spram.v
+$RTL_DIR/components/or1200r2/or1200_du.v
+$RTL_DIR/components/or1200r2/or1200_operandmuxes.v
+$RTL_DIR/components/or1200r2/or1200_dc_top.v
+$RTL_DIR/components/or1200r2/or1200_mem2reg.v
+$RTL_DIR/components/or1200r2/or1200_spram_64x22.v
+$RTL_DIR/components/or1200r2/or1200_except.v
+$RTL_DIR/components/or1200r2/or1200_immu_tlb.v
+$RTL_DIR/components/or1200r2/or1200_cpu.v
+$RTL_DIR/components/or1200r2/or1200_genpc.v
+$RTL_DIR/components/or1200r2/or1200_pic.v
+$RTL_DIR/components/or1200r2/or1200_dpram_32x32.v
+$RTL_DIR/components/or1200r2/or1200_lsu.v
+$RTL_DIR/components/or1200r2/or1200_spram_1024x32_bw.v
+$RTL_DIR/components/or1200r2/or1200_amultp2_32x32.v
+$RTL_DIR/components/or1200r2/or1200_iwb_biu.v
+$RTL_DIR/components/or1200r2/or1200_dc_ram.v
+$RTL_DIR/components/or1200r2/or1200_spram_1024x8.v
+$RTL_DIR/components/or1200r2/or1200_spram_2048x32.v
+$RTL_DIR/components/or1200r2/or1200_spram_256x21.v
+$RTL_DIR/components/or1200r2/or1200_ic_top.v
+$RTL_DIR/components/or1200r2/or1200_dmmu_top.v
+$RTL_DIR/components/or1200r2/or1200_dmmu_tlb.v
+$RTL_DIR/components/or1200r2/or1200_mult_mac.v
+$RTL_DIR/components/or1200r2/or1200_ctrl.v
+$RTL_DIR/components/or1200r2/or1200_ic_tag.v
+$RTL_DIR/components/or1200r2/or1200_top.v
+//$RTL_DIR/components/or1200r2/or1200_dpram.v
+$RTL_DIR/components/or1200r2/or1200_spram_32x24.v
+$RTL_DIR/components/or1200r2/or1200_if.v
+$RTL_DIR/components/or1200r2/or1200_dc_tag.v
+$RTL_DIR/components/or1200r2/or1200_spram_512x20.v
+$RTL_DIR/components/or1200r2/or1200_rf.v
+$RTL_DIR/components/or1200r2/or1200_spram_128x32.v
+$RTL_DIR/components/or1200r2/or1200_spram_2048x8.v
+$RTL_DIR/components/or1200r2/or1200_spram_64x14.v
+$RTL_DIR/components/or1200r2/or1200_gmultp2_32x32.v
+$RTL_DIR/components/or1200r2/or1200_sprs.v
+$RTL_DIR/components/or1200r2/or1200_reg2mem.v
+$RTL_DIR/components/or1200r2/or1200_qmem_top.v
+$RTL_DIR/components/or1200r2/or1200_tt.v
+$RTL_DIR/components/or1200r2/or1200_pm.v
+$RTL_DIR/components/or1200r2/or1200_tpram_32x32.v
+$RTL_DIR/components/or1200r2/or1200_alu.v
+$RTL_DIR/components/or1200r2/or1200_rfram_generic.v
+$RTL_DIR/components/or1200r2/or1200_ic_ram.v
+$RTL_DIR/components/or1200r2/or1200_cfgr.v
+$RTL_DIR/components/or1200r2/or1200_wbmux.v
+$RTL_DIR/components/or1200r2/or1200_sb.v
+$RTL_DIR/components/or1k_top/or1k_top.v
+$RTL_DIR/components/smii/smii_txrx.v
+$RTL_DIR/components/tap/tap_top.v
+$RTL_DIR/components/or1k_startup/OR1K_startup.v
+$RTL_DIR/components/or1k_startup/spi_flash_shift.v
+$RTL_DIR/components/or1k_startup/spi_flash_top.v
+$RTL_DIR/components/or1k_startup/spi_flash_clgen.v
+$RTL_DIR/components/ram_wb/ram_wb_sc_sw.v
+$RTL_DIR/components/ram_wb/ram_wb.v
+$RTL_DIR/components/debug_if/dbg_register.v
+$RTL_DIR/components/debug_if/dbg_cpu_registers.v
+$RTL_DIR/components/debug_if/dbg_crc32_d1.v
+$RTL_DIR/components/debug_if/dbg_top.v
+$RTL_DIR/components/debug_if/dbg_cpu.v
+$RTL_DIR/components/debug_if/dbg_wb.v
+$RTL_DIR/dummy_slave.v
+
+$RTL_DIR/orpsoc_top.v
+
+// Testbench support source
+//$BENCH_DIR/or1200_monitor.v
+
+// Testbench (top) source
+//$BENCH_DIR/orpsoc_testbench.v
+
Index: orpsocv2/sim/bin/icarus.scr
===================================================================
--- orpsocv2/sim/bin/icarus.scr (revision 54)
+++ orpsocv2/sim/bin/icarus.scr (revision 55)
@@ -34,5 +34,7 @@
$BENCH_DIR/orpsoc_testbench.v
// Couple of library files
-$RTL_DIR/components/smii/generic_buffers.v
+$BACKEND_DIR/generic_pll.v
+$BACKEND_DIR/generic_buffers.v
+$BACKEND_DIR/generic_gbuf.v
$BACKEND_DIR/sim_lib.v
/orpsocv2/sim/bin/Makefile
48,9 → 48,8
# make rtl-tests |
# |
# Run the software tests in the RTL model of the ORPSoC being |
# simulated with an event-driven simulator like Icarus. Also |
# possible to use Cadence's Verilog simulators with the |
# "rtl-nc-tests" target. |
# simulated with an event-driven simulator like Icarus. It's also |
# possible to use Modelsim's vsim and Cadence's Verilog simulators. |
# |
# make vlt-tests |
# |
264,6 → 263,7
ICARUS_COMMAND_FILE=icarus.scr |
VLT_COMMAND_FILE=verilator.scr |
SIM_SUCCESS_MESSAGE=deaddead |
MGC_COMMAND_FILE=modelsim.scr |
|
ARCH_SIM_EXE=or32-elf-sim |
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg |
275,8 → 275,51
EVENT_SIM_FLAGS += "-D USE_SDRAM=$(USE_SDRAM)" |
endif |
|
# Set SIMULATOR=vsim on command line to use Modelsim |
ifeq ($(SIMULATOR), vsim) |
# Modelsim |
SIM_COMMANDFILE=$(MGC_COMMAND_FILE) |
else |
# Icarus Verilog Simulator |
SIM_COMMANDFILE=$(ICARUS_COMMAND_FILE) |
endif |
|
GENERATED_COMMANDFILE=$(SIM_COMMANDFILE).generated |
|
# When Modelsim is selected as simulator, we compile |
# the ORPSoC system into one library called orpsoc and |
# then simply re-compile the testbench and or1200_monitor |
# whenever we run the simulation, so just that part is |
# recompiled for every test, instead of the whole thing. |
MGC_ORPSOC_LIB=orpsoc |
MGC_ORPSOC_LIB_DIR=$(SIM_RUN_DIR)/$(MGC_ORPSOC_LIB) |
|
# If VCD dump is desired, tell Modelsim not to optimise |
# away everything. |
ifeq ($(VCD), 1) |
VOPT_ARGS=-voptargs="+acc=rnp" |
endif |
|
# Simulation compile and run commands, depending on your |
# simulator. Currently only Modelsim (vsim) and Icarus right |
# now. |
# TODO: Put the NC-sim commands in here too and have just the |
# single simulation test loop rule. |
ifeq ($(SIMULATOR), vsim) |
# Line to compile the orpsoc design into a modelsim library. |
SIM_COMMANDCOMPILE=if [ ! -e work ]; then vlib work; vlib $(MGC_ORPSOC_LIB); vlog -work orpsoc -f $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); fi |
# Final modelsim compile, done each time, pulling in or1200 |
# monitor and the new test_defines.v file: |
VSIM_COMPILE_TB=vlog +incdir+. +incdir+$(BENCH_VERILOG_DIR) +incdir+$(RTL_VERILOG_DIR) +define+TEST_DEFINE_FILE $(BENCH_VERILOG_DIR)/or1200_monitor.v $(BENCH_VERILOG_DIR)/orpsoc_testbench.v |
# Simulation run command: |
SIM_COMMANDRUN=$(VSIM_COMPILE_TB); vsim -c -quiet +nowarnTFMPC -L $(MGC_ORPSOC_LIB) $(VOPT_ARGS) -do "run -all; exit" orpsoc_testbench |
else |
# Icarus Verilog Simulator compile command |
SIM_COMMANDCOMPILE=rm -f $(SIM_RUN_DIR)/a.out; $(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) $(EVENT_SIM_FLAGS) |
# Icarus Verilog run command |
SIM_COMMANDRUN=$(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out |
endif |
|
# Enable ethernet if defined on the command line |
ifdef USE_ETHERNET |
EVENT_SIM_FLAGS += "-D USE_ETHERNET=$(USE_ETHERNET) -D USE_ETHERNET_IO=$(USE_ETHERNET)" |
297,12 → 340,23
|
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v: |
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v |
$(RTL_VERILOG_DIR)/intercon.v: |
@cd $(RTL_VERILOG_DIR) && sed '/defparam/!s/\([a-zA-Z0-9_]\)\.//g' intercon.vm > intercon.v |
|
.PHONY: prepare_rtl |
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v #$(RTL_VERILOG_DIR)/intercon.v |
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v |
|
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) |
@sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \ |
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \ |
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \ |
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \ |
-e \\!^//.*\$$!d -e \\!^\$$!d ; \ |
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \ |
if [ ! -z $$VCD ]; \ |
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \ |
fi; \ |
if [ ! -z $$UART_PRINTF ]; \ |
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE); \ |
fi |
|
ifdef UART_PRINTF |
TEST_SW_MAKE_OPTS="UART_PRINTF=1" |
321,52 → 375,50
prepare_dirs: |
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi |
|
# Rough guide to how these tests work: |
# First, the couple of custom, required, software tools under sw/utils are |
# compiled, and then the software library files. |
# Next the few verilog files that need preperation are taken care of. |
# The test begins by starting a loop in bash using on the strings defined in |
# TESTS. Each one corresponds to a certain module of software for the OpenRISC |
# that is included in this test suite. Under the sw/ path is a set of paths, |
# and all except the support/ and utils/ paths contain code which is run to |
# test the OR1k used in this test suite. For each of these software modules, |
# it is possible that different tests are done using the same module. These |
# tests can vary by either using different levels of optimisation during |
# compilation, and/or by having the OR1k's caches enabled or disabled. |
# Each test has a unique name, and under the $(SIM_RESULTS_DIR), which is |
# usually just ../results, log files, and optionally VCD files, are created for |
# inspection later and are named according to the test. Inspect the file |
# bench/verilog/or1200_monitor.v to find out in detail what each log consists |
# of. |
# For each test, a few things occur. First the software that will run inside |
# the simulated OR1k system is compiled, converted to a format which can be |
# read |
# into the flash memory model via $readmemh() and linked to the sim/run |
# directory as $(SIM_FLASH_MEM_FILE), which currently is flash.in. Next a |
# compilation script for icarus is generated, containing a list of all the |
# RTL files and include directories. Next, an include file for the verilog |
# testbench is generated, containing a string of the name of the current |
# test, path to the results directory (for VCD generation) and any other |
# things which might vary from test to test. This is not done by +define |
# lines in the icarus script because of string handling incosistencies |
# between different simulators and shells. |
# Once all the files are generated, icarus is called to compile the rtl |
# design, and then run it. Each of the tested software modules have code which |
# will trigger the simulation to be stopped by use of the l.nop instruction |
# with an immediate value of 1. When the simulation finishes, the simulation |
# executable exits and the log of the simulation is inspected for the expected |
# output. Currently, the string "deaddead" indicates that the software |
# completed successfully. This is counted as the ORPSoC "passing" the test. In |
# fact, whether the system did the right thing or not requires more |
# inspection, but roughly this is a good indicator that nothing major went |
# wrong. |
# Once the current test is finished, the next begins with the compilation of its |
# software and linking of the resulting hex file to the run path, etc. |
# Main RAM setup - (RTL simulation with Icarus/NCSim only!): |
# Define USE_SDRAM to enable the external SDRAM, otherwise the simulation |
# defaults to an internal SRAM. Eg. $ make rtl-tests USE_SDRAM=1 VCD=1 |
# Verilator defaults to internal memories |
rtl-tests: prepare_sw prepare_rtl prepare_dirs |
# |
# Rough guide to how event driven simulation test loop works: |
# |
# 1. Compile software support programs. |
# 2. Generate RTL compilation script file |
# 3. For each test listed in $(TESTS), loop and |
# a) Compile software |
# b) Create appropriate image to be loaded into sim |
# c) Create a verilog file to be included by top level |
# d) Compile the RTL design |
# e) Run the RTL design in the chosen simulator |
# f) Check the output (files in ../results) |
# |
# Default setup is: |
# * Event-driven simulation with Icarus Verilog |
# * Internal SRAM memory, preloaded with application |
# * Ethernet disabled |
# * VCD generation disabled |
# * printf() via UART disabled |
# * Logging enabled |
# |
# Options: |
# SIMULATOR=vsim |
# Use Mentor Graphics Modelsim simulator |
# USE_SDRAM=1 |
# Enable use of SDRAM - changes boot sequence and takes |
# a lot longer due to application being loaded out of |
# external FLASH memory and into SDRAM before execution |
# from the SDRAM. |
# VCD=1 |
# Enable VCD generation. These files are output to |
# ../results |
# USE_ETHERNET=1 |
# Turns on ethernet core inclusion. There are currently |
# some tests, but not included by default. Check the sw |
# directory |
# UART_PRINTF=1 |
# Make the software use the UART core to print out |
# printf() calls. |
# NO_SIM_LOGGING=1 |
# Turn off generation of logging files in the ../results |
# directory. |
# |
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare_sw prepare_rtl prepare_dirs |
@echo |
@echo "Beginning loop that will complete the following tests: $(TESTS)" |
@echo |
381,20 → 433,14
rm -f $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \ |
ln -s $$CURRENT_TEST_SW_DIR/$$TEST$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \ |
ln -s $$CURRENT_TEST_SW_DIR/$$TEST.vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE); \ |
sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \ |
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \ |
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \ |
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \ |
-e \\!^//.*\$$!d -e \\!^\$$!d ; \ |
echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \ |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \ |
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \ |
if [ ! -z $$VCD ]; \ |
then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \ |
then echo "\`define VCD" >> $(SIM_RUN_DIR)/test_define.v; \ |
fi; \ |
if [ ! -z $$UART_PRINTF ]; \ |
then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; \ |
then echo "\`define UART_PRINTF" >> $(SIM_RUN_DIR)/test_define.v; \ |
fi; \ |
echo "\`define TEST_NAME_STRING \"$$TEST\"" > $(SIM_RUN_DIR)/test_define.v; \ |
echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v; \ |
if echo $$TEST | grep -q -i ^eth; then \ |
echo "\`define ENABLE_ETH_STIM" >> $(SIM_RUN_DIR)/test_define.v; \ |
echo "\`define ETH_PHY_VERBOSE" >> $(SIM_RUN_DIR)/test_define.v; \ |
404,11 → 450,10
fi; \ |
echo ; \ |
echo "\t#### Compiling RTL ####"; \ |
rm -f $(SIM_RUN_DIR)/a.out; \ |
$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS); \ |
$(SIM_COMMANDCOMPILE); \ |
echo; \ |
echo "\t#### Beginning simulation ####"; \ |
time -p $(ICARUS_VVP) -l $(SIM_RESULTS_DIR)/$$TEST-vvp-out.log a.out ; \ |
time -p $(SIM_COMMANDRUN) ; \ |
if [ $$? -gt 0 ]; then exit $$?; fi; \ |
TEST_RESULT=`cat $(SIM_RESULTS_DIR)/$$TEST-general.log | grep report | grep $(SIM_SUCCESS_MESSAGE) -c`; \ |
echo; echo "\t####"; \ |
779,7 → 824,7
@if [ -f $(SIM_VLT_DIR)/OrpsocMain.gcda ]; then echo;echo "\tBacking up verilator profiling output to /tmp"; echo; \ |
cp $(SIM_VLT_DIR)/*.gc* /tmp; \ |
cp $(BENCH_SYSC_SRC_DIR)/*.gc* /tmp; fi |
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR) |
rm -rf $(SIM_RESULTS_DIR) $(SIM_RUN_DIR)/*.* $(SIM_VLT_DIR) $(MGC_ORPSOC_LIB_DIR) $(SIM_RUN_DIR)/work $(SIM_RUN_DIR)/transcript |
|
clean-sysc: |
# Clean away dependency files generated by verilator |
787,6 → 832,5
|
clean-rtl: |
# Clean away temporary verilog source files |
rm -f $(RTL_VERILOG_DIR)/intercon.v |
rm -f $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v |
|
/orpsocv2/sim/bin/verilator.scr
32,8 → 32,11
// RTL files (top) |
$RTL_DIR/orpsoc_top.v |
|
-v $RTL_DIR/components/smii/generic_buffers.v |
-v $BACKEND_DIR/generic_pll.v |
-v $BACKEND_DIR/generic_buffers.v |
-v $BACKEND_DIR/generic_gbuf.v |
-v $BACKEND_DIR/sim_lib.v |
|
+define+DISABLE_IOS_FOR_VERILATOR |
+define+VERILATOR |
|