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/orpsocv2/doc/orpsoc.texi
73,9 → 73,9
 
@cindex introduction to this @value{ORPSOC}
 
@value{ORPSOC} is intended to be a reference implementation of processors in the OpenRISC family. It provides a smallest-possible reference system, primarily for testing of the processors. It also provides systems intended to be synthesized and run on physical hardware.
@value{ORPSOC} is intended to be a reference implementation of processors in the OpenRISC family. It provides a smallest-possible reference system, primarily for testing of the processors. It also provides systems intended to be synthesized and programmed on physical hardware.
 
The reference system is the least complex implementation and consists of just enough to test the processor's functionality. The board-targeted builds include many additional peripherals.
The reference system is the least complex implementation and consists of just enough to test the processor's functionality. The board-targeted builds typically include many additional peripherals.
 
The next section in this document outlines the organisation and structure of the project. The section ``@emph{Getting Started}'' goes through getting the project source and setting up any necessary tools. Each following section outlines a particular implementation of an OpenRISC-based system, beginning with the reference system. Each implementation section has an overview of the structure of the project (which probably won't vary much between the implementations), a section on setting up the required tools, running simulation, and if applicable, backend and debugging steps. There may be additional sections on modifying or customising each implementation system.
 
990,9 → 990,9
 
The OpenCores 10/100 Ethernet MAC can be used for Ethernet, but only with the PHY in 10/100 mode using the MII interface to the Marvel Alaska Ethernet PHY IC. There still may be bugs in the FIFO buffer configuration in the ML501's @code{ethmac_defines.v} file should not be changed.
 
The project is configured to generate either a @code{.bit} file for direct programming via JTAG, or a @code{.mcs} file with inbuilt bootloader software for the processor, meaning the board can be powered up and an application like ORPmon loaded without having to reprogram it from iMPACT between power cycles.
The ML501 build's scripts are capable of generating either a programming bitstream, @code{.bit}, file for direct programming of the FPGA via JTAG, or a flash image , @code{.mcs}, file which can be programmed into the on-board SPI flash which the FPGA can configure itself from on power-on. This flash image file may also contain a software image the processor can load at reset to, for example, present the user with the prompt for a boot monitor at power-on.
 
This guide is far from complete, but provides the basics on running simulations, and building the design.
This guide is a work in progress, and provides the basics on simulating, building and modifying the design.
 
@node ML501 Structure
@section Structure
1008,8 → 1008,14
@node ML501 XILINX_PATH
@subsection ML501 XILINX_PATH
 
Be sure to set the environment variable @code{XILINX_PATH} to the path of the ISE path on the host machine. This can be done with something like @kbd{export XILINX_PATH=/software/xilinx_11.1/ISE} and additionally a symbolic link to the Verilog simulation library sources will be required - see the simulation section on this. Note that it helps to add the @code{XILINX_PATH} variable to the user's @code{.bashrc} script or similar to save setting it each time a new shell is opened.
Be sure to set the environment variable @code{XILINX_PATH} to the path of the Xilinx tools' install path on the host machine. This path is usually the base install path for the Xilinx tool suite and contains subdirectories such as @code{ISE/}, @code{common/}, @code{PlanAhead/}, etc.
 
Most bash-like shells can use the following line to set this environment variable.
 
@example @kbd{export XILINX_PATH=/software/xilinx_12.3} @end example
 
Note that it helps to add the @code{XILINX_PATH} variable to the user's @code{.bashrc} script or similar to save setting it each time a new shell is opened.
 
If the @code{XILINX_PATH} variable is not set correctly, the makefiles will not run.
 
This build has been tested with ISE versions 11.1 and 12.3.
/orpsocv2/scripts/make/Makefile-board-modelsim.inc
3,13 → 3,13
#
# Modelsim-specific settings
#
VOPT_ARGS=$(QUIET) -suppress 2241
VOPT_ARGS+=$(QUIET) -suppress 2241
 
# If VCD dump is desired, tell Modelsim not to optimise
# away everything.
ifeq ($(VCD), 1)
#VOPT_ARGS=-voptargs="+acc=rnp"
VOPT_ARGS=+acc=rnpqv
VOPT_ARGS+=+acc=rnpqv
endif
 
# VSIM commands
16,7 → 16,7
# Suppressed warnings - 3009: Failed to open $readmemh() file
# Suppressed warnings - 3009: Module 'blah' does not have a `timescale directive in effect, but previous modules do.
# Suppressed warnings - 8598: Non-positive replication multiplier inside concat. Replication will be ignored
VSIM_ARGS= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
VSIM_ARGS+= -suppress 7 -suppress 3009 -suppress 8598 -c $(QUIET) -do "set StdArithNoWarnings 1; run -all; exit"
 
# VPI debugging interface set up
VPI_SRC_C_DIR=$(COMMON_BENCH_VERILOG_DIR)/vpi/c
62,8 → 62,8
echo "+libext+.vm" >> $@; \
fi
ifeq ($(FPGA_VENDOR), xilinx)
$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/unisims" >> $@;
$(Q)echo "-y "$(XILINX_PATH)"/verilog/src/XilinxCoreLib" >> $@;
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/unisims" >> $@;
$(Q)echo "-y "$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src/XilinxCoreLib" >> $@;
endif
$(Q)echo >> $@
 
77,7 → 77,7
$(Q)for vsrc in $(BOARD_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
$(Q)for vsrc in $(COMMON_BENCH_VERILOG_SRC); do echo $$vsrc >> $@; done
ifeq ($(FPGA_VENDOR), xilinx)
$(Q)echo "+incdir+"$(XILINX_PATH)"/verilog/src" >> $@;
$(Q)echo "+incdir+"$(TECHNOLOGY_LIBRARY_VERILOG_DIR)"/src" >> $@;
endif
$(Q)echo >> $@
 
121,6 → 121,9
ifeq ($(FPGA_VENDOR), xilinx)
$(MODELSIM): modelsim_bench.scr $(TEST_DEFINES_VLG) $(VPI_LIBS) work
$(Q)echo; echo "\t### Compiling Xilinx support libs, user design & testbench ###"; echo
ifeq ($(DO_XILINX_COMPXLIB), 1)
$(Q)$(TECHNOLOGY_BACKEND_BIN_DIR)/compxlib $(XLIB_ARGS)
endif
$(Q)vlog $(QUIET) -nologo -incr $(BENCH_TOP_FILE) -f $<
$(Q)vopt $(QUIET) glbl $(RTL_TESTBENCH_TOP_NAME) $(VOPT_ARGS) -o tb
$(Q)echo; echo "\t### Launching simulation ###"; echo
/orpsocv2/boards/xilinx/ml501/Makefile.inc
22,10 → 22,10
ifeq ($(XILINX_PATH),)
$(error XILINX_PATH environment variable not set. Set it and rerun)
endif
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/ISE/settings32.sh
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
$(error XILINX_PATH variable not set correctly. Cannot find $(XILINX_SETTINGS_SCRIPT))
endif
 
# Backend directories
36,7 → 36,7
# Technology backend (vendor-specific)
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend
# This path is for the technology library
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX_PATH)/verilog
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX_PATH)/ISE/verilog
 
# Bootrom setup
# BootROM code, which generates a verilog array select values
/orpsocv2/boards/xilinx/ml501/backend/par/bin/Makefile
124,7 → 124,7
 
#this target downloads the bitstream to the target fpga
download: $(BIT_FILE) $(BATCH_FILE)
$(Q)( . ${XILINX_PATH}/settings32.sh && \
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \
impact -batch $(BATCH_FILE) )
 
#This target uses netgen to make a simulation netlist

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