URL
https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk
Subversion Repositories openrisc_2011-10-31
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc/trunk
- from Rev 627 to Rev 628
- ↔ Reverse comparison
Rev 627 → Rev 628
/orpsocv2/boards/xilinx/atlys/Makefile.inc
0,0 → 1,83
# Makefile fragment with some variables global to this board board |
# Expects BOARD_ROOT to be set |
|
FPGA_VENDOR=xilinx |
FPGA_ARCH=spartan6 |
BOARD_NAME=atlys |
BOARD=$(FPGA_VENDOR)/$(BOARD_NAME) |
DESIGN_NAME=orpsoc |
|
# Path down to root of project |
PROJECT_ROOT=$(BOARD_ROOT)/../../.. |
|
SYNTHESIS_TOOL=xst |
|
export BOARD |
|
include $(PROJECT_ROOT)/scripts/make/Makefile-misc.inc |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-paths.inc |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-tops.inc |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-definesparse.inc |
|
# Check that the XILINX_PATH variable is set |
ifeq ($(XILINX_PATH),) |
$(error XILINX_PATH environment variable not set. Set it and rerun) |
endif |
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh |
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi) |
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0) |
$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh) |
endif |
|
# Backend directories |
# This one is the board build's backend dir. |
BOARD_BACKEND_DIR=$(BOARD_ROOT)/backend |
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog |
BOARD_BACKEND_BIN_DIR=$(BOARD_BACKEND_DIR)/bin |
# Technology backend (vendor-specific) |
TECHNOLOGY_BACKEND_DIR=$(BOARD_ROOT)/../backend |
# This path is for the technology library |
TECHNOLOGY_LIBRARY_VERILOG_DIR=$(XILINX_PATH)/ISE/verilog |
# This path is for the technology binaries |
TECHNOLOGY_BACKEND_BIN_DIR=$(XILINX_PATH)/ISE/bin/lin |
|
# Board specific modelsim options |
VSIM_ARGS= -L secureip |
VOPT_ARGS= -L secureip |
|
# Xilinx Xlib specific settings |
DO_XILINX_COMPXLIB=1 |
XLIB_ARGS=-intstyle silent -s mti_se -l all -arch $(FPGA_ARCH) -lib all |
|
# Bootrom setup |
# BootROM code, which generates a verilog array select values |
BOOTROM_FILE=bootrom.v |
BOOTROM_SW_DIR=$(BOARD_SW_DIR)/bootrom |
BOOTROM_SRC=$(shell ls $(BOOTROM_SW_DIR)/* | grep -v $(BOOTROM_FILE)) |
BOOTROM_VERILOG=$(BOOTROM_SW_DIR)/$(BOOTROM_FILE) |
|
bootrom: $(BOOTROM_VERILOG) |
|
$(BOOTROM_VERILOG): $(BOOTROM_SRC) |
$(Q)echo; echo "\t### Generating bootup ROM ###"; echo |
$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) $(BOOTROM_FILE) |
|
clean-bootrom: |
$(Q)echo; echo "\t### Cleaning bootup ROM ###"; echo |
$(Q)$(MAKE) -C $(BOOTROM_SW_DIR) clean |
|
include $(PROJECT_ROOT)/scripts/make/Makefile-board-rtlmodules.inc |
|
# "Backend" source file stuff (PLL, RAM macro models.) |
BOARD_BACKEND_VERILOG_SRC=$(shell ls $(BOARD_BACKEND_VERILOG_DIR)/*.v ) |
|
# Backend tool path |
|
# BACKEND_TECHNOLOGY_VERILOG_SRC should be set if we need to compile specific |
# libraries, as in the Actel and Altera case, and left empty for Xilinx who |
# allow us to simply pass the path with the -y option because they have each |
# bit of the tech library in individual files, and in which case this variable |
# should be left unset. |
|
# Keep this variable empty |
BACKEND_TECHNOLOGY_VERILOG_SRC= |
/orpsocv2/boards/xilinx/atlys/backend/par/run/Makefile
0,0 → 1,2
include ../bin/Makefile |
|
/orpsocv2/boards/xilinx/atlys/backend/par/bin/Makefile
0,0 → 1,153
###################################################################### |
#### #### |
#### ORPSoC Xilinx backend Makefile #### |
#### #### |
#### Author(s): #### |
#### - Julius Baxter, julius@opencores.org #### |
#### #### |
#### #### |
###################################################################### |
#### #### |
#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG #### |
#### #### |
#### This source file may be used and distributed without #### |
#### restriction provided that this copyright statement is not #### |
#### removed from the file and that any derivative work contains #### |
#### the original copyright notice and the associated disclaimer. #### |
#### #### |
#### This source file is free software; you can redistribute it #### |
#### and/or modify it under the terms of the GNU Lesser General #### |
#### Public License as published by the Free Software Foundation; #### |
#### either version 2.1 of the License, or (at your option) any #### |
#### later version. #### |
#### #### |
#### This source is distributed in the hope that it will be #### |
#### useful, but WITHOUT ANY WARRANTY; without even the implied #### |
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #### |
#### PURPOSE. See the GNU Lesser General Public License for more #### |
#### details. #### |
#### #### |
#### You should have received a copy of the GNU Lesser General #### |
#### Public License along with this source; if not, download it #### |
#### from http://www.opencores.org/lgpl.shtml #### |
#### #### |
###################################################################### |
|
# Name of the directory we're currently in |
CUR_DIR=$(shell pwd) |
|
# The root path of the board build |
BOARD_ROOT ?=$(CUR_DIR)/../../.. |
include $(BOARD_ROOT)/Makefile.inc |
|
# |
# Options for Xilinx PAR tools |
# |
FPGA_PART=xc6slx45-2-csg324 |
ifeq ($(V), 1) |
XILINX_FLAGS ?= |
else |
XILINX_FLAGS ?=-intstyle silent |
endif |
XILINX_MAP_FLAGS=-logic_opt off |
XILINX_AREA_TARGET = speed |
TIMING_REPORT_OPTIONS = -u 1000 -e 1000 |
SPI_FLASH_SIZE_KBYTES ?=16384 |
SPI_BOOTLOADER_SW_OFFSET_HEX ?=1c0000 |
|
print-config: |
$(Q)echo; echo "\t### Backend make configuration ###"; echo |
$(Q)echo "\tFPGA_PART="$(FPGA_PART) |
$(Q)echo "\tXILINX_FLAGS="$(XILINX_FLAGS) |
$(Q)echo "\tXILINX_MAP_FLAGS="$(XILINX_MAP_FLAGS) |
$(Q)echo "\tXILINX_AREA_TARGET="$(XILINX_AREA_TARGET) |
$(Q)echo "\tTIMING_REPORT_OPTIONS="$(TIMING_REPORT_OPTIONS) |
$(Q)echo "\tSPI_FLASH_SIZE_KBYTES="$(SPI_FLASH_SIZE_KBYTES) |
$(Q)echo "\tSPI_BOOTLOADER_SW_OFFSET_HEX="$(SPI_BOOTLOADER_SW_OFFSET_HEX) |
|
NGC_FILE=$(BOARD_SYN_RUN_DIR)/$(DESIGN_NAME).ngc |
NGD_FILE=$(DESIGN_NAME).ngd |
UCF_FILE=../bin/$(BOARD_NAME).ucf |
MAPPED_NCD=$(DESIGN_NAME)_mapped.ncd |
PARRED_NCD=$(DESIGN_NAME).ncd |
PCF_FILE=$(DESIGN_NAME).pcf |
BIT_FILE=$(DESIGN_NAME).bit |
BIT_FILE_FOR_SPI=$(DESIGN_NAME)_spiboot.bit |
BATCH_FILE=$(DESIGN_NAME).batch |
MCS_FILE=$(DESIGN_NAME).mcs |
|
$(NGC_FILE): |
$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) $(DESIGN_NAME).ngc |
|
$(NGD_FILE): $(UCF_FILE) $(NGC_FILE) |
@echo; echo "\t#### Running NGDBuild ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
ngdbuild -p $(FPGA_PART) -sd $(BOARD_BACKEND_BIN_DIR) -uc $(UCF_FILE) \ |
$(NGC_FILE) $@ ) |
|
#This target uses Xilinx tools to perform Mapping |
$(MAPPED_NCD): $(NGD_FILE) |
@echo; echo "\t#### Mapping ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
map -p $(FPGA_PART) -detail -pr b \ |
-timing -ol high -w $(XILINX_FLAGS) -o $@ -xe n $(NGD_FILE) $(PCF_FILE)) |
|
#This target uses Xilinx tools to Place & Route the design |
$(PARRED_NCD): $(MAPPED_NCD) |
@echo; echo "\t#### PAR'ing ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
par -w -ol high -xe n $(XILINX_FLAGS) $< $@ $(PCD_FILE) ) |
|
#This target uses Xilinx tools to generate a bitstream for download |
$(BIT_FILE): $(PARRED_NCD) |
@echo; echo "\t#### Generating .bit file ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
bitgen -w $(XILINX_FLAGS) -g StartUpClk:JtagClk $< $@ ) |
|
$(BIT_FILE_FOR_SPI): $(PARRED_NCD) |
@echo; echo "\t#### Generating .bit file for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
bitgen -w $(XILINX_FLAGS) -g StartUpClk:CClk $< $@ ) |
|
# Generate MCS with bootloader specified by user, if BOOTLOADER_BIN defined. |
ifeq ($(BOOTLOADER_BIN),) |
$(MCS_FILE): $(BIT_FILE_FOR_SPI) |
@echo; echo "\t#### Generating .mcs file for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< ) |
else |
$(MCS_FILE): $(BIT_FILE_FOR_SPI) |
@echo; echo "\t#### Generating .mcs file with bootloader for SPI load ####"; |
$(Q)( . $(XILINX_SETTINGS_SCRIPT) && \ |
promgen -spi -p mcs -w -o $@ -s $(SPI_FLASH_SIZE_KBYTES) -u 0 $< \ |
-data_file up $(SPI_BOOTLOADER_SW_OFFSET_HEX) $(BOOTLOADER_BIN) \ |
) |
endif |
|
#this target downloads the bitstream to the target fpga |
download: $(BIT_FILE) $(BATCH_FILE) |
$(Q)( . ${XILINX_PATH}/settings32.sh && \ |
impact -batch $(BATCH_FILE) ) |
|
#This target uses netgen to make a simulation netlist |
netlist: $(PARRED_NCD) |
@echo; echo "\t#### Generating netlist ####"; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \ |
netgen -ofmt verilog -sim -dir netlist -pcf $(PCF_FILE) $<) |
|
#This one uses TRCE to make a timing report |
timingreport: $(PARRED_NCD) |
@echo; echo "\t#### Generating timing report ####"; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) && \ |
trce $(TIMING_REPORT_OPTIONS) $< ) |
|
|
clean: |
$(Q)rm -rf *.* xlnx_auto* |
|
clean-syn: |
$(Q)$(MAKE) -C $(BOARD_SYN_RUN_DIR) distclean |
|
distclean: clean-syn clean |
|
.PRECIOUS : $(PARRED_NCD) $(MAPPED_NCD) $(NGC_FILE) $(NGD_FILE) $(BIT_FILE) $(BIT_FILE_FOR_SPI) |
/orpsocv2/boards/xilinx/atlys/sim/run/Makefile
0,0 → 1,153
include ../bin/Makefile |
/orpsocv2/boards/xilinx/atlys/sim/bin/Makefile
0,0 → 1,83
###################################################################### |
#### #### |
#### ORPSoCv2 Xilinx simulation Makefile #### |
#### #### |
#### Description #### |
#### ORPSoCv2 Testbenches Makefile, containing rules for #### |
#### configuring and running different tests on the current #### |
#### ORPSoC(v2) design. #### |
#### #### |
#### To do: #### |
#### #### |
#### Author(s): #### |
#### - Julius Baxter, julius@opencores.org #### |
#### #### |
#### #### |
###################################################################### |
#### #### |
#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG #### |
#### #### |
#### This source file may be used and distributed without #### |
#### restriction provided that this copyright statement is not #### |
#### removed from the file and that any derivative work contains #### |
#### the original copyright notice and the associated disclaimer. #### |
#### #### |
#### This source file is free software; you can redistribute it #### |
#### and/or modify it under the terms of the GNU Lesser General #### |
#### Public License as published by the Free Software Foundation; #### |
#### either version 2.1 of the License, or (at your option) any #### |
#### later version. #### |
#### #### |
#### This source is distributed in the hope that it will be #### |
#### useful, but WITHOUT ANY WARRANTY; without even the implied #### |
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #### |
#### PURPOSE. See the GNU Lesser General Public License for more #### |
#### details. #### |
#### #### |
#### You should have received a copy of the GNU Lesser General #### |
#### Public License along with this source; if not, download it #### |
#### from http://www.opencores.org/lgpl.shtml #### |
#### #### |
###################################################################### |
|
# Name of the directory we're currently in |
CUR_DIR=$(shell pwd) |
|
BOARD_ROOT=$(CUR_DIR)/../.. |
include $(BOARD_ROOT)/Makefile.inc |
|
# Simulation-specific paths and files from this one |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-benchsrc.inc |
|
TEST ?= or1200-simple |
TESTS ?= or1200-simple or1200-cbasic or1200-dctest or1200-float or1200-mmu or1200-basic or1200-except or1200-tick or1200-ticksyscall uart-simple |
|
include $(PROJECT_ROOT)/scripts/make/Makefile-simulators.inc |
|
# Gets turned into verilog `define |
SIM_TYPE=RTL |
|
SIMULATOR ?= $(MODELSIM) |
|
# Include the test-defines.v generation rule |
include $(PROJECT_ROOT)/scripts/make/Makefile-sim-definesgen.inc |
|
# |
# Modelsim make rules for RTL tests |
# |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-modelsim.inc |
|
# |
# RTL test rules |
# |
include $(PROJECT_ROOT)/scripts/make/Makefile-rtltestrules.inc |
|
# |
# Software make rules (called recursively) |
# |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-sw.inc |
|
# |
# Cleaning rules |
# |
include $(PROJECT_ROOT)/scripts/make/Makefile-board-simclean.inc |
/orpsocv2/boards/xilinx/atlys/sw/bootrom/Makefile
0,0 → 1,27
# Makefile for bootROM Verilog |
# We will do it by building the main one, and applying our local board's |
# settings. |
# To rebuild after board.h is changed, a clean must be done first. |
|
# Set the path to our board's root directory |
BOARD_SW_ROOT=.. |
|
include $(BOARD_SW_ROOT)/Makefile.inc |
|
all: bootrom.v |
|
# Copy the one build in the root software path to here. |
bootrom.v: $(SW_ROOT)/bootrom/bootrom.v |
$(Q)cp -v $< . |
|
# Export BOARD so the Make script in the root software path knows we're to |
# use our board.h file, not theirs. |
export BOARD |
|
$(SW_ROOT)/bootrom/bootrom.v: |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom bootrom.v |
|
clean: |
$(Q)rm -f *.o *.bin *.hex *.in *.dis *.v |
$(Q)$(MAKE) -C $(SW_ROOT)/bootrom clean |
|
/orpsocv2/boards/xilinx/atlys/sw/Makefile.inc
0,0 → 1,24
|
# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're |
# in the board's software root path is. |
|
# Root from the board's sw/ path |
PROJ_ROOT=../../../.. |
|
# Figure out actual path the common software directory |
SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw |
|
# Set the BOARD_PATH to point to the root of this board build |
BOARD=xilinx/atlys |
|
# Set RTL_VERILOG_INCLUDE_DIR so software |
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include |
|
# Set the processor capability flags |
MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float |
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float |
export MARCH_FLAGS |
|
# Finally include the main software include file |
|
include $(SW_ROOT)/Makefile.inc |
/orpsocv2/boards/xilinx/atlys/syn/xst/run/Makefile
0,0 → 1,2
include ../bin/Makefile |
|
/orpsocv2/boards/xilinx/atlys/syn/xst/bin/Makefile
0,0 → 1,179
###################################################################### |
#### #### |
#### ORPSoC Xilinx Synthesis Makefile #### |
#### #### |
#### Author(s): #### |
#### - Julius Baxter, julius@opencores.org #### |
#### #### |
#### #### |
###################################################################### |
#### #### |
#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG #### |
#### #### |
#### This source file may be used and distributed without #### |
#### restriction provided that this copyright statement is not #### |
#### removed from the file and that any derivative work contains #### |
#### the original copyright notice and the associated disclaimer. #### |
#### #### |
#### This source file is free software; you can redistribute it #### |
#### and/or modify it under the terms of the GNU Lesser General #### |
#### Public License as published by the Free Software Foundation; #### |
#### either version 2.1 of the License, or (at your option) any #### |
#### later version. #### |
#### #### |
#### This source is distributed in the hope that it will be #### |
#### useful, but WITHOUT ANY WARRANTY; without even the implied #### |
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #### |
#### PURPOSE. See the GNU Lesser General Public License for more #### |
#### details. #### |
#### #### |
#### You should have received a copy of the GNU Lesser General #### |
#### Public License along with this source; if not, download it #### |
#### from http://www.opencores.org/lgpl.shtml #### |
#### #### |
###################################################################### |
|
# Name of the directory we're currently in |
CUR_DIR=$(shell pwd) |
|
# We don't want the usbhostslave module to be pulled in during synthesis because |
# we haven't copied the headers to our RTL director |
#COMMON_VERILOG_MODULES_EXCLUDE+= usbhostslave |
|
|
# The root path of the board build |
BOARD_ROOT ?=$(CUR_DIR)/../../.. |
include $(BOARD_ROOT)/Makefile.inc |
|
RTL_TOP ?=$(DESIGN_NAME)_top |
|
SYN_RUN_DIR=$(BOARD_SYN_DIR)/run |
|
TIMESCALE_FILE=timescale.v |
SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE) |
$(SYNDIR_TIMESCALE_FILE): |
$(Q)echo "" > $@ |
|
SYN_VERILOG_DEFINES=synthesis-defines.v |
SYNDIR_SYN_VERILOG_DEFINES=$(SYN_RUN_DIR)/$(SYN_VERILOG_DEFINES) |
$(SYNDIR_SYN_VERILOG_DEFINES): |
$(Q)echo "\`define SYNTHESIS" > $@ |
$(Q)echo "\`define XILINX" >> $@ |
$(Q)echo "" >> $@ |
|
GENERATED_DEFINES = $(BOOTROM_VERILOG) |
GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE) |
GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES) |
|
|
FPGA_PART ?=xc6slx45-2-csg324 |
OPT_MODE ?=Speed |
OPT_LEVEL ?=2 |
|
ifeq ($(V), 1) |
XILINX_FLAGS ?= |
else |
XILINX_FLAGS ?=-intstyle silent |
endif |
|
XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 100000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5 |
|
XCF_FILE=$(DESIGN_NAME).xcf |
XST_FILE=$(DESIGN_NAME).xst |
PRJ_FILE=$(DESIGN_NAME).prj |
NGC_FILE=$(DESIGN_NAME).ngc |
NETLIST_FILE=$(DESIGN_NAME).v |
|
|
XST_PRJ_FILE_SRC_DECLARE=verilog work |
|
print-config: |
$(Q)echo; echo "\t### Synthesis make configuration ###"; echo |
$(Q)echo "\tFPGA_PART="$(FPGA_PART) |
$(Q)echo "\tOPT_MODE="$(OPT_MODE) |
$(Q)echo "\tOTP_LEVEL="$(OPT_LEVEL) |
$(Q)echo "\tXILINX_XST_FLAGS="$(XILINX_XST_FLAGS) |
$(Q)echo |
|
all: $(NGC_FILE) |
|
# Generate the .xst file |
# See this page for information on options: |
# http://www.xilinx.com/itp/xilinx4/data/docs/xst/command_line5.html |
$(XST_FILE): |
$(Q)echo; echo "\t#### Generating XST file ####"; echo |
$(Q)echo "# XST Script for ORPSoC Synthesis" > $@ |
$(Q)echo "# This file is autogenerated - any changes will be overwritten" >> $@ |
$(Q)echo "# See the Makefile in syn/xst/bin to make changes" >> $@ |
$(Q)echo "run" >> $@ |
$(Q)echo "-ifn "$(PRJ_FILE) >> $@ |
$(Q)echo "-ifmt mixed" >> $@ |
$(Q)echo "-top "$(RTL_TOP) >> $@ |
$(Q)echo "-ofmt NGC" >> $@ |
$(Q)echo "-ofn "$(NGC_FILE) >> $@ |
$(Q)echo "-p "$(FPGA_PART) >> $@ |
$(Q)echo "-opt_level "$(OPT_LEVEL) >> $@ |
$(Q)echo "-opt_mode "$(OPT_MODE) >> $@ |
$(Q)echo "-uc "$(XCF_FILE) >> $@ |
# $(Q)echo "elaborate " >> $@ |
# $(Q)echo -n "-vlgpath \"" >> $@ |
# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \ |
echo -n $$vlogpath" "; done >> $@ |
# $(Q)echo "\"" >> $@ |
# Give board then common verilog include paths, hoping xst does a sensible thing |
# and searches them in order. |
$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(COMMON_RTL_VERILOG_DIR)/include" "$(BOOTROM_SW_DIR) " }" >> $@ |
$(Q)echo >> $@ |
|
# Generate Xilinx project (.prj) file |
$(PRJ_FILE): $(RTL_VERILOG_SRC) |
$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####"; |
# $(Q)echo "# Autogenerated XST .prj file" > $@ |
# $(Q)echo "# Any changes will be written over." >> $@ |
$(Q)for file in $(RTL_VERILOG_SRC); do \ |
echo $(XST_PRJ_FILE_SRC_DECLARE) $$file >> $@ ; \ |
done |
$(Q)echo >> $@ |
$(Q)echo |
|
# Constraints file |
$(XCF_FILE): |
$(Q)echo; echo "\t#### Generating Xilinx XCF file ####"; echo |
$(Q)echo "# Autogenerated XST .prj file" > $@ |
$(Q)echo "#" >> $@ |
$(Q)echo "# Not much here, XST is smart enough to determine clocks through DCMs" >> $@ |
$(Q)echo "#" >> $@ |
$(Q)echo "# 100 MHz user clock" >> $@ |
$(Q)echo "NET \"sys_clk_in\" TNM_NET = \"sys_clk_in_grp\";" >> $@ |
$(Q)echo "TIMESPEC \"TS_sys_clk_in\" = PERIOD \"sys_clk_in_grp\" 10 ns HIGH 50%;" >> $@ |
$(Q)echo "# Ignore the reset logic" >> $@ |
$(Q)echo "NET rst_n_pad_i* TIG;" >> $@ |
$(Q)echo "# Define the two clock domains as timespecs" >> $@ |
$(Q)echo "#NET dcm0_clkdv TNM_NET=\"wb_clk\";" >> $@ |
$(Q)echo "#TIMESPEC \"TS_wb_clk\" = PERIOD \"wb_clk\" 20 ns HIGH 10;" >> $@ |
|
# XST command |
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES) |
$(Q)echo; echo "\t#### Running XST ####"; echo; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS) ) |
$(Q)echo |
|
netlist: $(NETLIST_FILE) |
|
# Netlist generation command |
$(NETLIST_FILE): $(NGC_FILE) |
$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo; |
$(Q)(. $(XILINX_SETTINGS_SCRIPT) ; \ |
netgen -sim -aka -dir . -ofmt verilog $< -w $@ ) |
|
|
clean: |
$(Q)rm -rf *.* xst |
|
clean-sw: |
$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean |
|
distclean: clean-sw clean |
|
|
.PRECIOUS : $(NGC_FILE) $(XST_FILE) $(XCF_FILE) |