OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc
    from Rev 40 to Rev 41
    Reverse comparison

Rev 40 → Rev 41

/trunk/orpsocv2/rtl/verilog/components/or1k_top/or1k_top.v
96,9 → 96,8
wire debug_tdi_o;
 
//-------------------------------------------------------
//BA12 BSEMI RISC Architecture 1 32-bit processor
//OR1200 other RISC Architecture 1 32-bit processor
//-------------------------------------------------------
wire boot_devsel_i;
//Debug interface
wire dbg_stall_i;
wire dbg_bp_o;
116,11 → 115,11
assign dwb_stb_o = (dwb_cyc_o == 1'b1) ? dwb_stb_o_tmp : 1'b0;
 
 
`ifdef USE_OR1200 // use OR1200 processor IP
`ifndef USE_OR1200_OTHER // use OR1200r2 processor IP
 
//=============================================================================
//
// OR1200 RISC Architecture 32-bit processor instantation
// OR1200r2 RISC Architecture 32-bit processor instantation
//
//=============================================================================
or1200_top i_or1200_top(
191,15 → 190,14
.pm_lvolt_o ( )
);
 
`else // use BA12 processor IP
`else // use other OR1200 version processor IP
 
assign boot_devsel_i = 1'b0;
//=============================================================================
//
// RISC Architecture 1 32-bit processor instantation
// OR1200 other RISC Architecture 32-bit processor instantation
//
//=============================================================================
ba12_top #(32 /* dw */, 32 /* aw */, 31 /* ppic_ints */) i_ba12_top(
or1200_other_top i_or1200_top(
// System
.clk_i ( clk_i ),
.rst_i ( rst_i ),
254,9 → 252,6
.dbg_dat_i ( cpu0_data_o2 ),
.dbg_ack_o ( dbg_ack_o ),
 
// SR register input
.boot_devsel_i ( boot_devsel_i ),
 
// Power Management
.pm_cpustall_i ( 1'b0 ),
.pm_clksd_o ( ),
/trunk/orpsocv2/rtl/verilog/components/or1k_top/or1k_top.h
1,3 → 1,2
// to use or1200 define
// to use ba12 undefine
`define USE_OR1200
// to use or1200r2 do NOT define the following, otherwise, to use the alternate processor, uncomment the following
//`define USE_OR1200_OTHER

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.