URL
https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk
Subversion Repositories openrisc_me
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc
- from Rev 418 to Rev 419
- ↔ Reverse comparison
Rev 418 → Rev 419
/trunk/bootloaders/orpmon/mc.h
File deleted
trunk/bootloaders/orpmon/mc.h
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: trunk/bootloaders/orpmon/include/int.h
===================================================================
--- trunk/bootloaders/orpmon/include/int.h (revision 418)
+++ trunk/bootloaders/orpmon/include/int.h (revision 419)
@@ -20,4 +20,4 @@
int int_enable(unsigned long vect);
/* Error vector handler */
-void int_error(int vect);
+void int_error(int vect, unsigned long epcr);
/trunk/bootloaders/orpmon/include/build.h
1,?rev1len? → 0,?rev2len?
#define BUILD_VERSION "Tue Nov 2 22:26:31 CET 2010" |
#define BUILD_VERSION "Thu Nov 11 12:46:20 CET 2010" |
/trunk/bootloaders/orpmon/include/board.h
13,6 → 13,7
* 1 - marvin |
* 2 - ORSoC A3PE1500 board |
* 3 - ORSoC A3P1000 board |
* 4 - ML501 |
*/ |
#define BOARD 2 |
|
65,7 → 66,7
# define FLASH_ORG_16_2 1 |
# define BOARD_DEF_NAME "ORSoC devboard" |
#elif BOARD==3 |
//ORSoC A3P1000 usbethdev board |
//ORSoC ordb1a3p1000 |
|
# define FLASH_BASE_ADDR 0xf0000000 |
# define FLASH_SIZE 0x04000000 |
78,6 → 79,20
# define FLASH_ORG_16_2 1 |
# define BOARD_DEF_NAME "ORSoC A3P1000 devboard" |
|
#elif BOARD==4 |
//Xilinx ML501 |
|
# define FLASH_BASE_ADDR 0xf0000000 |
# define FLASH_SIZE 0x04000000 |
# define FLASH_BLOCK_SIZE 0x00040000 |
# define START_ADD 0x0 |
# define SDRAM_SIZE 0x10000000 |
# define SDRAM_ROW_SIZE 0x00000400 |
# define SDRAM_BANK_SIZE 0x00800000 |
# define IN_CLK 50000000 |
# define FLASH_ORG_16_2 1 |
# define BOARD_DEF_NAME "Xilinx ML501" |
|
#else |
//Custom Board |
|
128,7 → 143,7
#elif IPCONFIG==2 |
|
#define BOARD_DEF_IP 0xac1e0002 // 172.30.0.2 |
#define BOARD_DEF_MASK 0xffffff00 // 255.255.255.0 |
#define BOARD_DEF_MASK 0xffff0000 // 255.255.0.0 |
#define BOARD_DEF_GW 0xac1e0001 //"172.30.0.1" |
#define BOARD_DEF_TBOOT_SRVR 0xac1e0001 //"172.30.0.1" |
#define BOARD_DEF_IMAGE_NAME "boot.img" |
/trunk/bootloaders/orpmon/reset.S
1,7 → 1,11
#include "spr-defs.h" |
#include "board.h" |
#include "mc.h" |
|
#define TRAP_ON_ERROR 0 |
#define LOOP_ON_ERROR 0 |
#define EXIT_NOP_ON_ERROR 1 |
#define PRINT_AND_RESET_ON_ERROR 1 |
|
.extern _src_beg |
.extern _dst_beg |
.extern _dst_end |
10,7 → 14,6
.extern tick_interrupt |
.extern _crc32 |
|
.global _align |
.global _calc_mycrc32 |
.global _mycrc32 |
.global _mysize |
58,12 → 61,6
.endif |
|
_reset: |
.if IN_FLASH |
l.movhi r3,hi(MC_BASE_ADDR) |
l.ori r3,r3,MC_BA_MASK |
l.addi r5,r0,0x00 |
l.sw 0(r3),r5 |
.endif |
l.movhi r0, 0 |
/* Clear status register, set supervisor mode */ |
l.ori r1, r0, SPR_SR_SM |
83,18 → 80,22
.org (0x200 - 0x100 + _reset) |
.endif |
_buserr: |
.if 0 |
.if TRAP_ON_ERROR |
/* Just trap */ |
l.trap 0 |
.endif |
.if 0 |
.if EXIT_NOP_ON_ERROR |
l.nop 0x1 |
.endif |
.if LOOP_ON_ERROR |
l.j 0 |
l.nop |
.endif |
l.j _int_error |
l.ori r3, r0, 0x2 |
|
.if PRINT_AND_RESET_ON_ERROR |
l.mfspr r4, r0, SPR_EPCR_BASE |
l.j _int_error /* This will reset */ |
l.ori r3, r0, 0x2 |
.endif |
.if IN_FLASH |
.section .vectors, "ax" |
.org 0x500 |
105,7 → 106,7
#define TIMER_RELOAD_VALUE (SPR_TTMR_IE | SPR_TTMR_RT | ((IN_CLK/TICKS_PER_SEC) & SPR_TTMR_PERIOD)) |
/* Simply load timer_ticks variable and increment */ |
.extern _timer_ticks |
l.addi r1, r1, -8 |
l.addi r1, r1, -136 /* 128 + what we need (8),avoid area used by gcc*/ |
l.sw 0(r1), r25 |
l.sw 4(r1), r26 |
l.movhi r25, hi(timestamp) |
118,7 → 119,7
l.mtspr r0, r25, SPR_TTMR /* Reset timer */ |
l.lwz r25, 0(r1) |
l.lwz r26, 4(r1) |
l.addi r1, r1, 8 |
l.addi r1, r1, 136 |
l.rfe |
|
.if IN_FLASH |
128,16 → 129,22
.org (0x600 - 0x100 + _reset) |
.endif |
_alignerr: |
.if 0 |
.if TRAP_ON_ERROR |
/* Just trap */ |
l.trap 0 |
.endif |
.if 0 |
.if EXIT_NOP_ON_ERROR |
l.nop 0x1 |
.endif |
.if LOOP_ON_ERROR |
l.j 0 |
l.nop |
.endif |
l.j _int_error |
.if PRINT_AND_RESET_ON_ERROR |
l.mfspr r4, r0, SPR_EPCR_BASE |
l.j _int_error /* This will reset */ |
l.ori r3, r0, 0x6 |
.endif |
|
.if IN_FLASH |
.org 0x700 |
145,18 → 152,22
.org (0x700 - 0x100 + _reset) |
.endif |
_illinsn: |
.if 0 |
/* Just trap */ |
.if TRAP_ON_ERROR |
/* Just trap */ |
l.trap 0 |
.endif |
.if 0 |
.if EXIT_NOP_ON_ERROR |
l.nop 0x1 |
.endif |
.if LOOP_ON_ERROR |
l.j 0 |
l.nop |
.endif |
l.j _int_error |
.if PRINT_AND_RESET_ON_ERROR |
l.mfspr r4, r0, SPR_EPCR_BASE |
l.j _int_error /* This will reset */ |
l.ori r3, r0, 0x7 |
|
.endif |
.if IN_FLASH |
.org 0x800 |
.else |
163,9 → 174,9
.org (0x800 - 0x100 + _reset) |
.endif |
_userint: |
l.addi r1,r1,-128 |
l.addi r1,r1,-256 /*(128 + 128) */ |
l.sw 0x0(r1),r2 |
l.addi r2, r1, 128 |
l.addi r2, r1, 256 |
l.sw 0x4(r1), r3 |
l.movhi r3,hi(_int_wrapper) |
l.ori r3,r3,lo(_int_wrapper) |
174,16 → 185,6
|
.section .text |
_start: |
.if IN_FLASH |
/* l.jal _init_mc |
l.nop |
*/ |
/* Wait for SDRAM */ |
l.addi r3,r0,0x1000 |
1: l.sfeqi r3,0 |
l.bnf 1b |
l.addi r3,r3,-1 |
.endif |
/* Copy form flash to sram */ |
.if IN_FLASH |
l.movhi r3,hi(_src_beg) |
333,7 → 334,6
l.ori r1,r1,lo(_stack-4) |
l.addi r2,r0,-3 |
l.and r1,r1,r2 |
/* l.or r2, r1, r1 - remove this helped with odd UART output problem?!*/ |
|
l.movhi r3,hi(main) |
l.ori r3,r3,lo(main) |
407,218 → 407,11
l.lwz r31,0x74(r1) |
|
l.lwz r2, 0x0(r1) |
l.addi r1,r1,128 |
l.addi r1,r1,256 |
l.rfe |
l.nop |
|
|
_align: |
l.sw 0x0c(r1),r3 |
l.sw 0x10(r1),r4 |
l.sw 0x14(r1),r5 |
l.sw 0x18(r1),r6 |
l.sw 0x1c(r1),r7 |
l.sw 0x20(r1),r8 |
l.sw 0x24(r1),r9 |
l.sw 0x28(r1),r10 |
l.sw 0x2c(r1),r11 |
l.sw 0x30(r1),r12 |
l.sw 0x34(r1),r13 |
l.sw 0x38(r1),r14 |
l.sw 0x3c(r1),r15 |
l.sw 0x40(r1),r16 |
l.sw 0x44(r1),r17 |
l.sw 0x48(r1),r18 |
l.sw 0x4c(r1),r19 |
l.sw 0x50(r1),r20 |
l.sw 0x54(r1),r21 |
l.sw 0x58(r1),r22 |
l.sw 0x5c(r1),r23 |
l.sw 0x60(r1),r24 |
l.sw 0x64(r1),r25 |
l.sw 0x68(r1),r26 |
l.sw 0x6c(r1),r27 |
l.sw 0x70(r1),r28 |
l.sw 0x74(r1),r29 |
l.sw 0x78(r1),r30 |
l.sw 0x7c(r1),r31 |
|
l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */ |
l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */ |
|
l.lwz r3,0(r5) /* Load insn */ |
l.srli r4,r3,26 /* Shift left to get the insn opcode */ |
|
l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */ |
l.bf jmp |
l.sfeqi r4,0x01 |
l.bf jmp |
l.sfeqi r4,0x03 |
l.bf jmp |
l.sfeqi r4,0x04 |
l.bf jmp |
l.sfeqi r4,0x11 |
l.bf jr |
l.sfeqi r4,0x12 |
l.bf jr |
l.nop |
l.j 1f |
l.addi r5,r5,4 /* Increment PC to get return insn address */ |
|
jmp: |
l.slli r4,r3,6 /* Get the signed extended jump length */ |
l.srai r4,r4,4 |
|
l.lwz r3,4(r5) /* Load the real load/store insn */ |
|
l.add r5,r5,r4 /* Calculate jump target address */ |
|
l.j 1f |
l.srli r4,r3,26 /* Shift left to get the insn opcode */ |
|
jr: |
l.slli r4,r3,9 /* Shift to get the reg nb */ |
l.andi r4,r4,0x7c |
|
l.lwz r3,4(r5) /* Load the real load/store insn */ |
|
l.add r4,r4,r1 /* Load the jump register value from the stack */ |
l.lwz r5,0(r4) |
|
l.srli r4,r3,26 /* Shift left to get the insn opcode */ |
|
|
1: l.mtspr r0,r5,SPR_EPCR_BASE |
|
l.sfeqi r4,0x26 |
l.bf lhs |
l.sfeqi r4,0x25 |
l.bf lhz |
l.sfeqi r4,0x22 |
l.bf lws |
l.sfeqi r4,0x21 |
l.bf lwz |
l.sfeqi r4,0x37 |
l.bf sh |
l.sfeqi r4,0x35 |
l.bf sw |
l.nop |
|
1: l.j 1b /* I don't know what to do */ |
l.nop |
|
lhs: l.lbs r5,0(r2) |
l.slli r5,r5,8 |
l.lbz r6,1(r2) |
l.or r5,r5,r6 |
l.srli r4,r3,19 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.j align_end |
l.sw 0(r4),r5 |
|
lhz: l.lbz r5,0(r2) |
l.slli r5,r5,8 |
l.lbz r6,1(r2) |
l.or r5,r5,r6 |
l.srli r4,r3,19 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.j align_end |
l.sw 0(r4),r5 |
|
lws: l.lbs r5,0(r2) |
l.slli r5,r5,24 |
l.lbz r6,1(r2) |
l.slli r6,r6,16 |
l.or r5,r5,r6 |
l.lbz r6,2(r2) |
l.slli r6,r6,8 |
l.or r5,r5,r6 |
l.lbz r6,3(r2) |
l.or r5,r5,r6 |
l.srli r4,r3,19 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.j align_end |
l.sw 0(r4),r5 |
|
lwz: l.lbz r5,0(r2) |
l.slli r5,r5,24 |
l.lbz r6,1(r2) |
l.slli r6,r6,16 |
l.or r5,r5,r6 |
l.lbz r6,2(r2) |
l.slli r6,r6,8 |
l.or r5,r5,r6 |
l.lbz r6,3(r2) |
l.or r5,r5,r6 |
l.srli r4,r3,19 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.j align_end |
l.sw 0(r4),r5 |
|
sh: |
l.srli r4,r3,9 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.lwz r5,0(r4) |
l.sb 1(r2),r5 |
l.srli r5,r5,8 |
l.j align_end |
l.sb 0(r2),r5 |
|
sw: |
l.srli r4,r3,9 |
l.andi r4,r4,0x7c |
l.add r4,r4,r1 |
l.lwz r5,0(r4) |
l.sb 3(r2),r5 |
l.srli r5,r5,8 |
l.sb 2(r2),r5 |
l.srli r5,r5,8 |
l.sb 1(r2),r5 |
l.srli r5,r5,8 |
l.j align_end |
l.sb 0(r2),r5 |
|
align_end: |
l.lwz r2,0x08(r1) |
l.lwz r3,0x0c(r1) |
l.lwz r4,0x10(r1) |
l.lwz r5,0x14(r1) |
l.lwz r6,0x18(r1) |
l.lwz r7,0x1c(r1) |
l.lwz r8,0x20(r1) |
l.lwz r9,0x24(r1) |
l.lwz r10,0x28(r1) |
l.lwz r11,0x2c(r1) |
l.lwz r12,0x30(r1) |
l.lwz r13,0x34(r1) |
l.lwz r14,0x38(r1) |
l.lwz r15,0x3c(r1) |
l.lwz r16,0x40(r1) |
l.lwz r17,0x44(r1) |
l.lwz r18,0x48(r1) |
l.lwz r19,0x4c(r1) |
l.lwz r20,0x50(r1) |
l.lwz r21,0x54(r1) |
l.lwz r22,0x58(r1) |
l.lwz r23,0x5c(r1) |
l.lwz r24,0x60(r1) |
l.lwz r25,0x64(r1) |
l.lwz r26,0x68(r1) |
l.lwz r27,0x6c(r1) |
l.lwz r28,0x70(r1) |
l.lwz r29,0x74(r1) |
l.lwz r30,0x78(r1) |
l.mfspr r31,r0,0x40 |
l.lwz r31,0x7c(r1) |
l.addi r1,r1,128 |
l.rfe |
|
|
/* Jump to error function. Clobber r2 */ |
_int_error: |
l.movhi r2,hi(int_error) |
/trunk/bootloaders/orpmon/sim.cfg
118,9 → 118,11
section memory |
/*random_seed = 12345 |
type = random*/ |
pattern = 0x00 |
type = unknown /* Fastest */ |
/*pattern = 0x00 |
type = unknown */ |
|
type = exitnops |
|
name = "RAM" |
ce = 1 |
mc = 0 |
/trunk/bootloaders/orpmon/config.mk
25,11 → 25,17
|
XCFLAGS += -I$(TOPDIR)/include -DOR1K -Wall -Wstrict-prototypes |
XCFLAGS += -Werror-implicit-function-declaration |
#XCFLAGS += -fno-omit-frame-pointer -g |
XCFLAGS += -fno-strength-reduce -O2 -pipe -fno-builtin -fomit-frame-pointer |
XCFLAGS += -fno-omit-frame-pointer |
#XCFLAGS += -fomit-frame-pointer |
#XCFLAGS += -O0 |
XCFLAGS += -O2 |
#XCFLAGS += -O3 |
#XCFLAGS += -Os |
XCFLAGS += -fno-strength-reduce -pipe -fno-builtin |
# Use all software flags, so is compatible with minimal implementation |
#XCFLAGS += -mhard-mul -mhard-div -msoft-float |
XCFLAGS += -msoft-mul -msoft-div -msoft-float |
XCFLAGS += -mhard-mul -msoft-div -msoft-float |
#XCFLAGS += -msoft-mul -msoft-div -msoft-float |
XCFLAGS += -nostdlib |
#XCFLAGS += -DDEBUG |
|
/trunk/bootloaders/orpmon/ram.ld
5,15 → 5,16
vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000 |
/* Use all RAM */ |
/* Put all sections into ram */ |
/* |
|
ram : ORIGIN = 0x00002000, LENGTH = 0x02000000 - 0x00002000 |
*/ |
|
/* Uncomment the following to work around bad pages in a flash mem */ |
/* Put all sections except data, rodata into ram2 */ |
/* On ORSoC dev board devices, for pages 132-134 (256Byte pages) */ |
/* |
ram : ORIGIN = 0x00001200, LENGTH = 0x8400 - 0x1200 |
ram2 : ORIGIN = 0x8700, LENGTH = 0x02000000 - 0x8700 |
|
*/ |
/* Uncomment the following to work around bad pages in a flash mem */ |
/* Put all sections except data, rodata into ram2 */ |
/* On ORSoC dev board devices, for pages 180-182 (256Byte pages) */ |
39,7 → 40,8
_text_begin = .; |
*(.text) |
_text_end = .; |
} > ram2 |
} > ram |
/* } > ram2*/ |
|
.data : |
/* AT ( ADDR (.text) + SIZEOF(.text) + SIZEOF(.mytext))*/ |
56,13 → 58,15
.bss : |
{ |
*(.bss) |
} > ram2 |
} > ram |
/* } > ram2 */ |
|
.stack : |
{ |
*(.stack) |
_src_addr = .; |
} > ram2 |
} > ram |
/* } > ram2 */ |
/* |
.monitor : |
{ |
/trunk/bootloaders/orpmon/drivers/int.c
75,7 → 75,7
|
|
void |
int_error(int vect) |
int_error(int vect, unsigned long epcr) |
{ |
printf("\n\nERROR - "); |
switch(vect) |
94,6 → 94,8
break; |
} |
|
printf("EPCR: 0x%.8x\n",epcr); |
|
printf("\n"); |
|
// TODO - print some more diagnostics here |