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URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

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  • This comparison shows the changes necessary to convert path 
    /openrisc
    from Rev 424 to Rev 425
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  •

Rev 424 → Rev 425

/trunk/orpsocv2/bench/sysc/src/GdbServerSC.cpp
962,8 → 962,15
void
GdbServerSC::rspQuery ()
{
if (0 == strcmp ("qC", pkt->data))
if (0 == strcmp ("qAttached", pkt->data))
{
// We are always attaching to an existing process with the bare metal
// embedded system.
pkt->packStr ("1");
rsp->putPkt (pkt);
}
else if (0 == strcmp ("qC", pkt->data))
{
// Return the current thread ID (unsigned hex). A null response
// indicates to use the previously selected thread. We use the constant
// OR1KSIM_TID to represent our single thread of control.
1053,6 → 1060,12
pkt->setLen (strlen (pkt->data));
rsp->putPkt (pkt);
}
else if (0 == strncmp ("qTStatus", pkt->data, strlen ("qTstatus")))
{
// We don't support tracing, return empty packet
pkt->packStr ("");
rsp->putPkt (pkt);
}
else if (0 == strncmp ("qXfer:", pkt->data, strlen ("qXfer:")))
{
// For now we support no 'qXfer' requests, but these should not be
/trunk/orpsocv2/bench/verilog/vpi/c/gdb.c
2804,8 → 2804,14
static void
rsp_query (struct rsp_buf *p_buf)
{
if (0 == strcmp ("qC", p_buf->data))
if (0 == strcmp ("qAttached", p_buf->data))
{
/* We are always attaching to an existing process with the bare metal
embedded system. */
put_str_packet ("1");
}
else if (0 == strcmp ("qC", p_buf->data))
{
/* Return the current thread ID (unsigned hex). A null response
indicates to use the previously selected thread. Since we do not
support a thread concept, this is the appropriate response. */
2884,6 → 2890,11
p_buf->len = strlen (p_buf->data);
put_packet (p_buf);
}
else if (0 == strncmp ("qTStatus", p_buf->data, strlen ("qTStatus")))
{
/* We don't support tracing, so return empty packet. */
put_str_packet ("");
}
else if (0 == strncmp ("qXfer:", p_buf->data, strlen ("qXfer:")))
{
/* For now we support no 'qXfer' requests, but these should not be
/trunk/orpsocv2/doc/orpsoc.texi
71,11 → 71,11
 
@cindex introduction to this @value{ORPSOC}
 
@value{ORPSOC} is intended to be a reference implementation of processors in the OpenRISC family. It provides a smallest-possible reference system, primarily for testing of the processors, and systems intended to be synthesized and run on physical hardware (boards.) The simple reference system contains just enough to test the processor's functionality, whereas the board targeted builds will include many additional peripherals.
@value{ORPSOC} is intended to be a reference implementation of processors in the OpenRISC family. It provides a smallest-possible reference system, primarily for testing of the processors. It also provides systems intended to be synthesized and run on physical hardware.
 
The reference design will contain a minimal set of resources to create an OpenRISC-based SoC. It is expected the board builds will contain their own set of peripheral modules and software, and still draw upon the resources available in the reference implementation. It is hoped that, with this structure, the project can serve dual roles; to be a development platform for OpenRISC family processors, and to provide a platform for development of complex OpenRISC-based systems on chip.
The reference system is the least complex implementation and consists of just enough to test the processor's functionality. The board-targeted builds include many additional peripherals.
 
This document, the user guide, focuses on getting the various designs in @value{ORPSOC} up and running. For matters relating to development of a board port, see the development guide included with this documentation.
The next section in this document outlines the organisation and structure of the project. The section ``@emph{Getting Started}'' goes through getting the project source and setting up any necessary tools. Each following section outlines a particular implementation of an OpenRISC-based system, beginning with the reference system. Each implementation section has an overview of the structure of the project (which probably won't vary much between the implementations), a section on setting up the required tools, running simulation, and if applicable, backend and debugging steps. There may be additional sections on modifying or customising each implementation system.
 
@c ****************************************************************************
@c Project Organisation
96,38 → 96,56
@node Organisation Overview
@section Organisation Overview
 
The @value{ORPSOC} project is intended for dual uses. One is to act as a development platform for OpenRISC processors, as well as development of complex OpenRISC-based SoCs. Organising a single project to satisfy these requirements can lead to some confusion. This section is intended to make the organisation of the project clear.
The @value{ORPSOC} project is intended to serve dual purposes. One is to act as a development platform for OpenRISC processors, and as a development platform of OpenRISC-based SoCs targeted at specific hardware.
 
In essence, the reference implementation based in the root of the project contains enough to get a simple OpenRISC-based SoC together, the board builds are intended to implement fully-featured systems. The project is organised in such a way that the board builds can use both the reference implementation's RTL and software, as well as its own set of RTL and software. The reference implementation, however, cannot use any board's modules, software or scripts.
Organising a single project to satisfy these requirements can lead to some confusion. This section is intended to make the organisation of the project clear.
 
The reference implementation based in the root (base directory) of the project contains enough componenets to create a simple OpenRISC-based SoC. Each board build is intended to implement as fully-featured a system as possible, depending on the targeted hardware.
 
The project is organised in such a way that each board build can use both the reference implementation's RTL modules and software, as well as its own set of RTL and software. The reference implementation is limited to what is available in the RTL and software directories in the root of the project, and is not technology dependent.
 
The following sections outline the organisation of the software, RTL, and board designs.
 
@node Software Organisation
@section Software
 
The @code{sw} path contains primarily target software (code intended for cross-compilation and execution on an OpenRISC processor) and a few custom tools for manipulation of binary software images.
The @code{sw} path contains primarily target software (code intended for cross-compilation and execution on an OpenRISC processor.) Thre is also a path, @code{sw/utils} containing custom tools, intended to be run on the host, for manipulation of binary software images.
 
Driver software, implementing access functions for hardware modules, are found under @code{sw/drivers}. There is the concept of a CPU library, providing CPU-specific functions, which can be changed to support different versions of OpenRISC processors. There is also a minimal support library under the @code{sw/lib} path. Both drivers and support library are compiled together to create a library called @code{liborpsoc} which is placed in @code{sw/lib}.
Driver software, implementing access functions for hardware modules, are found under @code{sw/drivers}.
 
There is a minimal support library under the @code{sw/lib} path. Both drivers and support library are compiled together to create a library called @code{liborpsoc} which is placed in @code{sw/lib}.
 
All CPU-related functions are made available through the file @code{cpu-utils.h} which is located in @code{sw/lib/include} and depending on the CPU being used, can be used to switch between different CPU driver functions. All CPU drivers are under the @code{sw/drivers} path.
 
Test software is found under @code{sw/tests}. Typically, each is for a specific module, or for a particular capability (eg. tests for the UART capability are under @code{sw/tests/uart}, rather than @code{sw/tests/uart16550} which.) There are no specific rules here.
 
Under each test directory are two directories, @code{board} and @code{sim}, containing the test software targeted at each. Code for simulation will produce less printfs and perhaps not run as long as tests intended to run at full speed on target.
Under each test directory are two directories, @code{board} and @code{sim}, containing appropriate test software. Code for simulation will produce less printfs and aim to execute within realistic timeframes for RTL simulation. Board targeted test software is obviously written with the opposite considerations in mind.
 
There are for naming software tests, so the automation scripts can locate them. The test directory name must be a single word (potentially with underscores), and then the tests must be in files of the format @emph{testdirname}-@emph{testname}.extension, eg. @code{uart-simple.c} or @code{or1200-fp.S}.
@node Software Test Naming
 
The rules for naming software tests are important to adhere to, so the automation scripts can locate them. The test directory name must be a single word (potentially with underscores), and then the tests must be in files of the format @emph{testdirname}-@emph{testname}.extension, eg. @code{uart-simple.c} or @code{or1200-fp.S}.
 
@node RTL Organisation
@section RTL
 
The HDL code layout conforms to those outlined in the OpenCores.org coding guidelines. http://cdn.opencores.org/downloads/opencores_coding_guidelines.pdf
 
Beyond that, there are some rules for the naming in modules. The directory name (presumably the name of the module, something like @code{uart16550}) should also be the name of the top level file, eg. @code{uart16550.v}, and the top level module should also be simply this name, eg. @code{module uart16550 (...}.
There are, however, some naming restrictions for this project.
 
The directory name (presumably the name of the module, something like @code{uart16550}) should also be the name of the top level file, eg. @code{uart16550.v}, and the top level module should also be simply this name, eg. @code{module uart16550 (...}.
 
This will avoid confusion and help the scripts locate modules.
 
@subsection Verilog HDL
 
All RTL included in the project at this point is Verilog HDL, although it would be fine to add VHDL to a board build.
 
@node Testbench Organisation
@section Testbench
 
For each design in @value{ORPSOC} there will be a testbench instantiating the top level, and any peripherals (at least, as many as there are models for.)
For each design in @value{ORPSOC} there will be a testbench instantiating the top level, and any required peripherals.
 
Despite this being far from a thorough verification platform, it is considered useful to be able to perform enough simulation to ensure that the fundamental system is correctly assembled and can communicate with the peripherals. However, this is not intended as a platform for peripheral development (although, it very well could be) the board designs are not expected to have thorough peripheral tests. They are expected to have just enough to prove that basic functionality.
Despite this being far from a thorough verification platform, it is considered useful to be able to perform enough simulation to ensure that the fundamental system is correctly assembled and can communicate with the peripherals.
 
@node Organisation of Reference And Board Designs
@section Reference And Board Designs
134,10 → 152,16
 
The goal of the reference design is to provide an environment to develop and test OpenRISC processors (also, potentially, basic components.) The goal of the various board-targeted designs is to provide ready-to-go implementations for hardware.
 
Typically, a board-targeted design will wish to reuse common components (processor, debug interface, Wishbone arbiters, UART etc.) The project has been configured to allow a board build to use either modules available in the ``common'' RTL path (@code{rtl/verilog/}) as well as those in their ``local'' RTL path (something like @code{boards/vendor/boardname/rtl/verilog}). In the event that some particular modification to a module in the common RTL set is desired for a particular board build, that module can simply be copied into the board's ``local'' RTL path and the scripts will that version instead of the common one.
@subsection Module Selection
 
Typically, a board-targeted design will wish to reuse common components (processor, debug interface, Wishbone arbiters, UART etc.)
 
The project has been configured so a board build will use modules in the ``common'' RTL path (@code{rtl/verilog/}) @emph{unless} there is a copy in the board's ``local'' RTL path ( @code{boards/vendor/boardname/rtl/verilog}).
 
For example, in the event that modification to a module in the common RTL set is required for it to function correctly in a board build, it's advisable to copy that module to the board's @emph{local} RTL path and modify it there. Simulation and backend scripts should then use this board-specific version instead of the one in the common RTL path.
 
 
 
@c ****************************************************************************
@c Getting started
@c ****************************************************************************
153,14 → 177,13
@end menu
 
@node Getting Started Supported Platforms
@section Supported Platforms
@cindex platforms supported by the @value{ORPSOC} project
@section Supported Host Platforms
@cindex host platforms supported by the @value{ORPSOC} project
 
At present the majority of @value{ORPSOC}'s development occurs with tools that run under the GNU/Linux operating system. All of the tools required to run the basic implementation are free, open source, and easily installable in any modern GNU/Linux distribution.
 
Unless indicated otherwise, support for the project under Cygwin on Microsoft Windows platforms is not a given.
Unless indicated otherwise, support for the project under Cygwin on Microsoft Windows platforms cannot be assumed.
 
 
@node Getting Started Obtaining Project Source
@section Obtaining Project Source
@cindex getting a copy of the @value{ORPSOC} project
223,7 → 246,7
@node Reference Design Overview
@subsection Overview
 
The reference design included in @value{ORPSOC} is intended to be the minimal implementation (or thereabouts) of a SoC required to exercise an OpenRISC processor. In this regard, very little apart from the processor, memory, debug interface and interconnect modules are instantiated.
The reference design included in @value{ORPSOC} is intended to be the minimal implementation (or thereabouts) of a SoC required to exercise an OpenRISC processor. Very little apart from the processor, memory, debug interface and interconnect modules are instantiated.
 
The primary role for this design is to implement a system that an OpenRISC processor can be instantiated in for for development purposes. The automated testing mechanism, capable of compiling, executing and checking software on the design, is used as a method of regression testing for the processor as it is developed. After features are added or modified in the processor, new software tests can be added to the existing suite, checking for the expected functionality and ensuring legacy behavior is also unchanged.
 
604,7 → 627,7
@kbd{make rtl-tests}
@end example
 
The same set of options for RTL tests available in the reference design should available in this build. @xref{Running A Set Of Specific Reference Design RTL Tests}.
The same set of options for RTL tests available in the reference design should be available in this build. @xref{Running A Set Of Specific Reference Design RTL Tests}.
 
Options specific to the ORDB1A3PE1500 build.
 
940,6 → 963,9
 
Backend files, mainly binary NGC files for mapping, are found in the board's @code{backend/bin} path.
 
@node ML501 XILINX_PATH
@subsubsection ML501 XILINX_PATH
 
Be sure to set the environment variable @code{XILINX_PATH} to the path of the ISE path on the host machine. This can be done with something like @kbd{export XILINX_PATH=/software/xilinx_11.1/ISE} and additionally a symbolic link to the Verilog simulation library sources will be required - see the simulation section on this. Note that it helps to add the @code{XILINX_PATH} variable to the user's @code{.bashrc} script or similar to save setting it each time a new shell is opened.
 
If the @code{XILINX_PATH} variable is not set correctly, the makefiles will not run.
988,21 → 1014,10
@subsection Simulating
@cindex simulating ML501
 
@node ML501 Xilinx Source Directory
@subsubsection Setup Link To Xilinx Simulation Library Directory
Ensure the @code{XILINX_PATH} environment variable is set correcetly. @xref{ML501 XILINX_PATH} for information.
 
The Xilinx simulation library is too big to include in this project, and is installed with ISE, which is required to run this project. The simplest way to get access to it is to create a @emph{symbolic link} to it.
Note that if this path is not set, simulations will not compile.
 
A link must be made in the board's @code{backend/rtl} path to ISE's @code{verilog} path.
 
If the @code{XILINX_PATH} environment variable is set, this is very easy to do in the board's @code{backend/rtl} path:
 
@example
@kbd{ln -s $XILINX_PATH/verilog verilog}
@end example
 
Note that if this path is not set, simulations will be unable to compile.
 
@subsubheading Run RTL Regression Test
 
To run the default set of regression tests for the build, run the following command in the board's @code{sw/run} path.
1011,7 → 1026,7
@kbd{make rtl-tests}
@end example
 
The same set of options for RTL tests available in the reference design should available in this build. @xref{Running A Set Of Specific Reference Design RTL Tests}.
The same set of options for RTL tests available in the reference design should be available in this build. @xref{Running A Set Of Specific Reference Design RTL Tests}.
 
Options specific to the ML501 build.
 
/trunk/orpsocv2/sim/bin/Makefile
314,7 → 314,7
 
 
.PHONY: rtl-test
rtl-test: clean-sim-test-sw sw clean-test-defines $(TEST_DEFINES_VLG) \
rtl-test: clean-sim-test-sw sw-vmem clean-test-defines $(TEST_DEFINES_VLG) \
$(SIMULATOR)
 
# Run an RTL test followed by checking of generated results
361,14 → 361,14
# Path for the current test
TEST_SW_DIR=$(SW_DIR)/tests/$(shell echo $(TEST) | cut -d "-" -f 1)/sim
 
# Name of the image the RAM model will attempt to load via Verilog $readmemh
# system function.
# This SHOULD be a VMEM file. sram.vmem is the name of the image the ram models
# attempt to load.
SIM_SW_IMAGE ?=sram.vmem
 
.PHONY : sw
sw: $(SIM_SW_IMAGE)
.PHONY : sw-vmem sw-elf
sw-vmem: $(SIM_SW_IMAGE)
 
sram.vmem: $(TEST_SW_DIR)/$(TEST).vmem
$(SIM_SW_IMAGE): $(TEST_SW_DIR)/$(TEST).vmem
$(Q)if [ -L $@ ]; then unlink $@; fi
$(Q)ln -s $< $@
 
377,6 → 377,15
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).vmem
 
# Compile ELF and copy it here
sw-elf: $(TEST_SW_DIR)/$(TEST).elf
$(Q)cp -v $< .
 
$(TEST_SW_DIR)/$(TEST).elf:
$(Q) echo; echo "\t### Compiling software ###"; echo;
$(Q)$(MAKE) -C $(TEST_SW_DIR) $(TEST).elf
 
 
# Rule to force generation of the processed orpsoc-defines.h file
processed-verilog-headers-in-c-for-vlt:
$(Q)$(MAKE) -C $(SW_DIR)/lib processed-verilog-headers
622,7 → 631,7
# Verilator model test rules
################################################################################
 
vlt-test: build-vlt clean-sim-test-sw sw
vlt-test: build-vlt clean-sim-test-sw sw-vmem
$(SIM_VLT_DIR)/$(VLT_EXE) $(TEST)
 
vlt-tests:
675,4 → 684,29
lint-vlt: $(SIM_VLT_DIR) rtl $(DUMMY_FILES_FOR_VLT) $(SIM_VLT_DIR)/$(VLT_SCRIPT)
$(Q)echo; echo "\tLinting design with Verilator"; echo
$(Q)cd $(SIM_VLT_DIR) && \
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
verilator -language 1364-2001 --top-module orpsoc_top --lint-only -Mdir . -sc $(VLT_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(BENCH_SYSC_SRC_DIR) -f $(SIM_VLT_DIR)/$(VLT_SCRIPT)
 
################################################################################
# Architectural simulator test rules
################################################################################
 
ARCH_SIM_EXE ?=or32-elf-sim
ARCH_SIM_CFG ?= ../bin/or1ksim-orpsocv2.cfg
ARCH_SIM_OPTS ?= -q
 
.PHONY: rtl-test
sim-test: clean-sim-test-sw sw-elf
$(Q)$(ARCH_SIM_EXE) $(ARCH_SIM_OPTS) -f $(ARCH_SIM_CFG) $(TEST).elf > \
$(RTL_SIM_RESULTS_DIR)/$(TEST)$(TEST_OUT_FILE_SUFFIX)
 
# Run tests in simulation, check output
sim-test-with-check: sim-test check-test-log
 
# Main architectural simulations test loop
sim-tests:
$(Q)for test in $(TESTS); do \
export TEST=$$test; \
$(MAKE) sim-test-with-check; \
if [ $$? -ne 0 ]; then break; fi; \
echo; echo "\t### $$test test OK ###"; echo; \
done
/trunk/orpsocv2/sim/bin/or1ksim-orpsocv2.cfg
1,126 → 1,7
/* sim.cfg -- Simulator configuration script file
Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
 
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
the simulator.
 
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
 
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 
 
/* INTRODUCTION
 
The ork1sim has various parameters, that are set in configuration files
like this one. The user can switch between configurations at startup by
specifying the required configuration file with the -f <filename.cfg> option.
If no configuration file is specified or1ksim searches for the default
configuration file sim.cfg. First it searches for './sim.cfg'. If this
file is not found, it searches for '~/or1k/sim.cfg'. If this file is
not found too, it reverts to the built-in default configuration.
NOTE: Users should not rely on the built-in configuration, since the
default configuration may differ between version.
Rather create a configuration file that sets all critical values.
 
This file may contain (standard C) comments only - no // support.
Configure files may be be included, using:
include "file_name_to_include"
 
Like normal configuration files, the included file is divided into
sections. Each section is described in detail also.
 
Some section have subsections. One example of such a subsection is:
 
device <index>
instance specific parameters...
enddevice
 
which creates a device instance.
*/
 
 
/* MEMORY SECTION
 
This section specifies how the memory is generated and the blocks
it consists of.
 
type = random/unknown/pattern
Specifies the initial memory values.
'random' generates random memory using seed 'random_seed'.
'pattern' fills memory with 'pattern'.
'unknown' does not specify how memory should be generated,
leaving the memory in a undefined state. This is the fastest
option.
 
random_seed = <value>
random seed for randomizer, used if type = 'random'.
 
pattern = <value>
pattern to fill memory, used if type = 'pattern'.
 
nmemories = <value>
number of memory instances connected
 
baseaddr = <hex_value>
memory start address
 
size = <hex_value>
memory size
 
name = "<string>"
memory block name
 
ce = <value>
chip enable index of the memory instance
 
mc = <value>
memory controller this memory is connected to
 
delayr = <value>
cycles, required for read access, -1 if instance does not support reading
 
delayw = <value>
cycles, required for write access, -1 if instance does not support writing
 
log = "<filename>"
filename, where to log memory accesses to, no log, if log command is not specified
*/
 
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "FLASH"
ce = 0
mc = 0
baseaddr = 0x04000000
size = 0x00200000
delayr = 1
delayw = -1
end
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "RAM"
ce = 1
mc = 0
130,22 → 11,6
delayw = 1
end
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
 
name = "ICM"
mc = 0
ce = 2
baseaddr = 0x02000000
size = 0x00004000
delayr = 1
delayw = 1
end
 
 
/* IMMU SECTION
 
This section configures the Instruction Memory Manangement Unit
255,7 → 120,7
*/
 
section ic
enabled = 1
enabled = 0
nsets = 512
nways = 1
blocksize = 16
299,7 → 164,7
*/
 
section dc
enabled = 1
enabled = 0
nsets = 512
nways = 1
blocksize = 16
371,7 → 236,7
*/
 
section sim
verbose = 1
verbose = 0
debug = 0
profile = 0
prof_fn = "sim.profile"
390,40 → 255,6
end
 
 
/* SECTION VAPI
 
This section configures the Verification API, used for Advanced
Core Verification.
 
enabled = 0/1
'0': disbable VAPI server
'1': enable/start VAPI server
 
server_port = <value>
TCP/IP port to start VAPI server on
 
log_enabled = 0/1
'0': disable VAPI requests logging
'1': enable VAPI requests logging
 
hide_device_id = 0/1
'0': don't log device id (for compatability with old version)
'1': log device id
 
vapi_fn = <filename>
filename for the log file.
valid only if log_enabled is set
*/
 
section VAPI
enabled = 0
server_port = 9998
log_enabled = 0
vapi_log_fn = "vapi.log"
end
 
 
/* CPU SECTION
 
This section specifies various CPU parameters.
460,8 → 291,8
*/
 
section cpu
ver = 0x1200
rev = 0x0001
ver = 0x12
rev = 0x0008
/* upr = */
superscalar = 0
hazards = 1
484,98 → 315,6
end
 
 
/* BPB SECTION
 
This section specifies how branch prediction should behave.
enabled = 0/1
'0': disable branch prediction
'1': enable branch prediction
btic = 0/1
'0': disable branch target instruction cache model
'1': enable branch target instruction cache model
 
sbp_bf_fwd = 0/1
Static branch prediction for 'l.bf'
'0': don't use forward prediction
'1': use forward prediction
sbp_bnf_fwd = 0/1
Static branch prediction for 'l.bnf'
'0': don't use forward prediction
'1': use forward prediction
 
hitdelay = <value>
number of cycles bpb hit costs
missdelay = <value>
number of cycles bpb miss costs
*/
 
section bpb
enabled = 1
btic = 1
sbp_bf_fwd = 0
sbp_bnf_fwd = 0
hitdelay = 0
missdelay = 0
end
 
 
/* DEBUG SECTION
 
This sections specifies how the debug unit should behave.
 
enabled = 0/1
'0': disable debug unit
'1': enable debug unit
 
gdb_enabled = 0/1
'0': don't start gdb server
'1': start gdb server at port 'server_port'
 
server_port = <value>
TCP/IP port to start gdb server on
valid only if gdb_enabled is set
 
vapi_id = <hex_value>
Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
/*
section debug
enabled = 1
gdb_enabled = 1
server_port = 12345
end
*/
 
/* MC SECTION
 
This section configures the memory controller
 
enabled = 0/1
'0': disable memory controller
'1': enable memory controller
 
baseaddr = <hex_value>
address of first MC register
 
POC = <hex_value>
Power On Configuration register
 
index = <value>
Index of this memory controller amongst all the memory controllers
*/
 
section mc
enabled = 0
baseaddr = 0x60000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
 
/* UART SECTION
 
This section configures the UARTs
643,261 → 382,3
16550 = 1
end
 
 
/* DMA SECTION
 
This section configures the DMAs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first DMA register for this device
 
irq = <value>
irq number for this device
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section dma
enabled = 0
baseaddr = 0x9a000000
irq = 11
end
 
 
/* ETHERNET SECTION
 
This section configures the ETHERNETs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first ethernet register for this device
 
dma = <value>
which controller is this ethernet "connected" to
 
irq = <value>
ethernet mac IRQ level
 
rtx_type = <value>
use 0 - file interface, 1 - socket interface
 
rx_channel = <value>
DMA channel used for RX
 
tx_channel = <value>
DMA channel used for TX
 
rxfile = "<filename>"
filename, where to read data from
 
txfile = "<filename>"
filename, where to write data to
 
sockif = "<ifacename>"
interface name of ethernet socket
 
vapi_id = <hex_value>
VAPI id of this instance
*/
 
section ethernet
enabled = 0
baseaddr = 0x92000000
dma = 0
irq = 4
rtx_type = 0
tx_channel = 0
rx_channel = 1
rxfile = "eth0.rx"
txfile = "eth0.tx"
sockif = "eth0"
end
 
 
/* GPIO SECTION
 
This section configures the GPIOs
 
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first GPIO register for this device
 
irq = <value>
irq number for this device
 
base_vapi_id = <hex_value>
first VAPI id of this instance
GPIO uses 8 consecutive VAPI IDs
*/
 
section gpio
enabled = 0
baseaddr = 0x91000000
irq = 3
base_vapi_id = 0x0200
end
 
/* VGA SECTION
This section configures the VGA/LCD controller
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
address of first VGA register
irq = <value>
irq number for this device
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section vga
enabled = 0
baseaddr = 0x97100000
irq = 8
refresh_rate = 100000
filename = "primary"
end
 
 
/* TICK TIMER SECTION
 
This section configures tick timer
 
enabled = 0/1
whether tick timer is enabled
*/
/*
section tick
enabled = 1
irq = 3
end
*/
/*
section pic
enabled = 1
edge_trigger = 1
end
*/
 
/* FB SECTION
This section configures the frame buffer
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
baseaddr = <hex_value>
base address of frame buffer
paladdr = <hex_value>
base address of first palette entry
refresh_rate = <value>
number of cycles between screen dumps
filename = "<filename>"
template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
 
section fb
enabled = 0
baseaddr = 0x97000000
refresh_rate = 1000000
filename = "primary"
end
 
 
/* KBD SECTION
 
This section configures the PS/2 compatible keyboard
baseaddr = <hex_value>
base address of the keyboard device
rxfile = "<filename>"
filename, where to read data from
*/
 
section kbd
enabled = 0
irq = 5
baseaddr = 0x94000000
rxfile = "kbd.rx"
end
 
 
/* ATA SECTION
This section configures the ATA/ATAPI host controller
baseaddr = <hex_value>
address of first ATA register
enabled = <0|1>
Enable/disable the peripheral. By default if it is enabled.
 
irq = <value>
irq number for this device
 
debug = <value>
debug level for ata models.
0: no debug messages
1: verbose messages
3: normal messages (more messages than verbose)
5: debug messages (normal debug messages)
7: flow control messages (debug statemachine flows)
9: low priority message (display everything the code does)
 
dev_type0/1 = <value>
ata device 0 type
0: NO_CONNeCT: none (not connected)
1: FILE : simulated harddisk
2: LOCAL : local system harddisk
 
dev_file0/1 = "<filename>"
filename for simulated ATA device
valid only if dev_type0 == 1
 
dev_size0/1 = <value>
size of simulated hard-disk (in MBytes)
valid only if dev_type0 == 1
 
dev_packet0/1 = <value>
0: simulated ATA device does NOT implement PACKET command feature set
1: simulated ATA device does implement PACKET command feature set
 
FIXME: irq number
*/
/*
section ata
enabled = 0
baseaddr = 0x9e000000
irq = 15
 
dev_type0 = 1
dev_file0 = "/tmp/sim_atadev0"
dev_size0 = 1
dev_packet0 = 0
 
dev_type1 = 0
dev_file1 = ""
dev_size1 = 0
dev_packet1 = 0
end
*/
 
/trunk/orpsocv2/sw/tests/ethmac/board/ethmac-ping.c
100,8 → 100,8
 
/* Buffer number (must be 2^n)
*/
#define OETH_RXBD_NUM 32
#define OETH_TXBD_NUM 32
#define OETH_RXBD_NUM 64
#define OETH_TXBD_NUM 64
#define OETH_RXBD_NUM_MASK (OETH_RXBD_NUM-1)
#define OETH_TXBD_NUM_MASK (OETH_TXBD_NUM-1)
 
1790,9 → 1790,10
}
if (bad) {
printf("RXE: 0x%x\n",rx_bdp[i].len_status & OETH_RX_BD_STATS);
rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
 
bad = 0;
continue;
}
else {
1844,6 → 1845,9
tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
 
/* Probably good to check for TX errors here */
// Check if either carrier sense lost or colission indicated
if (tx_bd[i].len_status & OETH_TX_BD_STATS)
printf("TXER: 0x%x\n",(tx_bd[i].len_status & OETH_TX_BD_STATS));
if (print_packet_contents)
printf("T%d",i);
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mac.S
240,6 → 240,8
 
l.movhi r3, 0x8000
l.ori r3, r3, 0x000d
l.nop 0x2
l.ori r3, r0, 0
l.nop 0x1
 
fail:
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-cbasic.c
195,7 → 195,8
 
// gives us 8000000d (goooood)
report(result3+0x3474E142);
//exit(result3-0x6cdd401e);
exit(result3+0x3474E142);
if (result3+0x3474E142 == 0x8000000d)
exit(0);
else
exit(1);
}
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-fp.S
2614,7 → 2614,7
 
l.movhi r3,hi(ALL_DONE)
l.ori r3,r3,lo(ALL_DONE)
l.nop NOP_REPORT /* Should be 0xdeaddead */
l.nop NOP_REPORT
 
l.addi r3,r0,0
l.nop NOP_EXIT
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-dctest.c
29,11 → 29,12
{
 
// Check data cache is present and enabled
if (!(mfspr(SPR_UPR)& SPR_UPR_DCP))
return 0x8000000d;
if (!(mfspr(SPR_SR) & SPR_SR_DCE))
return 0x8000000d;
if (!(mfspr(SPR_UPR)& SPR_UPR_DCP) | !(mfspr(SPR_SR) & SPR_SR_DCE))
{
// Not really a pass, but not really a fail, either.
report(0x8000000d);
return 0;
}
 
volatile char* ptr = (volatile char*) 0xe00000;
int i;
150,7 → 151,9
 
report(next_rand());
 
return 0x8000000d;
report(0x8000000d);
 
exit(0);
}
 
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-maci.S
125,4 → 125,8
l.mfspr r3,r0,SPR_MACLO
l.nop 0x2
l.nop
l.nop 0x1
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 0x2
l.ori r3, r0, 0
l.nop 0x1
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-mmu.c
1532,6 → 1532,5
printf("Tests completed\n");
report (0xdeaddead);
report (0x8000000d);
exit (0x8000000d);
return 0;
exit (0);
}
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-basic.S
1095,8 → 1095,9
l.add r3,r8,r3 /* Should be 0xdeaddead */
 
l.movhi r4, 0x5ead
l.ori r4, r4, 0xdea0
l.sub r3, r3, r4 /* Should now be 0x8000000d */
l.ori r4, r4, 0xdea0
l.sub r3, r3, r4 /* Should now be 0x8000000d */
l.nop 0x2
l.ori r3, r0, 0 /* Clear R3 */
l.nop 0x1 /* Exit simulation */
 
l.nop 0x1 /* Exit simulation */
 
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-float.c
39,6 → 39,8
if (*int_ptr != 0x45388615)
exit(3);
exit(0x8000000d);
report(0x8000000d);
 
exit(0);
}
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ticksyscall.S
333,6 → 333,8
l.nop
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 2
l.ori r3, r0, 0
l.nop 1
_fail:
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
514,8 → 514,10
l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
l.ori r5, r5, lo(0x44004800)
l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.movhi r5, 0x1500 /* l.nop after illegal instruction */
l.sw 0x8(r0), r5 /* Write nop to RAM addr 0x8 */
l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
/* Call 0x4, illegal opcode instruction */
l.ori r6, r0, 0x4
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-ffl1.S
271,7 → 271,7
 
fl1_error:
l.movhi r3, hi(0xbaaadf11)
l.ori r3, r3, lo(0xbaaadf11)
l.ori r3, r3, lo(0xbaaadf11)
l.nop 0x1
278,6 → 278,8
ffl1_ok:
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 0x1
l.ori r3, r3, lo(0x8000000d)
l.nop 0x2 /* Report */
l.ori r3, r0, 0 /* Return 0 */
l.nop 0x1
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-linkregtest.S
94,16 → 94,20
l.nop
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
/* Try writing to r9 during delay slot... */
/* Setup some code at address 0x0 */
l.movhi r4, hi(0x15000000) /* standard l.nop */
l.ori r5, r4, 0x2 /* l.nop that will report value in r3 */
l.sw 0x0(r0), r5 /* Write "l.nop 0x2" to 0x0 */
l.movhi r6, hi(0xa8600000) /*Assemble register with l.ori r3,r0,0 */
l.sw 0x4(r0), r6 /* Write "l.ori r3,r0,0" to 0x4*/
l.ori r5, r4, 0x1 /* l.nop that will exit simulation */
l.sw 0(r0), r4 /* Write l.nop to 0x0 */
l.sw 4(r0), r4 /* Write l.nop to 0x4 */
l.sw 8(r0), r5 /* Write l.nop 0x1 to 0x9 */
l.sw 12(r0), r4 /* Write l.nop to 0xc */
l.sw 0x8(r0), r5 /* Write l.nop 0x1 to 0x8 */
l.sw 0xc(r0), r0 /* Write "l.j 0" to address 0xc */
l.sw 0x10(r0), r4 /* Write l.nop to 0xc */
l.nop
/* Try writing to r9 during delay slot... */
l.jal _testjalfunc
l.or r9, r0, r0 /* Clear r9 */
l.or r9, r0, r0 /* Clear r9 - cause jump to 0 on return */
l.nop 1
 
 
/trunk/orpsocv2/sw/apps/testfloat/writeHex.c
29,7 → 29,7
/*
#include <stdio.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "printf.h"
#include "softfloat.h"
/trunk/orpsocv2/sw/apps/testfloat/testsoftfloat.c
31,7 → 31,7
#include <signal.h>
#include <string.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "fail.h"
#include "softfloat.h"
/trunk/orpsocv2/sw/apps/testfloat/testfloat.c
32,7 → 32,7
#include <signal.h>
#include <string.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "printf.h"
#include "spr-defs.h"
/trunk/orpsocv2/sw/apps/testfloat/fail.c
31,7 → 31,7
#include <stdarg.h>
#include <stdio.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "printf.h"
#include "fail.h"
/trunk/orpsocv2/sw/apps/testfloat/random.c
29,7 → 29,7
/*
#include <stdlib.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "random.h"
 
/trunk/orpsocv2/sw/apps/testfloat/testFunction.c
26,7 → 26,7
 
===============================================================================
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "printf.h"
#include "softfloat.h"
/trunk/orpsocv2/sw/apps/testfloat/testLoops.c
30,7 → 30,7
#include <stdlib.h>
#include <stdio.h>
*/
#include "or32-utils.h" // OR1k support C library
#include "cpu-utils.h" // OR1k support C library
#include "milieu.h"
#include "printf.h"
#include "softfloat.h"
/trunk/orpsocv2/sw/Makefile.inc
110,9 → 110,9
# Hardware integer arith, soft float
MARCH_FLAGS ?=-mhard-mul -mhard-div -msoft-float
# FPGA default - only hardware multiply
#MACH_FLAGS ?=-mhard-mul -msoft-div -msoft-float
#MARCH_FLAGS ?=-mhard-mul -msoft-div -msoft-float
# All software div, mul and FPU
#MACH_FLAGS ?=-msoft-mul -msoft-div -msoft-float
#MARCH_FLAGS ?=-msoft-mul -msoft-div -msoft-float
 
OR32_CFLAGS ?=-g -nostdlib -O2 $(MARCH_FLAGS) \
$(INCLUDE_FLAGS) \
/trunk/orpsocv2/sw/drivers/or1200/crt0.S
18,7 → 18,7
 
// Really goes to configurable interrupt handler
#define UNHANDLED_EXCEPTION \
l.addi r1, r1, -128; \
l.addi r1, r1, -256; \
l.sw 4(r1), r3; \
l.sw 8(r1), r4; \
l.mfspr r3,r0,SPR_NPC; \
71,7 → 71,7
//UNHANDLED_EXCEPTION
/* Simply load timer_ticks variable and increment */
.extern timer_ticks
l.addi r1, r1, -8
l.addi r1, r1, -136
l.sw 0(r1), r25
l.sw 4(r1), r26
l.movhi r25, hi(timer_ticks)
84,7 → 84,7
l.mtspr r0, r25, SPR_TTMR /* Reset timer */
l.lwz r25, 0(r1)
l.lwz r26, 4(r1)
l.addi r1, r1, 8
l.addi r1, r1, 136
l.rfe
 
/* ---[ 0x600: Aligment exception ]-------------------------------------- */
391,7 → 391,7
l.lwz r31, 0x74(r1)
l.lwz r32, 0x78(r1)
 
l.addi r1, r1, 128
l.addi r1, r1, 256
 
l.rfe
l.nop
/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/Makefile
1,3 → 1,5
# Makefile is stripped out only to build SDR_16 controller.
 
VERSATILE_FIFO_PROJECT_FILES =versatile_fifo_dual_port_ram.v
VERSATILE_FIFO_PROJECT_FILES +=versatile_fifo_async_cmp.v
VERSATILE_FIFO_PROJECT_FILES +=dff_sr.v
31,34 → 33,32
fifo_fill.v: fifo_fill.fzm
perl fizzim.pl -encoding onehot < fifo_fill.fzm > fifo_fill.v
 
ddr_16_generated.v: ddr_16.fzm ddr_16_defines.v
perl fizzim.pl -encoding onehot < ddr_16.fzm > $@
#ddr_16_generated.v: ddr_16.fzm ddr_16_defines.v
# perl fizzim.pl -encoding onehot < ddr_16.fzm > $@
 
ddr_16.v: ddr_16_generated.v
vppreproc --simple $^ > $@
#ddr_16.v: ddr_16_generated.v
# vppreproc --simple $^ > $@
 
#fifo_adr_counter.v:
# @echo;echo "\tThis file,"$@", doesn't exist, is it still needed?!. \n\tMake will now stop";echo
# ls notexisting
 
VERSATILE_MEM_CTRL_IP_FILES=versatile_fifo_async_cmp.v async_fifo_mq.v versatile_fifo_dual_port_ram_dc_dw.v ctrl_counter.v fifo.v fifo_fill.v inc_adr.v ref_counter.v ref_delay_counter.v pre_delay_counter.v burst_length_counter.v ddr_16.v fsm_wb.v delay.v ddr_ff.v dcm_pll.v dff_sr.v versatile_mem_ctrl_ddr.v ddr_16_defines.v sdr_16_defines.v codec.v gray_counter.v egress_fifo.v versatile_fifo_dual_port_ram_dc_sw.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v
 
versatile_mem_ctrl_ip.v: $(VERSATILE_MEM_CTRL_IP_FILES)
cat $^ | cat copyright.v - > $@
 
# SDRAM 16-bit wide databus dependency files - force a recompile
SDR_16_FILES=sdr_16_defines.v fsm_wb.v versatile_fifo_async_cmp.v async_fifo_mq.v delay.v codec.v gray_counter.v egress_fifo.v versatile_fifo_dual_port_ram_dc_sw.v dff_sr.v ref_counter.v fsm_sdr_16.v versatile_mem_ctrl_wb.v versatile_mem_ctrl_top.v
sdr_16.v: $(SDR_16_FILES)
vppreproc +define+SDR_16 +incdir+. $^ > $@
 
 
# the single all rule
all: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v counter_csvs fifo_fill.v sdr_16.v ddr_16.v versatile_mem_ctrl_ip.v
#all: versatile_fifo_dual_port_ram.v versatile_fifo_async_cmp.v versatile_fifo_dual_port_ram_dc_dw.v counter_csvs fifo_fill.v sdr_16.v ddr_16.v versatile_mem_ctrl_ip.v
all: sdr_16.v
 
 
 
clean:
rm -rf $(VERSATILE_FIFO_PROJECT_FILES) $(VERSATILE_COUNTER_PROJECT_FILES)
rm -rf fifo_fill.v sdr_16.v ddr_16.v
rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
# rm -f versatile_fifo_dual_port_ram_dc_dw.v ddr_16_generated.v
rm -rf *_counter.v
rm -rf *.csv
rm -rf *~
/trunk/orpsocv2/boards/actel/ordb1a3pe1500/rtl/verilog/versatile_mem_ctrl/rtl/verilog/versatile_fifo_dual_port_ram_dc_sw.v
0,0 → 1,32
// true dual port RAM, sync
 
`ifdef ACTEL
`define SYN /*synthesis syn_ramstyle = "no_rw_check"*/
`endif
module vfifo_dual_port_ram_dc_sw
(
d_a,
adr_a,
we_a,
clk_a,
q_b,
adr_b,
clk_b
);
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 8;
input [(DATA_WIDTH-1):0] d_a;
input [(ADDR_WIDTH-1):0] adr_a;
input [(ADDR_WIDTH-1):0] adr_b;
input we_a;
output [(DATA_WIDTH-1):0] q_b;
input clk_a, clk_b;
reg [(ADDR_WIDTH-1):0] adr_b_reg;
reg [DATA_WIDTH-1:0] ram [(1<<ADDR_WIDTH)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
always @ (posedge clk_a)
if (we_a)
ram[adr_a] <= d_a;
always @ (posedge clk_b)
adr_b_reg <= adr_b;
assign q_b = ram[adr_b_reg];
endmodule
/trunk/orpsocv2/boards/actel/ordb1a3pe1500/sw/Makefile.inc
18,8 → 18,8
# This doesn't work! :-( Need to figure out way to set these and have them
# carry through to things like the liborpsoc driver modules etc.
#MARCH_FLAGS =-mhard-mul -mhard-div -msoft-float
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
#export MARCH_FLAGS
MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
export MARCH_FLAGS
 
# Finally include the main software include file
 
/trunk/orpsocv2/boards/xilinx/ml501/sim/bin/Makefile
1,6 → 1,6
######################################################################
#### ####
#### ORPSoCv2 Testbenches Makefile ####
#### ORPSoCv2 Xilinx simulation Makefile ####
#### ####
#### Description ####
#### ORPSoCv2 Testbenches Makefile, containing rules for ####
107,6 → 107,18
@echo $(TESTS)
@echo
 
# Backend tool path
# Check that the XILINX_PATH variable is set
ifeq ($(XILINX_PATH),)
$(error XILINX_PATH environment variable not set. Set it and rerun)
endif
XILINX_SETTINGS_SCRIPT=$(XILINX_PATH)/settings32.sh
XILINX_SETTINGS_SCRIPT_EXISTS=$(shell if [ -e $(XILINX_SETTINGS_SCRIPT) ]; then echo 1; else echo 0; fi)
ifeq ($(XILINX_SETTINGS_SCRIPT_EXISTS),0)
$(error XILINX_PATH variable not set correctly. Cannot find $$XILINX_PATH/settings32.sh)
endif
 
 
# Simulation directories
SIM_DIR ?=$(BOARD_DIR)/sim
RTL_SIM_DIR=$(SIM_DIR)
132,7 → 144,9
BOARD_BACKEND_VERILOG_DIR=$(BOARD_BACKEND_DIR)/rtl/verilog
TECHNOLOGY_BACKEND_DIR=$(BOARD_DIR)/../backend
# This path is for the technology library
TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
#TECHNOLOGY_BACKEND_VERILOG_DIR=$(TECHNOLOGY_BACKEND_DIR)/rtl/verilog
# Depends on the XILINX_PATH variable - we check above if it's set properly.
TECHNOLOGY_BACKEND_VERILOG_DIR=$(XILINX_PATH)/verilog
 
# Synthesis directory for board
BOARD_SYN_DIR=$(BOARD_DIR)/syn/synplify
/trunk/orpsocv2/boards/xilinx/ml501/README
1,59 → 1,5
Xilinx ML501 board build
Xilinx ML501 board build
 
This board contains a Xilinx Virtex5 LX50 part. The key supported features in board build are the DDR2 SODIMM, the ZBT SRAM and the Ethernet MAC (only 10/100, no Gigabit support). Additionally configured features of the ML501 include the GPIO and UART.
See the project's main documentation in doc/ for information on this build.
 
For more information on the ML501, see Xilinx's page: http://www.xilinx.com/products/devkits/HW-V5-ML501-UNI-G.htm
 
Configuring the build:
 
The Verilog include file rtl/ml501_defines.v contains the defines which control how the RTL is configured. This is where the desired memory controller, and internal blockRAM memory configuration is set, as well as which peripherals to include. See that file for further details.
 
There are seperate defines files for each of the componenets in ORPSoC also included in the board's RTL directory, allowing an individual configuration of the OR1200, ethernet and Wishbone arbiter for this board.
 
How to simulate:
 
Ensure the Xilinx tools are installed on your system and their path is configured in the board/tools.inc file.
 
Mentor Graphics' Modelsim is required to perform the simulations (Icarus Verilog cannot compile the Xilinx libraries).
 
Go into boards/xilinx/ml501/sim/run and do a "make rtl-board-tests". This will start a loop which will run 3 tests, a boot test (UART printout, simulation may take several minutes to complete), a memory test, testing the selected memory controller, and a GPIO test. To see VCD dumps of these tests, also set "VCD=1" when running the tests. If any changes were made to the RTL configuration, it's recommended a clean is run before re-running the simulations.
 
How to synthesize:
 
It is possible to run a single make command to run the flow from RTL synthesis through to programming file generation. To do this, go to the par/ directory and run "make ml501.bit".
 
The design is configured with the DDR2 SDRAM controller, ethernet MAC, and GPIO enabled by default. If any of these are disabled, or say the ZBT SRAM controller is used instead of the DDR2, the Xilinx mapper will fail when attemping to assign pins to nonexistant ports on the design. The UCF will need to be changed to fix this, so edit the par/ml501_xst.ucf UCF file, commenting or uncommenting, as necessary, the required clearly-marked sections.
 
The resulting FPGA .bit file can be downloaded and is configured to run the sw/boot program on reset (as long as that section of the memory has not been written over.)
 
Debugging on the board:
 
The standard OpenRISC debug interface, controlled via the JTAG bus, is included in this design. A seperate JTAG TAP is included with ORPSoC and is used in this build, its pins connected to the expansion header, J4 (the middle column), in the following order:
Pin 2: UART Rx
Pin 4: UART Tx
Pin 6: JTAG Tdo
Pin 8: JTAG Tdi
Pin 10: JTAG Tms
Pin 12: JTAG Tck
 
This debugging interface has been tested with the ORSoC debug cable and seen to work. These UART pins go to the same UART as the 9-pin DSUB connector, either one can be used for the UART interface.
 
To do:
 
Notes:
 
* The design currently runs the Wishbone bus and processor at 50MHz, the ZBT SRAM at 200MHz, the DDR2 SDRAM at 266 MHz. There are a few multi-cycle paths in the design for these memory controllers and these are defined in the UCF.
 
* The DDR2 SDRAM controller was generated using the Xilinx Memory Interface Generator (MIG) tool and has been modified slightly. The small cache RAM that sits between the DDR2 MIG controller and Wishbone interface must convert from 128-bit wide 266MHz domain generated memory signals to the 32-bit wide Wishbone domain words, and to do this another Xilinx Coregen blockRAM setup has been used. The RTL instantiating it is in the rtl/ path and the NGC is included in the syn/ path.
 
* The mapper complains that the debug interface's JTAG tck signal isn't going on on an optimal pin, but we override that. So far it has not been seen to exhibit any problematic effects.
 
* There are several errors reported in the timing report, after place and route, related to some clock domain crossover signals in the ethernet MAC core. Despite timing ignore (TIG) markings in the UCF these remain. Please contact the maintainer if this looks like it really is an issue, or can be solved somehow.
 
* As the Ethernet MAC core is only 10/100, it cannot handle gigabit mode. There is software included which resets the Marvell ethernet PHY and disables advertisement of gigabit capability.
 
* There is a user-driven reset feature, meaning the user is able to reset the system by accessing any address starting at 0xe0000000. For this to be enabled, however, the pins 62 and 64 on expansion header J4 (bottom two pins on same column as JTAG debug pins) must be connected. This is useful for debugging the system and not requiring that the reset button be pushed to restart it.
 
* A post-synthesis netlist can be made by going so syn/ and running "make ml501.v", and a post-PAR netlist can be made by going to par/ and running "make ml501.netlist". It is possible to run the post-synthesis simulation in sim/run/ running "make syn-board-test", however no target for post-PAR netlist simulation exists yet, although it shouldn't be too hard to configure.
 
Maintained by Julius Baxter, julius.baxter@orsoc.se

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