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  • This comparison shows the changes necessary to convert path 
    /openrisc
    from Rev 425 to Rev 426
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Rev 425 → Rev 426

/trunk/orpsocv2/rtl/verilog/or1200/or1200_ic_top.v
233,12 → 233,11
// Tag comparison
//
// During line invalidate, ensure it stays the same
// /* TODO - do this properly! */
always @(tag or saved_addr or tag_v) begin
if ((tag != saved_addr[31:`OR1200_ICTAGL]) | !tag_v)
tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b1;
tagcomp_miss = 1'b1;
else
tagcomp_miss = (ic_inv | ic_inv_q) ? tagcomp_miss : 1'b0;
tagcomp_miss = 1'b0;
end
 
//
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-except.S
513,37 → 513,37
l.nop
l.movhi r5, hi(0x44004800) /* Put "l.jr r9" instruction in r5 */
l.ori r5, r5, lo(0x44004800)
l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.movhi r5, 0x1500 /* l.nop after illegal instruction */
l.sw 0x8(r0), r5 /* Write nop to RAM addr 0x8 */
l.sw 0x0(r0), r5 /* Write "l.j r9" to address 0x0 in RAM */
l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.movhi r5, 0x1500 /* l.nop after illegal instruction */
l.sw 0x8(r0), r5 /* Write nop to RAM addr 0x8 */
l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
/* Call 0x4, illegal opcode instruction */
/* Jump to 0x4 - illegal opcode instruction */
l.ori r6, r0, 0x4
l.jalr r6 /* Jump to address 0x4, landing on an illegal instruction */
l.addi r12,r12,1 /* Increment 2nd exception counter */
l.nop /* Should return here */
l.jalr r6 /* Jump to address 0x4, land on illegal insn */
l.addi r12,r12,1 /* Increment 2nd exception counter */
l.nop /* Should return here */
l.nop
 
/* Test in delay slot */
l.movhi r5, 0xff00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.movhi r5, 0xee00 /* Put an illegal instruction in r5 */
l.sw 0x4(r0), r5 /* Write illegal instruction to RAM addr 0x4 */
l.mtspr r0,r0,SPR_ICBIR /* Invalidate line 0 of cache */
l.jalr r0 /* Jump to address 0, will be a jump back but with an illegal
dslot instruction which will befixed by handler */
l.addi r12,r12,1 /* Increment 2nd exception counter */
l.nop /* Should return here */
l.addi r12,r12,1 /* Increment 2nd exception counter */
l.nop /* Should return here */
 
/* Check 1st and 2nd exception counters are equal */
l.sfeq r11,r12 /* Should be equal */
l.sfeq r11,r12 /* Should be equal */
l.bf 1f
l.nop
l.or r3, r12, r12
l.nop 2 /* Report expected exception count */
l.nop 2 /* Report expected exception count */
l.or r3, r11, r11
l.nop 2 /* Report actual exception count */
l.nop 2 /* Report actual exception count */
l.nop 1
1: l.nop
l.nop
/trunk/orpsocv2/sw/tests/sdram/board/sdram-rows.c
0,0 → 1,84
/*
* SDRAM row test, for running on the board (with printfs)
*
* Tests accessing every row
*
*/
 
#include "cpu-utils.h"
#include "board.h"
#include "sdram.h"
#include "uart.h"
#include "printf.h"
 
#ifndef _SDRAM_H_
#define _SDRAM_H_
 
#ifdef MT48LC32M16A2 // 64MB SDRAM part
#define SDRAM_SIZE 0x04000000
#define SDRAM_ROW_SIZE 2048 // in bytes (10 bits col addr, 2 bytes per)
#define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address
#define SDRAM_NUM_BANKS 4
#endif
 
#ifdef MT48LC16M16A2 // 32MB SDRAM part
#define SDRAM_SIZE 0x02000000
#define SDRAM_ROW_SIZE 1024 // in bytes (9 bits col addr, 2 bytes per)
#define SDRAM_NUM_ROWS_PER_BANK (8192) // 13-bit row address
#define SDRAM_NUM_BANKS 4
#endif
 
#ifdef MT48LC4M16A2 // 8MB SDRAM part
#define SDRAM_SIZE 0x800000
#define SDRAM_ROW_SIZE 512 // in bytes (8 bits col addr, 2 bytes per)
#define SDRAM_NUM_ROWS_PER_BANK (4096) // 12-bit row address
#define SDRAM_NUM_BANKS 4
#endif
 
 
#endif
 
 
#define SDRAM_NUM_ROWS (SDRAM_NUM_ROWS_PER_BANK * SDRAM_NUM_BANKS)
 
#define START_ROW 128
 
int main()
{
 
uart_init(DEFAULT_UART);
 
 
printf("\n\tSDRAM rows test\n");
 
printf("\n\tWriting\n");
int i; // Skip first 64KB, code/stack resides there - TODO determine this from
// stack linker variable!
for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
{
REG32((i*(SDRAM_ROW_SIZE))) = i;
printf("\r\t0x%x", i);
}
 
printf("\n\tReading\n");
 
int read_result = 0;
 
for(i=START_ROW;i<(SDRAM_NUM_ROWS);i++)
{
printf("\r\t0x%x", i);
read_result = REG32((i*(SDRAM_ROW_SIZE)));
if (read_result != i)
{
printf("\n\Error at 0x%x, read 0x%x, expected 0x%x\n",
(i*SDRAM_ROW_SIZE), read_result, i);
report(0xbaaaaaad);
report(i);
report(read_result);
exit(0xbaaaaaad);
}
}
printf("\n\tTest OK.\n");
exit(0x8000000d);
}
/trunk/orpsocv2/sw/tests/sdram/board/Makefile
0,0 → 1,14
SW_ROOT=../../..
include $(SW_ROOT)/Makefile.inc
 
OR32_CFLAGS += -I.
 
%.dis: %.elf
$(Q)$(OR32_OBJDUMP) -d $< > $@
 
%.bin: %.elf
$(Q)$(OR32_OBJCOPY) -O binary $< $@
 
clean:
$(Q)rm -f *.elf *.bin *.vmem *.flashin *.dis
 
/trunk/orpsocv2/sw/tests/sdram/sim/sdram-board-rows.c File deleted
/trunk/orpsocv2/sw/tests/sdram/sim/sdram-cols.c
6,7 → 6,7
*
*/
 
#include "or32-utils.h"
#include "cpu-utils.h"
#include "board.h"
#include "sdram.h"
 
/trunk/orpsocv2/sw/tests/uart/sim/uart-echo.c File deleted
/trunk/orpsocv2/boards/xilinx/ml501/rtl/verilog/include/or1200_defines.v
206,7 → 206,7
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
`define OR1200_NO_BURSTS
//
 
//
/trunk/orpsocv2/boards/xilinx/ml501/sw/board/include/board.h
2,12 → 2,6
#define _BOARD_H_
 
#define IN_CLK 50000000 // Hz
//#define IN_CLK 32000000 // Hz
//#define IN_CLK 30000000 // HZ
//#define IN_CLK 24000000 // HZ
//#define IN_CLK 20000000 // HZ
//#define IN_CLK 18000000 // HZ
//#define IN_CLK 16000000 // HZ
 
//
// ROM bootloader
22,6 → 16,7
//#define BOOTROM_LOOP_IN_ROM
 
// Address bootloader should start from in FLASH
// Last 256KB of 2MB flash - offset 0x1c0000 (2MB-256KB)
#define BOOTROM_ADDR_BYTE2 0x1c
#define BOOTROM_ADDR_BYTE1 0x00
#define BOOTROM_ADDR_BYTE0 0x00

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