OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path 
    /openrisc
    from Rev 457 to Rev 458
    ↔ Reverse comparison
  •

Rev 457 → Rev 458

/trunk/or1ksim/cpu/or32/or32.c
1090,6 → 1090,7
unsigned int trace_store_imm;
int trace_store_val_reg;
int trace_store_width;
int trace_dest_spr;
 
/* Automagically does zero- or sign- extension and also finds correct
sign bit position if sign extension is correct extension. Which extension
1320,6 → 1321,7
 
/* Set trace result defaults. */
trace_dest_reg = -1;
trace_dest_spr = -1;
trace_store_addr_reg = -1;
trace_store_imm = 0;
trace_store_val_reg = -1;
1346,6 → 1348,12
trace_store_width = 4;
}
 
/* Is it a move to SPR opcode? */
if (0 == strcmp ("l.mtspr", opcode->name))
{
trace_dest_spr = 1;
}
 
/* Copy the opcode and pad */
strcpy (dest, opcode->name);
 
1411,6 → 1419,17
trace_store_imm =
or1ksim_extend_imm (trace_store_imm, *s);
}
 
if (1 == trace_dest_spr)
{
trace_dest_spr =
or1ksim_or32_extract ('K', opcode->encoding,
insn);
trace_dest_reg =
or1ksim_or32_extract ('A', opcode->encoding,
insn);
}
}
else
{
/trunk/or1ksim/cpu/common/abstract.c
1253,8 → 1253,16
or1ksim_disassemble_trace_index (insn, index);
PRINTF ("%-24s", or1ksim_disassembled);
 
/* Put either the register assignment, or store */
if (-1 != trace_dest_reg)
/* Put either the register assignment, SPR value, or store */
if (-1 != trace_dest_spr)
{
PRINTF ("SPR[%04x] = %08x", (trace_dest_spr |
evalsim_reg (trace_dest_reg)),
cpu_state.sprs[(trace_dest_spr |
evalsim_reg (trace_dest_reg))]);
 
}
else if (-1 != trace_dest_reg)
{
PRINTF ("r%-2u = %" PRIxREG "", trace_dest_reg,
evalsim_reg (trace_dest_reg));
1291,6 → 1299,7
break;
}
}
 
/* Print the flag */
PRINTF (" flag: %u\n", cpu_state.sprs[SPR_SR] & SPR_SR_F ? 1 : 0);
/trunk/or1ksim/cpu/or1k/opcode/or32.h
171,6 → 171,7
extern unsigned int trace_store_imm;
extern int trace_store_val_reg;
extern int trace_store_width;
extern int trace_dest_spr;
 
/* Calculates instruction length in bytes. Always 4 for OR32. */
extern int or1ksim_insn_len PARAMS((int insn_index));
/trunk/or1ksim/ChangeLog
1,3 → 1,11
2011-01-04 Julius Baxter <julius@opencores.org>
* cpu/or32/or32.c: <trace_dest_spr>: Added.
(or1ksim_disassemble_trace_index): Added dumping of SPR content when
disassembling l.mtspr instruction.
* cpu/common/abstract.c:
(disassemble_instr): Added tracing of SPR contents after l.mtspr insn.
* cpu/or1k/opcode/or32.h: (trace_dest_spr): Added extern definition.
2010-12-27 Julius Baxter <julius@opencores.org>
 
* peripheral/eth.c: <RTX_RESCHED_PERIOD>: Changed to 10000.
/trunk/or1ksim/testsuite/libsim.tests/default.cfg
27,21 → 27,6
pattern = 0x00
type = unknown /* Fastest */
name = "FLASH"
ce = 0
mc = 0
baseaddr = 0xf0000000
size = 0x00200000
delayr = 10
delayw = -1
end
 
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "RAM"
ce = 1
mc = 0
104,7 → 89,7
ver = 0x12
rev = 0x0001
/* upr = */
sr = 0xc001
sr = 0x8001
superscalar = 0
hazards = 0
dependstats = 0
130,54 → 115,3
exe_log_type = software
exe_log_fn = "executed.log"
end
 
/* Memory instead of MC. Stops write errors when the startup code tries to
access a non-existent MC */
section memory
/*random_seed = 12345
type = random*/
pattern = 0x00
type = unknown /* Fastest */
name = "MC shadow"
baseaddr = 0x93000000
size = 0x00000080
delayr = 2
delayw = 4
end
 
/* Disabled */
section mc
enabled = 0
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
end
 
section ethernet
enabled = 0
baseaddr = 0x92000000
irq = 4
rtx_type = "file"
end
 
section VAPI
enabled = 0
server_port = 9998
end
 
section fb
enabled = 1
baseaddr = 0x97000000
refresh_rate = 10000
filename = "primary"
end
 
section kbd
enabled = 0
end
/trunk/or1ksim/testsuite/libsim.tests/int-edge.cfg
113,13 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/libsim.tests/int-level.cfg
113,13 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/libsim.tests/upcalls.cfg
113,41 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
end
 
section ethernet
enabled = 0
baseaddr = 0x92000000
irq = 4
rtx_type = "file"
end
 
section VAPI
enabled = 0
server_port = 9998
end
 
section fb
enabled = 1
baseaddr = 0x97000000
refresh_rate = 10000
filename = "primary"
end
 
section kbd
enabled = 0
end
 
section generic
enabled = 1
baseaddr = 0x98000000
/trunk/or1ksim/testsuite/test-code-or1k/configure
867,7 → 867,7
enable_libtool_lock
enable_dependency_tracking
enable_all_tests
enable_opt
enable_check_opt
'
ac_precious_vars='build_alias
host_alias
11046,15 → 11046,15
 
 
# Specify our baseline CFLAGS
CPPFLAGS="-I\${top_srcdir}/support -I\${top_srcdir}/mc-common"
CPPFLAGS="-I\${top_srcdir}/support -I\${top_srcdir}/except"
CFLAGS="-Wall -Werror -g -nostdlib -mhard-div -mhard-mul"
 
# Flag to specify whether we want optimization when checking
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable optimizations when checking" >&5
$as_echo_n "checking whether to enable optimizations when checking... " >&6; }
# Check whether --enable-opt was given.
if test "${enable_opt+set}" = set; then :
enableval=$enable_opt;
# Check whether --enable-check-opt was given.
if test "${enable_check_opt+set}" = set; then :
enableval=$enable_check_opt;
case "$enableval" in
yes)
CFLAGS="$CFLAGS -O"
/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.in
74,7 → 74,7
CONFIG_CLEAN_VPATH_FILES =
am_basic_OBJECTS = basic.$(OBJEXT)
basic_OBJECTS = $(am_basic_OBJECTS)
basic_LDADD = $(LDADD)
basic_DEPENDENCIES = ../except/except.lo ../support/libsupport.la
basic_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \
--mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(basic_LDFLAGS) \
$(LDFLAGS) -o $@
218,6 → 218,9
top_srcdir = @top_srcdir@
basic_SOURCES = basic.S
basic_LDFLAGS = -T$(srcdir)/../default.ld
basic_LDADD = ../except/except.lo \
../support/libsupport.la
 
all: all-am
 
.SUFFIXES:
/trunk/or1ksim/testsuite/test-code-or1k/basic/basic.S
30,62 → 30,11
 
#define MEM_RAM 0x00000000
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
.section .except, "ax"
l.addi r1,r0,0
 
.section .text
 
.org 0x100
_reset:
l.movhi r1,hi(_init_mc)
l.ori r1,r1,lo(_init_mc)
l.jr r1
.global main
main:
l.nop
 
_init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
 
_regs:
l.addi r1,r0,0x1
l.addi r2,r1,0x2
/trunk/or1ksim/testsuite/test-code-or1k/basic/Makefile.am
30,3 → 30,6
basic_SOURCES = basic.S
 
basic_LDFLAGS = -T$(srcdir)/../default.ld
 
basic_LDADD = ../except/except.lo \
../support/libsupport.la
/trunk/or1ksim/testsuite/test-code-or1k/default.ld
28,41 → 28,32
MEMORY
{
except : ORIGIN = 0x00000000, LENGTH = 0x00002000
flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000
ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
}
 
SECTIONS
{
/* Section .except-text guarantees that the code for exception
handling is placed first. For some reason the linker script can't
see the _reset_vector symbol (even if we declare it global), so we
explicitly set it. */
/*
For some reason the linker script can't see the _reset_vector symbol
(even if we declare it global), so we explicitly set it. */
 
.except :
{
_except_beg = .;
*(.except)
_reset_vector = DEFINED (_reset_vector) ? _reset_vector : 0x00000100;
_except_end = .;
} > except
 
.text :
{
*(.except-text)
_src_beg = .;
*(.text)
*(.rodata)
*(.rodata.*)
_reset_vector = DEFINED (_reset_vector) ? _reset_vector : 0x00000100;
_src_beg = .;
} > flash
} > ram
 
.dummy ALIGN(0x4):
{
_src_beg = .;
} > flash
 
.except :
AT ( ADDR (.dummy))
{
_except_beg = .;
*(.except)
_except_end = .;
} > except
 
.data :
AT ( ADDR (.dummy) + SIZEOF (.except))
{
_dst_beg = .;
*(.data)
73,7 → 64,9
 
.bss :
{
_bstart = .;
*(.bss)
_bend = .;
} > ram
 
.stack ALIGN(0x10) (NOLOAD):
/trunk/or1ksim/testsuite/test-code-or1k/except-mc.ld
48,6 → 48,7
_dst_beg = .;
*(.text)
*(.rodata)
*(.rodata.*)
} > ram
 
.data :
/trunk/or1ksim/testsuite/test-code-or1k/except/except.S
25,17 → 25,14
This code is commented throughout for use with Doxygen.
--------------------------------------------------------------------------*/
 
/* Support file for c based tests */
#include "spr-defs.h"
#include "board.h"
 
#define reset reset
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
#define REDZONE_SIZE 128
#define EXCEPT_STACK_SIZE (116 + REDZONE_SIZE)
.section .stack
.space 0x1000
stack:
56,367 → 53,302
.extern excpt_break
.extern excpt_trap
 
 
.section .except, "ax"
.section .except,"ax"
.org 0x100
reset_vector:
l.nop
l.nop
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
l.addi r9,r0,0x0
l.addi r10,r0,0x0
l.addi r11,r0,0x0
l.addi r12,r0,0x0
l.addi r13,r0,0x0
l.addi r14,r0,0x0
l.addi r15,r0,0x0
l.addi r16,r0,0x0
l.addi r17,r0,0x0
l.addi r18,r0,0x0
l.addi r19,r0,0x0
l.addi r20,r0,0x0
l.addi r21,r0,0x0
l.addi r22,r0,0x0
l.addi r23,r0,0x0
l.addi r24,r0,0x0
l.addi r25,r0,0x0
l.addi r26,r0,0x0
l.addi r27,r0,0x0
l.addi r28,r0,0x0
l.addi r29,r0,0x0
l.addi r30,r0,0x0
l.addi r31,r0,0x0
l.j start
l.nop
.org 0x200
buserr_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_buserr)
l.ori r10,r10,lo(excpt_buserr)
l.jr r9
l.lwz r10,0x0(r10)
l.jr r10
l.nop
buserr_vector_end:
 
.org 0x300
dpfault_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
 
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_dpfault)
l.ori r10,r10,lo(excpt_dpfault)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
dpfault_vector_end:
 
.org 0x400
ipfault_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_ipfault)
l.ori r10,r10,lo(excpt_ipfault)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
ipfault_vector_end:
 
.org 0x500
lpint_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_tick)
l.ori r10,r10,lo(excpt_tick)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
lpint_vector_end:
 
.org 0x600
align_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_align)
l.ori r10,r10,lo(excpt_align)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
align_vector_end:
 
.org 0x700
illinsn_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_illinsn)
l.ori r10,r10,lo(excpt_illinsn)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
illinsn_vector_end:
 
.org 0x800
hpint_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_int)
l.ori r10,r10,lo(excpt_int)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
hpint_vector_end:
 
.org 0x900
dtlbmiss_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
 
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_dtlbmiss)
l.ori r10,r10,lo(excpt_dtlbmiss)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
dtlbmiss_vector_end:
 
.org 0xa00
itlbmiss_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_itlbmiss)
l.ori r10,r10,lo(excpt_itlbmiss)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
itlbmiss_vector_end:
 
.org 0xb00
range_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_range)
l.ori r10,r10,lo(excpt_range)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
range_vector_end:
 
.org 0xc00
syscall_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_syscall)
l.ori r10,r10,lo(excpt_syscall)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
syscall_vector_end:
 
.org 0xd00
break_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_break)
l.ori r10,r10,lo(excpt_break)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
break_vector_end:
 
.org 0xe00
trap_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
l.sw 0x20(r1),r10
l.movhi r9,hi(store_regs)
l.ori r9,r9,lo(store_regs)
l.addi r1,r1,-EXCEPT_STACK_SIZE
l.sw 0x18(r1),r9
l.jal store_regs
l.nop
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.movhi r10,hi(excpt_trap)
l.ori r10,r10,lo(excpt_trap)
l.jr r9
l.lwz r10,0(r10)
l.jr r10
l.nop
trap_vector_end:
 
/* Our special text section is used to guarantee this code goes first
when linking. */
.section .except-text
 
.org 0x100
.align 4
reset_vector:
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
l.addi r9,r0,0x0
l.addi r10,r0,0x0
l.addi r11,r0,0x0
l.addi r12,r0,0x0
l.addi r13,r0,0x0
l.addi r14,r0,0x0
l.addi r15,r0,0x0
l.addi r16,r0,0x0
l.addi r17,r0,0x0
l.addi r18,r0,0x0
l.addi r19,r0,0x0
l.addi r20,r0,0x0
l.addi r21,r0,0x0
l.addi r22,r0,0x0
l.addi r23,r0,0x0
l.addi r24,r0,0x0
l.addi r25,r0,0x0
l.addi r26,r0,0x0
l.addi r27,r0,0x0
l.addi r28,r0,0x0
l.addi r29,r0,0x0
l.addi r30,r0,0x0
l.addi r31,r0,0x0
 
l.movhi r3,hi(start)
l.ori r3,r3,lo(start)
l.jr r3
l.nop
.global start
start:
l.jal init_mc
l.nop
 
l.movhi r1,hi(stack)
.section .text
start: l.movhi r1,hi(stack)
l.ori r1,r1,lo(stack)
l.ori r2,r1, 0
 
/* Setup exception wrappers */
l.movhi r3,hi(_src_beg)
l.ori r3,r3,lo(_src_beg)
l.addi r7,r0,0x100
 
1: l.addi r7,r7,0x100
l.sfeqi r7,0xf00
l.bf 1f
/* Call reset() function, in support library, which calls main() */
l.movhi r4,hi(reset)
l.ori r4,r4,lo(reset)
l.jr r4
l.nop
l.addi r4,r7,0
l.addi r5,r0,0
2:
l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,1
l.sfeqi r5,9
l.bf 1b
l.nop
l.j 2b
l.nop
1:
/* Copy data section */
l.movhi r4,hi(_dst_beg)
l.ori r4,r4,lo(_dst_beg)
l.movhi r5,hi(_dst_end)
l.ori r5,r5,lo(_dst_end)
l.sub r5,r5,r4
l.sfeqi r5,0
l.bf 2f
l.nop
1: l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,-4
l.sfgtsi r5,0
l.bf 1b
l.nop
 
2:
 
l.movhi r2,hi(reset)
l.ori r2,r2,lo(reset)
l.jr r2
l.nop
 
init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
store_regs:
l.sw 0x00(r1),r3
l.sw 0x04(r1),r4
l.sw 0x08(r1),r5
l.sw 0x0c(r1),r6
l.sw 0x10(r1),r7
l.sw 0x14(r1),r8
l.sw 0x1c(r1),r10
l.sw 0x20(r1),r11
l.sw 0x24(r1),r12
l.sw 0x28(r1),r13
l.sw 0x2c(r1),r14
l.sw 0x30(r1),r15
l.sw 0x34(r1),r16
l.sw 0x38(r1),r17
l.sw 0x3c(r1),r18
l.sw 0x40(r1),r19
l.sw 0x44(r1),r20
l.sw 0x48(r1),r21
l.sw 0x4c(r1),r22
l.sw 0x50(r1),r23
l.sw 0x54(r1),r24
l.sw 0x58(r1),r25
l.sw 0x5c(r1),r26
l.sw 0x60(r1),r27
l.sw 0x64(r1),r28
l.sw 0x68(r1),r29
l.sw 0x6c(r1),r30
l.sw 0x70(r1),r31
l.jr r9
l.nop
 
store_regs:
l.sw 0x00(r1),r2
l.sw 0x04(r1),r3
l.sw 0x08(r1),r4
l.sw 0x0c(r1),r5
l.sw 0x10(r1),r6
l.sw 0x14(r1),r7
l.sw 0x18(r1),r8
l.sw 0x24(r1),r11
l.sw 0x28(r1),r12
l.sw 0x2c(r1),r13
l.sw 0x30(r1),r14
l.sw 0x34(r1),r15
l.sw 0x38(r1),r16
l.sw 0x3c(r1),r17
l.sw 0x40(r1),r18
l.sw 0x44(r1),r19
l.sw 0x48(r1),r20
l.sw 0x4c(r1),r21
l.sw 0x50(r1),r22
l.sw 0x54(r1),r23
l.sw 0x58(r1),r24
l.sw 0x5c(r1),r25
l.sw 0x60(r1),r26
l.sw 0x64(r1),r27
l.sw 0x68(r1),r28
l.sw 0x6c(r1),r29
l.sw 0x70(r1),r30
l.sw 0x74(r1),r31
l.movhi r9,hi(end_except)
l.ori r9,r9,lo(end_except)
l.lwz r10,0(r10)
l.jr r10
l.nop
 
end_except:
l.lwz r2,0x00(r1)
l.lwz r3,0x04(r1)
l.lwz r4,0x08(r1)
l.lwz r5,0x0c(r1)
l.lwz r6,0x10(r1)
l.lwz r7,0x14(r1)
l.lwz r8,0x18(r1)
l.lwz r9,0x1c(r1)
l.lwz r10,0x20(r1)
l.lwz r11,0x24(r1)
l.lwz r12,0x28(r1)
l.lwz r13,0x2c(r1)
l.lwz r14,0x30(r1)
l.lwz r15,0x34(r1)
l.lwz r16,0x38(r1)
l.lwz r17,0x3c(r1)
l.lwz r18,0x40(r1)
l.lwz r19,0x44(r1)
l.lwz r20,0x48(r1)
l.lwz r21,0x4c(r1)
l.lwz r22,0x50(r1)
l.lwz r23,0x54(r1)
l.lwz r24,0x58(r1)
l.lwz r25,0x5c(r1)
l.lwz r26,0x60(r1)
l.lwz r27,0x64(r1)
l.lwz r28,0x68(r1)
l.lwz r29,0x6c(r1)
l.lwz r30,0x70(r1)
l.lwz r31,0x74(r1)
l.addi r1,r1,120
l.lwz r3,0x00(r1)
l.lwz r4,0x04(r1)
l.lwz r5,0x08(r1)
l.lwz r6,0x0c(r1)
l.lwz r7,0x10(r1)
l.lwz r8,0x14(r1)
l.lwz r9,0x18(r1)
l.lwz r10,0x1c(r1)
l.lwz r11,0x20(r1)
l.lwz r12,0x24(r1)
l.lwz r13,0x28(r1)
l.lwz r14,0x2c(r1)
l.lwz r15,0x30(r1)
l.lwz r16,0x34(r1)
l.lwz r17,0x38(r1)
l.lwz r18,0x3c(r1)
l.lwz r19,0x40(r1)
l.lwz r20,0x44(r1)
l.lwz r21,0x48(r1)
l.lwz r22,0x4c(r1)
l.lwz r23,0x50(r1)
l.lwz r24,0x54(r1)
l.lwz r25,0x58(r1)
l.lwz r26,0x5c(r1)
l.lwz r27,0x60(r1)
l.lwz r28,0x64(r1)
l.lwz r29,0x68(r1)
l.lwz r30,0x6c(r1)
l.lwz r31,0x70(r1)
l.addi r1,r1,EXCEPT_STACK_SIZE
l.rfe
l.nop
 
/trunk/or1ksim/testsuite/test-code-or1k/tick/tick.c
250,8 → 250,11
/* Allow MAX_SPURIOUS spurious spurious interrupt */
if (++tick_cnt == MAX_SPURIOUS)
{
ttmr &= ~SPR_TTMR_IE;
/* Clear mode register completely */
ttmr = 0;
mtspr (SPR_TTMR, ttmr);
}
} /* tick_int_spurious () */
 
574,7 → 577,7
tick_cnt = 0;
clear_ip = 0;
 
ttcr = clear_ttcr ();
clear_ttcr ();
ttmr = new_timer (0x100, SPR_TTMR_CR, SPR_TTMR_IE);
 
while(tick_cnt != MAX_SPURIOUS)
/trunk/or1ksim/testsuite/test-code-or1k/ext/ext.S
27,6 → 27,8
 
#include "spr-defs.h"
 
.section .except,"ax"
 
.org 0x100
l.j start_test
l.nop
117,6 → 119,7
l.bf ext_fail; \
l.nop;
 
.section .text
start_test:
/* Test l.extbs */
CHECK_HIGH3_CLEAR(l.extbs, 0x7f)
/trunk/or1ksim/testsuite/test-code-or1k/cache/cache.ld
28,7 → 28,6
MEMORY
{
except : ORIGIN = 0x00000000, LENGTH = 0x00002000
flash : ORIGIN = 0xf0000000, LENGTH = 0x00200000
ram : ORIGIN = 0x00002000, LENGTH = 0x001fe000
}
38,20 → 37,22
{
*(.reset)
_src_beg = .;
} > flash
} > except
 
.text :
AT ( ADDR (.reset) + SIZEOF (.reset) )
/* AT ( ADDR (.reset) + SIZEOF (.reset) )*/
{
_dst_beg = .;
*(.text)
} > ram
.data :
AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )
/* AT ( ADDR (.reset) + SIZEOF (.reset) + SIZEOF (.text) )*/
{
*(.data)
*(.data.rel)
*(.data.rel.local)
*(.rodata)
*(.rodata.*)
_dst_end = .;
} > ram
.bss :
/trunk/or1ksim/testsuite/test-code-or1k/cache/cache-asm.S
31,13 → 31,6
#define IC_ENABLE 0
#define DC_ENABLE 0
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
 
.extern main
 
.global ic_enable
92,77 → 85,16
l.jr r3
l.nop
start:
l.jal init_mc
l.nop
 
l.movhi r1,hi(stack)
l.ori r1,r1,lo(stack)
 
/* Copy data section */
l.movhi r3,hi(_src_beg)
l.ori r3,r3,lo(_src_beg)
l.movhi r4,hi(_dst_beg)
l.ori r4,r4,lo(_dst_beg)
l.movhi r5,hi(_dst_end)
l.ori r5,r5,lo(_dst_end)
l.sub r5,r5,r4
l.sfeqi r5,0
l.bf 2f
l.ori r2,r1, 0
l.movhi r3,hi(main)
l.ori r3,r3,lo(main)
l.jr r3
l.nop
1: l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,-4
l.sfgtsi r5,0
l.bf 1b
l.nop
2:
l.movhi r2,hi(main)
l.ori r2,r2,lo(main)
l.jr r2
l.nop
 
init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
l.jr r9
l.nop
 
 
.section .text
 
ic_enable:
/trunk/or1ksim/testsuite/test-code-or1k/cache/cache.c
29,124 → 29,38
#include "spr-defs.h"
 
 
#undef UART
 
#define MEM_RAM 0x00100000
 
/* Linker script symbols */
extern unsigned int _ram_end;
 
unsigned int program_ram_end;
 
unsigned int ic_present;
unsigned int dc_present;
 
/* Number of IC sets (power of 2) */
#define IC_SETS 256
#define DC_SETS 256
unsigned int ic_sets;
#define IC_SETS ic_sets
unsigned int dc_sets;
#define DC_SETS dc_sets
 
/* Block size in bytes (1, 2, 4, 8, 16, 32 etc.) */
#define IC_BLOCK_SIZE 16
#define DC_BLOCK_SIZE 16
unsigned int ic_bs;
#define IC_BLOCK_SIZE ic_bs
unsigned int dc_bs;
#define DC_BLOCK_SIZE dc_bs
/* Number of IC ways (1, 2, 3 etc.). */
#define IC_WAYS 1
#define DC_WAYS 1
unsigned int ic_ways;
#define IC_WAYS ic_ways
unsigned int dc_ways;
#define DC_WAYS dc_ways
/* Cache size */
#define IC_SIZE (IC_WAYS*IC_SETS*IC_BLOCK_SIZE)
#define DC_SIZE (DC_WAYS*DC_SETS*DC_BLOCK_SIZE)
 
#if UART
#include "uart.h"
#define IN_CLK 20000000
#define UART_BASE 0x9c000000
#define UART_BAUD_RATE 9600
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR \
(REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
#define print_n(x) \
{ \
uart_putc(s[((x) >> 28) & 0x0f]); \
uart_putc(s[((x) >> 24) & 0x0f]); \
uart_putc(s[((x) >> 20) & 0x0f]); \
uart_putc(s[((x) >> 16) & 0x0f]); \
uart_putc(s[((x) >> 12) & 0x0f]); \
uart_putc(s[((x) >> 8) & 0x0f]); \
uart_putc(s[((x) >> 4) & 0x0f]); \
uart_putc(s[((x) >> 0) & 0x0f]); \
}
 
const char s[] = "0123456789abcdef";
 
void uart_init(void)
{
int devisor;
/* Reset receiver and transmiter */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
/* Disable all interrupts */
REG8(UART_BASE + UART_IER) = 0x00;
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
/* Set baud rate */
devisor = IN_CLK/(16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLL) = devisor & 0x000000ff;
REG8(UART_BASE + UART_DLM) = (devisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
return;
}
 
static inline void uart_putc(char c)
{
unsigned char lsr;
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
if(c == '\n') {
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = '\r';
}
WAIT_FOR_XMITR;
}
 
static inline void print_str(char *str)
{
while(*str != 0) {
uart_putc(*str);
str++;
}
}
 
static inline char uart_getc()
{
unsigned char lsr;
char c;
 
WAIT_FOR_CHAR;
c = REG8(UART_BASE + UART_RX);
return c;
}
#endif
 
extern void ic_enable(void);
extern void ic_disable(void);
extern void dc_enable(void);
162,7 → 76,8
unsigned long jump_indx;
 
/* Jump address table */
unsigned long jump_add[15*IC_WAYS];
#define MAX_IC_WAYS 32
unsigned long jump_addr[15*MAX_IC_WAYS];
 
void dummy();
 
201,6 → 116,61
asm("l.nop" : :);
}
 
/* Determine cache configuration from cache configuration registers */
void init_cache_config(void)
{
 
unsigned long iccfgr, dccfgr;
unsigned long upr;
 
ic_present = dc_present = 0;
upr = mfspr (SPR_UPR);
 
if (!(upr & SPR_UPR_ICP))
{
printf("No instruction cache present. Skipping tests.\n");
}
else
{
iccfgr = mfspr (SPR_ICCFGR);
/* Number of ways */
ic_ways = (1 << (iccfgr & SPR_ICCFGR_NCW));
/* Number of sets */
ic_sets = 1 << ((iccfgr & SPR_ICCFGR_NCS) >>
SPR_ICCFGR_NCS_OFF);
/* Block size */
ic_bs = 16 << ((iccfgr & SPR_ICCFGR_CBS) >> SPR_ICCFGR_CBS_OFF);
 
ic_present = 1;
}
 
if (!(upr & SPR_UPR_DCP))
{
printf("No data cache present. Skipping tests.\n");
}
else
{
dccfgr = mfspr (SPR_DCCFGR);
/* Number of ways */
dc_ways = (1 << (dccfgr & SPR_DCCFGR_NCW));
/* Number of sets */
dc_sets = 1 << ((dccfgr & SPR_DCCFGR_NCS) >>
SPR_DCCFGR_NCS_OFF);
/* Block size */
dc_bs = 16 << ((dccfgr & SPR_DCCFGR_CBS) >> SPR_DCCFGR_CBS_OFF);
 
dc_present = 1;
}
}
 
int dc_test(void)
{
int i;
299,55 → 269,60
int ic_test(void)
{
int i;
unsigned long base, add;
unsigned long base, addr;
base = (((unsigned long)MEM_RAM / (IC_SETS*IC_BLOCK_SIZE)) * IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
base = (((unsigned int)program_ram_end / (IC_SETS*IC_BLOCK_SIZE)) *
IC_SETS*IC_BLOCK_SIZE) + IC_SETS*IC_BLOCK_SIZE;
//printf("ic_test\n");
//printf("Test program from base at 0x%08x\n",(unsigned int)base);
/* Copy jr to various location */
add = base;
addr = base;
for(i = 0; i < IC_WAYS; i++) {
copy_jr(add);
copy_jr(add + 2*IC_BLOCK_SIZE + 4);
copy_jr(add + 4*IC_BLOCK_SIZE + 8);
copy_jr(add + 6*IC_BLOCK_SIZE + 12);
copy_jr(addr);
copy_jr(addr + 2*IC_BLOCK_SIZE + 4);
copy_jr(addr + 4*IC_BLOCK_SIZE + 8);
copy_jr(addr + 6*IC_BLOCK_SIZE + 12);
copy_jr(add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);
copy_jr(add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);
copy_jr(add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);
copy_jr(add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);
add += IC_SETS*IC_BLOCK_SIZE;
copy_jr(addr + (IC_SETS - 2)*IC_BLOCK_SIZE + 0);
copy_jr(addr + (IC_SETS - 4)*IC_BLOCK_SIZE + 4);
copy_jr(addr + (IC_SETS - 6)*IC_BLOCK_SIZE + 8);
copy_jr(addr + (IC_SETS - 8)*IC_BLOCK_SIZE + 12);
addr += IC_SETS*IC_BLOCK_SIZE;
}
/* Load execution table which starts at address 4 (at address 0 is table index) */
add = base;
/* Load execution table which starts at address 4
(at address 0 is table index) */
addr = base;
for(i = 0; i < IC_WAYS; i++) {
/* Cache miss */
jump_add[15*i + 0] = add + 2*IC_BLOCK_SIZE + 4;
jump_add[15*i + 1] = add + 4*IC_BLOCK_SIZE + 8;
jump_add[15*i + 2] = add + 6*IC_BLOCK_SIZE + 12;
jump_addr[15*i + 0] = addr + 2*IC_BLOCK_SIZE + 4;
jump_addr[15*i + 1] = addr + 4*IC_BLOCK_SIZE + 8;
jump_addr[15*i + 2] = addr + 6*IC_BLOCK_SIZE + 12;
/* Cache hit/miss */
jump_add[15*i + 3] = add;
jump_add[15*i + 4] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
jump_add[15*i + 5] = add + 2*IC_BLOCK_SIZE + 4;
jump_add[15*i + 6] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
jump_add[15*i + 7] = add + 4*IC_BLOCK_SIZE + 8;
jump_add[15*i + 8] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
jump_add[15*i + 9] = add + 6*IC_BLOCK_SIZE + 12;
jump_add[15*i + 10] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
jump_addr[15*i + 3] = addr;
jump_addr[15*i + 4] = addr + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
jump_addr[15*i + 5] = addr + 2*IC_BLOCK_SIZE + 4;
jump_addr[15*i + 6] = addr + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
jump_addr[15*i + 7] = addr + 4*IC_BLOCK_SIZE + 8;
jump_addr[15*i + 8] = addr + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
jump_addr[15*i + 9] = addr + 6*IC_BLOCK_SIZE + 12;
jump_addr[15*i + 10] = addr + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
/* Cache hit */
jump_add[15*i + 11] = add + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
jump_add[15*i + 12] = add + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
jump_add[15*i + 13] = add + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
jump_add[15*i + 14] = add + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
jump_addr[15*i + 11] = addr + (IC_SETS - 2)*IC_BLOCK_SIZE + 0;
jump_addr[15*i + 12] = addr + (IC_SETS - 4)*IC_BLOCK_SIZE + 4;
jump_addr[15*i + 13] = addr + (IC_SETS - 6)*IC_BLOCK_SIZE + 8;
jump_addr[15*i + 14] = addr + (IC_SETS - 8)*IC_BLOCK_SIZE + 12;
 
add += IC_SETS*IC_BLOCK_SIZE;
addr += IC_SETS*IC_BLOCK_SIZE;
}
/* Go home */
jump_add[15*i] = (unsigned long)&jalr;
/* Warning - if using all 32 sets, the SET_MAX define above will need
to be incremented*/
jump_addr[15*i] = (unsigned long)&jalr;
/* Initilalize table index */
jump_indx = (unsigned long)&jump_add[0];
jump_indx = (unsigned long)&jump_addr[0];
ic_enable();
 
365,67 → 340,61
{
unsigned long rc, ret = 0;
 
#ifdef UART
/* Initialize controller */
uart_init();
#endif
program_ram_end = (unsigned int)&_ram_end;
program_ram_end += 4;
 
#ifdef UART
print_str("DC test : ");
#endif
rc = dc_test();
ret += rc;
#ifdef UART
print_n(rc+0xdeaddca1);
print_str("\n");
#else
report(rc + 0xdeaddca1);
#endif
#ifdef UART
print_str("DC invalidate test : ");
#endif
rc = dc_inv_test(MEM_RAM);
ret += rc;
#ifdef UART
print_n(rc + 0x9e8daa91);
print_str("\n");
#else
report(rc + 0x9e8daa91);
#endif
 
#ifdef UART
print_str("IC test : ");
#endif
rc = ic_test();
ret += rc;
#ifdef UART
print_n(rc + 0xdeaddead);
print_str("\n");
#else
report(rc + 0xdeaddead);
#endif
/* Read UPR and configuration registers, extract cache settings */
init_cache_config();
 
if (dc_present)
{
report(0);
rc = dc_test();
ret += rc;
 
#ifdef UART
print_str("IC invalidate test : ");
#endif
ic_enable();
rc = ic_inv_test();
ret += rc;
#ifdef UART
print_n(rc + 0xdeadde8f);
print_str("\n");
while(1);
#else
report(rc + 0xdeadde8f);
#endif
report(rc + 0xdeaddca1);
report(1);
rc = dc_inv_test(MEM_RAM);
ret += rc;
report(rc + 0x9e8daa91);
}
 
if (ic_present)
{
report(2);
rc = ic_test();
ret += rc;
report(rc + 0xdeaddead);
 
report(ret + 0x9e8da867);
exit(0);
report(3);
ic_enable();
report(4);
rc = ic_inv_test();
ret += rc;
report(rc + 0xdeadde8f);
report(ret + 0x9e8da867);
}
exit(0);
 
return 0;
 
}
 
/* just for size calculation */
/trunk/or1ksim/testsuite/test-code-or1k/configure.ac
81,12 → 81,12
AC_PROG_INSTALL
 
# Specify our baseline CFLAGS
CPPFLAGS="-I\${top_srcdir}/support -I\${top_srcdir}/mc-common"
CPPFLAGS="-I\${top_srcdir}/support -I\${top_srcdir}/except"
CFLAGS="-Wall -Werror -g -nostdlib -mhard-div -mhard-mul"
 
# Flag to specify whether we want optimization when checking
AC_MSG_CHECKING(whether to enable optimizations when checking)
AC_ARG_ENABLE(opt,
AC_ARG_ENABLE(check-opt,
[ --enable-check-opt enable optimizations
--enable-check-opt=level same as gcc -O switch ], [
case "$enableval" in
/trunk/or1ksim/testsuite/test-code-or1k/fp/fp.S
46,7 → 46,7
/* ----------------------------------------------------------------------------
* Coding conventions
*
* A simple rising stack is provided to starting at _stack and pointed to by
v * A simple rising stack is provided to starting at _stack and pointed to by
* r1. r1 points to the next free word. Only 32-bit registers may be pushed
* onto the stack.
*
67,12 → 67,6
 
#define MEM_RAM 0x00000000
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
/* ----------------------------------------------------------------------------
* Floating point constants (IEEE 754)
*
355,20 → 349,46
/* ----------------------------------------------------------------------------
* reset exception
* ------------------------------------------------------------------------- */
.section .except, "ax"
l.addi r1,r0,0
.section .text
.section .except,"ax"
 
.org 0x100
_reset:
l.movhi r1,hi(_stack) /* Set up the stack */
l.ori r1,r1,lo(_stack)
l.movhi r3,hi(_init_mc) /* Code starts with MC setup */
l.ori r3,r3,lo(_init_mc)
l.movhi r3,hi(start) /* Jump to test start */
l.ori r3,r3,lo(start)
l.jr r3
l.nop
 
.org 0x700
illegal_insn:
l.nop
.section .rodata ;\
1: ;\
.string "Illegal instruction. Enable hardware FPU.\n" ;\
;\
.section .except,"ax" ;\
l.movhi r3,hi(1b) ;\
l.ori r3,r3,lo(1b)
l.jal _puts
l.nop
 
.section .rodata ;\
1: ;\
.string "Exiting.\n" ;\
;\
.section .except,"ax" ;\
l.movhi r3,hi(1b) ;\
l.ori r3,r3,lo(1b)
l.jal _puts
l.nop
 
l.addi r3,r0,1
l.nop NOP_EXIT
 
.section .text
/* ----------------------------------------------------------------------------
* Subroutine to print out a string
*
492,48 → 512,15
l.jr r9
 
/* ----------------------------------------------------------------------------
* Memory controller initialization initialization
* Start of tests
* ------------------------------------------------------------------------- */
_init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
start:
/* ----------------------------------------------------------------------------
* Test of single precision add: lf.add.s
* ------------------------------------------------------------------------- */
.section .text
 
_add_s:
LOAD_STR (r3, "lf.add.s\n")
l.jal _puts
/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.in
218,6 → 218,7
mc_dram_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_dram_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-dram/Makefile.am
33,6 → 33,7
mc_dram_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_dram_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.in
218,6 → 218,7
mc_ssram_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_ssram_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/mc-ssram.c
95,7 → 95,7
unsigned char ch;
 
unsigned long test;
unsigned long gpio_pat;
unsigned long gpio_pat = 0;
 
unsigned long nAddress;
unsigned long nMemSize;
/trunk/or1ksim/testsuite/test-code-or1k/mc-ssram/Makefile.am
33,6 → 33,7
mc_ssram_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_ssram_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mul/mul.c
37,6 → 37,8
#define MACRC macrc()
static inline long macrc() {
long x;
asm volatile ("l.nop\t");
asm volatile ("l.nop\t");
asm volatile ("l.macrc\t%0" : "=r" (x));
return x;
}
/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu.c
27,26 → 27,65
 
/* This is MMU test for OpenRISC 1200 */
 
// Tests most functions of the MMUs.
// The tests attempt to keep the areas of instruction and data memory working
// as they should, while testing around them, higher in memory. Some linker
// variables are relied upon by the interrupt routines for checking if areas
// are within the expected text areas of memory, but usually we just keep
// above the stack (also set in the linker script) and things go OK.
 
// The tests for translation setup address translation in the MMU from areas
// in the 512kB - 1024kB region (64 sets in OR1200, 8kByte per set) to halfway
// through RAM. Usually the sets taht would encompass the actual program are
// skipped (TLB_TEXT_SET_NB) ie, we say how many sets encompass the program
// text for itlb tests and only do tests above it (so, on sets 8-64, meaning
// when we enable the iMMU and say have the execution bits disabled to force a
// page fault the program gets to continue and is translated 1-1 while
// accesses to the areas we are testing will cause a page fault) but it should
// still work to test all sets.
 
// In essense, the tests are aware that they could be operating out of the
// same memory the tests are being performed in and takes care of this.
 
// The use of the "match_space" variable is for the addresses we'll access
// when a non-1-1 translation will occur, otherwise usually the
// "translate_space" variable by itself is used (it's first setup to the
// desired address, and either data or the return instructions are placed
// where we expect the MMU to translate to)
 
#include "spr-defs.h"
#include "support.h"
 
// Set this to 1 to enable the DMMU tests
#define DO_DMMU_TESTS 1
 
// Symbols defined in linker script
extern unsigned long _ram_end;
extern unsigned long _src_beg;
 
unsigned long text_begin_addr;
unsigned long end_data_addr;
 
/* For shorter simulation run */
#define RTL_SIM 1
 
/* Define RAM physical location and size
Bottom half will be used for this program, the rest
will be used for testing */
#define FLASH_START 0xf0000000
#define FLASH_SIZE 0x00200000
Bottom half will be used for this program, the rest
will be used for testing */
#define RAM_START 0x00000000
// Assume only 2MB memory
#define RAM_SIZE 0x00200000
 
#define VM_BASE 0xc0000000
 
/* What is the last address in ram that is used by this program */
#define TEXT_END_ADD (FLASH_START + (FLASH_SIZE / 2))
#define DATA_END_ADD (RAM_START + (RAM_SIZE / 2))
#define TEXT_START_ADD text_begin_addr
#define TEXT_END_ADD end_data_addr
#define DATA_END_ADD end_data_addr
 
#define TLB_TEXT_SET_NB 8
#define TLB_DATA_SET_NB 4
// Uncomment the following to determine the page to test from at run-time
unsigned long TLB_TEXT_SET_NB;
unsigned long TLB_DATA_SET_NB;
 
/* MMU page size */
#define PAGE_SIZE 8192
53,7 → 92,7
 
/* Number of DTLB sets used (power of 2, max is 256) */
#define DTLB_SETS 64
 
/* Number of DTLB ways (1, 2, 3 etc., max is 4). */
#define DTLB_WAYS 1
 
78,30 → 117,23
#define ITLB_PR_NOLIMIT (SPR_ITLBTR_SXE | \
SPR_ITLBTR_UXE )
 
#if 1
#define debug printf
#else
#define debug
#endif
 
 
/* fails if x is false */
#define ASSERT(x) ((x)?1: fail (__FUNCTION__, __LINE__))
 
//#define TEST_JUMP(x) testjump( ((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD, (x))
#define TEST_JUMP(x) copy_jump (((x) & (RAM_SIZE/2 - 1)) + DATA_END_ADD); call (x)
 
/* Extern functions */
// iMMU and dMMU enable functions
extern void lo_dmmu_en (void);
extern void lo_immu_en (void);
extern int lo_dtlb_ci_test (unsigned long, unsigned long);
extern int lo_itlb_ci_test(unsigned long, unsigned long);
extern void testjump(unsigned long phy_addr, unsigned long virt_addr);
extern void (*jr)(void);
 
/* Local functions prototypes */
void dmmu_disable (void);
void immu_disable (void);
 
// Machine code for l.jr r9 and then l.nop
#define OR32_L_JR_R9 0x44004800
#define OR32_L_NOP 0x15000000
 
/* Global variables */
extern unsigned long ram_end;
 
135,11 → 167,14
/* EA of last insn page fault exception */
unsigned long ipage_fault_ea;
 
 
#define sys_call() __asm__ __volatile__("l.sys\t0");
/*
void sys_call (void)
{
asm("l.sys\t0");
}
 
*/
void fail (char *func, int line)
{
#ifndef __FUNCTION__
152,7 → 187,7
immu_disable ();
dmmu_disable ();
 
debug("Test failed in %s:%i\n", func, line);
report(line);
report (0xeeeeeeee);
exit (1);
}
159,20 → 194,21
 
void call(unsigned long add)
{
asm("l.jalr\t\t%0" : : "r" (add) : "r9", "r11");
asm("l.nop" : :);
asm("l.jalr\t\t%0" : : "r" (add) : "r9", "r11");
asm("l.nop" : :);
}
 
void jump(void)
{
asm("jr:");
asm("l.jr\t\tr9") ;
asm("l.nop" : :);
return;
/*asm("_jr:");
asm("l.jr\t\tr9") ;
asm("l.nop" : :);*/
}
 
void copy_jump(unsigned long phy_add)
{
memcpy((void *)phy_add, (void *)&jr, 8);
memcpy((void *)phy_add, (void *)&jump, (8*4));
}
 
/* Bus error exception handler */
179,7 → 215,7
void bus_err_handler (void)
{
/* This shouldn't happend */
debug("Test failed: Bus error\n");
printf("Test failed: Bus error\n");
report (0xeeeeeeee);
exit (1);
}
188,7 → 224,7
void ill_insn_handler (void)
{
/* This shouldn't happend */
debug("Test failed: Illegal insn\n");
printf("Test failed: Illegal insn\n");
report (0xeeeeeeee);
exit (1);
}
219,9 → 255,10
}
}
 
debug("ea = %08lx set = %d way = %d\n", ea, set, way);
printf("dtlb miss ea = %.8lx set = %d way = %d\n", ea, set, way);
 
if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) || ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {
// Anything under the stack belongs to the program, direct tranlsate it
if (ea < (unsigned long)&_ram_end){
/* If this is acces to data of this program set one to one translation */
mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | DTLB_PR_NOLIMIT);
232,10 → 269,10
dtlb_miss_count++;
dtlb_miss_ea = ea;
 
/* Whatever access is in progress, translated address have to point to physical RAM */
ta = (ea & ((RAM_SIZE/2) - 1)) + RAM_START + (RAM_SIZE/2);
// Everything gets translated back to the space halfway through RAM
ta = (set*PAGE_SIZE) + RAM_START + (RAM_SIZE/2);
tlbtr = (ta & SPR_DTLBTR_PPN) | (dtlb_val & TLB_PR_MASK);
debug("tlbtr = %08lx dtlb_val = %08lx\n", tlbtr, dtlb_val);
printf("ta = %.8lx tlbtr = %.8lx dtlb_val = %.8lx\n",ta, tlbtr, dtlb_val);
 
/* Set DTLB entry */
mtspr (SPR_DTLBMR_BASE(way) + set, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
255,15 → 292,17
/* Find TLB set and way */
set = (ea / PAGE_SIZE) % DTLB_SETS;
for (i = 0; i < DTLB_WAYS; i++) {
if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) == (ea & SPR_DTLBMR_VPN)) {
if ((mfspr (SPR_DTLBMR_BASE(i) + set) & SPR_DTLBMR_VPN) ==
(ea & SPR_DTLBMR_VPN)) {
way = i;
break;
}
}
 
debug("ea = %08lx set = %d way = %d\n", ea, set, way);
printf("ea = %.8lx set = %d way = %d\n", ea, set, way);
 
if (((RAM_START <= ea) && (ea < DATA_END_ADD) ) || ((FLASH_START <= ea) && (ea < TEXT_END_ADD))) {
if (((RAM_START <= ea) & (ea < DATA_END_ADD) ) |
((TEXT_START_ADD <= ea) & (ea < TEXT_END_ADD))) {
/* If this is acces to data of this program set one to one translation */
mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | DTLB_PR_NOLIMIT);
return;
274,7 → 313,8
dpage_fault_ea = ea;
 
/* Give permission */
mtspr (SPR_DTLBTR_BASE(way) + set, (mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);
mtspr (SPR_DTLBTR_BASE(way) + set,
(mfspr (SPR_DTLBTR_BASE(way) + set) & ~DTLB_PR_NOLIMIT) | dtlb_val);
}
 
297,9 → 337,9
}
}
 
debug("ea = %08lx set = %d way = %d\n", ea, set, way);
printf("itlb miss ea = %.8lx set = %d way = %d\n", ea, set, way);
 
if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {
if ((TEXT_START_ADD <= ea) && (ea < TEXT_END_ADD)) {
/* If this is acces to data of this program set one to one translation */
mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(way) + set, (ea & SPR_ITLBTR_PPN) | ITLB_PR_NOLIMIT);
310,11 → 350,13
itlb_miss_count++;
itlb_miss_ea = ea;
 
/* Whatever access is in progress, translated address have to point to physical RAM */
ta = (ea & ((RAM_SIZE/2) - 1)) + DATA_END_ADD;
/* Whatever access is in progress, translated address have to point to
physical RAM */
 
ta = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
tlbtr = (ta & SPR_ITLBTR_PPN) | (itlb_val & TLB_PR_MASK);
 
debug("ta = %08lx\n", ta);
printf("ta = %.8lx\n", ta);
 
/* Set ITLB entry */
mtspr (SPR_ITLBMR_BASE(way) + set, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
340,14 → 382,16
}
}
 
debug("ea = %08lx set = %d way = %d\n", ea, set, way);
printf("ipage fault: ea = %.8lx set = %d way = %d\n", ea, set, way);
 
if ((FLASH_START <= ea) && (ea < TEXT_END_ADD)) {
if ((TEXT_START_ADD <= ea) && (ea < TEXT_END_ADD)) {
/* If this is acces to data of this program set one to one translation */
mtspr (SPR_DTLBTR_BASE(way) + set, (ea & SPR_DTLBTR_PPN) | ITLB_PR_NOLIMIT);
return;
}
 
printf("ipage fault was outside of code area\n");
/* Update instruction page fault counter and EA */
ipage_fault_count++;
ipage_fault_ea = ea;
360,13 → 404,16
void dmmu_enable (void)
{
/* Register DTLB miss handler */
excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
//add_handler(0x9, dtlb_miss_handler);
excpt_dtlbmiss = (unsigned long)dtlb_miss_handler;
 
/* Register data page fault handler */
//add_handler(0x3, dpage_fault_handler);
excpt_dpfault = (unsigned long)dpage_fault_handler;
 
/* Enable DMMU */
lo_dmmu_en ();
 
}
 
/* Disable DMMU */
379,13 → 426,16
void immu_enable (void)
{
/* Register ITLB miss handler */
//add_handler(0xa, itlb_miss_handler);
excpt_itlbmiss = (unsigned long)itlb_miss_handler;
 
/* Register instruction page fault handler */
//add_handler(0x4, ipage_fault_handler);
excpt_ipfault = (unsigned long)ipage_fault_handler;
 
/* Enable IMMU */
lo_immu_en ();
 
}
 
/* Disable IMMU */
407,7 → 457,7
}
 
/* Translation address register test
Set various translation and check the pattern */
Set various translation and check the pattern */
int dtlb_translation_test (void)
{
int i, j;
416,6 → 466,8
/* Disable DMMU */
dmmu_disable();
 
printf("dtlb translation test set\n");
 
/* Invalidate all entries in DTLB */
for (i = 0; i < DTLB_WAYS; i++) {
for (j = 0; j < DTLB_SETS; j++) {
424,12 → 476,12
}
}
 
/* Set one to one translation for the use of this program */
/* Set one to one translation for program's data space */
for (i = 0; i < TLB_DATA_SET_NB; i++) {
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
mtspr (SPR_DTLBTR_BASE(0) + i, ta | (DTLB_PR_NOLIMIT));
}
 
/* Set dtlb permisions */
437,11 → 489,13
 
/* Write test pattern */
for (i = 0; i < DTLB_SETS; i++) {
REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = i;
REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
REG32(ea) = i;
ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
REG32(ea) = 0xffffffff - i;
}
/* Set one to one translation of the last way of DTLB */
/* Set one to one translation */
for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
462,8 → 516,10
 
/* Write new pattern */
for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {
REG32(RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE)) = 0xffffffff - i;
REG32(RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4) = i;
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
REG32(ea) = 0xffffffff - i;
ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
REG32(ea) = i;
}
 
/* Set 0 -> RAM_START + (RAM_SIZE/2) translation */
485,13 → 541,14
/* Write new pattern */
for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {
REG32(i*PAGE_SIZE) = i;
REG32(((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;
REG32(((i + 1)*PAGE_SIZE) - 4) = 0xffffffff - i;
}
 
/* Set hi -> lo, lo -> hi translation */
for (i = TLB_DATA_SET_NB; i < DTLB_SETS; i++) {
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + ((DTLB_SETS - i - 1 + TLB_DATA_SET_NB)*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + ((DTLB_SETS - i - 1 + TLB_DATA_SET_NB)*
PAGE_SIZE);
mtspr (SPR_DTLBMR_BASE(DTLB_WAYS - 1) + i, ea | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(DTLB_WAYS - 1) + i, ta | DTLB_PR_NOLIMIT);
}
520,22 → 577,30
ea = RAM_START + (RAM_SIZE/2) + ((i + 1)*PAGE_SIZE) - 4;
ASSERT(REG32(ea) == (DTLB_SETS - i - 1 + TLB_DATA_SET_NB));
}
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
 
/* EA match register test
Shifting one in DTLBMR and performing accesses to boundaries
of the page, checking the triggering of exceptions */
Shifting one in DTLBMR and performing accesses to boundaries
of the page, checking the triggering of exceptions */
int dtlb_match_test (int way, int set)
{
int i, j, tmp;
unsigned long add, t_add;
unsigned long large_offset_addr;
unsigned long ea, ta;
unsigned long match_space;
unsigned long translate_space;
unsigned long program_space_offset;
 
/* Disable DMMU */
dmmu_disable();
 
printf("dtlb_match_test - way %d set %d\n",way, set);
 
/* Invalidate all entries in DTLB */
for (i = 0; i < DTLB_WAYS; i++) {
for (j = 0; j < DTLB_SETS; j++) {
544,7 → 609,7
}
}
 
/* Set one to one translation for the use of this program */
// Program text/data pages should be 1-1 translation
for (i = 0; i < TLB_DATA_SET_NB; i++) {
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
555,11 → 620,28
/* Set dtlb permisions */
dtlb_val = DTLB_PR_NOLIMIT;
 
// Determine offset required to skip past area in use by program
program_space_offset = 0;
while (program_space_offset <= DATA_END_ADD)
program_space_offset += (PAGE_SIZE*DTLB_SETS);
 
// Setup match area address - based at halfway through RAM,
// and then offset by the area encompassed by the set we wish to test.
// TODO: Ensure this is on a page boundary
translate_space = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
 
/* Set pattern */
REG32(RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE) - 4) = 0x00112233;
REG32(RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE)) = 0x44556677;
REG32(RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE - 4) = 0x8899aabb;
REG32(RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE) = 0xccddeeff;
// Last word of page before the one covered by this set
REG32(translate_space - 4) = 0x00112233;
 
// First word of page covered by this set
REG32(translate_space) = 0x44556677;
 
// Last word of page covered by this set
REG32(translate_space + PAGE_SIZE - 4) = 0x8899aabb;
 
// First word of page covered by next set
REG32(translate_space + PAGE_SIZE) = 0xccddeeff;
/* Enable DMMU */
dmmu_enable();
566,43 → 648,61
 
/* Shifting one in DTLBMR */
i = 0;
add = (PAGE_SIZE*DTLB_SETS);
t_add = add + (set*PAGE_SIZE);
while (add != 0x00000000) {
mtspr (SPR_DTLBMR_BASE(way) + set, t_add | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(way) + set, (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE)) | DTLB_PR_NOLIMIT);
 
// Setup match space - place we will do accesses to, and have them
// tranlsated into the translate space addresses. Ensure it is above the end
// of the program's space.
match_space = program_space_offset + (set*PAGE_SIZE);
// This is used to provide a large match offset (ie. virtual address)
// We will offset the match address by this each time. This value is
// shifted left after each test, ensuring the high bits of address are
// tested.
large_offset_addr = (PAGE_SIZE*DTLB_SETS); // 8kB * 64, 512KB
 
while (large_offset_addr != 0x00000000) {
// Set MATCH register for the areas we will access explicitly, and
// validate them.
mtspr (SPR_DTLBMR_BASE(way) + set, match_space | SPR_DTLBMR_V);
 
// Set TRANSLATE register to the areas where we have set our data
mtspr (SPR_DTLBTR_BASE(way) + set, translate_space | DTLB_PR_NOLIMIT);
 
/* Reset DTLB miss counter and EA */
dtlb_miss_count = 0;
dtlb_miss_ea = 0;
 
if (((t_add < RAM_START) || (t_add >= DATA_END_ADD)) && ((t_add < FLASH_START) || (t_add >= TEXT_END_ADD))) {
 
printf("testing match space %8lx translate space %8lx\n",match_space,
translate_space);
// Only do the test if we won't tread on any memory being used for data
// and stack. It is unlikely this would occur.
if (match_space > DATA_END_ADD){
/* Read last address of previous page */
tmp = REG32(t_add - 4);
tmp = REG32(match_space - 4);
ASSERT(tmp == 0x00112233);
ASSERT(dtlb_miss_count == 1);
/* Read first address of the page */
tmp = REG32(t_add);
tmp = REG32(match_space);
ASSERT(tmp == 0x44556677);
ASSERT(dtlb_miss_count == 1);
/* Read last address of the page */
tmp = REG32(t_add + PAGE_SIZE - 4);
tmp = REG32(match_space + PAGE_SIZE - 4);
ASSERT(tmp == 0x8899aabb);
ASSERT(dtlb_miss_count == 1);
 
/* Read first address of next page */
tmp = REG32(t_add + PAGE_SIZE);
tmp = REG32(match_space + PAGE_SIZE);
ASSERT(tmp == 0xccddeeff);
ASSERT(dtlb_miss_count == 2);
}
 
i++;
add = (PAGE_SIZE*DTLB_SETS) << i;
t_add = add + (set*PAGE_SIZE);
large_offset_addr = (PAGE_SIZE*DTLB_SETS) << i;
match_space = large_offset_addr + program_space_offset + (set*PAGE_SIZE);
 
// Clear MR/T for space we just tested
for (j = 0; j < DTLB_WAYS; j++) {
mtspr (SPR_DTLBMR_BASE(j) + ((set - 1) & (DTLB_SETS - 1)), 0);
mtspr (SPR_DTLBMR_BASE(j) + ((set + 1) & (DTLB_SETS - 1)), 0);
612,13 → 712,16
/* Disable DMMU */
dmmu_disable();
 
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
/* Valid bit test
Set all ways of one set to be invalid, perform
access so miss handler will set them to valid,
try access again - there should be no miss exceptions */
Set all ways of one set to be invalid, perform
access so miss handler will set them to valid,
try access again - there should be no miss exceptions */
int dtlb_valid_bit_test (int set)
{
int i, j;
627,6 → 730,8
/* Disable DMMU */
dmmu_disable();
 
printf("dtlb_valid_bit_test, set %d\n", set);
 
/* Invalidate all entries in DTLB */
for (i = 0; i < DTLB_WAYS; i++) {
for (j = 0; j < DTLB_SETS; j++) {
696,18 → 801,23
/* Disable DMMU */
dmmu_disable();
 
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
 
/* Permission test
Set various permissions, perform r/w access
in user and supervisor mode and chack triggering
of page fault exceptions */
int dtlb_premission_test (int set)
Set various permissions, perform r/w access
in user and supervisor mode and chack triggering
of page fault exceptions */
int dtlb_permission_test (int set)
{
int i, j;
unsigned long ea, ta, tmp;
 
printf("dtlb_permission_test, set %d\n", set);
 
/* Disable DMMU */
dmmu_disable();
 
813,19 → 923,33
/* Disable DMMU */
dmmu_disable();
 
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
 
/* Data cache inhibit bit test
Set and clear CI bit and check the pattern. */
int dtlb_ci_test (void)
{
 
/* Dcache test - check inhibit
Write data with cache inhibit on and off, check for coherency
*/
int dtlb_dcache_test (int set)
{
int i, j;
unsigned long ea, ta, ret;
unsigned long ea, ta, vmea;
 
// Check data cache is present and enabled
if (!(mfspr(SPR_UPR)& SPR_UPR_DCP))
return 0;
if (!(mfspr(SPR_SR) & SPR_SR_DCE))
return 0;
 
printf("dtlb_dcache_test, set %d\n", set);
 
/* Disable DMMU */
dmmu_disable();
 
/* Invalidate all entries in DTLB */
for (i = 0; i < DTLB_WAYS; i++) {
for (j = 0; j < DTLB_SETS; j++) {
833,44 → 957,86
mtspr (SPR_DTLBTR_BASE(i) + j, 0);
}
}
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_DATA_SET_NB; i++) {
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
mtspr (SPR_DTLBMR_BASE(0) + i, ea | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
}
mtspr (SPR_DTLBTR_BASE(0) + i, ta | DTLB_PR_NOLIMIT);
}
 
/* Testing page */
ea = RAM_START + (RAM_SIZE/2) + (TLB_DATA_SET_NB*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + (TLB_DATA_SET_NB*PAGE_SIZE);
/* Write test pattern */
REG32(ea) = 0x01234567;
REG32(ea + PAGE_SIZE - 4) = 0x9abcdef;
/* Set one to one translation with CI bit for testing area */
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, ea | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
ret = lo_dtlb_ci_test(ea, TLB_DATA_SET_NB);
ASSERT(ret == 0);
ea = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
 
ta = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
 
vmea = VM_BASE + RAM_START + (RAM_SIZE/2) + ((DTLB_SETS-1)*PAGE_SIZE);
 
// Set a 1-1 translation for this page without cache inhibited
 
/* Set match register */
mtspr (SPR_DTLBMR_BASE(0) + set, ea | SPR_DTLBMR_V);
/* Set translate register */
mtspr (SPR_DTLBTR_BASE(0) + set, ta | DTLB_PR_NOLIMIT);
 
// Now set a far-off translation, VM_BASE, for this page with cache inhibited
// Use the last set
 
/* Set match register */
mtspr (SPR_DTLBMR_BASE(0) + (DTLB_SETS-1),
vmea | SPR_DTLBMR_V);
/* Set translate register */
mtspr (SPR_DTLBTR_BASE(0) + (DTLB_SETS-1),
ta | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
/* Enable DMMU */
dmmu_enable();
// First do a write with the cache inhibited mapping
unsigned long int testwrite_to_be_cached = 0xfeca1d0d ^ set;
REG32((vmea)) = testwrite_to_be_cached;
// Read it back to check that it's the same, this read should get cached
ASSERT(REG32(ea) == testwrite_to_be_cached);
// Now write again to the cache inhibited location
unsigned long int testwrite_not_to_be_cached = 0xbaadbeef ^ set;
REG32((vmea)) = testwrite_not_to_be_cached;
// Now check that the cached mapping doesn't read this value back
ASSERT(REG32(ea) == testwrite_to_be_cached);
// Now disable cache inhibition on the 1-1 mapping
/* Set translate register */
mtspr (SPR_DTLBTR_BASE(0) + set,
ea | DTLB_PR_NOLIMIT | SPR_DTLBTR_CI);
 
// Check that we now get the second value we wrote
testwrite_to_be_cached = testwrite_not_to_be_cached;
ASSERT(REG32(ea) == testwrite_to_be_cached);
/* Disable DMMU */
dmmu_disable();
 
printf("OK\n");
printf("-------------------------------------------\n");
return 0;
 
}
 
/* Translation address register test
Set various translation and check the pattern */
Set various translation and check the pattern */
int itlb_translation_test (void)
{
int i, j;
unsigned long ea, ta;
//unsigned long ea, ta;
unsigned long translate_space;
unsigned long match_space;
printf("itlb_translation_test\n");
 
/* Disable IMMU */
immu_disable();
 
/* Invalidate all entries in ITLB */
/* Invalidate all entries in DTLB */
for (i = 0; i < ITLB_WAYS; i++) {
for (j = 0; j < ITLB_SETS; j++) {
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
880,60 → 1046,61
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
match_space = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
translate_space = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, match_space | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, translate_space | ITLB_PR_NOLIMIT);
}
 
/* Set itlb permisions */
itlb_val = ITLB_PR_NOLIMIT;
 
/* Write test program */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
copy_jump (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
translate_space = (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
//printf("writing app to 0x%8lx to be translated in set %d\n",translate_space, i);
REG32(translate_space) = OR32_L_JR_R9;
REG32(translate_space + 4) = OR32_L_NOP;
// Now flush this in case DC isn't on write-through
mtspr(SPR_DCBFR, translate_space);
mtspr(SPR_DCBFR, translate_space+4);
}
/* Set one to one translation of the last way of ITLB */
/* Set one to one translation of the last ways of ITLB */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + i, ta | ITLB_PR_NOLIMIT);
translate_space = (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
//printf("translate_space: 0x%8lx set %d\n",translate_space, i);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + i, translate_space | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + i,
translate_space | ITLB_PR_NOLIMIT);
}
/* Enable IMMU */
immu_enable();
 
/* Check the pattern */
/* Check the tranlsation works by jumping there */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
call (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
translate_space = (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
//printf("calling 0x%.8lx - should use set %d\n",translate_space, i);
call (translate_space);
}
 
/* Set FLASH_END -> RAM_START + (RAM_SIZE/2) translation */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
ea = FLASH_START + FLASH_SIZE + i*PAGE_SIZE;
ta = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + i, ta | ITLB_PR_NOLIMIT);
}
 
/* Check the pattern */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
call (FLASH_START + FLASH_SIZE + (i*PAGE_SIZE) + (i*0x10));
}
 
/* Set hi -> lo, lo -> hi translation */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
ea = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
ta = RAM_START + (RAM_SIZE/2) + ((ITLB_SETS - i - 1 + TLB_TEXT_SET_NB)*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + i, ta | ITLB_PR_NOLIMIT);
match_space = RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE);
translate_space = RAM_START + (RAM_SIZE/2) +
(((ITLB_SETS-1)+TLB_TEXT_SET_NB - i)*PAGE_SIZE);
printf("setting itlb set %d match -> trans = 0x%.8lx -> 0x%.8lx\n",
i, match_space, translate_space);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + i, match_space | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + i, translate_space|ITLB_PR_NOLIMIT);
}
 
/* Check the pattern */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
call (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + ((ITLB_SETS - i - 1 + TLB_TEXT_SET_NB)*0x10));
match_space = RAM_START + (RAM_SIZE/2) + (((ITLB_SETS-1)+TLB_TEXT_SET_NB - i)*PAGE_SIZE) + (i*0x10);
printf("immu hi->lo check - calling 0x%.8lx\n",match_space);
call(match_space);
}
 
/* Disable IMMU */
941,20 → 1108,28
 
/* Check the pattern */
for (i = TLB_TEXT_SET_NB; i < ITLB_SETS; i++) {
call (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
translate_space = (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
//call (RAM_START + (RAM_SIZE/2) + (i*PAGE_SIZE) + (i*0x10));
//printf("immu disabled check of set %d - calling 0x%.8lx\n",i, translate_space);
call (translate_space);
}
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
 
/* EA match register test
Shifting one in ITLBMR and performing accesses to boundaries
of the page, checking the triggering of exceptions */
Shifting one in ITLBMR and performing accesses to boundaries
of the page, checking the triggering of exceptions */
int itlb_match_test (int way, int set)
{
int i, j;
unsigned long add, t_add;
unsigned long add;
unsigned long ea, ta;
printf("itlb_match_test\n");
 
/* Disable IMMU */
immu_disable();
969,8 → 1144,8
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
ta = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
978,12 → 1153,30
/* Set dtlb permisions */
itlb_val = ITLB_PR_NOLIMIT;
 
/* Set pattern */
copy_jump (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE) - 8);
copy_jump (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE));
copy_jump (RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE - 8);
copy_jump (RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE);
// Write program which will just return into these places
unsigned long translate_space = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
//copy_jump (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE) - 8);
REG32(translate_space-8) = OR32_L_JR_R9;
REG32(translate_space-4) = OR32_L_NOP;
//copy_jump (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE));
REG32(translate_space) = OR32_L_JR_R9;
REG32(translate_space+4) = OR32_L_NOP;
//copy_jump (RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE - 8);
REG32(translate_space + PAGE_SIZE - 8) = OR32_L_JR_R9;
REG32(translate_space + PAGE_SIZE - 4) = OR32_L_NOP;
//copy_jump (RAM_START + (RAM_SIZE/2) + (set + 1)*PAGE_SIZE);
REG32(translate_space + PAGE_SIZE) = OR32_L_JR_R9;
REG32(translate_space + PAGE_SIZE + 4) = OR32_L_NOP;
// Flush these areas incase cache doesn't write them through immediately
mtspr(SPR_DCBFR, translate_space-8);
mtspr(SPR_DCBFR, translate_space);
mtspr(SPR_DCBFR, translate_space+4);
mtspr(SPR_DCBFR, translate_space + PAGE_SIZE - 8);
mtspr(SPR_DCBFR, translate_space + PAGE_SIZE - 4);
mtspr(SPR_DCBFR, translate_space + PAGE_SIZE);
mtspr(SPR_DCBFR, translate_space + PAGE_SIZE + 4);
/* Enable IMMU */
immu_enable();
 
990,37 → 1183,39
/* Shifting one in ITLBMR */
i = 0;
add = (PAGE_SIZE*ITLB_SETS);
t_add = add + (set*PAGE_SIZE);
//t_add = add + (set*PAGE_SIZE);
// Space we'll access and expect the MMU to translate our requests
unsigned long match_space = (PAGE_SIZE*DTLB_SETS) + (set*PAGE_SIZE);
while (add != 0x00000000) {
mtspr (SPR_ITLBMR_BASE(way) + set, t_add | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(way) + set, (RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE)) | ITLB_PR_NOLIMIT);
mtspr (SPR_ITLBMR_BASE(way) + set, match_space | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(way) + set, translate_space | ITLB_PR_NOLIMIT);
 
/* Reset ITLB miss counter and EA */
itlb_miss_count = 0;
itlb_miss_ea = 0;
 
if (((t_add < RAM_START) || (t_add >= DATA_END_ADD)) && ((t_add < FLASH_START) || (t_add >= TEXT_END_ADD))) {
//if (((t_add < RAM_START) || (t_add >= DATA_END_ADD)) && ((t_add < TEXT_START_ADD) || (t_add >= TEXT_END_ADD))) {
 
/* Jump on last address of previous page */
call (t_add - 8);
call (match_space - 8);
ASSERT(itlb_miss_count == 1);
/* Jump on first address of the page */
call (t_add);
call (match_space);
ASSERT(itlb_miss_count == 1);
/* Jump on last address of the page */
call (t_add + PAGE_SIZE - 8);
call (match_space + PAGE_SIZE - 8);
ASSERT(itlb_miss_count == 1);
 
/* Jump on first address of next page */
call (t_add + PAGE_SIZE);
call (match_space + PAGE_SIZE);
ASSERT(itlb_miss_count == 2);
}
//}
 
i++;
add = (PAGE_SIZE*ITLB_SETS) << i;
t_add = add + (set*PAGE_SIZE);
match_space = add + (set*PAGE_SIZE);
 
for (j = 0; j < ITLB_WAYS; j++) {
mtspr (SPR_ITLBMR_BASE(j) + ((set - 1) & (ITLB_SETS - 1)), 0);
1028,6 → 1223,9
}
}
 
printf("OK\n");
printf("-------------------------------------------\n");
 
/* Disable IMMU */
immu_disable();
 
1035,14 → 1233,16
}
 
/* Valid bit test
Set all ways of one set to be invalid, perform
access so miss handler will set them to valid,
try access again - there should be no miss exceptions */
Set all ways of one set to be invalid, perform
access so miss handler will set them to valid,
try access again - there should be no miss exceptions */
int itlb_valid_bit_test (int set)
{
int i, j;
unsigned long ea, ta;
 
printf("itlb_valid_bit_test set = %d\n", set);
 
/* Disable IMMU */
immu_disable();
 
1056,8 → 1256,8
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
ta = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
1069,64 → 1269,72
/* Set itlb permisions */
itlb_val = ITLB_PR_NOLIMIT;
 
/* Resetv ITLBMR for every way */
for (i = 0; i < ITLB_WAYS; i++) {
/* Resetv ITLBMR for every way after the program code */
for (i = TLB_TEXT_SET_NB; i < ITLB_WAYS; i++) {
mtspr (SPR_ITLBMR_BASE(i) + set, 0);
}
 
/* Enable IMMU */
immu_enable();
 
// Address we'll jump to and expect it to be translated
unsigned long match_space = (PAGE_SIZE*ITLB_SETS) + (set*PAGE_SIZE);
// Address that we will actually access
unsigned long translate_space = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
/* Perform jumps to address, that is not in ITLB */
for (i = 0; i < ITLB_WAYS; i++) {
TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == (i + 1));
ASSERT(itlb_miss_ea == (RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
}
printf("writing program to 0x%.8lx\n", translate_space);
REG32(translate_space) = OR32_L_JR_R9;
REG32(translate_space+4) = OR32_L_NOP;
mtspr(SPR_DCBFR, translate_space);
mtspr(SPR_DCBFR, translate_space+4);
printf("jumping to 0x%.8lx, should be itlb miss\n",match_space);
call (match_space);
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == 1);
ASSERT(itlb_miss_ea == match_space);
 
/* Reset ITLB miss counter and EA */
itlb_miss_count = 0;
itlb_miss_ea = 0;
 
printf("jumping to 0x%.8lx again - should not be a miss\n", match_space);
/* Perform jumps to address, that is now in ITLB */
for (i = 0; i < ITLB_WAYS; i++) {
TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
call (match_space);
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == 0);
}
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == 0);
 
/* Reset valid bits */
for (i = 0; i < ITLB_WAYS; i++) {
mtspr (SPR_ITLBMR_BASE(i) + set, mfspr (SPR_ITLBMR_BASE(i) + set) & ~SPR_ITLBMR_V);
}
 
printf("jumping to 0x%.8lx again - mmu entries invalidated, so should be a miss\n", match_space);
/* Perform jumps to address, that is now in ITLB but is invalid */
for (i = 0; i < ITLB_WAYS; i++) {
TEST_JUMP(RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE));
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == (i + 1));
ASSERT(itlb_miss_ea == (RAM_START + RAM_SIZE + (i*ITLB_SETS*PAGE_SIZE) + (set*PAGE_SIZE)));
}
call (match_space);
/* Check if there was ITLB miss */
ASSERT(itlb_miss_count == 1);
ASSERT(itlb_miss_ea == match_space);
 
/* Disable IMMU */
immu_disable ();
 
printf("OK\n");
printf("-------------------------------------------\n");
 
return 0;
}
 
/* Permission test
Set various permissions, perform r/w access
in user and supervisor mode and check triggering
of page fault exceptions */
int itlb_premission_test (int set)
Set various permissions, perform r/w access
in user and supervisor mode and chack triggering
of page fault exceptions */
int itlb_permission_test (int set)
{
int i, j;
unsigned long ea, ta;
 
printf("itlb_permission_test set = %d\n", set);
 
/* Disable IMMU */
immu_disable();
 
1140,17 → 1348,17
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
ta = /*TEXT_START_ADD +*/ (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
 
/* Testing page */
ea = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
 
// Address that we will actually access
unsigned long match_space = RAM_START + (RAM_SIZE/2) + (set*PAGE_SIZE);
/* Set match register */
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + set, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBMR_BASE(ITLB_WAYS - 1) + set, match_space | SPR_ITLBMR_V);
 
/* Reset page fault counter and EA */
ipage_fault_count = 0;
1157,31 → 1365,41
ipage_fault_ea = 0;
 
/* Copy the code */
copy_jump (ea);
copy_jump (ea + 8);
REG32(match_space+0x0) = OR32_L_JR_R9;
REG32(match_space+0x4) = OR32_L_NOP;
REG32(match_space+0x8) = OR32_L_JR_R9;
REG32(match_space+0xc) = OR32_L_NOP;
mtspr(SPR_DCBFR, match_space);
mtspr(SPR_DCBFR, match_space+4);
mtspr(SPR_DCBFR, match_space+8);
mtspr(SPR_DCBFR, match_space+12);
 
/* Enable IMMU */
immu_enable ();
 
/* Execute supervisor */
printf("execute disable for supervisor - should cause ipage fault\n");
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + set, ea | (ITLB_PR_NOLIMIT & ~SPR_ITLBTR_SXE));
call (ea);
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + set, match_space | (ITLB_PR_NOLIMIT & ~SPR_ITLBTR_SXE));
printf("calling address 0x%.8lx\n", match_space);
call (match_space);
ASSERT(ipage_fault_count == 1);
call (ea + 8);
call (match_space + 8);
ASSERT(ipage_fault_count == 1);
 
/* Execute user */
printf("execute disable for user - should cause ipage fault\n");
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_UXE;
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + set, ea | (ITLB_PR_NOLIMIT & ~SPR_ITLBTR_UXE));
mtspr (SPR_ITLBTR_BASE(ITLB_WAYS - 1) + set, match_space | (ITLB_PR_NOLIMIT & ~SPR_ITLBTR_UXE));
 
/* Set user mode */
printf("disabling supervisor mode\n");
mtspr (SPR_SR, mfspr (SPR_SR) & ~SPR_SR_SM);
 
call (ea);
printf("calling address 0x%.8lx\n", match_space);
printf("instruction at jump space: 0x%.8lx\n",REG32(match_space));
call (match_space);
ASSERT(ipage_fault_count == 2);
call (ea + 8);
call (match_space + 8);
ASSERT(ipage_fault_count == 2);
 
/* Trigger sys call exception to enable supervisor mode again */
1190,41 → 1408,9
/* Disable IMMU */
immu_disable ();
 
return 0;
}
printf("OK\n");
printf("-------------------------------------------\n");
 
/* Instruction cache inhibit bit test
Set and clear CI bit and check the pattern. */
int itlb_ci_test(void)
{
int i, j;
unsigned long ea, ta, ret;
/* Disable IMMU */
immu_disable();
/* Invalidate all entries in DTLB */
for (i = 0; i < ITLB_WAYS; i++) {
for (j = 0; j < ITLB_SETS; j++) {
mtspr (SPR_ITLBMR_BASE(i) + j, 0);
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
}
}
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
/* Testing page */
ea = RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE);
ret = lo_itlb_ci_test (ea, TLB_TEXT_SET_NB);
ASSERT(ret == 0);
return 0;
}
 
1232,8 → 1418,20
{
int i, j;
 
text_begin_addr = (unsigned long)&_src_beg;
end_data_addr = (unsigned long)&_ram_end;
 
TLB_TEXT_SET_NB = TLB_DATA_SET_NB = (end_data_addr+PAGE_SIZE) / PAGE_SIZE;
 
// Some tests check page below, and if this page corresponds with set being
// used by program's data section, then could mean an incorrect mapping ends
// up in the TLB cache, which causes the program to do bad things, so to be
// safe incrementing the number of pages being used by the program.
TLB_TEXT_SET_NB++;
TLB_DATA_SET_NB++;
 
i = j = 0; /* Get rid of warnings */
 
/* Register bus error handler */
excpt_buserr = (unsigned long)bus_err_handler;
 
1243,74 → 1441,100
/* Register illegal insn handler */
excpt_syscall = (unsigned long)sys_call_handler;
 
#if 1
#if DO_DMMU_TESTS==1
 
/* Translation test */
dtlb_translation_test ();
 
printf("DTLB translation tests OK\n");
/* Virtual address match test */
#ifndef RTL_SIM
for (j = 0; j < DTLB_WAYS; j++) {
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
#endif
dtlb_match_test (j, i);
}
#else
dtlb_match_test (0, DTLB_SETS - 2);
#endif
printf("DTLB match tests OK\n");
 
/* Valid bit testing */
#ifndef RTL_SIM
 
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
dtlb_valid_bit_test (i);
#else
dtlb_valid_bit_test (DTLB_SETS - 2);
#endif
dtlb_valid_bit_test (i);
 
printf("DTLB valid bit tests OK\n");
 
/* Permission test */
#ifndef RTL_SIM
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 1); i++)
dtlb_premission_test (i);
#else
dtlb_premission_test (DTLB_SETS - 2);
#endif
dtlb_permission_test (i);
 
dtlb_ci_test();
printf("DTLB permission bit tests OK\n");
 
/* Data cache test - Disabled for now */
 
#if 0
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
for (i = TLB_DATA_SET_NB; i < (DTLB_SETS - 2); i++)
#endif
dtlb_dcache_test (i);
#endif
 
#if 1
#endif /* end of no DTLB tests */
 
 
/* Translation test */
itlb_translation_test ();
printf("ITLB translation tests OK\n");
 
/* Virtual address match test */
#ifndef RTL_SIM
 
for (j = 0; j < DTLB_WAYS; j++) {
for (i = TLB_TEXT_SET_NB + 1; i < (DTLB_SETS - 1); i++)
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB + 1; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
for (i = TLB_DATA_SET_NB + 1; i < (ITLB_SETS - 1); i++)
#endif
itlb_match_test (j, i);
}
#else
itlb_match_test (0, DTLB_SETS - 2);
#endif
 
printf("ITLB match tests OK\n");
 
/* Valid bit testing */
#ifndef RTL_SIM
for (i = TLB_TEXT_SET_NB; i < (ITLB_SETS); i++)
itlb_valid_bit_test (i);
#ifdef SHORT_TEST
for (i = TLB_DATA_SET_NB; i < (TLB_DATA_SET_NB+4 - 1); i++)
#else
itlb_valid_bit_test (ITLB_SETS-1);
for (i = TLB_DATA_SET_NB; i < (ITLB_SETS - 1); i++)
#endif
itlb_valid_bit_test (i);
 
printf("ITLB valid bit tests OK\n");
 
 
/* Permission test */
#ifndef RTL_SIM
#ifdef SHORT_TEST
for (i = TLB_TEXT_SET_NB; i < (TLB_TEXT_SET_NB + 4); i++)
#else
for (i = TLB_TEXT_SET_NB; i < (ITLB_SETS - 1); i++)
itlb_premission_test (i);
#else
itlb_premission_test (ITLB_SETS - 2);
#endif
itlb_permission_test (i);
 
itlb_ci_test();
#endif
printf("ITLB permission tests OK\n");
 
printf("Tests completed\n");
report (0xdeaddead);
report (0x8000000d);
exit (0);
return 0;
}
 
/trunk/or1ksim/testsuite/test-code-or1k/mmu/mmu-asm.S
61,9 → 61,9
l.nop
 
lo_immu_en:
l.mfspr r11,r0,SPR_SR
l.ori r11,r11,SPR_SR_IME
l.mtspr r0,r11,SPR_ESR_BASE
l.mfspr r3,r0,SPR_SR
l.ori r3,r3,SPR_SR_IME
l.mtspr r0,r3,SPR_ESR_BASE
l.mtspr r0,r9,SPR_EPCR_BASE
l.rfe
l.nop
/trunk/or1ksim/testsuite/test-code-or1k/cfg/cfg.S
27,10 → 27,7
 
#include "spr-defs.h"
.section .except, "ax"
l.addi r2,r0,0
 
.section .text
.section .except,"ax"
.org 0x100
_reset:
l.addi r1,r0,0x7f00
39,7 → 36,7
l.jr r2
l.nop
 
 
.section .text
_main:
l.addi r2,r0,0
 
/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test-s.S
30,12 → 30,6
 
#define reset main
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
.global except_basic
.global lo_dmmu_en
.global lo_immu_en
74,8 → 68,53
.extern excpt_break
.extern excpt_trap
 
.section .except, "ax"
/* Our special text section is used to guarantee this code goes first
when linking. */
 
.section .except,"ax"
 
.org 0x100
reset_vector:
l.nop
l.nop
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
l.addi r9,r0,0x0
l.addi r10,r0,0x0
l.addi r11,r0,0x0
l.addi r12,r0,0x0
l.addi r13,r0,0x0
l.addi r14,r0,0x0
l.addi r15,r0,0x0
l.addi r16,r0,0x0
l.addi r17,r0,0x0
l.addi r18,r0,0x0
l.addi r19,r0,0x0
l.addi r20,r0,0x0
l.addi r21,r0,0x0
l.addi r22,r0,0x0
l.addi r23,r0,0x0
l.addi r24,r0,0x0
l.addi r25,r0,0x0
l.addi r26,r0,0x0
l.addi r27,r0,0x0
l.addi r28,r0,0x0
l.addi r29,r0,0x0
l.addi r30,r0,0x0
l.addi r31,r0,0x0
 
l.movhi r3,hi(start)
l.ori r3,r3,lo(start)
l.jr r3
l.nop
 
 
.org 0x200
buserr_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
93,7 → 132,8
l.nop
l.nop
l.nop
 
.org 0x300
dpfault_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
112,6 → 152,7
l.nop
l.nop
 
.org 0x400
ipfault_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
130,6 → 171,7
l.nop
l.nop
 
.org 0x500
tick_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
148,6 → 190,7
l.nop
l.nop
 
.org 0x600
align_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
166,6 → 209,7
l.nop
l.nop
 
.org 0x700
illinsn_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
184,6 → 228,7
l.nop
l.nop
 
.org 0x800
int_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
202,6 → 247,7
l.nop
l.nop
 
.org 0x900
dtlbmiss_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
220,6 → 266,7
l.nop
l.nop
 
.org 0xa00
itlbmiss_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
238,6 → 285,7
l.nop
l.nop
 
.org 0xb00
range_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
256,6 → 304,7
l.nop
l.nop
 
.org 0xc00
syscall_vector:
l.addi r3,r3,4
 
279,6 → 328,7
l.rfe
l.addi r3,r3,8
 
.org 0xd00
break_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
297,6 → 347,7
l.nop
l.nop
 
.org 0xe00
trap_vector:
l.addi r1,r1,-120
l.sw 0x1c(r1),r9
314,144 → 365,34
l.nop
l.nop
l.nop
 
/* Our special text section is used to guarantee this code goes first
when linking. */
.section .except-text
 
.org 0x100
reset_vector:
l.nop
l.nop
l.addi r2,r0,0x0
l.addi r3,r0,0x0
l.addi r4,r0,0x0
l.addi r5,r0,0x0
l.addi r6,r0,0x0
l.addi r7,r0,0x0
l.addi r8,r0,0x0
l.addi r9,r0,0x0
l.addi r10,r0,0x0
l.addi r11,r0,0x0
l.addi r12,r0,0x0
l.addi r13,r0,0x0
l.addi r14,r0,0x0
l.addi r15,r0,0x0
l.addi r16,r0,0x0
l.addi r17,r0,0x0
l.addi r18,r0,0x0
l.addi r19,r0,0x0
l.addi r20,r0,0x0
l.addi r21,r0,0x0
l.addi r22,r0,0x0
l.addi r23,r0,0x0
l.addi r24,r0,0x0
l.addi r25,r0,0x0
l.addi r26,r0,0x0
l.addi r27,r0,0x0
l.addi r28,r0,0x0
l.addi r29,r0,0x0
l.addi r30,r0,0x0
l.addi r31,r0,0x0
 
l.movhi r3,hi(start)
l.ori r3,r3,lo(start)
l.jr r3
l.nop
.section .text
start:
l.jal init_mc
l.nop
 
l.movhi r1,hi(stack)
l.ori r1,r1,lo(stack)
l.ori r2,r1,0
 
/* Setup exception wrappers */
l.movhi r3,hi(_src_beg)
l.ori r3,r3,lo(_src_beg)
l.addi r7,r0,0x100
 
1: l.addi r7,r7,0x100
l.sfeqi r7,0xf00
l.bf 1f
bss_clear:
/* Clear BSS */
l.movhi r3, hi(_bstart)
l.ori r3, r3, lo(_bstart)
l.movhi r4, hi(_bend)
l.ori r4, r4, lo(_bend)
bss_clear_loop:
l.sw 0(r3), r0
l.sfgtu r3, r4
l.bnf bss_clear_loop
l.addi r3, r3, 4
l.movhi r3,hi(reset)
l.ori r3,r3,lo(reset)
l.jr r3
l.nop
l.addi r4,r7,0
l.addi r5,r0,0
2:
l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,1
l.sfeqi r5,16
l.bf 1b
l.nop
l.j 2b
l.nop
1:
/* Copy data section */
l.movhi r4,hi(_dst_beg)
l.ori r4,r4,lo(_dst_beg)
l.movhi r5,hi(_dst_end)
l.ori r5,r5,lo(_dst_end)
l.sub r5,r5,r4
l.sfeqi r5,0
l.bf 2f
l.nop
1: l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,-4
l.sfgtsi r5,0
l.bf 1b
l.nop
 
2:
 
l.movhi r2,hi(reset)
l.ori r2,r2,lo(reset)
l.jr r2
l.nop
 
init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
l.jr r9
l.nop
 
store_regs:
l.sw 0x00(r1),r2
l.sw 0x04(r1),r3
535,8 → 476,6
l.rfe
l.nop
 
.section .text
 
except_basic:
sys1:
l.addi r3,r0,-2 /* Enable exceptiom recognition and external interrupt,set user mode */
642,7 → 581,7
b_trap:
l.jr r9
trap:
l.trap 1
l.trap 15
l.jr r9
l.nop
 
668,4 → 607,3
l.addi r11,r0,0
l.jr r9
l.addi r11,r11,1
 
/trunk/or1ksim/testsuite/test-code-or1k/except-test/except-test.c
32,13 → 32,9
/* Define RAM physical location and size
Bottom half will be used for this program, the rest
will be used for testing */
#define FLASH_START 0xf0000000
#define FLASH_SIZE 0x00200000
#define RAM_START 0x00000000
#define RAM_SIZE 0x04000000
#define RAM_SIZE 0x00200000
 
#define TEST_BASE 0xa5000000
 
/* MMU page size */
#define PAGE_SIZE 8192
 
59,8 → 55,8
#define TLB_CODE_PLUS_ONE_PAGE 0x10000000
#define TLB_CODE_MINUS_ONE_PAGE 0x20000000
 
#define TLB_TEXT_SET_NB 6
#define TLB_DATA_SET_NB 2
#define TLB_TEXT_SET_NB 8
#define TLB_DATA_SET_NB 8
 
#define TLB_CODE_MASK 0xfffff000
#define TLB_PR_MASK 0x00000fff
439,8 → 435,8
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
627,8 → 623,8
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
658,8 → 654,11
/* Set IMMU translation */
ea = RAM_START + (RAM_SIZE) + ((TLB_TEXT_SET_NB)*PAGE_SIZE);
itlb_val = SPR_ITLBTR_CI | SPR_ITLBTR_SXE;
mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, ((ea + PAGE_SIZE) & SPR_ITLBTR_PPN) | itlb_val);
mtspr (SPR_ITLBMR_BASE(0) + TLB_TEXT_SET_NB, (ea & SPR_ITLBMR_VPN) |
SPR_ITLBMR_V);
// Set translate to invalid address: 0xee000000
mtspr (SPR_ITLBTR_BASE(0) + TLB_TEXT_SET_NB, (0xee000000 & SPR_ITLBTR_PPN) |
itlb_val);
 
/* Enable IMMU */
immu_enable ();
680,16 → 679,15
except_pc = 0;
except_ea = 0;
 
/* Copy jump instruction to last location of RAM */
ea = RAM_START + RAM_SIZE - 8;
memcpy((void *)ea, (void *)&jump_back, 8);
/* Set EA as an invalid memory location */
ea = 0xee000000;
 
/* Check if there was bus error exception */
ret = call (ea, 0);
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_BERR));
ASSERT(except_pc == ea + 4);
ASSERT(except_ea == ea + 8);
ASSERT(except_pc == ea);
ASSERT(except_ea == ea);
 
/* Reset except counter */
except_count = 0;
700,8 → 698,11
/* Set DMMU translation */
ea = RAM_START + (RAM_SIZE) + ((TLB_DATA_SET_NB)*PAGE_SIZE);
dtlb_val = SPR_DTLBTR_CI | SPR_DTLBTR_SRE;
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) | SPR_DTLBMR_V);
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, ((ea + PAGE_SIZE) & SPR_DTLBTR_PPN) | dtlb_val);
mtspr (SPR_DTLBMR_BASE(0) + TLB_DATA_SET_NB, (ea & SPR_DTLBMR_VPN) |
SPR_DTLBMR_V);
// Set translate to invalid address: 0xee000000
mtspr (SPR_DTLBTR_BASE(0) + TLB_DATA_SET_NB, (0xee000000 & SPR_DTLBTR_PPN) |
dtlb_val);
 
/* Enable DMMU */
dmmu_enable ();
723,6 → 724,9
except_pc = 0;
except_ea = 0;
 
// Set ea to invalid address
ea = 0xee000000;
/* Check if there was bus error exception */
ret = call ((unsigned long)&load_acc_32, ea );
ASSERT(except_count == 1);
753,13 → 757,13
it isn't - it's l.cust8 0x3ffffff.
 
Fixed by a) jumping to the correct location and b) really using an
illegal instruction. */
illegal instruction (opcode 0x3a. */
REG32(RAM_START + (RAM_SIZE/2)) = REG32((unsigned long)jump_back + 4);
REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe5dfffff;
REG32(RAM_START + (RAM_SIZE/2) + 4) = 0xe8000000;
 
/* Check if there was illegal insn exception. Note that if an illegal
instruction occurs in a delay slot (like this one), then the exception
PC is the address of the hump instruction. */
PC is the address of the jump instruction. */
ret = call (RAM_START + (RAM_SIZE/2), 0 ); /* JPB */
 
ASSERT(except_count == 1);
910,11 → 914,11
mtspr (SPR_ITLBTR_BASE(i) + j, 0);
}
}
 
/* Set one to one translation for the use of this program */
for (i = 0; i < TLB_TEXT_SET_NB; i++) {
ea = FLASH_START + (i*PAGE_SIZE);
ta = FLASH_START + (i*PAGE_SIZE);
ea = RAM_START + (i*PAGE_SIZE);
ta = RAM_START + (i*PAGE_SIZE);
mtspr (SPR_ITLBMR_BASE(0) + i, ea | SPR_ITLBMR_V);
mtspr (SPR_ITLBTR_BASE(0) + i, ta | ITLB_PR_NOLIMIT);
}
953,10 → 957,21
/* Enable IMMU */
immu_enable ();
 
/* The following is currently disabled due to differing behavior between
or1ksim and the OR1200 RTL. Or1ksim appears to receive only 1 exception
during the call_with_int() call. The OR1200 correctly, in my opionion,
reports 2 exceptions - ITLB miss and tick timer. -- Julius
TODO: Investigate why or1ksim isn't reporting ITLB miss.
 
*/
 
#if 0
/* Check if there was INT exception */
call_with_int (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_TICK));
printf("ec:%d 0x%lx\n",except_count,except_mask); ASSERT(except_count == 2);
ASSERT(except_mask == ((1 << V_TICK) | (1 << V_ITLB_MISS)));
printf("epc %8lx\n",except_pc);
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
 
/* Reset except counter */
964,6 → 979,7
except_mask = 0;
except_pc = 0;
except_ea = 0;
#endif
 
/* Check if there was ITLB exception */
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
993,20 → 1009,7
except_mask = 0;
except_pc = 0;
except_ea = 0;
 
/* Check if there was bus error exception */
call (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE), 0);
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_BERR));
ASSERT(except_pc == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_TEXT_SET_NB*PAGE_SIZE)));
 
/* Reset except counter */
except_count = 0;
except_mask = 0;
except_pc = 0;
except_ea = 0;
 
/* Disable MMU */
immu_disable ();
 
1013,7 → 1016,7
/* Set illegal instruction. JPB. Use a really illegal instruction, not
l.cust8 0x3ffffff. */
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 0) = 0x00000000;
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe5dfffff;
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 4) = 0xe8000000;
REG32(RAM_START + (RAM_SIZE/2) + (TLB_TEXT_SET_NB*PAGE_SIZE) + 8) = 0x00000000;
 
/* Check if there was illegal insn exception */
1070,7 → 1073,7
ASSERT(ret == 0x12345678);
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
 
/* Reset except counter */
except_count = 0;
except_mask = 0;
1077,20 → 1080,6
except_pc = 0;
except_ea = 0;
 
/* Check if there was bus error exception */
ret = call ((unsigned long)&load_acc_32, RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE));
ASSERT(except_count == 1);
ASSERT(except_mask == (1 << V_BERR));
ASSERT(ret == 0x12345678);
ASSERT(except_pc == ((unsigned long)(load_acc_32) + 8));
ASSERT(except_ea == (RAM_START + (RAM_SIZE) + (TLB_DATA_SET_NB*PAGE_SIZE)));
 
/* Reset except counter */
except_count = 0;
except_mask = 0;
except_pc = 0;
except_ea = 0;
 
/* Check if there was trap exception */
call ((unsigned long)&trap, 0);
ASSERT(except_count == 1);
1141,10 → 1130,11
/* Exception basic test */
ret = except_basic ();
ASSERT(ret == 0);
 
printf("interupt_test\n");
/* Interrupt exception test */
interrupt_test ();
 
printf("itlb_test\n");
/* ITLB exception test */
itlb_test ();
 
/trunk/or1ksim/testsuite/test-code-or1k/dhry/dhry.c
184,34 → 184,19
for (Run_Index = 1; Run_Index <= Number_Of_Runs; ++Run_Index)
{
 
#if DBG
report(1);
report(Run_Index);
#endif
Proc_5();
#if DBG
report(2);
#endif
 
Proc_4();
#if DBG
report(3);
#endif
 
/* Ch_1_Glob == 'A', Ch_2_Glob == 'B', Bool_Glob == true */
Int_1_Loc = 2;
Int_2_Loc = 3;
strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 2'ND STRING");
Enum_Loc = Ident_2;
#if DBG
report(0x31);
report((unsigned long)Str_1_Loc);
report((unsigned long)Str_2_Loc);
#endif
Bool_Glob = ! Func_2 (Str_1_Loc, Str_2_Loc);
 
/* Bool_Glob == 1 */
#if DBG
report(4);
#endif
while (Int_1_Loc < Int_2_Loc) /* loop body executed once */
{
Int_3_Loc = 5 * Int_1_Loc - Int_2_Loc;
220,31 → 205,12
/* Int_3_Loc == 7 */
Int_1_Loc += 1;
} /* while */
#if DBG
report(5);
#endif
 
/* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
#if DBG
printf("a) Int_1_Loc: %x\n", Int_1_Loc);
printf("a) Int_2_Loc: %x\n", Int_2_Loc);
printf("a) Int_3_Loc: %x\n\n", Int_3_Loc);
#endif
Proc_8 (Arr_1_Glob, Arr_2_Glob, Int_1_Loc, Int_3_Loc);
/* Int_Glob == 5 */
#if DBG
printf("b) Int_1_Loc: %x\n", Int_1_Loc);
printf("b) Int_2_Loc: %x\n", Int_2_Loc);
printf("b) Int_3_Loc: %x\n\n", Int_3_Loc);
report(6);
#endif
 
Proc_1 (Ptr_Glob);
#if DBG
printf("c) Int_1_Loc: %x\n", Int_1_Loc);
printf("c) Int_2_Loc: %x\n", Int_2_Loc);
printf("c) Int_3_Loc: %x\n\n", Int_3_Loc);
report(7);
#endif
 
for (Ch_Index = 'A'; Ch_Index <= Ch_2_Glob; ++Ch_Index)
/* loop body executed twice */
256,39 → 222,17
strcpy (Str_2_Loc, "DHRYSTONE PROGRAM, 3'RD STRING");
Int_2_Loc = Run_Index;
Int_Glob = Run_Index;
#if DBG
printf("d) Int_1_Loc: %x\n", Int_1_Loc);
printf("d) Int_2_Loc: %x\n", Int_2_Loc);
printf("d) Int_3_Loc: %x\n\n", Int_3_Loc);
#endif
}
}
#if DBG
report(8);
#endif
 
/* Int_1_Loc == 3, Int_2_Loc == 3, Int_3_Loc == 7 */
#if DBG
printf("e) Int_1_Loc: %x\n", Int_1_Loc);
printf("e) Int_2_Loc: %x\n", Int_2_Loc);
printf("e) Int_3_Loc: %x\n", Int_3_Loc);
printf("e) Ch_1_Glob: %c\n\n", Ch_1_Glob);
#endif
Int_2_Loc = Int_2_Loc * Int_1_Loc;
Int_1_Loc = Int_2_Loc / Int_3_Loc;
Int_2_Loc = 7 * (Int_2_Loc - Int_3_Loc) - Int_1_Loc;
/* Int_1_Loc == 1, Int_2_Loc == 13, Int_3_Loc == 7 */
Proc_2 (&Int_1_Loc);
#if DBG
report(9);
#endif
 
/* Int_1_Loc == 5 */
#if DBG
printf("f) Int_1_Loc: %x\n", Int_1_Loc);
printf("f) Int_2_Loc: %x\n", Int_2_Loc);
printf("f) Int_3_Loc: %x\n\n", Int_3_Loc);
#endif
 
} /* loop "for Run_Index" */
 
/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.ld File deleted
/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.in
217,8 → 217,7
top_builddir = @top_builddir@
top_srcdir = @top_srcdir@
int_test_SOURCES = int-test.S
int_test_LDFLAGS = -T$(srcdir)/int-test.ld
EXTRA_DIST = int-test.ld
int_test_LDFLAGS = -T$(srcdir)/../default.ld
all: all-am
 
.SUFFIXES:
/trunk/or1ksim/testsuite/test-code-or1k/int-test/int-test.S
52,13 → 52,8
 
#define RAM_START 0x00000000
 
#define MC_CSR (0x00)
#define MC_POC (0x04)
#define MC_BA_MASK (0x08)
#define MC_CSC(i) (0x10 + (i) * 8)
#define MC_TMS(i) (0x14 + (i) * 8)
 
.section .reset, "ax"
.section .except,"ax"
 
.org 0x100
 
94,81 → 89,13
l.addi r30,r0,0x0
l.addi r31,r0,0x0
 
l.movhi r3,hi(start)
l.ori r3,r3,lo(start)
l.movhi r3,hi(_start)
l.ori r3,r3,lo(_start)
l.jr r3
l.nop
start:
l.jal _init_mc
l.nop
 
/* Setup exception wrapper */
l.movhi r3,hi(_src_beg)
l.ori r3,r3,lo(_src_beg)
l.movhi r4,hi(_dst_beg)
l.ori r4,r4,lo(_dst_beg)
l.movhi r5,hi(_dst_end)
l.ori r5,r5,lo(_dst_end)
l.sub r5,r5,r4
l.sfeqi r5,0
l.bf 2f
l.nop
1:
l.lwz r6,0(r3)
l.sw 0(r4),r6
l.addi r3,r3,4
l.addi r4,r4,4
l.addi r5,r5,-4
l.sfgtsi r5,0
l.bf 1b
l.nop
2:
l.movhi r2,hi(_main)
l.ori r2,r2,lo(_main)
l.jr r2
l.nop
 
_init_mc:
l.movhi r3,hi(MC_BASE_ADDR)
l.ori r3,r3,lo(MC_BASE_ADDR)
l.addi r4,r3,MC_CSC(0)
l.movhi r5,hi(FLASH_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0025
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(0)
l.movhi r5,hi(FLASH_TMS_VAL)
l.ori r5,r5,lo(FLASH_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_BA_MASK
l.addi r5,r0,MC_MASK_VAL
l.sw 0(r4),r5
l.addi r4,r3,MC_CSR
l.movhi r5,hi(MC_CSR_VAL)
l.ori r5,r5,lo(MC_CSR_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_TMS(1)
l.movhi r5,hi(SDRAM_TMS_VAL)
l.ori r5,r5,lo(SDRAM_TMS_VAL)
l.sw 0(r4),r5
l.addi r4,r3,MC_CSC(1)
l.movhi r5,hi(SDRAM_BASE_ADDR)
l.srai r5,r5,6
l.ori r5,r5,0x0411
l.sw 0(r4),r5
l.jr r9
l.nop
 
.section .text
.org 0x500
_tick_handler:
#
# Tick timer exception handler
#
232,6 → 159,16
l.nop
 
 
.section .text
_start:
l.movhi r3,hi(_main)
l.ori r3,r3,lo(_main)
l.jr r3
l.nop
 
_main:
l.nop
l.addi r3,r0,SPR_SR_SM
/trunk/or1ksim/testsuite/test-code-or1k/int-test/Makefile.am
29,6 → 29,4
 
int_test_SOURCES = int-test.S
 
int_test_LDFLAGS = -T$(srcdir)/int-test.ld
 
EXTRA_DIST = int-test.ld
int_test_LDFLAGS = -T$(srcdir)/../default.ld
/trunk/or1ksim/testsuite/test-code-or1k/flag/flag.S
32,21 → 32,25
#define SET_ARITH_FLAG 0 /* If this is not set this test has no meaning */
 
.section .except, "ax"
l.movhi r10,0x8000
 
.section .text
.org 0x100
_reset:
l.nop
l.movhi r10,0x8000
l.addi r11,r0,-1
l.addi r12,r0,2
l.addi r13,r0,0x5678
l.movhi r14,0xdead
l.ori r14,r14,0xdead
l.addi r15,r0,0xdead
l.movhi r10,0x8000
l.addi r11,r0,-1
l.addi r12,r0,2
l.addi r13,r0,0x5678
l.movhi r14,0xdead
l.ori r14,r14,0xdead
l.addi r15,r0,0xdead
l.movhi r3,hi(start)
l.ori r3,r3,lo(start)
l.jr r3
l.nop
 
 
.section .text
start:
/* Test start */
#if SET_ARITH_FLAG
/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.in
218,6 → 218,7
mc_sync_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_sync_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-sync/Makefile.am
34,6 → 34,7
mc_sync_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_sync_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.in
218,6 → 218,7
mc_async_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_async_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/mc-async/Makefile.am
34,6 → 34,7
mc_async_CPPFLAGS = -I$(srcdir)/../../../peripheral \
-I$(srcdir)/../../../cpu/common \
-I$(srcdir)/../../../cpu/or1k \
-I$(srcdir)/../mc-common \
-I$(srcdir)/../../../port
 
mc_async_LDFLAGS = -T$(srcdir)/../except-mc.ld
/trunk/or1ksim/testsuite/test-code-or1k/support/support.c
477,6 → 477,10
/* Decode the field */
i++;
 
/* Ignore periods */
if ('.' == fmt[i])
i++;
 
/* Are leading zeros requested? */
if ('0' == fmt[i])
{
/trunk/or1ksim/testsuite/or1ksim.tests/default.cfg
113,13 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/or1ksim.tests/mem-test.exp
27,20 → 27,20
# Run the simple memory test.
run_or1ksim "mem-test" \
[list "report(0x12345678);" \
"report(0x00001234);" \
"report(0x00005678);" \
"report(0x00000012);" \
"report(0x00000034);" \
"report(0x00000056);" \
"report(0x00000078);" \
"report(0xdeaddead);" \
"report(0x5678dead);" \
"report(0x56781234);" \
"report(0xdd781234);" \
"report(0xddcc1234);" \
"report(0xddccbb34);" \
"report(0xddccbbaa);" \
"report(0xda25e544);" \
"report(0xdeaddead);" \
"!exit(0)"] \
"report(0x00001234);" \
"report(0x00005678);" \
"report(0x00000012);" \
"report(0x00000034);" \
"report(0x00000056);" \
"report(0x00000078);" \
"report(0xdeaddead);" \
"report(0x5678dead);" \
"report(0x56781234);" \
"report(0xdd781234);" \
"report(0xddcc1234);" \
"report(0xddccbb34);" \
"report(0xddccbbaa);" \
"report(0xda25e544);" \
"report(0xdeaddead);" \
"!exit(0)"] \
"" "mem-test/mem-test"
/trunk/or1ksim/testsuite/or1ksim.tests/mmu.cfg
81,6 → 81,15
blocksize = 16
end
 
section cpu
ver = 0x12
rev = 0x0001
/* upr = */
superscalar = 0
hazards = 0
dependstats = 0
end
 
section sim
/* verbose = 1 */
debug = 0
92,11 → 101,3
exe_log = 0
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
end
 
 
/trunk/or1ksim/testsuite/or1ksim.tests/cache.exp
26,10 → 26,15
 
# Run the cache test
run_or1ksim "cache" \
[list "report(0xdeaddead);" \
"report(0xdeaddead);" \
"report(0xdeaddead);" \
"report(0xdeaddead);" \
"report(0xdeaddead);" \
"!exit(0)"] \
[list "report(0x00000000);" \
"report(0xdeaddead);" \
"report(0x00000001);" \
"report(0xdeaddead);" \
"report(0x00000002);" \
"report(0xdeaddead);" \
"report(0x00000003);" \
"report(0x00000004);" \
"report(0xdeaddead);" \
"report(0xdeaddead);" \
"exit(0)"] \
"" "cache/cache"
/trunk/or1ksim/testsuite/or1ksim.tests/eth.cfg
113,13 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/or1ksim.tests/mmu.exp
24,118 → 24,18
# -----------------------------------------------------------------------------
 
 
# Run the Ethernet test
# Run the MMU test
run_or1ksim "mmu" \
[list "ea = 0017bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0017e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0027bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0027e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0047bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0047e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0087bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0087e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0107bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0107e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0207bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0207e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0407bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0407e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0807bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 0807e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 1007bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 1007e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 2007bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 2007e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 4007bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 4007e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 8007bffc set = 61 way = 0" \
"tlbtr = 0017b3c0 dtlb_val = 000003c0" \
"ea = 8007e000 set = 63 way = 0" \
"tlbtr = 0017e3c0 dtlb_val = 000003c0" \
"ea = 0027c000 set = 62 way = 0" \
"tlbtr = 0017c3c0 dtlb_val = 000003c0" \
"ea = 0027c000 set = 62 way = 0" \
"tlbtr = 0017c3c0 dtlb_val = 000003c0" \
"ea = 0017c000 set = 62 way = 0" \
"ea = 0017c000 set = 62 way = 0" \
"ea = 0017c000 set = 62 way = 0" \
"ea = 0017c000 set = 62 way = 0" \
"ea = 0017bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0017e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0027bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0027e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0047bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0047e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0087bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0087e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0107bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0107e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0207bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0207e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0407bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0407e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0807bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 0807e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 1007bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 1007e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 2007bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 2007e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 4007bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 4007e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 8007bff8 set = 61 way = 0" \
"ta = 0017bff8" \
"ea = 8007e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0027e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0027e000 set = 63 way = 0" \
"ta = 0017e000" \
"ea = 0017c000 set = 62 way = 0" \
"ea = 0017c000 set = 62 way = 0" \
"!report(0xdeaddead);" \
"!exit(0)"] \
[list "DTLB translation tests OK" \
"DTLB match tests OK" \
"DTLB valid bit tests OK" \
"DTLB permission bit tests OK" \
"ITLB translation tests OK" \
"ITLB match tests OK" \
"ITLB valid bit tests OK" \
"ITLB permission tests OK" \
"Tests completed" \
"report(0xdeaddead);" \
"report(0x8000000d);" \
"exit(0)"] \
"mmu.cfg" "mmu/mmu"
/trunk/or1ksim/testsuite/or1ksim.tests/kbdtest.cfg
113,13 → 113,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/or1ksim.tests/int-test.exp
27,92 → 27,92
# Run the Interrupt test. Note this is not a test of the Programmable
# Interrupt Controller.
run_or1ksim "int-test" \
[list "report(0x00000628);" \
"report(0x00000000);" \
"report(0x00000628);" \
"report(0x00000000);" \
"report(0x00000628);" \
"report(0x00000000);" \
"report(0x00000628);" \
"report(0x00000000);" \
"report(0x00000628);" \
"report(0x00000000);" \
"report(0x00000628);" \
"report(0x00000000);" \
"report(0x0000062c);" \
"report(0x00000004);" \
"report(0x0000062c);" \
"report(0x00000004);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000630);" \
"report(0x00000008);" \
"report(0x00000634);" \
"report(0x0000000c);" \
"report(0x00000634);" \
"report(0x0000000c);" \
"report(0x00000638);" \
"report(0x00000010);" \
"report(0x00000638);" \
"report(0x00000010);" \
"report(0x00000638);" \
"report(0x00000010);" \
"report(0x00000638);" \
"report(0x00000010);" \
"report(0x0000063c);" \
"report(0x00000014);" \
"report(0x0000063c);" \
"report(0x00000014);" \
"report(0x00000640);" \
"report(0x00000018);" \
"report(0x00000640);" \
"report(0x00000018);" \
"report(0x00000640);" \
"report(0x00000018);" \
"report(0x00000640);" \
"report(0x00000018);" \
"report(0x0000064c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000064c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000064c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000064c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x00000650);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x00000650);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x00000650);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x00000650);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x00000658);" \
"report(0x00000030);" \
"report(0x00000658);" \
"report(0x00000030);" \
"report(0x0000065c);" \
"report(0x00000034);" \
"report(0x0000065c);" \
"report(0x00000034);" \
"report(0x00000660);" \
"report(0x00000038);" \
"!report(0xdeaddead);" \
"!exit(0)"] \
[list "report(0x00002078);" \
"report(0x00000000);" \
"report(0x00002078);" \
"report(0x00000000);" \
"report(0x00002078);" \
"report(0x00000000);" \
"report(0x00002078);" \
"report(0x00000000);" \
"report(0x00002078);" \
"report(0x00000000);" \
"report(0x00002078);" \
"report(0x00000000);" \
"report(0x0000207c);" \
"report(0x00000004);" \
"report(0x0000207c);" \
"report(0x00000004);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002080);" \
"report(0x00000008);" \
"report(0x00002084);" \
"report(0x0000000c);" \
"report(0x00002084);" \
"report(0x0000000c);" \
"report(0x00002088);" \
"report(0x00000010);" \
"report(0x00002088);" \
"report(0x00000010);" \
"report(0x00002088);" \
"report(0x00000010);" \
"report(0x00002088);" \
"report(0x00000010);" \
"report(0x0000208c);" \
"report(0x00000014);" \
"report(0x0000208c);" \
"report(0x00000014);" \
"report(0x00002090);" \
"report(0x00000018);" \
"report(0x00002090);" \
"report(0x00000018);" \
"report(0x00002090);" \
"report(0x00000018);" \
"report(0x00002090);" \
"report(0x00000018);" \
"report(0x0000209c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000209c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000209c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x0000209c);" \
"report(0x00000024);" \
"report(0x00008203);" \
"report(0x000020a0);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x000020a0);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x000020a0);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x000020a0);" \
"report(0x00000028);" \
"report(0x00008003);" \
"report(0x000020a8);" \
"report(0x00000030);" \
"report(0x000020a8);" \
"report(0x00000030);" \
"report(0x000020ac);" \
"report(0x00000034);" \
"report(0x000020ac);" \
"report(0x00000034);" \
"report(0x000020b0);" \
"report(0x00000038);" \
"report(0xdeaddead);" \
"exit(0)"] \
"" "int-test/int-test"
/trunk/or1ksim/testsuite/or1ksim.tests/fp.cfg
114,13 → 114,6
exe_log_fn = "executed.log"
end
 
section mc
enabled = 1
baseaddr = 0x93000000
POC = 0x00000008 /* Power on configuration register */
index = 0
end
 
section dma
baseaddr = 0xB8000000
irq = 4
/trunk/or1ksim/testsuite/ChangeLog
1,3 → 1,82
2011-01-04 Julius Baxter <julius@opencores.org>
* libsim.tests/default.cfg: Remove superfluous sections. Change CPU
SR to 0x8001 (unset EPH bit).
* libsim.tests/int-edge.cfg: Remove MC section
* libsim.tests/int-level.cfg: Ditto
* libsim.tests/upcalls.cfg: Ditto, also remove other superfluous
section definitions.
* test-code-or1k/basic/Makefile.am: Add default linker and exception
library to LDADD flags.
* test-code-or1k/basic/basic.S: Remove reset section and MC init. Add
main section symbol.
* test-code-or1k/default.ld: Remove flash section (all flash boot
capability has been removed from software.)
Place exception handlers in except section.
<_bstart>:Added to indicate start of BSS section
<_bend>:Added to indicate end of BSS section
* test-code-or1k/except-mc.ld: Added (.rodata.*) to data section.
* test-code-or1k/except/except.S: Remove MC init code.
Remove code which copied program from flash to RAM on boot.
Added all handler sections.
Fixed bug with DTLB handler which would -4 off EPCR.
Now take care to create exception stack past redzone of 128 bytes.
* test-code-or1k/tick/tick.c:
(tick_int_spurious): Fix apparent bug with spurious interrupt test
which would continue interrupting the program, not allowing it to
proceed. Achieve by clearing ttmr when enough interrupts were seen.
* test-code-or1k/ext/ext.S: Add labels for linker sections.
* test-code-or1k/cache/cache.ld: Similar changes to default.ld
* test-code-or1k/cache/cache-asm.S: Remove MC init and relocation code.
* test-code-or1k/cache/cache.c: Remove UART code.
(init_cache_config): Add function for automatic detection of cache
settings.
* test-code-or1k/fp/fp.S: Remove MC init code.
(illegal_insn): Added illegal instruction handler to indicate if FPU
needs to be enabled.
* test-code-or1k/mc-ssram/mc-ssram.c: <gpio_pat>: Init to 0 to stop GCC
warning.
* test-code-or1k/mul/mul.c:
(macrc): Add l.nops before l.macrc. Workaround for bug #1930.
* test-code-or1k/mmu/mmu.c: Almost entirely reimplemented, based on
version from ORPSoC.
* test-code-or1k/mmu/mmu-asm.S: Clobber r3 instead of r11 in lo_immu_en
* test-code-or1k/cfg/cfg.S: Change section labels to allow use with new
default.ld.
* test-code-or1k/except-test/except-test-s.S: Remove MC init code.
Add new reset section code.
Add .org directives for each vector handler.
Change immediate of l.trap to 15 from 1
* test-code-or1k/except-test/except-test.c: <FLASH_START>: Removed,
substituted with RAM_START where appropriate.
<FLASH_SIZE>: Removed.
<RAM_SIZE>: Changed to 2MB.
<TEST_BASE>: Removed as was not used.
Added some printf() output to indicate progress of test.
* test-code-or1k/dhry/dhry.c: <DBG>: Removed all #if sections for this
define.
* test-code-or1k/int-test/int-test.ld: Removed
* test-code-or1k/int-test/int-test.S: Remove MC init code.
Changed reset section to except section.
* test-code-or1k/int-test/Makefile.am: <int_test_LDFLAGS>: Changed to
use default.ld.
* test-code-or1k/flag/flag.S: Change exceptions to be in .except section
* test-code-or1k/mc-sync/Makefile.am: <mc_sync_CPPFLAGS>: Added
mc-common as include path.
* test-code-or1k/mc-async/Makefile.am: <mc_async_CPPFLAGS>: Ditto.
* test-code-or1k/support/support.c:
(printf): Added ignoring of '.' in printf format fields.
* or1ksim.tests/default.cfg: Removed MC section.
* or1ksim.tests/mem-test.exp: Updated expect list.
* or1ksim.tests/mmu.cfg: Added CPU section. Removed MC section.
* or1ksim.tests/cache.exp: Updated expect list.
* or1ksim.tests/eth.cfg: Removed MC section.
* or1ksim.tests/mmu.exp: Updated expect list.
* or1ksim.tests/kbdtest.cfg: Removed MC section.
* or1ksim.tests/int-test.exp: Updated expect list.
* or1ksim.tests/fp.cfg: Removed MC section.
* test-code/lib-upcalls/lib-upcalls.c: Added explicit handling of
OR1KSIM_RC_HALTED return code from library run execute function.
2010-12-27 Julius Baxter <julius@opencores.org>
 
* or1ksim.tests/eth.cfg: Ethernet section, commented out sockif setting,
/trunk/or1ksim/testsuite/test-code/lib-upcalls/lib-upcalls.c
357,14 → 357,18
case OR1KSIM_RC_OK:
break;
 
case OR1KSIM_RC_HALTED:
printf ("Test completed successfully: hit exit l.nop.\n");
return 0;
 
case OR1KSIM_RC_BRKPT:
printf ("Test completed successfully: hit breakpoint.\n");
return 0;
 
default:
printf ("ERROR: run failed\n");
return 1;
}
}
}
while (upcall_count > 0);
 
375,6 → 379,10
printf ("Test completed successfully: All upcalls processed.\n");
return 0;
 
case OR1KSIM_RC_HALTED:
printf ("Test completed successfully: hit exit l.nop.\n");
return 0;
 
case OR1KSIM_RC_BRKPT:
printf ("Test completed successfully: hit breakpoint.\n");
return 0;

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