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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

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    from Rev 503 to Rev 504
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Rev 503 → Rev 504

/trunk/orpsocv2/rtl/verilog/include/or1200_defines.v
359,11 → 359,12
//
// Type of ALU compare to implement
//
// Try either one to find what yields
// higher clock frequencyin your case.
// Try to find which synthesizes with
// most efficient logic use or highest speed.
//
//`define OR1200_IMPL_ALU_COMP1
`define OR1200_IMPL_ALU_COMP2
//`define OR1200_IMPL_ALU_COMP2
`define OR1200_IMPL_ALU_COMP3
 
//
// Implement Find First/Last '1'
/trunk/orpsocv2/rtl/verilog/or1200/or1200_alu.v
100,10 → 100,8
reg ov_we;
wire [width-1:0] comp_a;
wire [width-1:0] comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire a_eq_b;
wire a_lt_b;
`endif
wire [width-1:0] result_sum;
wire [width-1:0] result_and;
wire cy_sum;
120,6 → 118,7
//
// Combinatorial logic
//
 
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
126,9 → 125,22
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
(!a[width-1] & !b[width-1] & result_sum[width-1])|
(a[width-1] & b[width-1] & result_sum[width-1])):
result_sum[width-1];
`endif
`ifdef OR1200_IMPL_SUB
`ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
`else
assign cy_sub = (comp_a < comp_b);
`endif
`endif
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
{{width-1{1'b0}},carry} : {width{1'b0}};
135,11 → 147,21
`else
assign carry_in = {width-1{1'b0}};
`endif
 
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
(~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
409,7 → 431,29
flagcomp = 1'b0;
endcase
end
`endif // `ifdef OR1200_IMPL_ALU_COMP2
 
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
case(comp_op[2:0]) // synopsys parallel_case
`OR1200_COP_SFEQ:
flagcomp = a_eq_b;
`OR1200_COP_SFNE:
flagcomp = ~a_eq_b;
`OR1200_COP_SFGT:
flagcomp = ~(a_eq_b | a_lt_b);
`OR1200_COP_SFGE:
flagcomp = ~a_lt_b;
`OR1200_COP_SFLT:
flagcomp = a_lt_b;
`OR1200_COP_SFLE:
flagcomp = a_eq_b | a_lt_b;
default:
flagcomp = 1'b0;
endcase
end
`endif
 
`ifdef OR1200_IMPL_ALU_EXT
always @(alu_op or alu_op2 or a) begin
/trunk/orpsocv2/rtl/verilog/or1200/or1200_rf.v
197,29 → 197,21
else if (~wb_freeze)
rf_we_allow <= ~flushpipe;
 
//assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow;
//assign cy_we_o = cy_we_i && rf_we;
 
assign cy_we_o = cy_we_i && ~wb_freeze && rf_we_allow;
//
// CS RF A asserted when instruction reads operand A and ID stage
// is not stalled
//
//assign rf_ena = rda & ~id_freeze | spr_valid; // probably works with fixed binutils
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe; // probably works with fixed binutils
// assign rf_ena = 1'b1; // does not work with single-stepping
//assign rf_ena = ~id_freeze | spr_valid; // works with broken binutils
assign rf_ena = (rda & ~id_freeze) | (spr_valid & !spr_write) | spr_cs_fe;
 
//
// CS RF B asserted when instruction reads operand B and ID stage
// is not stalled
//
//assign rf_enb = rdb & ~id_freeze | spr_valid;
assign rf_enb = rdb & ~id_freeze;
// assign rf_enb = 1'b1;
//assign rf_enb = ~id_freeze | spr_valid; // works with broken binutils
 
`ifdef OR1200_RFRAM_TWOPORT
 
/trunk/orpsocv2/sw/tests/or1200/sim/or1200-sf.S
0,0 → 1,221
/*
 
Basic l.sfxx comparison instruction tests.
 
Does not cover set-flag-against-immediate
 
Julius Baxter, ORSoC AB, <julius.baxter@orsoc.se>
*/
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
#include "spr-defs.h"
 
 
/* =================================================== [ exceptions ] === */
.section .vectors, "ax"
 
 
/* ---[ 0x100: RESET exception ]----------------------------------------- */
.org 0x100
l.movhi r0, 0
/* Clear status register */
l.ori r1, r0, SPR_SR_SM
l.mtspr r0, r1, SPR_SR
/* Clear timer */
l.mtspr r0, r0, SPR_TTMR
 
/* Jump to program initialisation code */
.global _start
l.movhi r4, hi(_start)
l.ori r4, r4, lo(_start)
l.jr r4
l.nop
 
 
/* =================================================== [ text ] === */
.section .text
 
/* =================================================== [ start ] === */
 
#define SHOULD_BE_SET l.bnf _fail
#define SHOULDNT_BE_SET l.bf _fail
 
#define MOVE_TO_R4R5_AND_REPORT(a,b) \
l.movhi r3,hi(a) ; \
l.ori r3,r3,lo(a) ; \
l.nop 0x2 ; \
l.or r4,r3,r3 ; \
l.movhi r3,hi(b) ; \
l.ori r3,r3,lo(b) ; \
l.nop 0x2 ; \
l.or r5,r3,r3
 
// Tests to check these values should be less than
#define SHOULD_BE_LESS_THAN_SIGNED(a,b) \
MOVE_TO_R4R5_AND_REPORT(a,b) ; \
l.sfeq r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfne r4,r5 ; \
SHOULD_BE_SET ; \
l.sfgts r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfges r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfles r4,r5 ; \
SHOULD_BE_SET ; \
l.sflts r4,r5 ; \
SHOULD_BE_SET
 
#define SHOULD_BE_GREATER_THAN_SIGNED(a,b) \
MOVE_TO_R4R5_AND_REPORT(a,b) ; \
l.sfeq r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfne r4,r5 ; \
SHOULD_BE_SET ; \
l.sfgts r4,r5 ; \
SHOULD_BE_SET ; \
l.sfges r4,r5 ; \
SHOULD_BE_SET ; \
l.sfles r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sflts r4,r5 ; \
SHOULDNT_BE_SET
#define SHOULD_BE_LESS_THAN_UNSIGNED(a,b) \
MOVE_TO_R4R5_AND_REPORT(a,b) ; \
l.sfeq r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfne r4,r5 ; \
SHOULD_BE_SET ; \
l.sfgtu r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfgeu r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfleu r4,r5 ; \
SHOULD_BE_SET ; \
l.sfltu r4,r5 ; \
SHOULD_BE_SET
 
#define SHOULD_BE_GREATER_THAN_UNSIGNED(a,b) \
MOVE_TO_R4R5_AND_REPORT(a,b) ; \
l.sfeq r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfne r4,r5 ; \
SHOULD_BE_SET ; \
l.sfgtu r4,r5 ; \
SHOULD_BE_SET ; \
l.sfgeu r4,r5 ; \
SHOULD_BE_SET ; \
l.sfleu r4,r5 ; \
SHOULDNT_BE_SET ; \
l.sfltu r4,r5 ; \
SHOULDNT_BE_SET
 
#define INT_MAX 2147483647 /*0x7fffffff*/
#define INT_MAX_MIN1 2147483646 /*0x7ffffffe*/
#define NEG_INT_MAX -2147483648 /*0x80000000*/
#define NEG_INT_MAX_PL1 -2147483647 /*0x80000001*/
#define MIN1 -1 /*0xffffffff*/
#define UINT_MAX 4294967295 /*0xffffffff*/
#define UINT_MAX_MIN1 4294967294 /*0xfffffffe*/
 
.global _start
_start:
/* Signed tests */
SHOULD_BE_LESS_THAN_SIGNED(0,1)
SHOULD_BE_LESS_THAN_SIGNED(MIN1,0)
SHOULD_BE_LESS_THAN_SIGNED(INT_MAX_MIN1,INT_MAX)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX,INT_MAX)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX,INT_MAX_MIN1)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX_PL1,INT_MAX)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX_PL1,INT_MAX_MIN1)
 
SHOULD_BE_LESS_THAN_SIGNED(-7,-6)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX,NEG_INT_MAX_PL1)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX,MIN1)
SHOULD_BE_LESS_THAN_SIGNED(NEG_INT_MAX,0)
 
SHOULD_BE_GREATER_THAN_SIGNED(1,0)
SHOULD_BE_GREATER_THAN_SIGNED(0,MIN1)
SHOULD_BE_GREATER_THAN_SIGNED(INT_MAX,INT_MAX_MIN1)
SHOULD_BE_GREATER_THAN_SIGNED(INT_MAX,NEG_INT_MAX)
SHOULD_BE_GREATER_THAN_SIGNED(INT_MAX_MIN1,NEG_INT_MAX)
SHOULD_BE_GREATER_THAN_SIGNED(INT_MAX,NEG_INT_MAX_PL1)
SHOULD_BE_GREATER_THAN_SIGNED(INT_MAX_MIN1,NEG_INT_MAX_PL1)
 
SHOULD_BE_GREATER_THAN_SIGNED(-6,-7)
SHOULD_BE_GREATER_THAN_SIGNED(NEG_INT_MAX_PL1,NEG_INT_MAX)
SHOULD_BE_GREATER_THAN_SIGNED(MIN1,NEG_INT_MAX)
SHOULD_BE_GREATER_THAN_SIGNED(0,NEG_INT_MAX)
 
/* Unsigned tests */
SHOULD_BE_LESS_THAN_UNSIGNED(0,1)
SHOULD_BE_LESS_THAN_UNSIGNED(UINT_MAX_MIN1,UINT_MAX)
 
SHOULD_BE_GREATER_THAN_UNSIGNED(1,0)
SHOULD_BE_GREATER_THAN_UNSIGNED(UINT_MAX,UINT_MAX_MIN1)
 
 
 
_finish:
l.movhi r3, hi(0x8000000d)
l.ori r3, r3, lo(0x8000000d)
l.nop 0x2
l.ori r3, r0, 0
l.nop 0x1
 
_fail:
l.ori r3, r0, 0x1
l.nop 0x1

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