URL
https://opencores.org/ocsvn/openrisc/openrisc/trunk
Subversion Repositories openrisc
Compare Revisions
- This comparison shows the changes necessary to convert path
/openrisc
- from Rev 516 to Rev 517
- ↔ Reverse comparison
Rev 516 → Rev 517
/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/Makefile.in
83,7 → 83,8
ARFLAGS = cru |
lib_a_AR = $(AR) $(ARFLAGS) |
lib_a_LIBADD = |
am_lib_a_OBJECTS = lib_a-longjmp.$(OBJEXT) lib_a-setjmp.$(OBJEXT) |
am_lib_a_OBJECTS = lib_a-longjmp.$(OBJEXT) lib_a-setjmp.$(OBJEXT) \ |
lib_a-or1k-support.$(OBJEXT) lib_a-or1k-support-asm.$(OBJEXT) |
lib_a_OBJECTS = $(am_lib_a_OBJECTS) |
DEFAULT_INCLUDES = -I. -I$(srcdir) |
depcomp = |
212,7 → 213,7
INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS) |
AM_CCASFLAGS = $(INCLUDES) |
noinst_LIBRARIES = lib.a |
lib_a_SOURCES = longjmp.S setjmp.S |
lib_a_SOURCES = longjmp.S setjmp.S or1k-support.c or1k-support-asm.S |
lib_a_CCASFLAGS = $(AM_CCASFLAGS) |
lib_a_CFLAGS = $(AM_CFLAGS) |
ACLOCAL_AMFLAGS = -I ../../.. -I ../../../.. |
285,6 → 286,19
|
lib_a-setjmp.obj: setjmp.S |
$(CCAS) $(lib_a_CCASFLAGS) $(CCASFLAGS) -c -o lib_a-setjmp.obj `if test -f 'setjmp.S'; then $(CYGPATH_W) 'setjmp.S'; else $(CYGPATH_W) '$(srcdir)/setjmp.S'; fi` |
|
lib_a-or1k-support-asm.o: or1k-support-asm.S |
$(CCAS) $(lib_a_CCASFLAGS) $(CCASFLAGS) -c -o lib_a-or1k-support-asm.o `test -f 'or1k-support-asm.S' || echo '$(srcdir)/'`or1k-support-asm.S |
|
lib_a-or1k-support-asm.obj: or1k-support-asm.S |
$(CCAS) $(lib_a_CCASFLAGS) $(CCASFLAGS) -c -o lib_a-or1k-support-asm.obj `if test -f 'or1k-support-asm.S'; then $(CYGPATH_W) 'or1k-support-asm.S'; else $(CYGPATH_W) '$(srcdir)/or1k-support-asm.S'; fi` |
|
lib_a-or1k-support.o: or1k-support.c |
$(CC) $(lib_a_CFLAGS) $(CFLAGS) -c -o lib_a-or1k-support.o `test -f 'or1k-support.c' || echo '$(srcdir)/'`or1k-support.c |
|
lib_a-or1k-support.obj: or1k-support.c |
$(CC) $(lib_a_CFLAGS) $(CFLAGS) -c -o lib_a-or1k-support.obj `if test -f 'or1k-support.c'; then $(CYGPATH_W) 'or1k-support.c'; else $(CYGPATH_W) '$(srcdir)/or1k-support.c'; fi` |
|
uninstall-info-am: |
|
ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) |
/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/include/spr-defs.h
0,0 → 1,629
/* ipc.h. Microkernel IPC header for Or1ksim |
|
Copyright (C) 2000 Damjan Lampret |
Copyright (C) 2008, 2010 Embecosm Limited |
|
Contributor Damjan Lampret <lampret@opencores.org> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http: www.gnu.org/licenses/>. */ |
|
/* ---------------------------------------------------------------------------- |
This code is commented throughout for use with Doxygen. |
--------------------------------------------------------------------------*/ |
|
/* This file is part of test microkernel for OpenRISC 1000. */ |
/* spr-defs.h -- Defines OR1K architecture specific special-purpose registers |
|
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
Copyright (C) 2008 Embecosm Limited |
|
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
/* This program is commented throughout in a fashion suitable for processing |
with Doxygen. */ |
|
|
#ifndef SPR_DEFS__H |
#define SPR_DEFS__H |
|
/* Definition of special-purpose registers (SPRs). */ |
|
#define MAX_GRPS (32) |
#define MAX_SPRS_PER_GRP_BITS (11) |
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) |
#define MAX_SPRS (0x10000) |
|
/* Base addresses for the groups */ |
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_FP (11<< MAX_SPRS_PER_GRP_BITS) |
|
/* System control and status group */ |
#define SPR_VR (SPRGROUP_SYS + 0) |
#define SPR_UPR (SPRGROUP_SYS + 1) |
#define SPR_CPUCFGR (SPRGROUP_SYS + 2) |
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) |
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) |
#define SPR_DCCFGR (SPRGROUP_SYS + 5) |
#define SPR_ICCFGR (SPRGROUP_SYS + 6) |
#define SPR_DCFGR (SPRGROUP_SYS + 7) |
#define SPR_PCCFGR (SPRGROUP_SYS + 8) |
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ |
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ |
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ |
#define SPR_FPCSR (SPRGROUP_SYS + 20) /* CZ 21/06/01 */ |
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ |
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ |
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) |
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) |
#define SPR_ESR_BASE (SPRGROUP_SYS + 64) |
#define SPR_ESR_LAST (SPRGROUP_SYS + 79) |
#define SPR_GPR_BASE (SPRGROUP_SYS + 1024) |
|
/* Data MMU group */ |
#define SPR_DMMUCR (SPRGROUP_DMMU + 0) |
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) |
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) |
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) |
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) |
|
/* Instruction MMU group */ |
#define SPR_IMMUCR (SPRGROUP_IMMU + 0) |
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) |
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) |
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) |
|
/* Data cache group */ |
#define SPR_DCCR (SPRGROUP_DC + 0) |
#define SPR_DCBPR (SPRGROUP_DC + 1) |
#define SPR_DCBFR (SPRGROUP_DC + 2) |
#define SPR_DCBIR (SPRGROUP_DC + 3) |
#define SPR_DCBWR (SPRGROUP_DC + 4) |
#define SPR_DCBLR (SPRGROUP_DC + 5) |
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) |
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) |
|
/* Instruction cache group */ |
#define SPR_ICCR (SPRGROUP_IC + 0) |
#define SPR_ICBPR (SPRGROUP_IC + 1) |
#define SPR_ICBIR (SPRGROUP_IC + 2) |
#define SPR_ICBLR (SPRGROUP_IC + 3) |
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) |
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) |
|
/* MAC group */ |
#define SPR_MACLO (SPRGROUP_MAC + 1) |
#define SPR_MACHI (SPRGROUP_MAC + 2) |
|
/* Debug group */ |
#define SPR_DVR(N) (SPRGROUP_D + (N)) |
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) |
#define SPR_DMR1 (SPRGROUP_D + 16) |
#define SPR_DMR2 (SPRGROUP_D + 17) |
#define SPR_DWCR0 (SPRGROUP_D + 18) |
#define SPR_DWCR1 (SPRGROUP_D + 19) |
#define SPR_DSR (SPRGROUP_D + 20) |
#define SPR_DRR (SPRGROUP_D + 21) |
|
/* Performance counters group */ |
#define SPR_PCCR(N) (SPRGROUP_PC + (N)) |
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) |
|
/* Power management group */ |
#define SPR_PMR (SPRGROUP_PM + 0) |
|
/* PIC group */ |
#define SPR_PICMR (SPRGROUP_PIC + 0) |
#define SPR_PICPR (SPRGROUP_PIC + 1) |
#define SPR_PICSR (SPRGROUP_PIC + 2) |
|
/* Tick Timer group */ |
#define SPR_TTMR (SPRGROUP_TT + 0) |
#define SPR_TTCR (SPRGROUP_TT + 1) |
|
/* |
* Bit definitions for the Version Register |
* |
*/ |
#define SPR_VR_VER 0xff000000 /* Processor version */ |
#define SPR_VR_CFG 0x00ff0000 /* Processor configuration */ |
#define SPR_VR_RES 0x00ff0000 /* Reserved */ |
#define SPR_VR_REV 0x0000003f /* Processor revision */ |
|
#define SPR_VR_VER_OFF 24 |
#define SPR_VR_CFG_OFF 16 |
#define SPR_VR_REV_OFF 0 |
|
/* |
* Bit definitions for the Unit Present Register |
* |
*/ |
#define SPR_UPR_UP 0x00000001 /* UPR present */ |
#define SPR_UPR_DCP 0x00000002 /* Data cache present */ |
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ |
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ |
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ |
#define SPR_UPR_MP 0x00000020 /* MAC present */ |
#define SPR_UPR_DUP 0x00000040 /* Debug unit present */ |
#define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ |
#define SPR_UPR_PMP 0x00000100 /* Power management present */ |
#define SPR_UPR_PICP 0x00000200 /* PIC present */ |
#define SPR_UPR_TTP 0x00000400 /* Tick timer present */ |
#define SPR_UPR_RES 0x00fe0000 /* Reserved */ |
#define SPR_UPR_CUP 0xff000000 /* Context units present */ |
|
/* |
* JPB: Bit definitions for the CPU configuration register |
* |
*/ |
#define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ |
#define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ |
#define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ |
#define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ |
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ |
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ |
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ |
#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ |
|
/* |
* JPB: Bit definitions for the Debug configuration register and other |
* constants. |
* |
*/ |
|
#define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ |
#define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ |
#define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ |
#define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ |
#define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ |
#define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ |
#define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ |
#define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ |
#define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ |
#define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */ |
|
#define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ |
2 == n ? SPR_DCFGR_NDP2 : \ |
3 == n ? SPR_DCFGR_NDP3 : \ |
4 == n ? SPR_DCFGR_NDP4 : \ |
5 == n ? SPR_DCFGR_NDP5 : \ |
6 == n ? SPR_DCFGR_NDP6 : \ |
7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) |
#define MAX_MATCHPOINTS 8 |
#define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) |
|
/* |
* Bit definitions for the Supervision Register |
* |
*/ |
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ |
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ |
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ |
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ |
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ |
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ |
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ |
#define SPR_SR_CE 0x00000100 /* CID Enable */ |
#define SPR_SR_F 0x00000200 /* Condition Flag */ |
#define SPR_SR_CY 0x00000400 /* Carry flag */ |
#define SPR_SR_OV 0x00000800 /* Overflow flag */ |
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ |
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ |
#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ |
#define SPR_SR_FO 0x00008000 /* Fixed one */ |
#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ |
#define SPR_SR_RES 0x0ffe0000 /* Reserved */ |
#define SPR_SR_CID 0xf0000000 /* Context ID */ |
|
/* |
* Bit definitions for the Data MMU Control Register |
* |
*/ |
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
|
/* |
* Bit definitions for the Instruction MMU Control Register |
* |
*/ |
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
|
/* |
* Bit definitions for the Data TLB Match Register |
* |
*/ |
#define SPR_DTLBMR_V 0x00000001 /* Valid */ |
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Data TLB Translate Register |
* |
*/ |
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_DTLBTR_A 0x00000010 /* Accessed */ |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */ |
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ |
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ |
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ |
|
#define DTLB_PR_NOLIMIT ( SPR_DTLBTR_URE | \ |
SPR_DTLBTR_UWE | \ |
SPR_DTLBTR_SRE | \ |
SPR_DTLBTR_SWE ) |
|
/* |
* Bit definitions for the Instruction TLB Match Register |
* |
*/ |
#define SPR_ITLBMR_V 0x00000001 /* Valid */ |
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Translate Register |
* |
*/ |
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_ITLBTR_A 0x00000010 /* Accessed */ |
#define SPR_ITLBTR_D 0x00000020 /* Dirty */ |
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ |
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ |
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ |
|
#define ITLB_PR_NOLIMIT ( SPR_ITLBTR_SXE | \ |
SPR_ITLBTR_UXE ) |
|
|
/* |
* Bit definitions for Data Cache Control register |
* |
*/ |
#define SPR_DCCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Insn Cache Control register |
* |
*/ |
#define SPR_ICCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Data Cache Configuration Register |
* |
*/ |
|
#define SPR_DCCFGR_NCW 0x00000007 |
#define SPR_DCCFGR_NCS 0x00000078 |
#define SPR_DCCFGR_CBS 0x00000080 |
#define SPR_DCCFGR_CWS 0x00000100 |
#define SPR_DCCFGR_CCRI 0x00000200 |
#define SPR_DCCFGR_CBIRI 0x00000400 |
#define SPR_DCCFGR_CBPRI 0x00000800 |
#define SPR_DCCFGR_CBLRI 0x00001000 |
#define SPR_DCCFGR_CBFRI 0x00002000 |
#define SPR_DCCFGR_CBWBRI 0x00004000 |
|
#define SPR_DCCFGR_NCW_OFF 0 |
#define SPR_DCCFGR_NCS_OFF 3 |
#define SPR_DCCFGR_CBS_OFF 7 |
|
/* |
* Bit definitions for Instruction Cache Configuration Register |
* |
*/ |
#define SPR_ICCFGR_NCW 0x00000007 |
#define SPR_ICCFGR_NCS 0x00000078 |
#define SPR_ICCFGR_CBS 0x00000080 |
#define SPR_ICCFGR_CCRI 0x00000200 |
#define SPR_ICCFGR_CBIRI 0x00000400 |
#define SPR_ICCFGR_CBPRI 0x00000800 |
#define SPR_ICCFGR_CBLRI 0x00001000 |
|
#define SPR_ICCFGR_NCW_OFF 0 |
#define SPR_ICCFGR_NCS_OFF 3 |
#define SPR_ICCFGR_CBS_OFF 7 |
|
/* |
* Bit definitions for Data MMU Configuration Register |
* |
*/ |
|
#define SPR_DMMUCFGR_NTW 0x00000003 |
#define SPR_DMMUCFGR_NTS 0x0000001C |
#define SPR_DMMUCFGR_NAE 0x000000E0 |
#define SPR_DMMUCFGR_CRI 0x00000100 |
#define SPR_DMMUCFGR_PRI 0x00000200 |
#define SPR_DMMUCFGR_TEIRI 0x00000400 |
#define SPR_DMMUCFGR_HTR 0x00000800 |
|
#define SPR_DMMUCFGR_NTW_OFF 0 |
#define SPR_DMMUCFGR_NTS_OFF 2 |
|
/* |
* Bit definitions for Instruction MMU Configuration Register |
* |
*/ |
|
#define SPR_IMMUCFGR_NTW 0x00000003 |
#define SPR_IMMUCFGR_NTS 0x0000001C |
#define SPR_IMMUCFGR_NAE 0x000000E0 |
#define SPR_IMMUCFGR_CRI 0x00000100 |
#define SPR_IMMUCFGR_PRI 0x00000200 |
#define SPR_IMMUCFGR_TEIRI 0x00000400 |
#define SPR_IMMUCFGR_HTR 0x00000800 |
|
#define SPR_IMMUCFGR_NTW_OFF 0 |
#define SPR_IMMUCFGR_NTS_OFF 2 |
|
/* |
* Bit definitions for Debug Control registers |
* |
*/ |
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ |
#define SPR_DCR_CC 0x0000000e /* Compare condition */ |
#define SPR_DCR_SC 0x00000010 /* Signed compare */ |
#define SPR_DCR_CT 0x000000e0 /* Compare to */ |
|
/* Bit results with SPR_DCR_CC mask */ |
#define SPR_DCR_CC_MASKED 0x00000000 |
#define SPR_DCR_CC_EQUAL 0x00000002 |
#define SPR_DCR_CC_LESS 0x00000004 |
#define SPR_DCR_CC_LESSE 0x00000006 |
#define SPR_DCR_CC_GREAT 0x00000008 |
#define SPR_DCR_CC_GREATE 0x0000000a |
#define SPR_DCR_CC_NEQUAL 0x0000000c |
|
/* Bit results with SPR_DCR_CT mask */ |
#define SPR_DCR_CT_DISABLED 0x00000000 |
#define SPR_DCR_CT_IFEA 0x00000020 |
#define SPR_DCR_CT_LEA 0x00000040 |
#define SPR_DCR_CT_SEA 0x00000060 |
#define SPR_DCR_CT_LD 0x00000080 |
#define SPR_DCR_CT_SD 0x000000a0 |
#define SPR_DCR_CT_LSEA 0x000000c0 |
#define SPR_DCR_CT_LSD 0x000000e0 |
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */ |
|
/* |
* Bit definitions for Debug Mode 1 register |
* |
*/ |
#define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ |
#define SPR_DMR1_CW0_AND 0x00000001 |
#define SPR_DMR1_CW0_OR 0x00000002 |
#define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) |
#define SPR_DMR1_CW1_AND 0x00000004 |
#define SPR_DMR1_CW1_OR 0x00000008 |
#define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) |
#define SPR_DMR1_CW2_AND 0x00000010 |
#define SPR_DMR1_CW2_OR 0x00000020 |
#define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) |
#define SPR_DMR1_CW3_AND 0x00000040 |
#define SPR_DMR1_CW3_OR 0x00000080 |
#define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) |
#define SPR_DMR1_CW4_AND 0x00000100 |
#define SPR_DMR1_CW4_OR 0x00000200 |
#define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) |
#define SPR_DMR1_CW5_AND 0x00000400 |
#define SPR_DMR1_CW5_OR 0x00000800 |
#define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) |
#define SPR_DMR1_CW6_AND 0x00001000 |
#define SPR_DMR1_CW6_OR 0x00002000 |
#define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) |
#define SPR_DMR1_CW7_AND 0x00004000 |
#define SPR_DMR1_CW7_OR 0x00008000 |
#define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) |
#define SPR_DMR1_CW8_AND 0x00010000 |
#define SPR_DMR1_CW8_OR 0x00020000 |
#define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) |
#define SPR_DMR1_CW9_AND 0x00040000 |
#define SPR_DMR1_CW9_OR 0x00080000 |
#define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) |
#define SPR_DMR1_RES1 0x00300000 /* Reserved */ |
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ |
#define SPR_DMR1_BT 0x00800000 /* Branch trace */ |
#define SPR_DMR1_RES2 0xff000000 /* Reserved */ |
|
/* |
* Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB |
* |
*/ |
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ |
#define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ |
#define SPR_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */ |
#define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ |
#define SPR_DMR2_WBS 0xffc00000 /* JPB: Watchpoint status */ |
#define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ |
|
/* |
* Bit definitions for Debug watchpoint counter registers |
* |
*/ |
#define SPR_DWCR_COUNT 0x0000ffff /* Count */ |
#define SPR_DWCR_MATCH 0xffff0000 /* Match */ |
#define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ |
|
/* |
* Bit definitions for Debug stop register |
* |
*/ |
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ |
#define SPR_DSR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DSR_RE 0x00000400 /* Range exception */ |
#define SPR_DSR_SCE 0x00000800 /* System call exception */ |
#define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */ |
#define SPR_DSR_TE 0x00002000 /* Trap exception */ |
|
/* |
* Bit definitions for Debug reason register |
* |
*/ |
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ |
#define SPR_DRR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DRR_RE 0x00000400 /* Range exception */ |
#define SPR_DRR_SCE 0x00000800 /* System call exception */ |
#define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */ |
#define SPR_DRR_TE 0x00002000 /* Trap exception */ |
|
/* |
* Bit definitions for Performance counters mode registers |
* |
*/ |
#define SPR_PCMR_CP 0x00000001 /* Counter present */ |
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ |
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ |
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ |
#define SPR_PCMR_LA 0x00000010 /* Load access event */ |
#define SPR_PCMR_SA 0x00000020 /* Store access event */ |
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ |
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ |
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ |
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ |
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ |
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ |
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ |
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ |
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ |
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ |
|
/* |
* Bit definitions for the Power management register |
* |
*/ |
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ |
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ |
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ |
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ |
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ |
|
/* |
* Bit definitions for PICMR |
* |
*/ |
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ |
|
/* |
* Bit definitions for PICPR |
* |
*/ |
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ |
|
/* |
* Bit definitions for PICSR |
* |
*/ |
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ |
|
/* |
* Bit definitions for Tick Timer Control Register |
* |
*/ |
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ |
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD |
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ |
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ |
#define SPR_TTMR_RT 0x40000000 /* Restart tick */ |
#define SPR_TTMR_SR 0x80000000 /* Single run */ |
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ |
#define SPR_TTMR_M 0xc0000000 /* Tick mode */ |
|
/* |
* Bit definitions for the FP Control Status Register |
* |
*/ |
#define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */ |
#define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */ |
#define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */ |
#define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */ |
#define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */ |
#define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */ |
#define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */ |
#define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */ |
#define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */ |
#define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */ |
#define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */ |
#define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \ |
SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \ |
SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF) |
|
#define FPCSR_RM_RN (0<<1) |
#define FPCSR_RM_RZ (1<<1) |
#define FPCSR_RM_RIP (2<<1) |
#define FPCSR_RM_RIN (3<<1) |
|
#endif /* SPR_DEFS__H */ |
/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/include/or1k-newlib-support.h
0,0 → 1,101
/* OR1K support defines |
|
Copyright (C) 2011, ORSoC AB |
Copyright (C) 2008, 2010 Embecosm Limited |
|
Contributor Julius Baxter <julius.baxter@orsoc.se> |
Contributor Jeremy Bennett <jeremy.bennett@embecosm.com> |
|
This file is part of Newlib. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
/* -------------------------------------------------------------------------- */ |
/* This program is commented throughout in a fashion suitable for processing |
with Doxygen. */ |
/* -------------------------------------------------------------------------- */ |
|
/* This machine configuration matches the Or1ksim configuration file in this |
directory. */ |
|
#ifndef OR1K_NEWLIB_SUPPORT__H |
#define OR1K_NEWLIB_SUPPORT__H |
|
/*! External symbols from each board's object file */ |
extern unsigned long _board_clk_freq; |
|
extern unsigned long _board_uart_base; |
extern unsigned long _board_uart_baud; |
extern unsigned long _board_uart_irq; |
|
/*! Check if board has UART - test base address */ |
#define BOARD_HAS_UART (_board_uart_base) |
|
/*! l.nop constants */ |
#define NOP_NOP 0x0000 /* Normal nop instruction */ |
#define NOP_EXIT 0x0001 /* End of simulation */ |
#define NOP_REPORT 0x0002 /* Simple report */ |
/*#define NOP_PRINTF 0x0003 Simprintf instruction (obsolete)*/ |
#define NOP_PUTC 0x0004 /* JPB: Simputc instruction */ |
#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ |
#define NOP_GET_TICKS 0x0006 /* JPB: Get # ticks running */ |
#define NOP_GET_PS 0x0007 /* JPB: Get picosecs/cycle */ |
#define NOP_REPORT_FIRST 0x0400 /* Report with number */ |
#define NOP_REPORT_LAST 0x03ff /* Report with number */ |
|
/*! Register access macro */ |
#define REG8(add) *((volatile unsigned char *) (add)) |
#define REG16(add) *((volatile unsigned short *) (add)) |
#define REG32(add) *((volatile unsigned long *) (add)) |
|
/*! Interrupt control function prototypes */ |
void or1k_interrupt_handler_add(int, void(*)(void*)); |
void or1k_interrupt_enable(int); |
void or1k_interrupt_disable(int); |
|
/*! Exception handler insertion prototype */ |
void or1k_exception_handler_add(int, void (*)(void)); |
|
/*! SPR access prototypes */ |
void or1k_mtspr (unsigned long int spr, |
unsigned long int value); |
unsigned long int or1k_mfspr (unsigned long int spr); |
|
/*! Simulator prototypes */ |
void or1k_report (unsigned long int value); |
|
/*! Cache control prototypes */ |
void or1k_icache_enable(void); |
void or1k_icache_disable(void); |
void or1k_icache_flush(unsigned long); |
void or1k_dcache_enable(void); |
void or1k_dcache_disable(void); |
void or1k_dcache_flush(unsigned long); |
|
/*! MMU control prototypes */ |
void or1k_immu_enable(void); |
void or1k_immu_disable(void); |
void or1k_dmmu_enable(void); |
void or1k_dmmu_disable(void); |
|
/*! Timer prototypes */ |
void or1k_timer_init(unsigned int hz); |
void or1k_timer_enable(void); |
void or1k_timer_disable(void); |
unsigned long or1k_timer_get_ticks(void); |
void or1k_timer_reset_ticks(void); |
|
/*! Utility function prototypes */ |
unsigned long int or1k_rand(void); |
|
#endif /* OR1K_NEWLIB_SUPPORT__H */ |
/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/or1k-support-asm.S
0,0 → 1,721
/* or1k-support - OR1K CPU support functions |
|
Copyright (C) 2011, ORSoC AB |
|
Contributor Julius Baxter <julius.baxter@orsoc.se> |
|
This file is part of Newlib. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
#include "spr-defs.h" |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to control MMU |
*/ |
/* -------------------------------------------------------------------------- */ |
|
/* MMU control functions always switch MMU control with a l.rfe to return |
from function */ |
.section .text |
|
.global or1k_dmmu_enable |
or1k_dmmu_enable: |
l.mfspr r3,r0,SPR_SR |
l.ori r3,r3,SPR_SR_DME |
l.mtspr r0,r3,SPR_ESR_BASE |
l.mtspr r0,r9,SPR_EPCR_BASE |
l.rfe |
l.nop |
|
|
.global or1k_dmmu_disable |
or1k_dmmu_disable: |
l.ori r3,r0,SPR_SR_DME |
l.xori r4,r3,0xffff |
l.mfspr r3,r0,SPR_SR |
l.and r3,r4,r3 |
l.mtspr r0,r3,SPR_ESR_BASE |
l.mtspr r0,r9,SPR_EPCR_BASE |
l.rfe |
l.nop |
|
|
.global or1k_immu_enable |
or1k_immu_enable: |
l.mfspr r3,r0,SPR_SR |
l.ori r3,r3,SPR_SR_IME |
l.mtspr r0,r3,SPR_ESR_BASE |
l.mtspr r0,r9,SPR_EPCR_BASE |
l.rfe |
l.nop |
|
.global or1k_immu_disable |
or1k_immu_disable: |
l.ori r3,r0,SPR_SR_IME |
l.xori r4,r3,0xffff |
l.mfspr r3,r0,SPR_SR |
l.and r3,r4,r3 |
l.mtspr r0,r3,SPR_ESR_BASE |
l.mtspr r0,r9,SPR_EPCR_BASE |
l.rfe |
l.nop |
|
|
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function used at reset to clear and enable all caches |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_cache_init |
.type or1k_cache_init,@function |
|
or1k_cache_init: |
/* Instruction cache enable */ |
/* Check if IC present and skip enabling otherwise */ |
.L6: l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_ICP |
l.sfeq r4,r0 |
l.bf .L8 |
l.nop |
|
/* Disable IC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_ICE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
|
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_ICCFGR |
l.andi r4,r3,SPR_ICCFGR_CBS |
l.srli r7,r4,7 |
l.ori r8,r0,16 |
l.sll r14,r8,r7 |
|
/* Establish number of cache sets |
r13 contains number of cache sets |
r7 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_ICCFGR_NCS |
l.srli r7,r4,3 |
l.ori r8,r0,1 |
l.sll r13,r8,r7 |
|
/* Invalidate IC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r7 |
|
.L7: l.mtspr r0,r6,SPR_ICBIR |
l.sfne r6,r5 |
l.bf .L7 |
l.add r6,r6,r14 |
|
/* Enable IC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_ICE |
l.mtspr r0,r6,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
|
/* Data cache enable */ |
/* Check if DC present and skip enabling otherwise */ |
.L8: l.mfspr r3,r0,SPR_UPR |
l.andi r4,r3,SPR_UPR_DCP |
l.sfeq r4,r0 |
l.bf .L10 |
l.nop |
/* Disable DC */ |
l.mfspr r6,r0,SPR_SR |
l.addi r5,r0,-1 |
l.xori r5,r5,SPR_SR_DCE |
l.and r5,r6,r5 |
l.mtspr r0,r5,SPR_SR |
/* Establish cache block size |
If BS=0, 16; |
If BS=1, 32; |
r14 contain block size |
*/ |
l.mfspr r3,r0,SPR_DCCFGR |
l.andi r4,r3,SPR_DCCFGR_CBS |
l.srli r7,r4,7 |
l.ori r8,r0,16 |
l.sll r14,r8,r7 |
/* Establish number of cache sets |
r13 contains number of cache sets |
r7 contains log(# of cache sets) |
*/ |
l.andi r4,r3,SPR_DCCFGR_NCS |
l.srli r7,r4,3 |
l.ori r8,r0,1 |
l.sll r13,r8,r7 |
/* Invalidate DC */ |
l.addi r6,r0,0 |
l.sll r5,r14,r7 |
|
.L9: l.mtspr r0,r6,SPR_DCBIR |
l.sfne r6,r5 |
l.bf .L9 |
l.add r6,r6,r14 |
/* Enable DC */ |
l.mfspr r6,r0,SPR_SR |
l.ori r6,r6,SPR_SR_DCE |
l.mtspr r0,r6,SPR_SR |
|
.L10: |
/* Return */ |
l.jr r9 |
l.nop |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to enable instruction cache |
*/ |
/* -------------------------------------------------------------------------- */ |
|
.global or1k_icache_enable |
.type or1k_icache_enable,@function |
|
or1k_icache_enable: |
/* Enable IC */ |
l.mfspr r13,r0,SPR_SR |
l.ori r13,r13,SPR_SR_ICE |
l.mtspr r0,r13,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.jr r9 |
l.nop |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to disable instruction cache |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_icache_disable |
.type or1k_icache_disable,@function |
|
or1k_icache_disble: |
/* Disable IC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r12,r0,-1 |
l.xori r12,r12,SPR_SR_ICE |
l.and r12,r13,r12 |
l.mtspr r0,r12,SPR_SR |
l.jr r9 |
l.nop |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to flush address of instruction cache |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_icache_flush |
.type or1k_icache_flush,@function |
|
or1k_icache_flush: |
/* Push r3 into IC invalidate reg */ |
l.jr r9 |
l.mtspr r0,r3,SPR_ICBIR |
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function to enable data cache |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_dcache_enable |
.type or1k_dcache_enable,@function |
|
or1k_dcache_enable: |
/* Enable DC */ |
l.mfspr r13,r0,SPR_SR |
l.ori r13,r13,SPR_SR_DCE |
l.mtspr r0,r13,SPR_SR |
l.nop |
l.nop |
l.nop |
l.nop |
l.nop |
l.jr r9 |
l.nop |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to disable data cache |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_dcache_disable |
.type or1k_dcache_disable,@function |
|
or1k_dcache_disble: |
/* Disable DC */ |
l.mfspr r13,r0,SPR_SR |
l.addi r12,r0,-1 |
l.xori r12,r12,SPR_SR_DCE |
l.and r12,r13,r12 |
l.mtspr r0,r12,SPR_SR |
l.jr r9 |
l.nop |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to flush address of data cache |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_dcache_flush |
.type or1k_dcache_flush,@function |
|
or1k_dcache_flush: |
/* Push r3 into DC invalidate reg */ |
l.jr r9 |
l.mtspr r0,r3,SPR_DCBIR |
|
|
|
|
/* -------------------------------------------------------------------------- */ |
/*!Generic interrupt handler function for or1k |
*/ |
/* -------------------------------------------------------------------------- */ |
|
#define INTERRUPT_HANDLER_NOT_SET -1 |
|
.data |
.align 4 |
.global or1k_interrupt_handler_table |
or1k_interrupt_handler_table: |
or1k_interrupt_handler0: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler1: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler2: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler3: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler4: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler5: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler6: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler7: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler8: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler9: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler10: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler11: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler12: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler13: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler14: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler15: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler16: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler17: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler18: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler19: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler20: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler21: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler22: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler23: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler24: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler25: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler26: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler27: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler28: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler29: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler30: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler31: .long INTERRUPT_HANDLER_NOT_SET |
|
.global or1k_interrupt_handler_data_ptr_table |
or1k_interrupt_handler_data_ptr_table: |
or1k_interrupt_handler_data_ptr0: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr1: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr2: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr3: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr4: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr5: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr6: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr7: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr8: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr9: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr10: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr11: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr12: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr13: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr14: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr15: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr16: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr17: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr18: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr19: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr20: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr21: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr22: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr23: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr24: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr25: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr26: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr27: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr28: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr29: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr30: .long INTERRUPT_HANDLER_NOT_SET |
or1k_interrupt_handler_data_ptr31: .long INTERRUPT_HANDLER_NOT_SET |
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function to call appropriate interrupt handler |
*/ |
/* -------------------------------------------------------------------------- */ |
|
.section .text |
.global or1k_interrupt_handler |
.type or1k_interrupt_handler,@function |
|
or1k_interrupt_handler: |
/* Make room on stack, save link register */ |
l.addi r1,r1,-12 |
l.sw 0(r1),r9 |
|
/* Read PICSR */ |
l.mfspr r3,r0,SPR_PICSR |
|
/* Load handler table base address */ |
l.movhi r7,hi(or1k_interrupt_handler_table) |
l.ori r7,r7,lo(or1k_interrupt_handler_table) |
/* Check to see if this handler has been set yet */ |
l.movhi r8,hi(INTERRUPT_HANDLER_NOT_SET) |
l.ori r8,r8,lo(INTERRUPT_HANDLER_NOT_SET) |
/* Load data pointer table base address */ |
l.movhi r12,hi(or1k_interrupt_handler_data_ptr_table) |
l.ori r12,r12,lo(or1k_interrupt_handler_data_ptr_table) |
|
.L0: |
/* Find first set bit in PICSR */ |
l.ff1 r4,r3 |
/* Any bits set? */ |
l.sfne r4,r0 |
/* If none, finish */ |
l.bnf .L2 |
l.nop |
/* What is IRQ function table offset? */ |
l.addi r5,r4,-1 |
l.slli r6,r5,2 |
/* Add this to table bases */ |
l.add r6,r6,r7 |
l.add r13,r6,r12 |
|
/* Fetch handler function address */ |
l.lwz r6,0(r6) |
|
/* Double check it's valid, compare against INTERRUPT_HANDLER_NOT_SET */ |
l.sfne r6,r8 |
/* Skip if no handler: TODO: Indicate interrupt fired but no handler*/ |
l.bnf .L1 |
l.nop |
|
/* Pull out data pointer from table, save r3, we'll write over it */ |
l.sw 4(r1),r3 |
l.lwz r3,0(r13) |
/* Call handler, save r5 in delay slot */ |
l.jalr r5 |
l.sw 8(r1),r5 |
|
/* Reload r3,r5 */ |
l.lwz r3,4(r1) |
l.lwz r5,8(r1) |
.L1: |
/* Clear bit from PICSR, return to start of checking loop */ |
l.ori r6,r0,1 |
l.sll r6,r6,r5 |
l.j .L0 |
l.xor r3,r3,r6 |
|
.L2: |
/* Finish up - write PICSR back, restore r9*/ |
l.lwz r9,0(r1) |
l.mtspr r0,r3,SPR_PICSR |
l.jr r9 |
l.addi r1,r1,12 |
|
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function to add handler to table |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_interrupt_handler_add |
.type or1k_interrupt_handler_add,@function |
|
/* r3 should have IRQ line for peripheral */ |
/* r4 should have handler function address */ |
or1k_interrupt_handler_add: |
l.addi r1,r1,-4 |
l.sw 0(r1),r6 |
/* Convert interrupt number into word address */ |
l.slli r3,r3,2 |
l.addi r3,r3,-4 |
/* Get address of interrupt handler table */ |
l.movhi r6,hi(or1k_interrupt_handler_table) |
l.ori r6,r6,lo(or1k_interrupt_handler_table) |
/* Add handler offset to table base */ |
l.add r6,r6,r3 |
/* Store handler function address */ |
l.sw 0(r6),r4 |
/* Get address of interrupt handler data ptr table */ |
l.movhi r6,hi(or1k_interrupt_handler_data_ptr_table) |
l.ori r6,r6,lo(or1k_interrupt_handler_data_ptr_table) |
/* Add handler offset to table base */ |
l.add r6,r6,r3 |
/* Store handler data pointer address */ |
l.sw 0(r6),r5 |
/* Restore r6 */ |
l.lwz r6,0(r1) |
/* Return via link register */ |
l.jr r9 |
/* Restore stack value */ |
l.addi r1,r1,4 |
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function to enable an interrupt handler in the PICMR |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_interrupt_enable |
.type or1k_interrupt_enable,@function |
|
/* r3 should have IRQ line for peripheral */ |
or1k_interrupt_enable: |
l.addi r1,r1,-4 |
l.sw 0(r1),r4 |
l.ori r4,r0,0x1 |
l.sll r4,r4,r3 |
l.mfspr r3,r0,SPR_PICMR |
l.or r3,r3,r4 |
l.mtspr r0,r3,SPR_PICMR |
l.lwz r4,0(r1) |
l.jr r9 |
l.addi r1,r1,4 |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to disable an interrupt handler in the PICMR |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_interrupt_disable |
.type or1k_interrupt_disable,@function |
|
/* r3 should have IRQ line for peripheral */ |
or1k_interrupt_disable: |
l.addi r1,r1,-4 |
l.sw 0(r1),r4 |
l.ori r4,r0,0x1 |
l.sll r4,r4,r3 |
l.xori r4,r4,0xffff |
l.mfspr r3,r0,SPR_PICMR |
l.and r3,r3,r4 |
l.mtspr r0,r3,SPR_PICMR |
l.lwz r4,0(r1) |
l.jr r9 |
l.addi r1,r1,4 |
|
|
/* -------------------------------------------------------------------------- */ |
/*!Generic exception handler function |
*/ |
/* -------------------------------------------------------------------------- */ |
// Warning - this must be the same as specified in crt0.S |
#define EXCEPTION_STACK_SIZE 128+128 |
|
// Value handler addresses are initialised to |
#define EXCEPTION_HANDLER_NOT_SET -1 |
|
|
.data |
.align 4 |
.global or1k_exception_handler_table |
.extern _interrupt_handler |
or1k_exception_handler_table: |
or1k_exception_handler_buserr: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_dpfault: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_ipfault: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_tick: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_align: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_illegal: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_interrupt: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_dtlbmiss: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_itlbmiss: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_range: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_systemcall: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_float: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_trap: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved0: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved1: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved2: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved3: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved4: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved5: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved6: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved7: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved8: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved9: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved10: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved11: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved12: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved13: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved14: .long EXCEPTION_HANDLER_NOT_SET |
or1k_exception_handler_reserved15: .long EXCEPTION_HANDLER_NOT_SET |
|
/* -------------------------------------------------------------------------- */ |
/*!Function to call appropriate exception handler |
*/ |
/* -------------------------------------------------------------------------- */ |
.section .text |
.global or1k_exception_handler |
.type or1k_exception_handler,@function |
|
/* |
r3 = address of exception vector |
r4 = address where exception occurred |
*/ |
|
or1k_exception_handler: |
/* Store remainder of state (r3,r4 stored in vector entry)*/ |
l.sw 0x00(r1), r2 |
l.sw 0x0c(r1), r5 |
l.sw 0x10(r1), r6 |
l.sw 0x14(r1), r7 |
l.sw 0x18(r1), r8 |
l.sw 0x1c(r1), r9 |
l.sw 0x20(r1), r10 |
l.sw 0x24(r1), r11 |
l.sw 0x28(r1), r12 |
l.sw 0x2c(r1), r13 |
l.sw 0x30(r1), r14 |
l.sw 0x34(r1), r15 |
l.sw 0x38(r1), r16 |
l.sw 0x3c(r1), r17 |
l.sw 0x40(r1), r18 |
l.sw 0x44(r1), r19 |
l.sw 0x48(r1), r20 |
l.sw 0x4c(r1), r21 |
l.sw 0x50(r1), r22 |
l.sw 0x54(r1), r23 |
l.sw 0x58(r1), r24 |
l.sw 0x5c(r1), r25 |
l.sw 0x60(r1), r26 |
l.sw 0x64(r1), r27 |
l.sw 0x68(r1), r28 |
l.sw 0x6c(r1), r29 |
l.sw 0x70(r1), r30 |
l.sw 0x74(r1), r31 |
|
/* Determine offset in table of exception handler using r3*/ |
l.andi r13,r3,0xffff |
l.srli r13,r13,6 |
/* Substract 2 words, as we have no vector at 0 and no reset handler */ |
l.addi r13,r13,-8 |
/* r13 now contains offset in or1k_exception_handler_table for |
function |
*/ |
/* Get or1k_exception_handler_table address */ |
l.movhi r14,hi(or1k_exception_handler_table) |
l.ori r14,r14,lo(or1k_exception_handler_table) |
/* r14 now contains base of exception handler table */ |
l.add r14,r14,r13 |
l.lwz r13, 0(r14) |
|
/* Check to see if this handler has been set yet */ |
l.movhi r15,hi(EXCEPTION_HANDLER_NOT_SET) |
l.ori r15,r15,lo(EXCEPTION_HANDLER_NOT_SET) |
l.sfne r13,r15 |
l.bnf exception_exit |
l.nop |
|
/* Call exception handler, copy EPCR to r3 */ |
l.jalr r13 |
l.or r3,r4,r4 |
|
/* Restore state */ |
l.lwz r2, 0x00(r1) |
l.lwz r3, 0x04(r1) |
l.lwz r4, 0x08(r1) |
l.lwz r5, 0x0c(r1) |
l.lwz r6, 0x10(r1) |
l.lwz r7, 0x14(r1) |
l.lwz r8, 0x18(r1) |
l.lwz r9, 0x1c(r1) |
l.lwz r10, 0x20(r1) |
l.lwz r11, 0x24(r1) |
l.lwz r12, 0x28(r1) |
l.lwz r13, 0x2c(r1) |
l.lwz r14, 0x30(r1) |
l.lwz r15, 0x34(r1) |
l.lwz r16, 0x38(r1) |
l.lwz r17, 0x3c(r1) |
l.lwz r18, 0x40(r1) |
l.lwz r19, 0x44(r1) |
l.lwz r20, 0x48(r1) |
l.lwz r21, 0x4c(r1) |
l.lwz r22, 0x50(r1) |
l.lwz r23, 0x54(r1) |
l.lwz r24, 0x58(r1) |
l.lwz r25, 0x5c(r1) |
l.lwz r26, 0x60(r1) |
l.lwz r27, 0x64(r1) |
l.lwz r28, 0x68(r1) |
l.lwz r29, 0x6c(r1) |
l.lwz r30, 0x70(r1) |
l.lwz r31, 0x74(r1) |
|
l.addi r1, r1, EXCEPTION_STACK_SIZE |
|
l.rfe |
l.nop |
|
exception_exit: |
/* Exception handler not set, exit */ |
l.jal exit |
l.or r3,r4,r4 |
|
|
|
/* -------------------------------------------------------------------------- */ |
/*!Function to add handler to table |
*/ |
/* -------------------------------------------------------------------------- */ |
.global or1k_exception_handler_add |
.type or1k_exception_handler_add,@function |
|
.extern or1k_exception_handler_table |
|
/* r3 should have exception number (2 for buserr, 5 for tick, etc.) */ |
/* r4 should have handler function address */ |
or1k_exception_handler_add: |
l.addi r1,r1,-4 |
l.sw 0(r1),r5 |
/* Convert exception number into word address */ |
l.slli r3,r3,2 |
l.addi r3,r3,-8 |
/* Get address of exception handler table */ |
l.movhi r5,hi(or1k_exception_handler_table) |
l.ori r5,r5,lo(or1k_exception_handler_table) |
/* Add handler offset to table base */ |
l.add r5,r5,r3 |
/* Store handler function address */ |
l.sw 0(r5),r4 |
/* Restore r5 */ |
l.lwz r5,0(r1) |
/* Return via link register */ |
l.jr r9 |
/* Restore stack value */ |
l.addi r1,r1,4 |
|
/trunk/gnu-src/newlib-1.18.0/newlib/libc/machine/or32/or1k-support.c
0,0 → 1,197
/* or1k-support - OR1K CPU support functions |
|
Copyright (C) 2011, ORSoC AB |
|
Contributor Julius Baxter <julius.baxter@orsoc.se> |
|
This file is part of Newlib. |
|
This program is free software; you can redistribute it and/or modify it |
under the terms of the GNU General Public License as published by the Free |
Software Foundation; either version 3 of the License, or (at your option) |
any later version. |
|
This program is distributed in the hope that it will be useful, but WITHOUT |
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
more details. |
|
You should have received a copy of the GNU General Public License along |
with this program. If not, see <http://www.gnu.org/licenses/>. */ |
|
#include "or1k-newlib-support.h" |
#include "spr-defs.h" |
|
/* Board-specific CPU clk HZ value */ |
extern unsigned long _board_clk_freq; |
|
/* Tick timer variable */ |
volatile unsigned long or1k_timer_ticks; |
|
/* Tick rate storage */ |
unsigned long or1k_timer_period; |
|
|
/* --------------------------------------------------------------------------*/ |
/*!Report a 32-bit value |
|
Uses the built-in simulator functionality. |
|
@param[in] value Value to report. */ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_report (unsigned long int value) |
{ |
__asm__ __volatile__ ("l.addi\tr3,%0,0\n\t" |
"l.nop %1": : "r" (value), "K" (NOP_REPORT)); |
|
} /* report () */ |
|
/* --------------------------------------------------------------------------*/ |
/*!Write a SPR |
|
@todo Surely the SPR should be a short int, since it is only 16-bits. Left |
as is for now due to large amount of user code that might need |
changing. |
|
@param[in] spr The SPR to write |
@param[in] value The value to write to the SPR */ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_mtspr (unsigned long int spr, |
unsigned long int value) |
{ |
__asm__ __volatile__ ("l.mtspr\t\t%0,%1,0": : "r" (spr), "r" (value)); |
|
} /* mtspr () */ |
|
/* --------------------------------------------------------------------------*/ |
/*!Read a SPR |
|
@todo Surely the SPR should be a short int, since it is only 16-bits. Left |
as is for now due to large amount of user code that might need |
changing. |
|
@param[in] spr The SPR to write |
|
@return The value read from the SPR */ |
/* --------------------------------------------------------------------------*/ |
unsigned long int |
or1k_mfspr (unsigned long spr) |
{ |
unsigned long value; |
|
__asm__ __volatile__ ("l.mfspr\t\t%0,%1,0" : "=r" (value) : "r" (spr)); |
|
return value; |
|
} /* mfspr () */ |
|
/* --------------------------------------------------------------------------*/ |
/*!Pseudo-random number generator |
|
This should return pseudo-random numbers, based on a Galois LFSR |
|
@return The next pseudo-random number */ |
/* --------------------------------------------------------------------------*/ |
unsigned long int |
or1k_rand () |
{ |
static unsigned long int lfsr = 1; |
static int period = 0; |
/* taps: 32 31 29 1; characteristic polynomial: x^32 + x^31 + x^29 + x + 1 */ |
lfsr = (lfsr >> 1) ^ (unsigned long int)((0 - (lfsr & 1u)) & 0xd0000001u); |
++period; |
return lfsr; |
} |
|
|
/* --------------------------------------------------------------------------*/ |
/*!Tick timer interrupt handler |
|
Increment timer ticks counter, reload TTMR |
*/ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_timer_interrupt_handler(void) |
{ |
or1k_timer_ticks++; |
or1k_mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | |
(or1k_timer_period & SPR_TTMR_PERIOD)); |
} |
|
/* --------------------------------------------------------------------------*/ |
/*!Enable tick timer |
|
Install handler, calculate TTMR period, reset tick counter |
|
@param[in] hz Rate at which to trigger timer ticks */ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_timer_init(unsigned int hz) |
{ |
|
/* Set this, for easy access when reloading */ |
or1k_timer_period = _board_clk_freq/hz; |
|
/* Reset timer tick counter */ |
or1k_timer_ticks = 0; |
|
/* Install handler */ |
or1k_exception_handler_add(0x5,or1k_timer_interrupt_handler); |
|
} |
|
/* --------------------------------------------------------------------------*/ |
/*!Enable tick timer |
|
Enable timer interrupt, install handler, load TTMR |
*/ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_timer_enable(void) |
{ |
or1k_mtspr(SPR_TTMR, SPR_TTMR_IE | SPR_TTMR_RT | |
(or1k_timer_period & SPR_TTMR_PERIOD)); |
or1k_mtspr(SPR_SR, SPR_SR_TEE | or1k_mfspr(SPR_SR)); |
|
} |
|
/* --------------------------------------------------------------------------*/ |
/*!Disable tick timer |
|
Disable timer interrupt in SR |
*/ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_timer_disable(void) |
{ |
or1k_mtspr(SPR_SR, ~SPR_SR_TEE & or1k_mfspr(SPR_SR)); |
} |
|
/* --------------------------------------------------------------------------*/ |
/*!Get tick timer |
|
Return value of tick timer |
*/ |
/* --------------------------------------------------------------------------*/ |
unsigned long |
or1k_timer_get_ticks(void) |
{ |
return or1k_timer_ticks; |
} |
|
/* --------------------------------------------------------------------------*/ |
/*!Reset tick timer |
|
Clear value of tick timer |
*/ |
/* --------------------------------------------------------------------------*/ |
void |
or1k_timer_reset_ticks(void) |
{ |
or1k_timer_ticks = 0; |
} |
|
|
|
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/_cache.S
File deleted
\ No newline at end of file
trunk/gnu-src/newlib-1.18.0/libgloss/or32/spr-defs.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: trunk/gnu-src/newlib-1.18.0/libgloss/or32/uart-dummy.c
===================================================================
--- trunk/gnu-src/newlib-1.18.0/libgloss/or32/uart-dummy.c (revision 516)
+++ trunk/gnu-src/newlib-1.18.0/libgloss/or32/uart-dummy.c (nonexistent)
@@ -1,45 +0,0 @@
-/* uart-dummy.c. UART dummy initialization function.
-
- Copyright (C) 2004, Jacob Bower
- Copyright (C) 2010, Embecosm Limited
-
- Contributor Jeremy Bennett
-
- This file is part of Newlib.
-
- The original work by Jacob Bower is provided as-is without any kind of
- warranty. Use it at your own risk!
-
- All subsequent work is bound by version 3 of the GPL as follows.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 3 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along
- with this program. If not, see . */
-/* -------------------------------------------------------------------------- */
-/* This program is commented throughout in a fashion suitable for processing
- with Doxygen. */
-/* -------------------------------------------------------------------------- */
-
-
-/* -------------------------------------------------------------------------- */
-/*!Dummy UART initialization.
-
- To allow the same crt0 to be used with or without a UART, we provide a
- dummy UART initialization, which can be called when the UART is not
- actually present.
-
- It does nothing!
-/* -------------------------------------------------------------------------- */
-void
-__uart_init ()
-{
-} /* __uart_init () */
trunk/gnu-src/newlib-1.18.0/libgloss/or32/uart-dummy.c
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: trunk/gnu-src/newlib-1.18.0/libgloss/or32/_interrupt_handler.S
===================================================================
--- trunk/gnu-src/newlib-1.18.0/libgloss/or32/_interrupt_handler.S (revision 516)
+++ trunk/gnu-src/newlib-1.18.0/libgloss/or32/_interrupt_handler.S (nonexistent)
@@ -1,222 +0,0 @@
-/* _interrupt_handler.S. OR1K interrupt handling function.
-
- Copyright (C) 2010, 2011, ORSoC AB
-
- Constributor Julius Baxter
-
- This file is part of Newlib.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 3 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along
- with this program. If not, see . */
-
-/*
-
- This function is to be called from the exception handler ONLY! It
- relies on the ability to trash all registers due to them having been
- saved on entry to the interrupt exception.
-
- This function should be installed in the exception handler's
- user interrupt exception function slot at reset.
-
-*/
-
-#include "spr-defs.h"
-
-#define INTERRUPT_HANDLER_NOT_SET -1
-
- .data
- .align 4
- .global _interrupt_handler_table
-_interrupt_handler_table:
-_interrupt_handler0: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler1: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler2: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler3: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler4: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler5: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler6: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler7: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler8: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler9: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler10: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler11: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler12: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler13: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler14: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler15: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler16: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler17: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler18: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler19: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler20: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler21: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler22: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler23: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler24: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler25: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler26: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler27: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler28: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler29: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler30: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler31: .long INTERRUPT_HANDLER_NOT_SET
-
- .global _interrupt_handler_data_ptr_table
-_interrupt_handler_data_ptr_table:
-_interrupt_handler_data_ptr0: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr1: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr2: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr3: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr4: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr5: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr6: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr7: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr8: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr9: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr10: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr11: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr12: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr13: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr14: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr15: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr16: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr17: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr18: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr19: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr20: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr21: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr22: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr23: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr24: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr25: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr26: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr27: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr28: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr29: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr30: .long INTERRUPT_HANDLER_NOT_SET
-_interrupt_handler_data_ptr31: .long INTERRUPT_HANDLER_NOT_SET
-
-
-/* -------------------------------------------------------------------------- */
-/*!Function to call appropriate interrupt handler
- */
-/* -------------------------------------------------------------------------- */
-
- .section .text
- .global _interrupt_handler
- .type _interrupt_handler,@function
-
-_interrupt_handler:
- /* Make room on stack, save link register */
- l.addi r1,r1,-12
- l.sw 0(r1),r9
-
- /* Read PICSR */
- l.mfspr r3,r0,SPR_PICSR
-
- /* Load handler table base address */
- l.movhi r7,hi(_interrupt_handler_table)
- l.ori r7,r7,lo(_interrupt_handler_table)
- /* Check to see if this handler has been set yet */
- l.movhi r8,hi(INTERRUPT_HANDLER_NOT_SET)
- l.ori r8,r8,lo(INTERRUPT_HANDLER_NOT_SET)
- /* Load data pointer table base address */
- l.movhi r12,hi(_interrupt_handler_data_ptr_table)
- l.ori r12,r12,lo(_interrupt_handler_data_ptr_table)
-
-.L0:
- /* Find first set bit in PICSR */
- l.ff1 r4,r3
- /* Any bits set? */
- l.sfne r4,r0
- /* If none, finish */
- l.bnf .L2
- l.nop
- /* What is IRQ function table offset? */
- l.addi r5,r4,-1
- l.slli r6,r5,2
- /* Add this to table bases */
- l.add r6,r6,r7
- l.add r13,r6,r12
-
- /* Fetch handler function address */
- l.lwz r6,0(r6)
-
- /* Double check it's valid, compare against INTERRUPT_HANDLER_NOT_SET */
- l.sfne r6,r8
- /* Skip if no handler: TODO: Indicate interrupt fired but no handler*/
- l.bnf .L1
- l.nop
-
- /* Pull out data pointer from table, save r3, we'll write over it */
- l.sw 4(r1),r3
- l.lwz r3,0(r13)
- /* Call handler, save r5 in delay slot */
- l.jalr r5
- l.sw 8(r1),r5
-
- /* Reload r3,r5 */
- l.lwz r3,4(r1)
- l.lwz r5,8(r1)
-.L1:
- /* Clear bit from PICSR, return to start of checking loop */
- l.ori r6,r0,1
- l.sll r6,r6,r5
- l.j .L0
- l.xor r3,r3,r6
-
-.L2:
- /* Finish up - write PICSR back, restore r9*/
- l.lwz r9,0(r1)
- l.mtspr r0,r3,SPR_PICSR
- l.jr r9
- l.addi r1,r1,12
-
-
-
-/* -------------------------------------------------------------------------- */
-/*!Function to add handler to table
- */
-/* -------------------------------------------------------------------------- */
- .global _interrupt_handler_add
- .type _interrupt_handler_add,@function
-
- /* r3 should have IRQ line for peripheral */
- /* r4 should have handler function address */
-_interrupt_handler_add:
- l.addi r1,r1,-4
- l.sw 0(r1),r6
- /* Convert interrupt number into word address */
- l.slli r3,r3,2
- l.addi r3,r3,-4
- /* Get address of interrupt handler table */
- l.movhi r6,hi(_interrupt_handler_table)
- l.ori r6,r6,lo(_interrupt_handler_table)
- /* Add handler offset to table base */
- l.add r6,r6,r3
- /* Store handler function address */
- l.sw 0(r6),r4
- /* Get address of interrupt handler data ptr table */
- l.movhi r6,hi(_interrupt_handler_data_ptr_table)
- l.ori r6,r6,lo(_interrupt_handler_data_ptr_table)
- /* Add handler offset to table base */
- l.add r6,r6,r3
- /* Store handler data pointer address */
- l.sw 0(r6),r5
- /* Restore r6 */
- l.lwz r6,0(r1)
- /* Return via link register */
- l.jr r9
- /* Restore stack value */
- l.addi r1,r1,4
-
\ No newline at end of file
Index: trunk/gnu-src/newlib-1.18.0/libgloss/or32/_exception_handler.S
===================================================================
--- trunk/gnu-src/newlib-1.18.0/libgloss/or32/_exception_handler.S (revision 516)
+++ trunk/gnu-src/newlib-1.18.0/libgloss/or32/_exception_handler.S (nonexistent)
@@ -1,205 +0,0 @@
-/* _exception_handler.S. OR1K exception handling function.
-
- Copyright (C) 2010, 2011, ORSoC AB
-
- Constributor Julius Baxter
-
- This file is part of Newlib.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 3 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along
- with this program. If not, see . */
-
-
-#include "spr-defs.h"
-
-// Warning - this must be the same as specified in crt0.S
-#define EXCEPTION_STACK_SIZE 128
-
-// Value handler addresses are initialised to
-#define EXCEPTION_HANDLER_NOT_SET -1
-
- .data
- .align 4
- .global _exception_handler_table
-_exception_handler_table:
-_exception_handler_buserr: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_dpfault: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_ipfault: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_tick: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_align: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_illegal: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_interrupt: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_dtlbmiss: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_itlbmiss: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_range: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_systemcall: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_float: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_trap: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved0: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved1: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved2: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved3: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved4: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved5: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved6: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved7: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved8: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved9: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved10: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved11: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved12: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved13: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved14: .long EXCEPTION_HANDLER_NOT_SET
-_exception_handler_reserved15: .long EXCEPTION_HANDLER_NOT_SET
-
-/* -------------------------------------------------------------------------- */
-/*!Function to call appropriate exception handler
- */
-/* -------------------------------------------------------------------------- */
-
- .section .text
- .global _exception_handler
- .type _exception_handler,@function
-
- /*
- r3 = address of exception vector
- r4 = address where exception occurred
- */
-
-_exception_handler:
- /* Store remainder of state (r3,r4 stored in vector entry)*/
- l.sw 0x00(r1), r2
- l.sw 0x0c(r1), r5
- l.sw 0x10(r1), r6
- l.sw 0x14(r1), r7
- l.sw 0x18(r1), r8
- l.sw 0x1c(r1), r9
- l.sw 0x20(r1), r10
- l.sw 0x24(r1), r11
- l.sw 0x28(r1), r12
- l.sw 0x2c(r1), r13
- l.sw 0x30(r1), r14
- l.sw 0x34(r1), r15
- l.sw 0x38(r1), r16
- l.sw 0x3c(r1), r17
- l.sw 0x40(r1), r18
- l.sw 0x44(r1), r19
- l.sw 0x48(r1), r20
- l.sw 0x4c(r1), r21
- l.sw 0x50(r1), r22
- l.sw 0x54(r1), r23
- l.sw 0x58(r1), r24
- l.sw 0x5c(r1), r25
- l.sw 0x60(r1), r26
- l.sw 0x64(r1), r27
- l.sw 0x68(r1), r28
- l.sw 0x6c(r1), r29
- l.sw 0x70(r1), r30
- l.sw 0x74(r1), r31
-
- /* Determine offset in table of exception handler using r3*/
- l.andi r13,r3,0xffff
- l.srli r13,r13,6
- /* Substract 2 words, as we have no vector at 0 and no reset handler */
- l.addi r13,r13,-8
- /* r13 now contains offset in _exception_handler_table for function */
- /* Get _exception_handler_table address */
- l.movhi r14,hi(_exception_handler_table)
- l.ori r14,r14,lo(_exception_handler_table)
- /* r14 now contains base of exception handler table */
- l.add r14,r14,r13
- l.lwz r13, 0(r14)
-
- /* Check to see if this handler has been set yet */
- l.movhi r15,hi(EXCEPTION_HANDLER_NOT_SET)
- l.ori r15,r15,lo(EXCEPTION_HANDLER_NOT_SET)
- l.sfne r13,r15
- l.bnf .L1
- l.nop
-
- /* Call exception handler, copy EPCR to r3 */
- l.jalr r13
- l.or r3,r4,r4
-
- /* Restore state */
- l.lwz r2, 0x00(r1)
- l.lwz r3, 0x04(r1)
- l.lwz r4, 0x08(r1)
- l.lwz r5, 0x0c(r1)
- l.lwz r6, 0x10(r1)
- l.lwz r7, 0x14(r1)
- l.lwz r8, 0x18(r1)
- l.lwz r9, 0x1c(r1)
- l.lwz r10, 0x20(r1)
- l.lwz r11, 0x24(r1)
- l.lwz r12, 0x28(r1)
- l.lwz r13, 0x2c(r1)
- l.lwz r14, 0x30(r1)
- l.lwz r15, 0x34(r1)
- l.lwz r16, 0x38(r1)
- l.lwz r17, 0x3c(r1)
- l.lwz r18, 0x40(r1)
- l.lwz r19, 0x44(r1)
- l.lwz r20, 0x48(r1)
- l.lwz r21, 0x4c(r1)
- l.lwz r22, 0x50(r1)
- l.lwz r23, 0x54(r1)
- l.lwz r24, 0x58(r1)
- l.lwz r25, 0x5c(r1)
- l.lwz r26, 0x60(r1)
- l.lwz r27, 0x64(r1)
- l.lwz r28, 0x68(r1)
- l.lwz r29, 0x6c(r1)
- l.lwz r30, 0x70(r1)
- l.lwz r31, 0x74(r1)
-
- l.addi r1, r1, EXCEPTION_STACK_SIZE
-
- l.rfe
- l.nop
-
-.L1:
- /* Exception handler not set, exit */
- l.jal exit
- l.or r3,r4,r4
-
-
-/* -------------------------------------------------------------------------- */
-/*!Function to add handler to table
- */
-/* -------------------------------------------------------------------------- */
- .global _exception_handler_add
- .type _exception_handler_add,@function
-
- /* r3 should have exception number (2 for buserr, 5 for tick, etc.) */
- /* r4 should have handler function address */
-_exception_handler_add:
- l.addi r1,r1,-4
- l.sw 0(r1),r5
- /* Convert exception number into word address */
- l.slli r3,r3,2
- l.addi r3,r3,-8
- /* Get address of exception handler table */
- l.movhi r5,hi(_exception_handler_table)
- l.ori r5,r5,lo(_exception_handler_table)
- /* Add handler offset to table base */
- l.add r5,r5,r3
- /* Store handler function address */
- l.sw 0(r5),r4
- /* Restore r5 */
- l.lwz r5,0(r1)
- /* Return via link register */
- l.jr r9
- /* Restore stack value */
- l.addi r1,r1,4
-
\ No newline at end of file
Index: trunk/gnu-src/newlib-1.18.0/libgloss/or32/or1k-support.h
===================================================================
--- trunk/gnu-src/newlib-1.18.0/libgloss/or32/or1k-support.h (revision 516)
+++ trunk/gnu-src/newlib-1.18.0/libgloss/or32/or1k-support.h (nonexistent)
@@ -1,51 +0,0 @@
-/* OR1K support defines
-
- Copyright (C) 2011, ORSoC AB
- Copyright (C) 2008, 2010 Embecosm Limited
-
- Contributor Julius Baxter
- Contributor Jeremy Bennett
-
- This file is part of Newlib.
-
- This program is free software; you can redistribute it and/or modify it
- under the terms of the GNU General Public License as published by the Free
- Software Foundation; either version 3 of the License, or (at your option)
- any later version.
-
- This program is distributed in the hope that it will be useful, but WITHOUT
- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- more details.
-
- You should have received a copy of the GNU General Public License along
- with this program. If not, see . */
-/* -------------------------------------------------------------------------- */
-/* This program is commented throughout in a fashion suitable for processing
- with Doxygen. */
-/* -------------------------------------------------------------------------- */
-
-/* This machine configuration matches the Or1ksim configuration file in this
- directory. */
-
-#ifndef OR1K_SUPPORT__H
-#define OR1K_SUPPORT__H
-
-/* External symbols from each board's object file */
-extern unsigned long _board_clk_freq;
-
-extern unsigned long _board_uart_base;
-extern unsigned long _board_uart_baud;
-extern unsigned long _board_uart_irq;
-
-/* Check if board has UART - test base address */
-#define BOARD_HAS_UART (_board_uart_base)
-
-/* l.nop constants */
-#define NOP_EXIT 0x0001 /*!< End of simulation */
-#define NOP_PUTC 0x0004 /*!< Put a character */
-
-/*! 8-bit register access macro */
-#define REG8(add) *((volatile unsigned char *) (add))
-
-#endif /* OR1K_SUPPORT__H */
trunk/gnu-src/newlib-1.18.0/libgloss/or32/or1k-support.h
Property changes :
Deleted: svn:eol-style
## -1 +0,0 ##
-native
\ No newline at end of property
Deleted: svn:keywords
## -1 +0,0 ##
-Id
\ No newline at end of property
Index: trunk/gnu-src/newlib-1.18.0/libgloss/or32/Makefile.in
===================================================================
--- trunk/gnu-src/newlib-1.18.0/libgloss/or32/Makefile.in (revision 516)
+++ trunk/gnu-src/newlib-1.18.0/libgloss/or32/Makefile.in (revision 517)
@@ -88,10 +88,7 @@
OUTPUTS = $(CRT0) $(LIBOR32)
# The standard object files for the library
-LIBOR32_OBJS = _exception_handler.o \
- _cache.o \
- _exit.o \
- _interrupt_handler.o \
+LIBOR32_OBJS = _exit.o \
close.o \
environ.o \
execve.o \
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/read.c
32,7 → 32,7
#include <errno.h> |
#include <unistd.h> |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
#undef errno |
extern int errno; |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/crt0.S
59,7 → 59,7
l.sw 4(r1), r3; \ |
l.sw 8(r1), r4; \ |
l.mfspr r3,r0,SPR_NPC; \ |
l.j _exception_handler; \ |
l.j or1k_exception_handler; \ |
l.mfspr r4,r0,SPR_EPCR_BASE |
|
/* -------------------------------------------------------------------------- */ |
263,32 → 263,32
l.or r2,r1,r1 |
|
/* Store stack address in stack variable */ |
l.movhi r26,hi(stack) |
l.ori r26,r26,lo(stack) |
l.sw 0(r26),r1 |
l.movhi r3,hi(stack) |
l.ori r3,r3,lo(stack) |
l.sw 0(r3),r1 |
|
/* Initialise cache */ |
/* TODO - potentially make this optional for simulation targets to save |
time during startup */ |
l.jal _cache_init |
l.jal or1k_cache_init |
l.nop |
|
/* Clear BSS */ |
.L10: l.movhi r28,hi(__bss_start) |
l.ori r28,r28,lo(__bss_start) |
l.movhi r30,hi(end) |
l.ori r30,r30,lo(end) |
.L10: l.movhi r3,hi(__bss_start) |
l.ori r3,r3,lo(__bss_start) |
l.movhi r4,hi(end) |
l.ori r4,r4,lo(end) |
|
.L1: l.sw (0)(r28),r0 |
l.sfltu r28,r30 |
.L1: l.sw (0)(r3),r0 |
l.sfltu r3,r4 |
l.bf .L1 |
l.addi r28,r28,4 /* Delay slot */ |
l.addi r3,r3,4 /* Delay slot */ |
|
/* Call global and static constructors */ |
l.jal __init |
l.nop |
|
/* Set up destructors to be called from exit if main never returns */ |
/* Set up destructors to be called from exit if main ever returns */ |
l.movhi r3,hi(__fini) |
l.jal atexit |
l.ori r3,r3,lo(__fini) /* Delay slot */ |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/lseek.c
32,7 → 32,7
#include <errno.h> |
#include <unistd.h> |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
#undef errno |
extern int errno; |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/_exit.c
29,7 → 29,7
with Doxygen. */ |
/* -------------------------------------------------------------------------- */ |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
|
/* -------------------------------------------------------------------------- */ |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/uart.c
29,7 → 29,7
with Doxygen. */ |
/* -------------------------------------------------------------------------- */ |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
#include "uart.h" |
|
/*! Macro to access a UART register */ |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/isatty.c
32,7 → 32,7
#include <errno.h> |
#include <unistd.h> |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
#undef ERRNO |
extern int errno; |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/fstat.c
33,7 → 33,7
#include <sys/stat.h> |
#include <unistd.h> |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
#undef errno |
extern int errno; |
/trunk/gnu-src/newlib-1.18.0/libgloss/or32/write.c
32,7 → 32,7
#include <errno.h> |
#include <unistd.h> |
|
#include "or1k-support.h" |
#include "or1k-newlib-support.h" |
|
|
#undef errno |