OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

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  • This comparison shows the changes necessary to convert path 
    /openrisc
    from Rev 56 to Rev 57
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  •

Rev 56 → Rev 57

/trunk/orpsocv2/bench/sysc/src/Or1200MonitorSC.cpp
25,7 → 25,7
 
// ----------------------------------------------------------------------------
 
// $Id: Or1200MonitorSC.cpp 303 2009-02-16 11:20:17Z jeremy $
// $Id$
 
#include <iostream>
#include <iomanip>
141,6 → 141,12
}
// checkInstruction monitors the bus for special NOP instructionsl
SC_METHOD (checkInstruction);
sensitive << clk.pos();
dont_initialize();
 
if (profiling_enabled)
{
215,19 → 221,8
memdump_start_addr = memdump_start;
memdump_end_addr = memdump_end;
}
 
 
 
}
// checkInstruction monitors the bus for special NOP instructionsl
SC_METHOD (checkInstruction);
sensitive << clk.pos();
dont_initialize();
} // Or1200MonitorSC ()
 
//! Print command line switches for the options of this module
256,6 → 251,10
//! - l.nop 2 Report the value in R3
//! - l.nop 3 Printf the string with the arguments in R3, etc
//! - l.nop 4 Print a character
 
//#define OR1200_OR32_NOP_BITS_31_TO_26 6'b000101
#define OR1200_OR32_NOP 0x14000000
 
extern int SIM_RUNNING;
void
Or1200MonitorSC::checkInstruction()
264,14 → 263,20
double ts;
cycle_count++;
 
/* Check if this counts as an "executed" instruction */
if (!accessor->getWbFreeze())
if ((((accessor->getWbInsn() & 0xfc000000) != (uint32_t) OR1200_OR32_NOP) || !(accessor->getWbInsn() & (1<<16))) && !(accessor->getExceptFlushpipe() && accessor->getExDslot()))
insn_count++;
else
// Exception version
if (accessor->getExceptFlushpipe())
insn_count++;
// Check the instruction when the freeze signal is low.
//if (!accessor->getWbFreeze())
if ((!accessor->getWbFreeze()) && (accessor->getExceptType() == 0))
{
// Increment instruction counter
insn_count++;
 
// Do something if we have l.nop
switch (accessor->getWbInsn())
{
375,50 → 380,66
 
}
}
} // checkInstruction()
} // callLog()
 
 
//! Method to output the state of the processor
 
//! This function will output to a file, if enabled, the status of the processor
//! For now, it's just the PPC and instruction.
//! This copies what the verilog testbench module, or1200_monitor does in it its
//! process which calls the display_arch_state tasks. This is designed to be
//! identical to that process, so the output is identical
#define PRINT_REGS 1
void
Or1200MonitorSC::displayState()
{
uint32_t wbinsn;
// Calculate how many instructions we've actually calculated by ignoring cycles where we're frozen, delay slots and flushpipe cycles
if ((!accessor->getWbFreeze()) && !(accessor->getExceptFlushpipe() && accessor->getExDslot()))
 
if (logging_enabled == 0)
return; // If we didn't inialise a file, then just return.
 
bool printregs = false;
// Output the state if we're not frozen and not flushing during a delay slot
if ((!accessor->getWbFreeze()) && !(accessor->getExceptFlushpipe() && accessor->getExDslot()))
if (!accessor->getWbFreeze())
{
// Print PC, instruction
statusFile << "\nEXECUTED("<< std::setfill(' ') << std::setw(11) << dec << insn_count << "): " << std::setfill('0') << hex << std::setw(8) << accessor->getWbPC() << ": " << hex << accessor->getWbInsn() << endl;
if ((((accessor->getWbInsn() & 0xfc000000) != (uint32_t) OR1200_OR32_NOP) || !(accessor->getWbInsn() & (1<<16))) && !(accessor->getExceptFlushpipe() && accessor->getExDslot()))
{
// Print PC, instruction
statusFile << "\nEXECUTED("<< std::setfill(' ') << std::setw(11) << dec << insn_count << "): " << std::setfill('0') << hex << std::setw(8) << accessor->getWbPC() << ": " << hex << std::setw(8) << accessor->getWbInsn() << endl;
#if PRINT_REGS
// Print general purpose register contents
for (int i=0; i<32; i++)
{
if ((i%4 == 0)&&(i>0)) statusFile << endl;
statusFile << std::setfill('0');
statusFile << "GPR" << dec << std::setw(2) << i << ": " << hex << std::setw(8) << (uint32_t) accessor->getGpr(i) << " ";
printregs = true;
#endif
}
statusFile << endl;
 
statusFile << "SR : " << hex << std::setw(8) << (uint32_t) accessor->getSprSr() << " ";
statusFile << "EPCR0: " << hex << std::setw(8) << (uint32_t) accessor->getSprEpcr() << " ";
statusFile << "EEAR0: " << hex << std::setw(8) << (uint32_t) accessor->getSprEear() << " ";
statusFile << "ESR0 : " << hex << std::setw(8) << (uint32_t) accessor->getSprEsr() << endl;
else
{
// Exception version
if (accessor->getExceptFlushpipe())
{
// Print PC, instruction, indicate it caused an exception
statusFile << "\nEXECUTED("<< std::setfill(' ') << std::setw(11) << dec << insn_count << "): " << std::setfill('0') << hex << std::setw(8) << accessor->getExPC() << ": " << hex << std::setw(8) << accessor->getExInsn() << " (exception)" << endl;
#if PRINT_REGS
printregs = true;
#endif
 
}
}
if (printregs)
{
// Print general purpose register contents
for (int i=0; i<32; i++)
{
if ((i%4 == 0)&&(i>0)) statusFile << endl;
statusFile << std::setfill('0');
statusFile << "GPR" << dec << std::setw(2) << i << ": " << hex << std::setw(8) << (uint32_t) accessor->getGpr(i) << " ";
}
statusFile << endl;
statusFile << "SR : " << hex << std::setw(8) << (uint32_t) accessor->getSprSr() << " ";
statusFile << "EPCR0: " << hex << std::setw(8) << (uint32_t) accessor->getSprEpcr() << " ";
statusFile << "EEAR0: " << hex << std::setw(8) << (uint32_t) accessor->getSprEear() << " ";
statusFile << "ESR0 : " << hex << std::setw(8) << (uint32_t) accessor->getSprEsr() << endl;
}
}
 
return;
 
} // displayState()
 
//! Function to calculate the number of instructions performed and the time taken
437,7 → 458,7
double ips = (insn_count/elapsed_time);
double mips = (insn_count/elapsed_time)/1000000;
int hertz = (int) ((cycles/elapsed_time)/1000);
std::cout << "* Or1200Monitor: simulated " << sc_time_stamp() << ",time elapsed: " << elapsed_time << " seconds" << endl;
std::cout << "* Or1200Monitor: simulated " << sc_time_stamp() << ", time elapsed: " << elapsed_time << " seconds" << endl;
std::cout << "* Or1200Monitor: simulated " << dec << cycles << " clock cycles, executed at approx " << hertz << "kHz" << endl;
std::cout << "* Or1200Monitor: simulated " << insn_count << " instructions, insn/sec. = " << ips << ", mips = " << mips << endl;
}
/trunk/orpsocv2/bench/verilog/or1200_monitor.v
231,6 → 231,38
end
endtask // display_arch_state
 
//
// Write state of the OR1200 registers into a file; version for exception
//
task display_arch_state_except;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_DISPLAY_ARCH_STATE
ref = ref + 1;
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
get_gpr(i, r);
$fwrite(fexe, "GPR%d: %h ", i, r);
end
$fdisplay(fexe);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
$fwrite(fexe, "SR : %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
$fwrite(fexe, "EPCR0: %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
$fwrite(fexe, "EEAR0: %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
insns = insns + 1;
`endif
end
endtask // display_arch_state_except
/* Keep a trace buffer of the last lot of instructions and addresses
* "executed",as read from the writeback stage, and cause a $finish if we hit
* an instruction that is invalid, such as all zeros.
275,40 → 307,7
end
endtask // monitor_for_crash
 
//
// Write state of the OR1200 registers into a file; version for exception
//
task display_arch_state_except;
reg [5:0] i;
reg [31:0] r;
integer j;
begin
`ifdef OR1200_DISPLAY_ARCH_STATE
ref = ref + 1;
$fdisplay(flookup, "Instruction %d: %t", insns, $time);
$fwrite(fexe, "\nEXECUTED(%d): %h: %h (exception)", insns, `OR1200_TOP.or1200_cpu.or1200_except.ex_pc, `OR1200_TOP.or1200_cpu.or1200_ctrl.ex_insn);
for(i = 0; i < 32; i = i + 1) begin
if (i % 4 == 0)
$fdisplay(fexe);
get_gpr(i, r);
$fwrite(fexe, "GPR%d: %h ", i, r);
end
$fdisplay(fexe);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.sr;
$fwrite(fexe, "SR : %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.epcr;
$fwrite(fexe, "EPCR0: %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.eear;
$fwrite(fexe, "EEAR0: %h ", r);
r = `OR1200_TOP.or1200_cpu.or1200_sprs.esr;
$fdisplay(fexe, "ESR0 : %h", r);
insns = insns + 1;
`endif
end
endtask
 
integer iwb_progress;
reg [31:0] iwb_progress_addr;
//
/trunk/orpsocv2/rtl/verilog/or1200_defines.v
403,7 → 403,7
// Disable bursts if they are not supported by the
// memory subsystem (only affect cache line fill)
//
//`define OR1200_NO_BURSTS
`define OR1200_NO_BURSTS
//
 
//
/trunk/orpsocv2/sim/bin/Makefile
268,6 → 268,14
ARCH_SIM_EXE=or32-elf-sim
ARCH_SIM_CFG_FILE=or1ksim-orpsocv2.cfg
 
# Set V=1 when calling make to enable verbose output
# mainly for debugging purposes.
ifeq ($(V), 1)
Q=
else
Q=@
endif
 
# If USE_SDRAM is defined we'll add it to the simulator's defines on the
# command line becuase it's used by many different modules and it's easier
# to do it this way than make them all include a file.
341,11 → 349,11
$(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v:
@cd $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl && perl fizzim.pl -encoding onehot -terse < wb_sdram_ctrl_fsm.fzm > wb_sdram_ctrl_fsm.v
 
.PHONY: prepare_rtl
prepare_rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
.PHONY: prepare-rtl
prepare-rtl: $(RTL_VERILOG_DIR)/components/wb_sdram_ctrl/wb_sdram_ctrl_fsm.v
 
$(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE): $(SIM_BIN_DIR)/$(SIM_COMMANDFILE)
@sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
$(Q)sed < $(SIM_BIN_DIR)/$(SIM_COMMANDFILE) > $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
362,18 → 370,18
TEST_SW_MAKE_OPTS="UART_PRINTF=1"
endif
 
.PHONY: prepare_sw
prepare_sw:
@$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
@$(MAKE) -C $(SW_DIR)/utils all
.PHONY: prepare-sw
prepare-sw:
$(Q)$(MAKE) -C $(SW_DIR)/support all $(TEST_SW_MAKE_OPTS)
$(Q)$(MAKE) -C $(SW_DIR)/utils all
 
# A rule with UART_PRINTF hard defined ... used by verilator make sw
prepare_sw_uart_printf:
@$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
@$(MAKE) -C $(SW_DIR)/utils all
prepare-sw-uart-printf:
$(Q)$(MAKE) -C $(SW_DIR)/support all UART_PRINTF=1 $(TEST_SW_MAKE_OPTS)
$(Q)$(MAKE) -C $(SW_DIR)/utils all
 
prepare_dirs:
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
prepare-dirs:
$(Q)if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
 
#
# Rough guide to how event driven simulation test loop works:
418,11 → 426,11
# Turn off generation of logging files in the ../results
# directory.
#
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare_sw prepare_rtl prepare_dirs
rtl-tests: $(SIM_RUN_DIR)/$(GENERATED_COMMANDFILE) prepare-sw prepare-rtl prepare-dirs
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
$(Q)for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
469,11 → 477,11
 
 
# Use NCSIM instead of icarus
rtl-nc-tests: prepare_sw prepare_rtl prepare_dirs
rtl-nc-tests: prepare-sw prepare-rtl prepare-dirs
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
$(Q)for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
540,7 → 548,7
ICARUS_VPI_OPTS=-M$(VPI_C_DIR) -m$(VPI_LIB_NAME)
VPI_TEST_SW ?= dhry-nocache-O2
 
prepare_vpi:
prepare-vpi:
## Build the VPI library
$(MAKE) -C $(VPI_C_DIR) $(VPI_LIB_NAME)
 
547,7 → 555,7
clean-vpi:
$(MAKE) -C $(VPI_C_DIR) clean
 
rtl-debug: prepare_sw_uart_printf prepare_rtl prepare_vpi prepare_dirs
rtl-debug: prepare-sw-uart-printf prepare-rtl prepare-vpi prepare-dirs
## Prepare the software for the test
@echo "\t#### Compiling software ####"; echo; \
CURRENT_TEST_SW_DIR=$(SW_DIR)/`echo $(VPI_TEST_SW) | cut -d "-" -f 1`; \
557,28 → 565,28
ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW)$(FLASH_MEM_FILE_SUFFIX) $(SIM_RUN_DIR)/$(SIM_FLASH_MEM_FILE); \
ln -s $$CURRENT_TEST_SW_DIR/$(VPI_TEST_SW).vmem $(SIM_RUN_DIR)/$(SIM_SRAM_MEM_FILE)
## Generate the icarus script we'll compile with
@sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
$(Q)sed < $(SIM_BIN_DIR)/$(ICARUS_COMMAND_FILE) > $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
-e \\!^//.*\$$!d -e \\!^\$$!d
## Add a couple of extra defines to the icarus compile script
@echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
$(Q)echo "+define+TEST_DEFINE_FILE=\"test_define.v\"" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
## The define that enables the VPI debug module
@echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
@if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
$(Q)echo "+define+VPI_DEBUG_ENABLE" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated
$(Q)if [ ! -z $$VCD ];then echo "+define+VCD" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated;fi
## Unless NO_UART_PRINTF=1 we use printf via the UART
@if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
@echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
@echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
@if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
$(Q)if [ -z $$NO_UART_PRINTF ];then echo "+define+UART_PRINTF" >> $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated; fi
$(Q)echo "\`define TEST_NAME_STRING \"$(VPI_TEST_SW)-vpi\"" > $(SIM_RUN_DIR)/test_define.v
$(Q)echo "\`define TEST_RESULTS_DIR \"$(SIM_RESULTS_DIR)/\" " >> $(SIM_RUN_DIR)/test_define.v
$(Q)if [ -z $$NO_SIM_LOGGING ]; then echo "\`define OR1200_DISPLAY_ARCH_STATE" >> $(SIM_RUN_DIR)/test_define.v; fi
@echo
@echo "\t#### Compiling RTL ####"
@rm -f $(SIM_RUN_DIR)/a.out
@$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
$(Q)rm -f $(SIM_RUN_DIR)/a.out
$(Q)$(ICARUS) -sorpsoc_testbench -c $(SIM_RUN_DIR)/$(ICARUS_COMMAND_FILE).generated $(EVENT_SIM_FLAGS)
@echo
@echo "\t#### Beginning simulation with VPI debug module enabled ####"; echo
@$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
$(Q)$(ICARUS_VVP) $(ICARUS_VPI_OPTS) -l $(SIM_RESULTS_DIR)/$(VPI_TEST_SW)-vvp-out.log a.out
 
################################################################################
# Verilator model build rules
628,7 → 636,7
# Included is the SystemPerl trace model
SYSC_MODELS_BUILD=$(SYSC_MODELS) $(VLT_TRACEOBJ)
 
prepare_vlt: prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
prepare-vlt: prepare-rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
@echo;echo "\tCycle-accurate model compiled successfully"
@echo;echo "\tRun the executable with the -h option for usage instructions:";echo
$(SIM_VLT_DIR)/Vorpsoc_top -h
644,10 → 652,10
@echo; echo "\tCompiling top level SystemC testbench"; echo
cd $(SIM_VLT_DIR) && g++ $(VLT_DEBUG_COMPILE_FLAGS) $(VLT_CPPFLAGS) $(TRACE_FLAGS) -I$(BENCH_SYSC_INCLUDE_DIR) -I$(SIM_VLT_DIR) -I$(VERILATOR_ROOT)/include -I$(SYSTEMC)/include -c $(BENCH_SYSC_SRC_DIR)/OrpsocMain.cpp
 
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt_modules_compile $(SIM_VLT_DIR)/verilated.o
$(SIM_VLT_DIR)/libVorpsoc_top.a: $(SIM_VLT_DIR)/Vorpsoc_top__ALL.a vlt-modules-compile $(SIM_VLT_DIR)/verilated.o
# Now archive all of the libraries from verilator witht he other modules we might have
@echo; echo "\tArchiving libraries into libVorpsoc_top.a"; echo
@cd $(SIM_VLT_DIR) && \
$(Q)cd $(SIM_VLT_DIR) && \
cp Vorpsoc_top__ALL.a libVorpsoc_top.a && \
ar rcs libVorpsoc_top.a verilated.o; \
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
656,17 → 664,17
 
$(SIM_VLT_DIR)/verilated.o:
@echo; echo "\tCompiling verilated.o"; echo
@cd $(SIM_VLT_DIR) && \
$(Q)cd $(SIM_VLT_DIR) && \
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
$(MAKE) -f Vorpsoc_top.mk verilated.o
 
.PHONY: vlt_modules_compile
vlt_modules_compile:
.PHONY: vlt-modules-compile
vlt-modules-compile:
# Compile the module files
@echo; echo "\tCompiling SystemC models"
@cd $(SIM_VLT_DIR) && \
$(Q)cd $(SIM_VLT_DIR) && \
for SYSCMODEL in $(SYSC_MODELS_BUILD); do \
echo;echo "\t$$SYSCMODEL"; echo; \
export CXXFLAGS=$(VLT_DEBUG_COMPILE_FLAGS); \
677,7 → 685,7
 
$(SIM_VLT_DIR)/Vorpsoc_top__ALL.a: $(SIM_VLT_DIR)/Vorpsoc_top.mk
@echo; echo "\tCompiling main design"; echo
@cd $(SIM_VLT_DIR) && \
$(Q)cd $(SIM_VLT_DIR) && \
export USER_CPPFLAGS="$(VLT_CPPFLAGS)"; \
export USER_LDDFLAGS="$(VLT_CPPFLAGS)"; \
$(MAKE) -f Vorpsoc_top.mk Vorpsoc_top__ALL.a
691,7 → 699,7
# SystemC modules library
$(SIM_VLT_DIR)/libmodules.a:
@echo; echo "\tCompiling SystemC modules"; echo
@export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
$(Q)export VLT_CPPFLAGS="$(VLT_CPPFLAGS)"; \
$(MAKE) -C $(BENCH_SYSC_SRC_DIR) -f $(BENCH_SYSC_SRC_DIR)/Modules.make $(VLT_SYSC_DEBUG_DEFINE)
 
 
701,7 → 709,7
# Generate the compile script to give Verilator - make it sensitive to the RTL
$(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated: $(ALL_VLOG)
@echo; echo "\tGenerating verilator compile script"; echo
@sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
$(Q)sed < $(SIM_BIN_DIR)/$(VLT_COMMAND_FILE) > $(SIM_VLT_DIR)/$(VLT_COMMAND_FILE).generated \
-e s!\$$BENCH_DIR!$(BENCH_VERILOG_DIR)! \
-e s!\$$RTL_DIR!$(RTL_VERILOG_DIR)! \
-e s!\$$BACKEND_DIR!$(BACKEND_DIR)! \
712,7 → 720,7
# Link all the required system C model files into the verilator work dir
@echo; echo "\tLinking SystemC model source to verilator build path"; echo
@if [ ! -d $(SIM_VLT_DIR) ]; then mkdir $(SIM_VLT_DIR); fi
@cd $(SIM_VLT_DIR) && \
$(Q)cd $(SIM_VLT_DIR) && \
for SYSCMODEL in $(SYSC_MODELS); do \
if [ ! -e $$SYSCMODEL.cpp ]; then \
ln -s $(BENCH_SYSC_SRC_DIR)/$$SYSCMODEL.cpp .; \
726,11 → 734,11
################################################################################
 
# Verilator defaults to internal memories
vlt-tests: prepare_sw_uart_printf prepare_rtl prepare_dirs prepare_vlt
vlt-tests: prepare-sw-uart-printf prepare-rtl prepare-dirs prepare-vlt
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
$(Q)for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \
756,18 → 764,18
###############################################################################
# Verilator profiled module make
###############################################################################
# To run this, first run a "make prepare_vlt VLT_DO_PROFILING=1" then do a
# "make clean" and then a "make prepare_vlt_profiled"
# To run this, first run a "make prepare-vlt VLT_DO_PROFILING=1" then do a
# "make clean" and then a "make prepare-vlt_profiled"
# This new make target copies athe results of the profiling back to the right
# paths before we create everything again
###############################################################################
prepare_vlt_profiled: vlt_restore_profileoutput prepare_rtl vlt_model_links $(SIM_VLT_DIR)/Vorpsoc_top
prepare-vlt-profiled: vlt_restore-profileoutput prepare-rtl vlt-model-links $(SIM_VLT_DIR)/Vorpsoc_top
 
vlt_restore_profileoutput:
vlt-restore-profileoutput:
@echo;echo "\tRestoring profiling outputs"; echo
@mkdir -p ../vlt
@cp /tmp/*.gc* $(SIM_VLT_DIR)
@cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
$(Q)mkdir -p ../vlt
$(Q)cp /tmp/*.gc* $(SIM_VLT_DIR)
$(Q)cp /tmp/*.gc* $(BENCH_SYSC_SRC_DIR)
 
################################################################################
# Architectural simulator test loop
774,12 → 782,12
################################################################################
 
# Verilator defaults to internal memories
sim-tests: prepare_sw_uart_printf
sim-tests: prepare-sw-uart-printf
@if [ ! -d $(SIM_RESULTS_DIR) ]; then mkdir -p $(SIM_RESULTS_DIR); fi
@echo
@echo "Beginning loop that will complete the following tests: $(TESTS)"
@echo
@for TEST in $(TESTS); do \
$(Q)for TEST in $(TESTS); do \
echo "################################################################################"; \
echo; \
echo "\t#### Current test: $$TEST ####"; echo; \

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