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URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /openrisc
    from Rev 621 to Rev 622
    ↔ Reverse comparison
  •

Rev 621 → Rev 622

/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/main.c
157,7 → 157,7
 
static void prvSetupHardware(void) {
// UART controller use 25 Mhz Wishbone bus clock, define in board.h
uart_init();
uart_init(0);
 
// Initialize internal Programmable Interrupt Controller
int_init();
/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.h
118,9 → 118,20
#define UART_EFR_SCD 0x20 /* Special character detect */
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */
 
void uart_init(void);
void uart_putc(char);
char uart_getc(void);
void uart_init(int core);
void uart_putc(int core, char c);
void uart_putc_noblock(int core, char c);
char uart_getc(int core);
int uart_check_for_char(int core);
char uart_getc_noblock(int core);
void uart_rxint_enable(int core);
void uart_rxint_disable(int core);
void uart_txint_enable(int core);
void uart_txint_disable(int core);
char uart_get_iir(int core);
char uart_get_lsr(int core);
char uart_get_msr(int core);
 
void uart_print_str(char *p);
void uart_print_int(int n);
 
/trunk/rtos/freertos-6.1.1/Demo/OpenRISC_SIM_GCC/drivers/uart.c
1,87 → 1,155
#include "support.h"
#include "board.h"
 
#include "uart.h"
#include "support.h"
 
#ifdef UART_NUM_CORES
const int UART_BASE_ADR[UART_NUM_CORES] = {UART0_BASE, UART1_BASE};
const int UART_BAUDS[UART_NUM_CORES] = {UART0_BAUD_RATE, UART1_BAUS_RATE};
#else
const int UART_BASE_ADR[1] = {UART0_BASE};
const int UART_BAUDS[1] = {UART0_BAUD_RATE};
#endif
 
#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 
#define WAIT_FOR_XMITR \
#define WAIT_FOR_XMITR(core) \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
 
#define WAIT_FOR_THRE \
#define WAIT_FOR_THRE(core) \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
} while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
 
#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
#define CHECK_FOR_CHAR(core) (REG8(UART_BASE_ADR[core] + UART_LSR) & UART_LSR_DR)
 
#define WAIT_FOR_CHAR \
#define WAIT_FOR_CHAR(core) \
do { \
lsr = REG8(UART_BASE + UART_LSR); \
lsr = REG8(UART_BASE_ADR[core] + UART_LSR); \
} while ((lsr & UART_LSR_DR) != UART_LSR_DR)
 
#define UART_TX_BUFF_LEN 32
#define UART_TX_BUFF_MASK (UART_TX_BUFF_LEN -1)
 
void uart_init(void) {
void uart_init(int core)
{
int divisor;
float float_divisor;
 
/* Diable interrupt */
REG8(UART_BASE + UART_IER) = 0x0;
 
/* Reset receiver and transmiter */
/* Set RX interrupt for each byte */
REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_1;
REG8(UART_BASE_ADR[core] + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
 
/* Disable all interrupts */
REG8(UART_BASE_ADR[core] + UART_IER) = 0x00;
 
/* Set 8 bit char, 1 stop bit, no parity */
REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
REG8(UART_BASE_ADR[core] + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
 
/* Set baud rate */
divisor = IN_CLK / (16 * UART_BAUD_RATE);
REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
float_divisor = (float) IN_CLK/(16 * UART_BAUDS[core]);
float_divisor += 0.50f; // Ensure round up
divisor = (int) float_divisor;
 
REG8(UART_BASE_ADR[core] + UART_LCR) |= UART_LCR_DLAB;
REG8(UART_BASE_ADR[core] + UART_DLL) = divisor & 0x000000ff;
REG8(UART_BASE_ADR[core] + UART_DLM) = (divisor >> 8) & 0x000000ff;
REG8(UART_BASE_ADR[core] + UART_LCR) &= ~(UART_LCR_DLAB);
 
return;
}
 
void uart_putc(char c) {
void uart_putc(int core, char c)
{
unsigned char lsr;
 
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = c;
WAIT_FOR_THRE(core);
REG8(UART_BASE_ADR[core] + UART_TX) = c;
if(c == '\n') {
WAIT_FOR_THRE;
REG8(UART_BASE + UART_TX) = '\r';
WAIT_FOR_THRE(core);
REG8(UART_BASE_ADR[core] + UART_TX) = '\r';
}
WAIT_FOR_XMITR;
WAIT_FOR_XMITR(core);
}
 
// Only used when we know THRE is empty, typically in interrupt
void uart_putc_noblock(int core, char c)
{
REG8(UART_BASE_ADR[core] + UART_TX) = c;
}
 
char uart_getc(void) {
char uart_getc(int core)
{
unsigned char lsr;
char c;
 
WAIT_FOR_CHAR;
c = REG8(UART_BASE + UART_RX);
WAIT_FOR_CHAR(core);
c = REG8(UART_BASE_ADR[core] + UART_RX);
return c;
}
 
void uart_print_str(char *p) {
char uart_getc_noblock(int core)
{
char c;
c = REG8(UART_BASE_ADR[core] + UART_RX);
return c;
}
 
int uart_check_for_char(int core)
{
return CHECK_FOR_CHAR(core);
}
 
void uart_rxint_enable(int core)
{
REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_RDI;
}
 
void uart_rxint_disable(int core)
{
REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_RDI);
}
 
void uart_txint_enable(int core)
{
REG8(UART_BASE_ADR[core] + UART_IER) |= UART_IER_THRI;
}
 
void uart_txint_disable(int core)
{
REG8(UART_BASE_ADR[core] + UART_IER) &= ~(UART_IER_THRI);
}
 
char uart_get_iir(int core)
{
return REG8(UART_BASE_ADR[core] + UART_IIR);
}
 
 
char uart_get_lsr(int core)
{
return REG8(UART_BASE_ADR[core] + UART_LSR);
}
 
 
char uart_get_msr(int core)
{
return REG8(UART_BASE_ADR[core] + UART_MSR);
}
 
 
void uart_print_str(char *p)
{
while(*p != 0) {
uart_putc(*p);
uart_putc(0, *p);
p++;
}
}
 
void uart_print_int(int n) {
void uart_print_int(int n)
{
int a;
char c;
if (n<0) {
uart_putc('-');
uart_putc(0, '-');
n = -n;
}
 
89,7 → 157,5
if(a) uart_print_int(a);
 
c = '0' + (n % 10);
uart_putc(c);
uart_putc(0, c);
}
 
 

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