OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /openrisc
    from Rev 82 to Rev 83
    Reverse comparison

Rev 82 → Rev 83

/trunk/or1ksim/cache/icache-model.c
226,7 → 226,7
/*---------------------------------------------------------------------------*/
/*!Enable or disable the instruction cache
 
Set the corresponding field in the UPR
Set the corresponding fields in the UPR
 
@param[in] val The value to use
@param[in] dat The config data structure */
483,9 → 483,11
exit (1);
}
 
/* Clear the cache data. John Alfredo's fix for using 0 (which is a
valid tag), so we now use -1 */
memset (ic->mem, 0, size);
memset (ic->lrus, 0, ic->nsets * ic->nways * sizeof (unsigned int));
memset (ic->tags, 0, ic->nsets * ic->nways * sizeof (oraddr_t));
memset (ic->tags, -1, ic->nsets * ic->nways * sizeof (oraddr_t));
}
else
{

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