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/cyc_or12_mini_top.qpf
0,0 → 1,23
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
 
QUARTUS_VERSION = "6.1"
DATE = "06:48:46 June 20, 2007"
 
 
# Revisions
 
PROJECT_REVISION = "cyc_or12_mini_top"
/cyc_or12_mini_top.cof
0,0 → 1,18
<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>
<cof>
<eprom_name>NONE</eprom_name>
<output_filename>cyc_or12_mini_top.rbf</output_filename>
<n_pages>1</n_pages>
<width>1</width>
<mode>0</mode>
<sof_data>
<user_name>Page_0</user_name>
<page_flags>1</page_flags>
<bit0>
<sof_filename>cyc_or12_mini_top.sof</sof_filename>
</bit0>
</sof_data>
<version>4</version>
<options>
</options>
</cof>
/cyc_or12_mini_top.qsf
0,0 → 1,387
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
 
 
# The default values for assignments are stored in the file
# cyc_or12_mini_top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
# assignment_defaults.qdf
 
# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
 
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C20Q240C8
set_global_assignment -name TOP_LEVEL_ENTITY cyc_or12_mini_top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "06:48:46 JUNE 20, 2007"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
 
#48MHz local oscillator
set_global_assignment -name FMAX_REQUIREMENT "20.83 ns" -section_id clk
set_global_assignment -name DUTY_CYCLE 50 -section_id clk
set_instance_assignment -name CLOCK_SETTINGS clk -to clk
 
set_global_assignment -name RESERVE_PIN "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
 
 
set_location_assignment PIN_30 -to clk
set_location_assignment PIN_57 -to uart_srx
set_location_assignment PIN_56 -to uart_stx
# set_location_assignment PIN_56 -to uart_stx_temp
set_location_assignment PIN_46 -to watchDogStrobe
 
set_location_assignment PIN_52 -to jtag_tms
set_location_assignment PIN_55 -to jtag_tdi
set_location_assignment PIN_51 -to jtag_tdo
set_location_assignment PIN_50 -to jtag_tck
set_location_assignment PIN_54 -to jtag_trst
 
#NET "jtag_tms" LOC = "D7" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
#NET "jtag_tdi" LOC = "C7" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
#NET "jtag_tdo" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
#NET "jtag_tck" LOC = "E8" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
#NET "jtag_trst" LOC = "H13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
 
 
set_location_assignment PIN_97 -to mc_addr[0]
set_location_assignment PIN_96 -to mc_addr[1]
set_location_assignment PIN_90 -to mc_addr[2]
set_location_assignment PIN_166 -to mc_addr[3]
set_location_assignment PIN_165 -to mc_addr[4]
set_location_assignment PIN_164 -to mc_addr[5]
set_location_assignment PIN_162 -to mc_addr[6]
set_location_assignment PIN_161 -to mc_addr[7]
set_location_assignment PIN_159 -to mc_addr[8]
set_location_assignment PIN_157 -to mc_addr[9]
set_location_assignment PIN_100 -to mc_addr[10]
set_location_assignment PIN_109 -to mc_addr[11]
 
set_location_assignment PIN_106 -to mc_ba[0]
set_location_assignment PIN_105 -to mc_ba[1]
 
set_location_assignment PIN_113 -to mc_cas_
set_location_assignment PIN_156 -to mc_cke_
set_location_assignment PIN_155 -to sdram_clk
set_location_assignment PIN_110 -to sdram_cs
set_location_assignment PIN_116 -to mc_dqm[0]
set_location_assignment PIN_150 -to mc_dqm[1]
set_location_assignment PIN_88 -to mc_dqm[2]
set_location_assignment PIN_167 -to mc_dqm[3]
set_location_assignment PIN_132 -to mc_dq[0]
set_location_assignment PIN_131 -to mc_dq[1]
set_location_assignment PIN_130 -to mc_dq[2]
set_location_assignment PIN_128 -to mc_dq[3]
set_location_assignment PIN_126 -to mc_dq[4]
set_location_assignment PIN_125 -to mc_dq[5]
set_location_assignment PIN_119 -to mc_dq[6]
set_location_assignment PIN_118 -to mc_dq[7]
set_location_assignment PIN_149 -to mc_dq[8]
set_location_assignment PIN_141 -to mc_dq[9]
set_location_assignment PIN_140 -to mc_dq[10]
set_location_assignment PIN_139 -to mc_dq[11]
set_location_assignment PIN_137 -to mc_dq[12]
set_location_assignment PIN_136 -to mc_dq[13]
set_location_assignment PIN_135 -to mc_dq[14]
set_location_assignment PIN_134 -to mc_dq[15]
set_location_assignment PIN_87 -to mc_dq[16]
set_location_assignment PIN_86 -to mc_dq[17]
set_location_assignment PIN_84 -to mc_dq[18]
set_location_assignment PIN_80 -to mc_dq[19]
set_location_assignment PIN_79 -to mc_dq[20]
set_location_assignment PIN_78 -to mc_dq[21]
set_location_assignment PIN_73 -to mc_dq[22]
set_location_assignment PIN_72 -to mc_dq[23]
set_location_assignment PIN_178 -to mc_dq[24]
set_location_assignment PIN_177 -to mc_dq[25]
set_location_assignment PIN_175 -to mc_dq[26]
set_location_assignment PIN_174 -to mc_dq[27]
set_location_assignment PIN_173 -to mc_dq[28]
set_location_assignment PIN_171 -to mc_dq[29]
set_location_assignment PIN_170 -to mc_dq[30]
set_location_assignment PIN_168 -to mc_dq[31]
 
 
set_location_assignment PIN_111 -to mc_ras_
set_location_assignment PIN_114 -to mc_we_
 
set_location_assignment PIN_47 -to spiClk
set_location_assignment PIN_49 -to spiMasterDataIn
set_location_assignment PIN_20 -to spiMasterDataOut
set_location_assignment PIN_44 -to spiCS_n
 
 
# Santa Cruz Connector
set_location_assignment PIN_16 -to SC_P_CLK
set_location_assignment PIN_15 -to SC_PCS_N
set_location_assignment PIN_188 -to SC_RST_N
set_location_assignment PIN_191 -to SC_P0
set_location_assignment PIN_189 -to SC_P1
set_location_assignment PIN_194 -to SC_P2
set_location_assignment PIN_192 -to SC_P3
set_location_assignment PIN_199 -to SC_P4
set_location_assignment PIN_197 -to SC_P5
set_location_assignment PIN_208 -to SC_P6
set_location_assignment PIN_203 -to SC_P7
set_location_assignment PIN_218 -to SC_P8
set_location_assignment PIN_216 -to SC_P9
set_location_assignment PIN_226 -to SC_P10
set_location_assignment PIN_223 -to SC_P11
set_location_assignment PIN_231 -to SC_P12
set_location_assignment PIN_230 -to SC_P13
set_location_assignment PIN_234 -to SC_P14
set_location_assignment PIN_233 -to SC_P15
set_location_assignment PIN_236 -to SC_P16
set_location_assignment PIN_237 -to SC_P17
set_location_assignment PIN_238 -to SC_P18
set_location_assignment PIN_5 -to SC_P19
set_location_assignment PIN_4 -to SC_P20
set_location_assignment PIN_6 -to SC_P21
set_location_assignment PIN_7 -to SC_P22
set_location_assignment PIN_8 -to SC_P23
set_location_assignment PIN_9 -to SC_P24
set_location_assignment PIN_11 -to SC_P25
set_location_assignment PIN_13 -to SC_P26
set_location_assignment PIN_14 -to SC_P27
set_location_assignment PIN_18 -to SC_P28
set_location_assignment PIN_184 -to SC_P29
set_location_assignment PIN_185 -to SC_P30
set_location_assignment PIN_186 -to SC_P31
set_location_assignment PIN_187 -to SC_P32
set_location_assignment PIN_195 -to SC_P33
set_location_assignment PIN_200 -to SC_P34
set_location_assignment PIN_214 -to SC_P35
set_location_assignment PIN_222 -to SC_P36
set_location_assignment PIN_228 -to SC_P37
set_location_assignment PIN_232 -to SC_P38
set_location_assignment PIN_235 -to SC_P39
 
 
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
 
 
 
 
 
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_global_assignment -name USER_LIBRARIES "..\\rtl\\or1200;..\\rtl\\usbhostslave\\include"
 
 
 
set_global_assignment -name NUMBER_OF_PATHS_TO_REPORT 1000
 
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER ON
set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
 
 
set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 
 
# ----------------- top level ---------------------
# Set the top level module to correspond to your Santa Cruz daughter card
set_global_assignment -name VERILOG_FILE ../rtl/top/cyc_or12_mini_top.v
# set_global_assignment -name VERILOG_FILE ../rtl/top/cyc_or12_mini_top_sdCard.v
 
 
 
# ----------------- Block RAM initialization ---------------------
# Set the onchip RAM module to load your desired firmware program
# If you are actively developing an application then it is quicker to
# stick with onchip_ram_loadDRAM.v, which initializes block RAM with a boot
# loader, that then loads your application from flash memory. This way you can
# simply copy your firmware image file from the PC to flash memory. Otherwise
# you need to recompile the hardware project, every time you recompile the firmware.
set_global_assignment -name VERILOG_FILE ../rtl/mem_if/onchip_ram_loadDRAM.v
# set_global_assignment -name VERILOG_FILE ../rtl/mem_if/onchip_ram_memTest.v
 
 
 
set_global_assignment -name VERILOG_FILE ../rtl/mem_if/onchip_ram.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbSlaveCyc2Wrap_usb1t11.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbHostCyc2Wrap_usb1t11.v
set_global_assignment -name SDC_FILE cyc_or12_mini_top.sdc
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbSlaveCyc2Wrap.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbHost.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbHostCyc2Wrap.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/wrapper/usbSlave.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/USBSlaveControlBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/endpMux.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/fifoMux.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/sctxportarbiter.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/slavecontroller.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/slaveDirectcontrol.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/slaveGetpacket.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/slaveRxStatusMonitor.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/slaveSendpacket.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/slaveController/usbSlaveControl.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/writeUSBWireData.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/lineControlUpdate.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/processRxBit.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/processRxByte.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/processTxByte.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/readUSBWireData.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/siereceiver.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/SIETransmitter.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/updateCRC5.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/updateCRC16.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/usbSerialInterfaceEngine.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/serialInterfaceEngine/usbTxWireArbiter.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/busInterface/wishBoneBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostSlaveMux/hostSlaveMuxBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostSlaveMux/hostSlaveMux.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/USBHostControlBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/directcontrol.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/getpacket.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/hctxportarbiter.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/hostcontroller.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/rxStatusMonitor.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/sendpacket.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/sendpacketarbiter.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/sendpacketcheckpreamble.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/sofcontroller.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/softransmit.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/speedCtrlMux.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/hostController/usbHostControl.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/TxFifoBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/dpMem_dc.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/fifoRTL.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/RxFifo.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/RxFifoBI.v
set_global_assignment -name VERILOG_FILE ../rtl/usbhostslave/buffers/TxFifo.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/spiMasterWishBoneBI.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_dpMem_dc.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_fifoRTL.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_RxFifo.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_RxFifoBI.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_TxFifo.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sm_TxFifoBI.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/spiMaster_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/top/pll_30MHz_15MHz.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/ctrlStsRegBI.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/initSD.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/readWriteSDBlock.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/readWriteSPIWireData.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/sendCmd.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/spiCtrl.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/spiMaster.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/spiTxRxData.v
set_global_assignment -name VERILOG_FILE ../rtl/spiMaster/timescale.v
set_global_assignment -name VERILOG_FILE ../rtl/top/ddrClkOut.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_wb_if.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_adr_sel.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_cs_rf.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_dp.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_incn_r.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_mem_if.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_obct.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_obct_top.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_rd_fifo.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_refresh.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_rf.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_timing.v
set_global_assignment -name VERILOG_FILE ../rtl/mem_ctrl/mc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/raminfr.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_debug_if.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_receiver.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_regs.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_rfifo.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_sync_flops.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_tfifo.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_top.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_transmitter.v
set_global_assignment -name VERILOG_FILE ../rtl/uart16550/uart_wb.v
set_global_assignment -name VERILOG_FILE ../rtl/top/tc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/top/cyc_or12_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_xcv_ram32x8d.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_alu.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_amultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_cfgr.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_cpu.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_ctrl.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dc_fsm.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dc_ram.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dc_tag.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dc_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dmmu_tlb.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dmmu_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dpram_32x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_dpram_256x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_du.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_except.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_freeze.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_genpc.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_gmultp2_32x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_ic_fsm.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_ic_ram.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_ic_tag.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_ic_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_if.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_immu_tlb.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_immu_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_iwb_biu.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_lsu.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_mem2reg.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_mult_mac.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_operandmuxes.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_pic.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_pm.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_qmem_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_reg2mem.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_rf.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_rfram_generic.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_sb.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_sb_fifo.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_32x24.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_64x14.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_64x22.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_64x24.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_128x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_256x21.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_512x20.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_1024x8.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_1024x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_1024x32_bw.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_2048x8.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_2048x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_spram_2048x32_bw.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_sprs.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_top.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_tpram_32x32.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_tt.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_wb_biu.v
set_global_assignment -name VERILOG_FILE ../rtl/or1200/or1200_wbmux.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/timescale.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_crc8_d1.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_defines.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_register.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_registers.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_sync_clk1_clk2.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_top.v
set_global_assignment -name VERILOG_FILE ../rtl/dbg_interface/dbg_trace.v
/cyc_or12_mini_top.sdc
0,0 → 1,116
## Generated SDC file "cyc_or12_mini_top.sdc"
 
## Copyright (C) 1991-2007 Altera Corporation
## Your use of Altera Corporation's design tools, logic functions
## and other software and tools, and its AMPP partner logic
## functions, and any output files from any of the foregoing
## (including device programming or simulation files), and any
## associated documentation or information are expressly subject
## to the terms and conditions of the Altera Program License
## Subscription Agreement, Altera MegaCore Function License
## Agreement, or other applicable license agreement, including,
## without limitation, that your use is for the sole purpose of
## programming logic devices manufactured by Altera and sold by
## Altera or its authorized distributors. Please refer to the
## applicable agreement for further details.
 
 
## VENDOR "Altera"
## PROGRAM "Quartus II"
## VERSION "Version 7.2 Build 203 02/05/2008 Service Pack 2 SJ Web Edition"
 
## DATE "Fri May 16 09:55:20 2008"
 
##
## DEVICE "EP2C20Q240C8"
##
 
 
#**************************************************************
# Time Information
#**************************************************************
 
set_time_format -unit ns -decimal_places 3
 
 
 
#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {clk} -period 20.830 -waveform { 0.000 10.415 } [get_ports {clk}] -add
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
derive_pll_clocks -use_tan_name
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
 
 
#**************************************************************
# Set False Path
#**************************************************************
 
set_false_path -from [get_clocks {clk}] -to [get_clocks {pll_30MHz_15MHz:pll_30MHz_15MHz_inst|altpll:altpll_component|_clk0}]
set_false_path -from [get_clocks {pll_30MHz_15MHz:pll_30MHz_15MHz_inst|altpll:altpll_component|_clk0}] -to [get_clocks {clk}]
 
 
#**************************************************************
# Set Multicycle Path
#**************************************************************
 
 
 
#**************************************************************
# Set Maximum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Minimum Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Input Transition
#**************************************************************
 
 
 
#**************************************************************
# Set Load
#**************************************************************
 
/download.bat
0,0 → 1,3
fpgaConfig -i cyc_or12_mini_top.rbf -r -a 0 -w -l
pause
 

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