URL
https://opencores.org/ocsvn/openverifla/openverifla/trunk
Subversion Repositories openverifla
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- This comparison shows the changes necessary to convert path
/openverifla/trunk
- from Rev 30 to Rev 31
- ↔ Reverse comparison
Rev 30 → Rev 31
/openverifla_2.2.d/verilog/verifla/monitor_of_verifla.v
61,7 → 61,7
reg [MON_STATES_BITS-1:0] mon_state, next_mon_state; |
reg [LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1:0] |
next_mon_samples_after_trigger, mon_samples_after_trigger; |
reg [LA_MEM_ADDRESS_BITS-1:0] next_mon_write_address, mon_write_address, old_mon_write_address; |
reg [LA_MEM_ADDRESS_BITS-1:0] next_mon_write_address, mon_write_address; |
reg [LA_MEM_ADDRESS_BITS-1:0] next_bt_queue_tail_address, bt_queue_tail_address; |
reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] mon_old_data_in, |
mon_current_data_in; //={LA_DATA_INPUT_WORDLEN_BITS{1'b0}}; |
92,7 → 92,6
begin |
mon_state <= MON_STATE_IDLE; |
sc_run <= 0; |
old_mon_write_address <= LA_MEM_FIRST_ADDR; |
mon_write_address <= LA_MEM_FIRST_ADDR; |
bt_queue_tail_address <= 0; |
mon_samples_after_trigger <= 0; |
101,7 → 100,6
else begin |
mon_state <= next_mon_state; |
sc_run <= next_sc_run; |
old_mon_write_address <= mon_write_address; |
mon_write_address <= next_mon_write_address; |
bt_queue_tail_address <= next_bt_queue_tail_address; |
mon_samples_after_trigger <= next_mon_samples_after_trigger; |
142,7 → 140,7
or mon_current_data_in or mon_old_data_in or mon_clones_nr |
or data_in_changed or oneplus_mon_clones_nr or one_plus_mon_write_address |
or not_maximum_mon_clones_nr |
or last_mem_addr_before_trigger or old_mon_write_address) |
or last_mem_addr_before_trigger) |
*/ |
begin |
// implicit |
223,7 → 221,7
mem_port_A_wen=1; |
next_mon_write_address=LA_TRIGGER_MATCH_MEM_ADDR; |
next_mon_clones_nr=2; |
next_bt_queue_tail_address = old_mon_write_address; |
next_bt_queue_tail_address = mon_write_address; |
next_mon_samples_after_trigger=1; |
end |
end |
/openverifla_2.2.d/vhdl/verifla/monitor_of_verifla.vhd
67,7 → 67,7
signal mon_state, next_mon_state: std_logic_vector(3 downto 0); |
signal next_mon_samples_after_trigger, mon_samples_after_trigger: |
std_logic_vector(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1 downto 0); |
signal next_mon_write_address, mon_write_address, old_mon_write_address: |
signal next_mon_write_address, mon_write_address: |
std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0); |
signal next_bt_queue_tail_address, bt_queue_tail_address: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0); |
signal mon_old_data_in, mon_current_data_in: std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0); |
101,7 → 101,6
if (rst_l='0') then |
mon_state <= MON_STATE_IDLE; |
sc_run_aux <= '0'; |
old_mon_write_address <= std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS)); |
mon_write_address <= std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS)); |
bt_queue_tail_address <= (others => '0'); |
mon_samples_after_trigger <= (others => '0'); |
109,7 → 108,6
elsif (rising_edge(clk)) then |
mon_state <= next_mon_state; |
sc_run_aux <= next_sc_run_aux; |
old_mon_write_address <= mon_write_address; |
mon_write_address <= next_mon_write_address; |
bt_queue_tail_address <= next_bt_queue_tail_address; |
mon_samples_after_trigger <= next_mon_samples_after_trigger; |
134,7 → 132,7
mon_write_address, bt_queue_tail_address, mon_samples_after_trigger, |
mon_current_data_in, mon_old_data_in, mon_clones_nr, |
data_in_changed, oneplus_mon_clones_nr, one_plus_mon_write_address, |
not_maximum_mon_clones_nr, last_mem_addr_before_trigger, old_mon_write_address) |
not_maximum_mon_clones_nr, last_mem_addr_before_trigger) |
begin |
-- implicit |
next_mon_state <= mon_state; |
261,7 → 259,7
mem_port_A_wen <= '1'; |
next_mon_write_address <= LA_TRIGGER_MATCH_MEM_ADDR_SLV; |
next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS)); |
next_bt_queue_tail_address <= old_mon_write_address; |
next_bt_queue_tail_address <= mon_write_address; |
next_mon_samples_after_trigger <= std_logic_vector(to_unsigned(1, LA_MAX_SAMPLES_AFTER_TRIGGER_BITS)); |
end if; |
when MON_STATE_AFTER_TRIGGER_INT => |