URL
https://opencores.org/ocsvn/openverifla/openverifla/trunk
Subversion Repositories openverifla
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- This comparison shows the changes necessary to convert path
/openverifla
- from Rev 37 to Rev 38
- ↔ Reverse comparison
Rev 37 → Rev 38
/trunk/openverifla_2.3/java/UARTSendReceive.class
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trunk/openverifla_2.3/java/UARTSendReceive.class
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Added: svn:executable
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+*
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Index: trunk/openverifla_2.3/java/UARTSendReceive.java
===================================================================
--- trunk/openverifla_2.3/java/UARTSendReceive.java (nonexistent)
+++ trunk/openverifla_2.3/java/UARTSendReceive.java (revision 38)
@@ -0,0 +1,156 @@
+/*
+UARTSendReceive.java
+License: GNU GPL
+
+Revision history:
+revistion date: 2018/07/20; author: Laurentiu Duca
+- port of SerialPort jssc instead of rxtx
+revision date: 2007/Sep/03; author: Laurentiu Duca
+- captureOnly feature
+- consider that the bt_queue_head_address is wrote at the end of the data capture.
+- use HOUR_OF_DAY (0..23)
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.io.File;
+import java.io.FileInputStream;
+import java.io.FileOutputStream;
+import java.io.FileNotFoundException;
+import java.io.FileReader;
+import java.io.BufferedReader;
+import java.util.Properties;
+import java.util.Enumeration;
+import java.util.Calendar;
+import java.util.GregorianCalendar;
+import java.util.StringTokenizer;
+
+import jssc.SerialPort;
+import jssc.SerialPortException;
+
+public class UARTSendReceive extends Object {
+
+ // Data members are declared at the end.
+
+ /**
+ * Creates a new object.
+ *
+ */
+ public UARTSendReceive() {
+ this.serialPort = null;
+ //this.properties = new Properties();
+ }
+
+ /**
+ * Attaches the given serial serialPort to the device object.
+ * The method will try to open the serialPort.
+ */
+ public boolean attach(String portName, String strBaudRate, String parity) {
+ serialPort = new SerialPort(portName);
+
+ byte pb[]=parity.getBytes();
+ int b=pb[0]=='1'?SerialPort.PARITY_ODD:SerialPort.PARITY_NONE;
+ System.out.println("parity="+b);
+ try {
+ serialPort.openPort();//Open serial port
+ int baudrate=Integer.parseInt(strBaudRate);
+ //strBaudRate.equals("115200")?SerialPort.BAUDRATE_115200:
+ //strBaudRate.equals("38400")?SerialPort.BAUDRATE_38400:SerialPort.BAUDRATE_9600;
+ serialPort.setParams(baudrate,
+ SerialPort.DATABITS_8,
+ SerialPort.STOPBITS_1,
+ b); //SerialPort.PARITY_NONE);
+ //Set params. Also you can set params by this string: serialPort.setParams(9600, 8, 1, 0);
+ //serialPort.writeBytes("This is a test string".getBytes());//Write data to port
+ } catch (SerialPortException ex) {
+ ex.printStackTrace(System.out);
+ return false;
+ }
+
+ return true;
+ }
+
+ /**
+ * Detaches the currently attached serialPort, if one exists.
+ * This will close the serial port.
+ *
+ */
+ public void detach() {
+ if (serialPort != null) {
+ try {
+ serialPort.closePort();
+ } catch (SerialPortException ex) {
+ ex.printStackTrace(System.out);
+ }
+ }
+ }
+
+ public void sendReceive(String msg) throws IOException, SerialPortException {
+ byte rawByte[]=new byte[1];
+ rawByte = msg.getBytes();
+
+ System.out.println("Sending...");
+ serialPort.writeBytes(rawByte);
+ System.out.println("Done sending.");
+
+ // Read Captured data
+ System.out.println("Reading");
+ byte readByte[] = serialPort.readBytes(1);
+ System.out.printf("Read: '%c'=0x%x\n", (char) readByte[0], (int) readByte[0]);
+ }
+
+ public void getCapturedData(String portName, String strBaudRate, String parity, String msg)
+ {
+ boolean found;
+ found = attach(portName, strBaudRate, parity);
+ if(!found) {
+ System.out.println("Port " + portName + " not found.\n");
+ System.exit(0);
+ }
+ try {
+ sendReceive(msg);
+ } catch (Exception ex) {
+ ex.printStackTrace(System.out);
+ }
+ detach();
+ }
+
+
+ public static void fatalError(String errorName)
+ {
+ System.out.println("Fatal error: " + errorName);
+ System.exit(-1);
+ }
+
+
+ public static void main(String[] args) throws Exception
+ {
+ if(args.length != 4)
+ UARTSendReceive.fatalError("Number of arguments is not 4; is "+args.length+"\n"+
+ "Sintax is:\njava UARTSendReceive \n"+
+ "Examples:\n"+
+ "java UARTSendReceive COM5 9600 0 a\n"+
+ "java UARTSendReceive /dev/ttyUSB0 115200 0 a\n");
+ // 1st arg.
+ System.out.println("port = " + args[0]);
+ System.out.println("baudrate = " + args[1]);
+ //if(!args[1].equals("115200") && !args[1].equals("38400") && !args[1].equals("9600"))
+ // fatalError("Invalid baudrate");
+ System.out.println("parity = " + args[2]);
+ System.out.println("char = " + args[3]);
+ UARTSendReceive usr;
+ usr = new UARTSendReceive();
+ usr.getCapturedData(args[0], args[1], args[2], args[3]);
+ }
+
+ SerialPort serialPort;
+ byte [][] memoryDataWords;
+ int octetsPerWord, idOfTypeBitInLastOctet, totalmemoryDataBytes;
+ // Properties file members
+ String portName;
+}
trunk/openverifla_2.3/java/UARTSendReceive.java
Property changes :
Added: svn:executable
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+*
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Index: trunk/openverifla_2.3/java/VeriFLA.class
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Index: trunk/openverifla_2.3/java/VeriFLA.class
===================================================================
--- trunk/openverifla_2.3/java/VeriFLA.class (nonexistent)
+++ trunk/openverifla_2.3/java/VeriFLA.class (revision 38)
trunk/openverifla_2.3/java/VeriFLA.class
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
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Index: trunk/openverifla_2.3/java/VeriFLA.java
===================================================================
--- trunk/openverifla_2.3/java/VeriFLA.java (nonexistent)
+++ trunk/openverifla_2.3/java/VeriFLA.java (revision 38)
@@ -0,0 +1,693 @@
+/*
+VeriFLA.java
+License: GNU GPL
+
+Revision history:
+revistion date: 2018/07/20; author: Laurentiu Duca
+- port of SerialPort jssc instead of rxtx
+- redesign of memory contents implied modification in the java source
+revision date: 2007/Sep/03; author: Laurentiu Duca
+- sendRunCommand feature
+- consider that the bt_queue_head_address is wrote at the end of the data capture.
+- use HOUR_OF_DAY (0..23)
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+import java.io.IOException;
+import java.io.InputStream;
+import java.io.OutputStream;
+import java.io.File;
+import java.io.FileInputStream;
+import java.io.FileOutputStream;
+import java.io.FileNotFoundException;
+import java.io.FileReader;
+import java.io.BufferedReader;
+import java.util.Properties;
+import java.util.Enumeration;
+import java.util.Calendar;
+import java.util.GregorianCalendar;
+import java.util.StringTokenizer;
+
+import jssc.SerialPort;
+import jssc.SerialPortException;
+
+public class VeriFLA extends Object {
+
+ // Data members are declared at the end.
+
+ /**
+ * Creates a new object.
+ *
+ */
+ public VeriFLA() {
+ this.serialPort = null;
+ this.properties = new Properties();
+ }
+
+ /**
+ * Attaches the given serial serialPort to the device object.
+ * The method will try to open the serialPort.
+ */
+ public boolean attach(String portName) {
+ serialPort = new SerialPort(portName);
+ try {
+ int baudrate=Integer.parseInt(strBaudRate);
+ //strBaudRate.equals("115200")?SerialPort.BAUDRATE_115200:
+ //strBaudRate.equals("38400")?SerialPort.BAUDRATE_38400:SerialPort.BAUDRATE_9600;
+ serialPort.openPort();//Open serial port
+ serialPort.setParams(baudrate,
+ SerialPort.DATABITS_8,
+ SerialPort.STOPBITS_1,
+ SerialPort.PARITY_NONE);
+ //Set params. Also you can set params by this string: serialPort.setParams(9600, 8, 1, 0);
+ //serialPort.writeBytes("This is a test string".getBytes());//Write data to port
+ } catch (SerialPortException ex) {
+ ex.printStackTrace(System.out);
+ return false;
+ }
+
+ return true;
+ }
+
+ /**
+ * Detaches the currently attached serialPort, if one exists.
+ * This will close the serial port.
+ *
+ */
+ public void detach() {
+ if (serialPort != null) {
+ try {
+ serialPort.closePort();
+ } catch (SerialPortException ex) {
+ ex.printStackTrace(System.out);
+ }
+ }
+ }
+
+ public void run() throws IOException, SerialPortException {
+ byte rawByte[]=new byte[1];
+
+ if(sendRunCommand == 1) {
+ // Send USERCMD_RESET command
+ //rawByte[0]=USERCMD_RESET;
+ //System.out.println("Sending USERCMD_RESET command");
+ //serialPort.writeBytes(rawByte);
+ //System.out.println("Done sending USERCMD_RESET command.");
+
+ // Send USERCMD_RUN command
+ rawByte[0]=USERCMD_RUN;
+ System.out.println("Sending user_run command..");
+ serialPort.writeBytes(rawByte);
+ System.out.println("Done sending user_run command.");
+ }
+
+ // Read Captured data
+ System.out.println("Waiting for data capture:");
+ int i,j,ret;
+ rawByte = new byte[memWords * octetsPerWord];
+ rawByte = serialPort.readBytes(memWords * octetsPerWord);
+ for(i=0; i=0; j--)
+ System.out.printf("%02x ", memoryLineBytes[i][j]);
+ System.out.println();
+ }
+
+ //System.exit(1);
+ }
+
+ public void getCapturedData(String portName)
+ {
+ boolean found;
+ found = attach(portName);
+ if(!found) {
+ System.out.println("Port " + portName + " not found.\n"+
+ "\tPlease update the properties file.\n");
+ System.exit(0);
+ }
+ try {
+ run();
+ } catch (Exception ex) {
+ ex.printStackTrace(System.out);
+ }
+ detach();
+ }
+
+ public void saveCapturedData() throws IOException
+ {
+ // Create a new file with the name "capture_timestamp.v".
+ String strTime=getTime();
+ String outputFileName, moduleName;
+ moduleName="capture_"+strTime;
+ outputFileName = moduleName+".v";
+ File outputFile = new File(outputFileName);
+ if (!outputFile.createNewFile()) {
+ System.out.println("Error: Can not create file: " + outputFileName);
+ System.exit(-1);
+ }
+ OutputStream stream = new FileOutputStream(outputFile);
+
+
+ // Write the timescale directive.
+ String strLine;
+ int i,j,k;
+ strLine = "`timescale " + strTimescaleUnit + " / " + strTimescalePrecision + "\n\n";
+ stream.write(strLine.getBytes());
+
+
+ // Write the module name and output params.
+ strLine = "module " + moduleName + "(clk_of_verifla, la_trigger_matched, ";
+ for (i = 0; i < signalGroups; i++) {
+ strLine += groupName[i];
+ if(i != (signalGroups - 1))
+ strLine += ", ";
+ }
+ strLine += ", memory_line_id";
+ strLine += ");\n\n";
+ stream.write(strLine.getBytes());
+
+
+ // Write the declaration of signals
+ strLine = "output clk_of_verifla;\n" + "output la_trigger_matched;\n" + "output ["+(memWords/4)+":0] memory_line_id;\n";
+ stream.write(strLine.getBytes());
+ for (k = 0; k < 2; k++) {
+ for (i = 0; i < signalGroups; i++) {
+ if(k == 0)
+ strLine = "output ";
+ else
+ strLine = "reg ";
+ if(groupSize[i] > 1) {
+ if(groupEndian[i] != 0)
+ strLine += "[0:"+(groupSize[i]-1)+"] ";
+ else
+ strLine += "["+(groupSize[i]-1)+":0] ";
+ }
+ strLine += groupName[i] + ";\n";
+ stream.write(strLine.getBytes());
+ }
+ }
+ strLine =
+ "reg ["+(memWords/4)+":0] memory_line_id;\n" +
+ "reg la_trigger_matched;\n" +
+ "reg clk_of_verifla;" + "\n\n" +
+ "parameter PERIOD = " + clockPeriod + ";" + "\n";
+ stream.write(strLine.getBytes());
+
+
+ // Write the clock task.
+ strLine =
+ "initial // Clock process for clk_of_verifla" + "\n" +
+ "begin" + "\n" +
+ " forever" + "\n" +
+ " begin" + "\n" +
+ " clk_of_verifla = 1'b0;" + "\n" +
+ " #("+ (int)(clockPeriod / 2) + "); clk_of_verifla = 1'b1;" + "\n" +
+ " #("+ (int)(clockPeriod / 2) + ");" + "\n" +
+ " end" + "\n" +
+ "end" + "\n\n" ;
+ stream.write(strLine.getBytes());
+
+
+ // Write captured data
+ strLine = "initial begin\n";
+ strLine += "#("+ (int)(clockPeriod / 2) + ");\n";
+ strLine += "la_trigger_matched = 0;\n";
+ stream.write(strLine.getBytes());
+
+ // Compute the name of the signals
+ String signalsToken;
+ signalsToken = "{";
+ for (i = signalGroups-1; i >= 0 ; i--) {
+ signalsToken += groupName[i];
+ if (i > 0)
+ signalsToken += ",";
+ }
+ signalsToken += "} = ";
+
+ // Write name of the signals, values and delays in the verilog file.
+ String strWord;
+ int currentTime=(clockPeriod / 2), delay;
+
+ // compute the oldest wrote-info before trigger event
+ int bt_queue_head_address=0, bt_queue_tail_address=0;
+ // the word at address (memWords-1) represents bt_queue_tail_address.
+ for(j = 0; j < (octetsPerWord-1); j++) {
+ bt_queue_tail_address += ((0x000000FF) & (int) memoryLineBytes[memWords-1][j]) << (8*j);
+ }
+ System.out.println("bt_queue_tail_address=" + bt_queue_tail_address);
+ // Find the first
+ // before the trigger event (not an memory word).
+ if(bt_queue_tail_address == (triggerMatchMemAddr - 1))
+ bt_queue_head_address = 0;
+ else
+ bt_queue_head_address = bt_queue_tail_address + 1;
+ boolean before_trigger=true;
+ boolean foundAnEffectiveCaptureWord=false, wentBack=false;
+ i = bt_queue_head_address;
+ do
+ {
+ for(j = 0; j < (octetsPerWord-1); j++) {
+ if(memoryLineBytes[i][j] != 0)
+ foundAnEffectiveCaptureWord = true;
+ }
+ if(foundAnEffectiveCaptureWord)
+ break;
+ i++;
+ if(i >= triggerMatchMemAddr)
+ if(!foundAnEffectiveCaptureWord && !wentBack) {
+ i = 0;
+ wentBack = true;
+ }
+ } while (i <= triggerMatchMemAddr);
+ if(!foundAnEffectiveCaptureWord)
+ fatalError("Could not find the first efffective capture before trigger match");
+ if(i >= triggerMatchMemAddr)
+ before_trigger=false;
+
+ // Walk through the captured data and write it to capture.v
+ do {
+ // Check if this is an empty line
+ boolean allMemoryLineIsZero=true;
+ for(j=octetsPerWord-1; j>=0; j--) {
+ if(memoryLineBytes[i][j] != 0) {
+ allMemoryLineIsZero = false;
+ break;
+ }
+ }
+ if(allMemoryLineIsZero) {
+ if(debugVeriFLA) {
+ strLine = "// info: line "+i+" is empty.\n";
+ System.out.println(strLine);
+ stream.write(strLine.getBytes());
+ }
+ } else {
+ // Write memory line index.
+ strLine = "memory_line_id=" + i + ";\n";
+ stream.write(strLine.getBytes());
+ // Data capture
+ strWord = totalSignals + "'b";
+ for(j=octetsPerWord-1; j>=0; j--) {
+ if((j * 8) < dataWordLenBits)
+ for(k=7; k>=0; k--) {
+ if((j*8+k) < totalSignals) {
+ strWord += (memoryLineBytes[i][j] >> k) & 1;
+ }
+ }
+ }
+ strWord += ';';
+ strLine = signalsToken + strWord + "\n";
+ if(i == triggerMatchMemAddr)
+ strLine += "la_trigger_matched = 1;\n";
+ //strLine += "#" + clockPeriod + ";\n";
+ // Write to file
+ //System.out.println(strLine);
+ stream.write(strLine.getBytes());
+
+
+ // Time interval in which data is constant.
+ delay=0;
+ for(j = 0; j < octetsPerWord; j++) {
+ if((j * 8) >= dataWordLenBits)
+ delay += ((0x000000FF) & (int) memoryLineBytes[i][j]) << (8*j - dataWordLenBits);
+ }
+ currentTime += delay * clockPeriod;
+ strLine = "#" + (delay * clockPeriod) + ";\n";
+ // Write to file
+ //System.out.println(strLine);
+ stream.write(strLine.getBytes());
+ // Also write the time stamp
+ strLine = "// ------------- Current Time: " + currentTime + "*(" + strTimescaleUnit + ") "+"\n";
+ stream.write(strLine.getBytes());
+ }
+
+ // Compute the new value of i
+ if(before_trigger) {
+ i = (i+1) % triggerMatchMemAddr;
+ if(i == bt_queue_head_address) {
+ before_trigger = false;
+ i = triggerMatchMemAddr;
+ }
+ }
+ else
+ i = i + 1;
+ } while (i < (memWords-1));
+
+ strLine = "$stop;\nend\nendmodule\n";
+ stream.write(strLine.getBytes());
+
+ // Write raw memory information.
+ strLine = "/*\n"+STR_ORIGINAL_CAPTURE_DUMP+"\n";
+ for(i=0; i=0; j--) {
+ //strLine += "["+j+"]"+" " + Integer.toHexString(memoryLineBytes[i][j]) + " ";
+ if((0x000000FF & (int) memoryLineBytes[i][j]) <= 0x0F)
+ strLine += "0";
+ strLine += Integer.toHexString(
+ 0x000000FF & (int) memoryLineBytes[i][j]).toUpperCase() + " ";
+ }
+ strLine += "\n";
+ }
+/*
+ for(i=0; i=0; j--) {
+ if((0x000000FF & (int) memoryLineBytes[i][j]) <= 0x0F)
+ strLine += "0";
+ strLine += Integer.toHexString(
+ 0x000000FF & (int) memoryLineBytes[i][j]).toUpperCase() + " ";
+ }
+ strLine += "\n";
+ stream.write(strLine.getBytes());
+ }
+*/
+ strLine += "*/\n";
+ stream.write(strLine.getBytes());
+
+ stream.close();
+ System.out.println("Job done. Please simulate " + outputFileName);
+ }
+
+ private void allocateMemory()
+ {
+ // Allocate memory
+ int i,j;
+ memoryLineBytes = new byte[memWords][];
+ for(i=0; i=0; j--) {
+ memoryLineBytes[i][j] = (byte) Integer.parseInt(st.nextToken(), 16);
+ }
+ i++;
+ if(i >= memWords)
+ allMemoryRead = true;
+ //}
+ //else
+ //if (line.startsWith(STR_ORIGINAL_CAPTURE_DUMP)) {
+ // startOfMemory=true;
+ // i = 0;
+ //}
+ } while (!allMemoryRead);
+ } catch (Exception e) {
+ e.printStackTrace();
+ fatalError("rebuildCapturedDataFromFile exception");
+ }
+ }
+
+ public void job(String propertiesFileName, String strRebuildFileName)
+ {
+ getProperties(propertiesFileName);
+ allocateMemory();
+ if(strRebuildFileName == null)
+ getCapturedData(portName);
+ else
+ rebuildCapturedDataFromFile(strRebuildFileName);
+ try {
+ saveCapturedData();
+ } catch (IOException e) {
+ e.printStackTrace();
+ fatalError("Error saving Captured Data");
+ }
+ }
+
+ public static void fatalError(String errorName)
+ {
+ System.out.println("Fatal error: " + errorName);
+ System.exit(-1);
+ }
+
+ public void getProperties(String fileName)
+ {
+ File f;
+ f = new File(fileName);
+ if (!f.isFile()) {
+ System.out.println("Error: File does not exist: " + fileName);
+ System.exit(-1);
+ }
+
+ InputStream stream;
+ try {
+ stream = new FileInputStream(f);
+ try {
+ properties.load(stream);
+ } catch (IOException e) {
+ fatalError("IOException " + fileName);
+ }
+ } catch (FileNotFoundException e) {
+ fatalError("FileNotFoundException "+ fileName);
+ }
+
+ String strVal;
+ portName = properties.getProperty(NAME + ".portName");
+ if(portName == null)
+ fatalError("Properties: missing portName");
+ strBaudRate = properties.getProperty(NAME + ".baudRate");
+ if(strBaudRate == null)
+ fatalError("Properties: missing baudRate");
+ //if(!strBaudRate.equals("115200") && !strBaudRate.equals("38400") && !strBaudRate.equals("9600"))
+ //fatalError("Invalid baudRate (must be 115200 or 38400 or 9600)");
+
+ // time units
+ strTimescaleUnit=properties.getProperty(NAME + ".timescaleUnit");
+ strTimescalePrecision=properties.getProperty(NAME + ".timescalePrecision");
+ if(strTimescaleUnit == null || strTimescalePrecision == null)
+ fatalError("Properties: Not found timescale - unit or precision");
+ // clockPeriod
+ strVal=properties.getProperty(NAME + ".clockPeriod");
+ if(strVal != null)
+ clockPeriod=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: clockPeriod not found");
+
+ // User signals
+ strVal=properties.getProperty(NAME + ".totalSignals");
+ if(strVal != null)
+ totalSignals=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: endian not found");
+ // Groups of signals
+ strVal=properties.getProperty(NAME + ".signalGroups");
+ if(strVal != null)
+ signalGroups=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: signalGroups not found");
+ groupName=new String[signalGroups];
+ groupSize=new int[signalGroups];
+ groupEndian=new int[signalGroups];
+ int i;
+ int sumOfSignals=0;
+ for (i=0; i < signalGroups; i++)
+ {
+ String strGroupName, strGroupSize, strGroupEndian;
+ strGroupName=properties.getProperty(NAME + ".groupName."+i);
+ strGroupSize=properties.getProperty(NAME + ".groupSize."+i);
+ strGroupEndian=properties.getProperty(NAME + ".groupEndian."+i);
+ if(strGroupName == null || strGroupSize == null || strGroupEndian == null)
+ fatalError("Properties: group " + i + " not found groupName or groupSize or groupEndian");
+ else {
+ groupName[i]=strGroupName;
+ groupSize[i]=Integer.parseInt(strGroupSize);
+ sumOfSignals += groupSize[i];
+ groupEndian[i]=Integer.parseInt(strGroupEndian);
+ }
+ }
+ if(sumOfSignals != totalSignals)
+ fatalError("Properties: totalSignals != sum of all group sizes: " + totalSignals + " != "+sumOfSignals);
+
+
+ // Memory
+ strVal=properties.getProperty(NAME + ".memWords");
+ if(strVal != null)
+ memWords=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: memWords not found");
+ strVal=properties.getProperty(NAME + ".dataWordLenBits");
+ if(strVal != null)
+ dataWordLenBits=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: dataWordLenBits not found");
+ if((dataWordLenBits % 8) != 0)
+ fatalError("Properties: dataWordLenBits is not multiple of 8");
+ strVal=properties.getProperty(NAME + ".clonesWordLenBits");
+ if(strVal != null)
+ clonesWordLenBits=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: clonesWordLenBits not found");
+ if((clonesWordLenBits % 8) != 0)
+ fatalError("Properties: clonesWordLenBits is not multiple of 8");
+ memWordLenBits = dataWordLenBits + clonesWordLenBits;
+ // Compute sizes
+ // octetsPerWord
+ octetsPerWord = memWordLenBits / 8;
+ if (memWordLenBits % 8 > 0)
+ octetsPerWord++;
+ totalmemoryDataBytes = memWords*octetsPerWord;
+ // Trigger
+ strVal=properties.getProperty(NAME + ".triggerMatchMemAddr");
+ if(strVal != null)
+ triggerMatchMemAddr=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: triggerMatchMemAddr not found");
+/*
+ strVal=properties.getProperty(NAME + ".maxSamplesAfterTrigger");
+ if(strVal != null)
+ maxSamplesAfterTrigger=Integer.parseInt(strVal);
+ else
+ fatalError("Properties: maxSamplesAfterTrigger not found");
+
+ // triggerLastValue
+ strVal=properties.getProperty(NAME + ".triggerLastValue");
+ if(strVal != null) {
+ StringTokenizer st;
+ int j, tNo;
+ st = new StringTokenizer(strVal," ");
+ tNo= st.countTokens();
+ if(tNo != octetsPerWord)
+ fatalError("triggerLastValue " + " tNo != octetsPerWord: " + tNo + " != " + octetsPerWord);
+ triggerLastValue = new int[octetsPerWord];
+ for(j=octetsPerWord-1; j>=0; j--) {
+ triggerLastValue[j] = (byte) Integer.parseInt(st.nextToken(), 16);
+ }
+ }
+ else
+ fatalError("Properties: triggerLastValue not found");
+*/
+ }
+
+ public String getTime()
+ {
+ Calendar calendar=new GregorianCalendar();
+ String strTime;
+ int field;
+ strTime = "" + calendar.get(Calendar.YEAR);
+ field = 1 + calendar.get(Calendar.MONTH);
+ if(field < 10)
+ strTime += "0";
+ strTime += field;
+ if(calendar.get(Calendar.DAY_OF_MONTH) < 10)
+ strTime += "0";
+ strTime += calendar.get(Calendar.DAY_OF_MONTH) + "_" ;
+ if(calendar.get(Calendar.HOUR_OF_DAY) < 10)
+ strTime += "0";
+ strTime += calendar.get(Calendar.HOUR_OF_DAY);
+ if(calendar.get(Calendar.MINUTE) < 10)
+ strTime += "0";
+ strTime += calendar.get(Calendar.MINUTE) + "_";
+ if(calendar.get(Calendar.SECOND) < 10)
+ strTime += "0";
+ strTime += calendar.get(Calendar.SECOND) ;
+ System.out.println("date and time: "+strTime);
+ return strTime;
+ }
+
+ public static void main(String[] args) throws Exception
+ {
+ if(args.length < 1)
+ VeriFLA.fatalError("Too few arguments: "+args.length+
+ "\nSintax is:\n\tjava VeriFLA [=0/1 (default 0)] [sourceToRebuild_capture]\n"+
+ "Examples:\n1. Wait for FPGA to send capture:\n\tjava VeriFLA verifla_properties_keyboard.txt\n"+
+ "2. Send to the monitor the run command and wait for FPGA to send capture:\n\tjava VeriFLA verifla_properties_keyboard.txt 1\n"
+ );
+ // 1st arg.
+ System.out.println("propertiesFileName = " + args[0]);
+ // 2nd arg.
+ sendRunCommand = 0;
+ if(args.length >= 2) {
+ System.out.println(" sendRunCommand = " + args[1]);
+ sendRunCommand = Integer.parseInt(args[1]);
+ }
+ // 3rd arg.
+ String sourceToRebuildCaptureFile=null;
+ if(args.length >= 3) {
+ System.out.println(" sourceToRebuild_capture = " + args[2]);
+ sourceToRebuildCaptureFile = args[2];
+ }
+ VeriFLA verifla;
+ verifla = new VeriFLA();
+ verifla.job(args[0], sourceToRebuildCaptureFile);
+ }
+
+ // This java app. data members
+ boolean debugVeriFLA=true;
+
+ String propertiesFileName;
+ Properties properties;
+ SerialPort serialPort;
+ String strBaudRate;
+ final static String NAME = "LA";
+ final static String STR_ORIGINAL_CAPTURE_DUMP = "ORIGINAL CAPTURE DUMP";
+ final static int USERCMD_RESET=0x00, USERCMD_RUN = 0x01;
+ byte [][] memoryLineBytes;
+ int octetsPerWord, totalmemoryDataBytes;
+ int totalSignals;
+ public static int sendRunCommand=0;
+ int clockPeriod;
+
+ // Properties file members
+ String portName;
+ int memWords, memWordLenBits, dataWordLenBits, clonesWordLenBits,
+ triggerMatchMemAddr, maxSamplesAfterTrigger;
+ //int [] triggerLastValue;
+ String strTimescaleUnit, strTimescalePrecision;
+ int signalGroups;
+ String [] groupName;
+ int [] groupSize, groupEndian;
+}
trunk/openverifla_2.3/java/VeriFLA.java
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/java/capture_20181016_1230_58.v
===================================================================
--- trunk/openverifla_2.3/java/capture_20181016_1230_58.v (nonexistent)
+++ trunk/openverifla_2.3/java/capture_20181016_1230_58.v (revision 38)
@@ -0,0 +1,356 @@
+`timescale 1ns / 10ps
+
+module capture_20181016_1230_58(clk_of_verifla, la_trigger_matched, KBD_KEY, kbd_clk_line, kbd_data_line, not_used, memory_line_id);
+
+output clk_of_verifla;
+output la_trigger_matched;
+output [16:0] memory_line_id;
+output [7:0] KBD_KEY;
+output kbd_clk_line;
+output kbd_data_line;
+output [5:0] not_used;
+reg [7:0] KBD_KEY;
+reg kbd_clk_line;
+reg kbd_data_line;
+reg [5:0] not_used;
+reg [16:0] memory_line_id;
+reg la_trigger_matched;
+reg clk_of_verifla;
+
+parameter PERIOD = 20;
+initial // Clock process for clk_of_verifla
+begin
+ forever
+ begin
+ clk_of_verifla = 1'b0;
+ #(10); clk_of_verifla = 1'b1;
+ #(10);
+ end
+end
+
+initial begin
+#(10);
+la_trigger_matched = 0;
+memory_line_id=6;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 1310670*(1ns)
+memory_line_id=7;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 2621330*(1ns)
+memory_line_id=0;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 3931990*(1ns)
+memory_line_id=1;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 5242650*(1ns)
+memory_line_id=2;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 6553310*(1ns)
+memory_line_id=3;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 7863970*(1ns)
+memory_line_id=4;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1198240;
+// ------------- Current Time: 9062210*(1ns)
+memory_line_id=5;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000100000000;
+#11540;
+// ------------- Current Time: 9073750*(1ns)
+memory_line_id=8;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000000000000;
+la_trigger_matched = 1;
+#60;
+// ------------- Current Time: 9073810*(1ns)
+memory_line_id=9;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#44180;
+// ------------- Current Time: 9117990*(1ns)
+memory_line_id=10;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010100000000;
+#34280;
+// ------------- Current Time: 9152270*(1ns)
+memory_line_id=11;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#60;
+// ------------- Current Time: 9152330*(1ns)
+memory_line_id=12;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#43140;
+// ------------- Current Time: 9195470*(1ns)
+memory_line_id=13;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100100000000;
+#34280;
+// ------------- Current Time: 9229750*(1ns)
+memory_line_id=14;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#60;
+// ------------- Current Time: 9229810*(1ns)
+memory_line_id=15;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110000000000;
+#43140;
+// ------------- Current Time: 9272950*(1ns)
+memory_line_id=16;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110100000000;
+#11460;
+// ------------- Current Time: 9284410*(1ns)
+memory_line_id=17;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111100000000;
+#24900;
+// ------------- Current Time: 9309310*(1ns)
+memory_line_id=18;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111000000000;
+#60;
+// ------------- Current Time: 9309370*(1ns)
+memory_line_id=19;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#43100;
+// ------------- Current Time: 9352470*(1ns)
+memory_line_id=20;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001110000000;
+#36400;
+// ------------- Current Time: 9388870*(1ns)
+memory_line_id=21;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#60;
+// ------------- Current Time: 9388930*(1ns)
+memory_line_id=22;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#43100;
+// ------------- Current Time: 9432030*(1ns)
+memory_line_id=23;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011111000000;
+#36400;
+// ------------- Current Time: 9468430*(1ns)
+memory_line_id=24;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#60;
+// ------------- Current Time: 9468490*(1ns)
+memory_line_id=25;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101011100000;
+#43100;
+// ------------- Current Time: 9511590*(1ns)
+memory_line_id=26;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101111100000;
+#12340;
+// ------------- Current Time: 9523930*(1ns)
+memory_line_id=27;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100111100000;
+#22000;
+// ------------- Current Time: 9545930*(1ns)
+memory_line_id=28;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100011100000;
+#60;
+// ------------- Current Time: 9545990*(1ns)
+memory_line_id=29;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#43140;
+// ------------- Current Time: 9589130*(1ns)
+memory_line_id=30;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110101110000;
+#34260;
+// ------------- Current Time: 9623390*(1ns)
+memory_line_id=31;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#60;
+// ------------- Current Time: 9623450*(1ns)
+memory_line_id=32;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#43140;
+// ------------- Current Time: 9666590*(1ns)
+memory_line_id=33;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000100111000;
+#34280;
+// ------------- Current Time: 9700870*(1ns)
+memory_line_id=34;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#60;
+// ------------- Current Time: 9700930*(1ns)
+memory_line_id=35;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#44180;
+// ------------- Current Time: 9745110*(1ns)
+memory_line_id=36;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010100011100;
+#41600;
+// ------------- Current Time: 9786710*(1ns)
+memory_line_id=37;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#60;
+// ------------- Current Time: 9786770*(1ns)
+memory_line_id=38;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100000011100;
+#43140;
+// ------------- Current Time: 9829910*(1ns)
+memory_line_id=39;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100100011100;
+#11460;
+// ------------- Current Time: 9841370*(1ns)
+memory_line_id=40;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101100011100;
+#30120;
+// ------------- Current Time: 9871490*(1ns)
+memory_line_id=41;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101000011100;
+#60;
+// ------------- Current Time: 9871550*(1ns)
+memory_line_id=42;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111000011100;
+#49380;
+// ------------- Current Time: 9920930*(1ns)
+memory_line_id=43;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 11231590*(1ns)
+memory_line_id=44;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 12542250*(1ns)
+memory_line_id=45;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 13852910*(1ns)
+memory_line_id=46;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 15163570*(1ns)
+memory_line_id=47;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 16474230*(1ns)
+memory_line_id=48;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 17784890*(1ns)
+memory_line_id=49;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 19095550*(1ns)
+memory_line_id=50;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 20406210*(1ns)
+memory_line_id=51;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 21716870*(1ns)
+memory_line_id=52;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 23027530*(1ns)
+memory_line_id=53;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 24338190*(1ns)
+memory_line_id=54;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 25648850*(1ns)
+memory_line_id=55;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 26959510*(1ns)
+memory_line_id=56;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 28270170*(1ns)
+memory_line_id=57;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 29580830*(1ns)
+memory_line_id=58;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 30891490*(1ns)
+memory_line_id=59;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 32202150*(1ns)
+memory_line_id=60;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 33512810*(1ns)
+memory_line_id=61;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 34823470*(1ns)
+memory_line_id=62;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 36134130*(1ns)
+$stop;
+end
+endmodule
+/*
+ORIGINAL CAPTURE DUMP
+memory_line_id=0: FF FD 03 00
+memory_line_id=1: FF FD 03 00
+memory_line_id=2: FF FD 03 00
+memory_line_id=3: FF FD 03 00
+memory_line_id=4: EA 08 03 00
+memory_line_id=5: 02 41 01 00
+memory_line_id=6: FF FD 03 00
+memory_line_id=7: FF FD 03 00
+memory_line_id=8: 00 03 00 00
+memory_line_id=9: 08 A1 04 00
+memory_line_id=10: 06 B2 05 00
+memory_line_id=11: 00 03 04 00
+memory_line_id=12: 08 6D 08 00
+memory_line_id=13: 06 B2 09 00
+memory_line_id=14: 00 03 08 00
+memory_line_id=15: 08 6D 0C 00
+memory_line_id=16: 02 3D 0D 00
+memory_line_id=17: 04 DD 0F 00
+memory_line_id=18: 00 03 0E 00
+memory_line_id=19: 08 6B 12 80
+memory_line_id=20: 07 1C 13 80
+memory_line_id=21: 00 03 12 80
+memory_line_id=22: 08 6B 16 C0
+memory_line_id=23: 07 1C 17 C0
+memory_line_id=24: 00 03 16 C0
+memory_line_id=25: 08 6B 1A E0
+memory_line_id=26: 02 69 1B E0
+memory_line_id=27: 04 4C 19 E0
+memory_line_id=28: 00 03 18 E0
+memory_line_id=29: 08 6D 1C 70
+memory_line_id=30: 06 B1 1D 70
+memory_line_id=31: 00 03 1C 70
+memory_line_id=32: 08 6D 20 38
+memory_line_id=33: 06 B2 21 38
+memory_line_id=34: 00 03 20 38
+memory_line_id=35: 08 A1 24 1C
+memory_line_id=36: 08 20 25 1C
+memory_line_id=37: 00 03 24 1C
+memory_line_id=38: 08 6D 28 1C
+memory_line_id=39: 02 3D 29 1C
+memory_line_id=40: 05 E2 2B 1C
+memory_line_id=41: 00 03 2A 1C
+memory_line_id=42: 09 A5 2E 1C
+memory_line_id=43: FF FD 2F 1C
+memory_line_id=44: FF FD 2F 1C
+memory_line_id=45: FF FD 2F 1C
+memory_line_id=46: FF FD 2F 1C
+memory_line_id=47: FF FD 2F 1C
+memory_line_id=48: FF FD 2F 1C
+memory_line_id=49: FF FD 2F 1C
+memory_line_id=50: FF FD 2F 1C
+memory_line_id=51: FF FD 2F 1C
+memory_line_id=52: FF FD 2F 1C
+memory_line_id=53: FF FD 2F 1C
+memory_line_id=54: FF FD 2F 1C
+memory_line_id=55: FF FD 2F 1C
+memory_line_id=56: FF FD 2F 1C
+memory_line_id=57: FF FD 2F 1C
+memory_line_id=58: FF FD 2F 1C
+memory_line_id=59: FF FD 2F 1C
+memory_line_id=60: FF FD 2F 1C
+memory_line_id=61: FF FD 2F 1C
+memory_line_id=62: FF FD 2F 1C
+memory_line_id=63: 00 00 00 05
+*/
Index: trunk/openverifla_2.3/java/capture_20181016_1235_36.v
===================================================================
--- trunk/openverifla_2.3/java/capture_20181016_1235_36.v (nonexistent)
+++ trunk/openverifla_2.3/java/capture_20181016_1235_36.v (revision 38)
@@ -0,0 +1,356 @@
+`timescale 1ns / 10ps
+
+module capture_20181016_1235_36(clk_of_verifla, la_trigger_matched, KBD_KEY, kbd_clk_line, kbd_data_line, not_used, memory_line_id);
+
+output clk_of_verifla;
+output la_trigger_matched;
+output [16:0] memory_line_id;
+output [7:0] KBD_KEY;
+output kbd_clk_line;
+output kbd_data_line;
+output [5:0] not_used;
+reg [7:0] KBD_KEY;
+reg kbd_clk_line;
+reg kbd_data_line;
+reg [5:0] not_used;
+reg [16:0] memory_line_id;
+reg la_trigger_matched;
+reg clk_of_verifla;
+
+parameter PERIOD = 20;
+initial // Clock process for clk_of_verifla
+begin
+ forever
+ begin
+ clk_of_verifla = 1'b0;
+ #(10); clk_of_verifla = 1'b1;
+ #(10);
+ end
+end
+
+initial begin
+#(10);
+la_trigger_matched = 0;
+memory_line_id=4;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 1310670*(1ns)
+memory_line_id=5;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 2621330*(1ns)
+memory_line_id=6;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 3931990*(1ns)
+memory_line_id=7;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 5242650*(1ns)
+memory_line_id=0;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 6553310*(1ns)
+memory_line_id=1;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 7863970*(1ns)
+memory_line_id=2;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1029400;
+// ------------- Current Time: 8893370*(1ns)
+memory_line_id=3;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000100000000;
+#11540;
+// ------------- Current Time: 8904910*(1ns)
+memory_line_id=8;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000000000000;
+la_trigger_matched = 1;
+#60;
+// ------------- Current Time: 8904970*(1ns)
+memory_line_id=9;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#44180;
+// ------------- Current Time: 8949150*(1ns)
+memory_line_id=10;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010100000000;
+#34300;
+// ------------- Current Time: 8983450*(1ns)
+memory_line_id=11;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#60;
+// ------------- Current Time: 8983510*(1ns)
+memory_line_id=12;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#43140;
+// ------------- Current Time: 9026650*(1ns)
+memory_line_id=13;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100100000000;
+#34280;
+// ------------- Current Time: 9060930*(1ns)
+memory_line_id=14;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#60;
+// ------------- Current Time: 9060990*(1ns)
+memory_line_id=15;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110000000000;
+#43160;
+// ------------- Current Time: 9104150*(1ns)
+memory_line_id=16;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110100000000;
+#11460;
+// ------------- Current Time: 9115610*(1ns)
+memory_line_id=17;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111100000000;
+#24900;
+// ------------- Current Time: 9140510*(1ns)
+memory_line_id=18;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111000000000;
+#60;
+// ------------- Current Time: 9140570*(1ns)
+memory_line_id=19;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#43100;
+// ------------- Current Time: 9183670*(1ns)
+memory_line_id=20;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001110000000;
+#36400;
+// ------------- Current Time: 9220070*(1ns)
+memory_line_id=21;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#60;
+// ------------- Current Time: 9220130*(1ns)
+memory_line_id=22;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#43120;
+// ------------- Current Time: 9263250*(1ns)
+memory_line_id=23;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011111000000;
+#36400;
+// ------------- Current Time: 9299650*(1ns)
+memory_line_id=24;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#60;
+// ------------- Current Time: 9299710*(1ns)
+memory_line_id=25;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101011100000;
+#43120;
+// ------------- Current Time: 9342830*(1ns)
+memory_line_id=26;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101111100000;
+#12320;
+// ------------- Current Time: 9355150*(1ns)
+memory_line_id=27;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100111100000;
+#22020;
+// ------------- Current Time: 9377170*(1ns)
+memory_line_id=28;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100011100000;
+#60;
+// ------------- Current Time: 9377230*(1ns)
+memory_line_id=29;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#43140;
+// ------------- Current Time: 9420370*(1ns)
+memory_line_id=30;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110101110000;
+#34280;
+// ------------- Current Time: 9454650*(1ns)
+memory_line_id=31;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#60;
+// ------------- Current Time: 9454710*(1ns)
+memory_line_id=32;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#43160;
+// ------------- Current Time: 9497870*(1ns)
+memory_line_id=33;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000100111000;
+#34280;
+// ------------- Current Time: 9532150*(1ns)
+memory_line_id=34;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#60;
+// ------------- Current Time: 9532210*(1ns)
+memory_line_id=35;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#44180;
+// ------------- Current Time: 9576390*(1ns)
+memory_line_id=36;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010100011100;
+#41620;
+// ------------- Current Time: 9618010*(1ns)
+memory_line_id=37;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#60;
+// ------------- Current Time: 9618070*(1ns)
+memory_line_id=38;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100000011100;
+#43140;
+// ------------- Current Time: 9661210*(1ns)
+memory_line_id=39;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100100011100;
+#11460;
+// ------------- Current Time: 9672670*(1ns)
+memory_line_id=40;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101100011100;
+#30140;
+// ------------- Current Time: 9702810*(1ns)
+memory_line_id=41;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101000011100;
+#60;
+// ------------- Current Time: 9702870*(1ns)
+memory_line_id=42;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111000011100;
+#49380;
+// ------------- Current Time: 9752250*(1ns)
+memory_line_id=43;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 11062910*(1ns)
+memory_line_id=44;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 12373570*(1ns)
+memory_line_id=45;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 13684230*(1ns)
+memory_line_id=46;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 14994890*(1ns)
+memory_line_id=47;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 16305550*(1ns)
+memory_line_id=48;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 17616210*(1ns)
+memory_line_id=49;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 18926870*(1ns)
+memory_line_id=50;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 20237530*(1ns)
+memory_line_id=51;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 21548190*(1ns)
+memory_line_id=52;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 22858850*(1ns)
+memory_line_id=53;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 24169510*(1ns)
+memory_line_id=54;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 25480170*(1ns)
+memory_line_id=55;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 26790830*(1ns)
+memory_line_id=56;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 28101490*(1ns)
+memory_line_id=57;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 29412150*(1ns)
+memory_line_id=58;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 30722810*(1ns)
+memory_line_id=59;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 32033470*(1ns)
+memory_line_id=60;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 33344130*(1ns)
+memory_line_id=61;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 34654790*(1ns)
+memory_line_id=62;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 35965450*(1ns)
+$stop;
+end
+endmodule
+/*
+ORIGINAL CAPTURE DUMP
+memory_line_id=0: FF FD 03 00
+memory_line_id=1: FF FD 03 00
+memory_line_id=2: C9 0E 03 00
+memory_line_id=3: 02 41 01 00
+memory_line_id=4: FF FD 03 00
+memory_line_id=5: FF FD 03 00
+memory_line_id=6: FF FD 03 00
+memory_line_id=7: FF FD 03 00
+memory_line_id=8: 00 03 00 00
+memory_line_id=9: 08 A1 04 00
+memory_line_id=10: 06 B3 05 00
+memory_line_id=11: 00 03 04 00
+memory_line_id=12: 08 6D 08 00
+memory_line_id=13: 06 B2 09 00
+memory_line_id=14: 00 03 08 00
+memory_line_id=15: 08 6E 0C 00
+memory_line_id=16: 02 3D 0D 00
+memory_line_id=17: 04 DD 0F 00
+memory_line_id=18: 00 03 0E 00
+memory_line_id=19: 08 6B 12 80
+memory_line_id=20: 07 1C 13 80
+memory_line_id=21: 00 03 12 80
+memory_line_id=22: 08 6C 16 C0
+memory_line_id=23: 07 1C 17 C0
+memory_line_id=24: 00 03 16 C0
+memory_line_id=25: 08 6C 1A E0
+memory_line_id=26: 02 68 1B E0
+memory_line_id=27: 04 4D 19 E0
+memory_line_id=28: 00 03 18 E0
+memory_line_id=29: 08 6D 1C 70
+memory_line_id=30: 06 B2 1D 70
+memory_line_id=31: 00 03 1C 70
+memory_line_id=32: 08 6E 20 38
+memory_line_id=33: 06 B2 21 38
+memory_line_id=34: 00 03 20 38
+memory_line_id=35: 08 A1 24 1C
+memory_line_id=36: 08 21 25 1C
+memory_line_id=37: 00 03 24 1C
+memory_line_id=38: 08 6D 28 1C
+memory_line_id=39: 02 3D 29 1C
+memory_line_id=40: 05 E3 2B 1C
+memory_line_id=41: 00 03 2A 1C
+memory_line_id=42: 09 A5 2E 1C
+memory_line_id=43: FF FD 2F 1C
+memory_line_id=44: FF FD 2F 1C
+memory_line_id=45: FF FD 2F 1C
+memory_line_id=46: FF FD 2F 1C
+memory_line_id=47: FF FD 2F 1C
+memory_line_id=48: FF FD 2F 1C
+memory_line_id=49: FF FD 2F 1C
+memory_line_id=50: FF FD 2F 1C
+memory_line_id=51: FF FD 2F 1C
+memory_line_id=52: FF FD 2F 1C
+memory_line_id=53: FF FD 2F 1C
+memory_line_id=54: FF FD 2F 1C
+memory_line_id=55: FF FD 2F 1C
+memory_line_id=56: FF FD 2F 1C
+memory_line_id=57: FF FD 2F 1C
+memory_line_id=58: FF FD 2F 1C
+memory_line_id=59: FF FD 2F 1C
+memory_line_id=60: FF FD 2F 1C
+memory_line_id=61: FF FD 2F 1C
+memory_line_id=62: FF FD 2F 1C
+memory_line_id=63: 00 00 00 03
+*/
Index: trunk/openverifla_2.3/java/capture_keyboard_20180823_1508.v
===================================================================
--- trunk/openverifla_2.3/java/capture_keyboard_20180823_1508.v (nonexistent)
+++ trunk/openverifla_2.3/java/capture_keyboard_20180823_1508.v (revision 38)
@@ -0,0 +1,356 @@
+`timescale 1ns / 10ps
+
+module capture_20180823_1508_56(clk_of_verifla, la_trigger_matched, KBD_KEY, kbd_clk_line, kbd_data_line, not_used, memory_line_id);
+
+output clk_of_verifla;
+output la_trigger_matched;
+output [16:0] memory_line_id;
+output [7:0] KBD_KEY;
+output kbd_clk_line;
+output kbd_data_line;
+output [5:0] not_used;
+reg [7:0] KBD_KEY;
+reg kbd_clk_line;
+reg kbd_data_line;
+reg [5:0] not_used;
+reg [16:0] memory_line_id;
+reg la_trigger_matched;
+reg clk_of_verifla;
+
+parameter PERIOD = 20;
+initial // Clock process for clk_of_verifla
+begin
+ forever
+ begin
+ clk_of_verifla = 1'b0;
+ #(10); clk_of_verifla = 1'b1;
+ #(10);
+ end
+end
+
+initial begin
+#(10);
+la_trigger_matched = 0;
+memory_line_id=3;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 1310670*(1ns)
+memory_line_id=4;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 2621330*(1ns)
+memory_line_id=5;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 3931990*(1ns)
+memory_line_id=6;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 5242650*(1ns)
+memory_line_id=7;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 6553310*(1ns)
+memory_line_id=0;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#1310660;
+// ------------- Current Time: 7863970*(1ns)
+memory_line_id=1;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000001100000000;
+#767700;
+// ------------- Current Time: 8631670*(1ns)
+memory_line_id=2;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000100000000;
+#11460;
+// ------------- Current Time: 8643130*(1ns)
+memory_line_id=8;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000000000000000;
+la_trigger_matched = 1;
+#60;
+// ------------- Current Time: 8643190*(1ns)
+memory_line_id=9;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#43880;
+// ------------- Current Time: 8687070*(1ns)
+memory_line_id=10;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010100000000;
+#34020;
+// ------------- Current Time: 8721090*(1ns)
+memory_line_id=11;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000010000000000;
+#60;
+// ------------- Current Time: 8721150*(1ns)
+memory_line_id=12;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#42860;
+// ------------- Current Time: 8764010*(1ns)
+memory_line_id=13;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100100000000;
+#34020;
+// ------------- Current Time: 8798030*(1ns)
+memory_line_id=14;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000100000000000;
+#40;
+// ------------- Current Time: 8798070*(1ns)
+memory_line_id=15;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110000000000;
+#42860;
+// ------------- Current Time: 8840930*(1ns)
+memory_line_id=16;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000110100000000;
+#11380;
+// ------------- Current Time: 8852310*(1ns)
+memory_line_id=17;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111100000000;
+#24700;
+// ------------- Current Time: 8877010*(1ns)
+memory_line_id=18;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0000111000000000;
+#60;
+// ------------- Current Time: 8877070*(1ns)
+memory_line_id=19;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#42800;
+// ------------- Current Time: 8919870*(1ns)
+memory_line_id=20;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001110000000;
+#36140;
+// ------------- Current Time: 8956010*(1ns)
+memory_line_id=21;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001001010000000;
+#60;
+// ------------- Current Time: 8956070*(1ns)
+memory_line_id=22;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#42800;
+// ------------- Current Time: 8998870*(1ns)
+memory_line_id=23;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011111000000;
+#36140;
+// ------------- Current Time: 9035010*(1ns)
+memory_line_id=24;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001011011000000;
+#60;
+// ------------- Current Time: 9035070*(1ns)
+memory_line_id=25;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101011100000;
+#42800;
+// ------------- Current Time: 9077870*(1ns)
+memory_line_id=26;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001101111100000;
+#12220;
+// ------------- Current Time: 9090090*(1ns)
+memory_line_id=27;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100111100000;
+#21860;
+// ------------- Current Time: 9111950*(1ns)
+memory_line_id=28;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001100011100000;
+#60;
+// ------------- Current Time: 9112010*(1ns)
+memory_line_id=29;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#42840;
+// ------------- Current Time: 9154850*(1ns)
+memory_line_id=30;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110101110000;
+#34020;
+// ------------- Current Time: 9188870*(1ns)
+memory_line_id=31;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0001110001110000;
+#60;
+// ------------- Current Time: 9188930*(1ns)
+memory_line_id=32;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#42840;
+// ------------- Current Time: 9231770*(1ns)
+memory_line_id=33;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000100111000;
+#34020;
+// ------------- Current Time: 9265790*(1ns)
+memory_line_id=34;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010000000111000;
+#60;
+// ------------- Current Time: 9265850*(1ns)
+memory_line_id=35;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#43880;
+// ------------- Current Time: 9309730*(1ns)
+memory_line_id=36;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010100011100;
+#41300;
+// ------------- Current Time: 9351030*(1ns)
+memory_line_id=37;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010010000011100;
+#60;
+// ------------- Current Time: 9351090*(1ns)
+memory_line_id=38;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100000011100;
+#42840;
+// ------------- Current Time: 9393930*(1ns)
+memory_line_id=39;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010100100011100;
+#11380;
+// ------------- Current Time: 9405310*(1ns)
+memory_line_id=40;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101100011100;
+#29900;
+// ------------- Current Time: 9435210*(1ns)
+memory_line_id=41;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010101000011100;
+#60;
+// ------------- Current Time: 9435270*(1ns)
+memory_line_id=42;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111000011100;
+#49060;
+// ------------- Current Time: 9484330*(1ns)
+memory_line_id=43;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 10794990*(1ns)
+memory_line_id=44;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 12105650*(1ns)
+memory_line_id=45;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 13416310*(1ns)
+memory_line_id=46;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 14726970*(1ns)
+memory_line_id=47;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 16037630*(1ns)
+memory_line_id=48;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 17348290*(1ns)
+memory_line_id=49;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 18658950*(1ns)
+memory_line_id=50;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 19969610*(1ns)
+memory_line_id=51;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 21280270*(1ns)
+memory_line_id=52;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 22590930*(1ns)
+memory_line_id=53;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 23901590*(1ns)
+memory_line_id=54;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 25212250*(1ns)
+memory_line_id=55;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 26522910*(1ns)
+memory_line_id=56;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 27833570*(1ns)
+memory_line_id=57;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 29144230*(1ns)
+memory_line_id=58;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 30454890*(1ns)
+memory_line_id=59;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 31765550*(1ns)
+memory_line_id=60;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 33076210*(1ns)
+memory_line_id=61;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 34386870*(1ns)
+memory_line_id=62;
+{not_used,kbd_data_line,kbd_clk_line,KBD_KEY} = 16'b0010111100011100;
+#1310660;
+// ------------- Current Time: 35697530*(1ns)
+$stop;
+end
+endmodule
+/*
+ORIGINAL CAPTURE DUMP
+memory_line_id=0: FF FD 03 00
+memory_line_id=1: 95 F1 03 00
+memory_line_id=2: 02 3D 01 00
+memory_line_id=3: FF FD 03 00
+memory_line_id=4: FF FD 03 00
+memory_line_id=5: FF FD 03 00
+memory_line_id=6: FF FD 03 00
+memory_line_id=7: FF FD 03 00
+memory_line_id=8: 00 03 00 00
+memory_line_id=9: 08 92 04 00
+memory_line_id=10: 06 A5 05 00
+memory_line_id=11: 00 03 04 00
+memory_line_id=12: 08 5F 08 00
+memory_line_id=13: 06 A5 09 00
+memory_line_id=14: 00 02 08 00
+memory_line_id=15: 08 5F 0C 00
+memory_line_id=16: 02 39 0D 00
+memory_line_id=17: 04 D3 0F 00
+memory_line_id=18: 00 03 0E 00
+memory_line_id=19: 08 5C 12 80
+memory_line_id=20: 07 0F 13 80
+memory_line_id=21: 00 03 12 80
+memory_line_id=22: 08 5C 16 C0
+memory_line_id=23: 07 0F 17 C0
+memory_line_id=24: 00 03 16 C0
+memory_line_id=25: 08 5C 1A E0
+memory_line_id=26: 02 63 1B E0
+memory_line_id=27: 04 45 19 E0
+memory_line_id=28: 00 03 18 E0
+memory_line_id=29: 08 5E 1C 70
+memory_line_id=30: 06 A5 1D 70
+memory_line_id=31: 00 03 1C 70
+memory_line_id=32: 08 5E 20 38
+memory_line_id=33: 06 A5 21 38
+memory_line_id=34: 00 03 20 38
+memory_line_id=35: 08 92 24 1C
+memory_line_id=36: 08 11 25 1C
+memory_line_id=37: 00 03 24 1C
+memory_line_id=38: 08 5E 28 1C
+memory_line_id=39: 02 39 29 1C
+memory_line_id=40: 05 D7 2B 1C
+memory_line_id=41: 00 03 2A 1C
+memory_line_id=42: 09 95 2E 1C
+memory_line_id=43: FF FD 2F 1C
+memory_line_id=44: FF FD 2F 1C
+memory_line_id=45: FF FD 2F 1C
+memory_line_id=46: FF FD 2F 1C
+memory_line_id=47: FF FD 2F 1C
+memory_line_id=48: FF FD 2F 1C
+memory_line_id=49: FF FD 2F 1C
+memory_line_id=50: FF FD 2F 1C
+memory_line_id=51: FF FD 2F 1C
+memory_line_id=52: FF FD 2F 1C
+memory_line_id=53: FF FD 2F 1C
+memory_line_id=54: FF FD 2F 1C
+memory_line_id=55: FF FD 2F 1C
+memory_line_id=56: FF FD 2F 1C
+memory_line_id=57: FF FD 2F 1C
+memory_line_id=58: FF FD 2F 1C
+memory_line_id=59: FF FD 2F 1C
+memory_line_id=60: FF FD 2F 1C
+memory_line_id=61: FF FD 2F 1C
+memory_line_id=62: FF FD 2F 1C
+memory_line_id=63: 00 00 00 02
+*/
Index: trunk/openverifla_2.3/java/capture_spi_slave_20180824_1626.v
===================================================================
--- trunk/openverifla_2.3/java/capture_spi_slave_20180824_1626.v (nonexistent)
+++ trunk/openverifla_2.3/java/capture_spi_slave_20180824_1626.v (revision 38)
@@ -0,0 +1,1322 @@
+`timescale 1ns / 10ps
+
+module capture_20180824_1626_23(clk_of_verifla, la_trigger_matched, SCK, SSEL, MOSI, MISO, bitcnt_0, byte_received, byte_data_sent_10, memory_line_id);
+
+output clk_of_verifla;
+output la_trigger_matched;
+output [64:0] memory_line_id;
+output SCK;
+output SSEL;
+output MOSI;
+output MISO;
+output bitcnt_0;
+output byte_received;
+output [1:0] byte_data_sent_10;
+reg SCK;
+reg SSEL;
+reg MOSI;
+reg MISO;
+reg bitcnt_0;
+reg byte_received;
+reg [1:0] byte_data_sent_10;
+reg [64:0] memory_line_id;
+reg la_trigger_matched;
+reg clk_of_verifla;
+
+parameter PERIOD = 20;
+initial // Clock process for clk_of_verifla
+begin
+ forever
+ begin
+ clk_of_verifla = 1'b0;
+ #(10); clk_of_verifla = 1'b1;
+ #(10);
+ end
+end
+
+initial begin
+#(10);
+la_trigger_matched = 0;
+memory_line_id=2;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 5070*(1ns)
+memory_line_id=3;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 10130*(1ns)
+memory_line_id=4;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 15190*(1ns)
+memory_line_id=5;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 20250*(1ns)
+memory_line_id=6;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 25310*(1ns)
+memory_line_id=7;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 30370*(1ns)
+memory_line_id=0;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 35430*(1ns)
+memory_line_id=1;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#2760;
+// ------------- Current Time: 38190*(1ns)
+memory_line_id=8;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+la_trigger_matched = 1;
+#5060;
+// ------------- Current Time: 43250*(1ns)
+memory_line_id=9;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#5060;
+// ------------- Current Time: 48310*(1ns)
+memory_line_id=10;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#3460;
+// ------------- Current Time: 51770*(1ns)
+memory_line_id=11;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 52270*(1ns)
+memory_line_id=12;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 52330*(1ns)
+memory_line_id=13;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 52770*(1ns)
+memory_line_id=14;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 53270*(1ns)
+memory_line_id=15;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 53330*(1ns)
+memory_line_id=16;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 53770*(1ns)
+memory_line_id=17;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 54270*(1ns)
+memory_line_id=18;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 54330*(1ns)
+memory_line_id=19;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 54770*(1ns)
+memory_line_id=20;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 55270*(1ns)
+memory_line_id=21;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 55330*(1ns)
+memory_line_id=22;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 55770*(1ns)
+memory_line_id=23;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 56270*(1ns)
+memory_line_id=24;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 56330*(1ns)
+memory_line_id=25;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 56770*(1ns)
+memory_line_id=26;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 57270*(1ns)
+memory_line_id=27;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 57330*(1ns)
+memory_line_id=28;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 57770*(1ns)
+memory_line_id=29;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 58270*(1ns)
+memory_line_id=30;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 58330*(1ns)
+memory_line_id=31;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 58770*(1ns)
+memory_line_id=32;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 59270*(1ns)
+memory_line_id=33;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 59330*(1ns)
+memory_line_id=34;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00100101;
+#440;
+// ------------- Current Time: 59770*(1ns)
+memory_line_id=35;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00100000;
+#60;
+// ------------- Current Time: 59830*(1ns)
+memory_line_id=36;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 64890*(1ns)
+memory_line_id=37;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 69950*(1ns)
+memory_line_id=38;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 75010*(1ns)
+memory_line_id=39;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 80070*(1ns)
+memory_line_id=40;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 85130*(1ns)
+memory_line_id=41;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 90190*(1ns)
+memory_line_id=42;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 95250*(1ns)
+memory_line_id=43;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 100310*(1ns)
+memory_line_id=44;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 105370*(1ns)
+memory_line_id=45;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 110430*(1ns)
+memory_line_id=46;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 115490*(1ns)
+memory_line_id=47;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 120550*(1ns)
+memory_line_id=48;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 125610*(1ns)
+memory_line_id=49;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 130670*(1ns)
+memory_line_id=50;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 135730*(1ns)
+memory_line_id=51;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 140790*(1ns)
+memory_line_id=52;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 145850*(1ns)
+memory_line_id=53;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 150910*(1ns)
+memory_line_id=54;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 155970*(1ns)
+memory_line_id=55;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 161030*(1ns)
+memory_line_id=56;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 166090*(1ns)
+memory_line_id=57;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 171150*(1ns)
+memory_line_id=58;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 176210*(1ns)
+memory_line_id=59;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#1340;
+// ------------- Current Time: 177550*(1ns)
+memory_line_id=60;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 182610*(1ns)
+memory_line_id=61;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 187670*(1ns)
+memory_line_id=62;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#680;
+// ------------- Current Time: 188350*(1ns)
+memory_line_id=63;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#60;
+// ------------- Current Time: 188410*(1ns)
+memory_line_id=64;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 193470*(1ns)
+memory_line_id=65;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 198530*(1ns)
+memory_line_id=66;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 203590*(1ns)
+memory_line_id=67;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 208650*(1ns)
+memory_line_id=68;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 213710*(1ns)
+memory_line_id=69;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 218770*(1ns)
+memory_line_id=70;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 223830*(1ns)
+memory_line_id=71;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 228890*(1ns)
+memory_line_id=72;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 233950*(1ns)
+memory_line_id=73;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 239010*(1ns)
+memory_line_id=74;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 244070*(1ns)
+memory_line_id=75;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 249130*(1ns)
+memory_line_id=76;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#2000;
+// ------------- Current Time: 251130*(1ns)
+memory_line_id=77;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100001;
+#60;
+// ------------- Current Time: 251190*(1ns)
+memory_line_id=78;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01010001;
+#440;
+// ------------- Current Time: 251630*(1ns)
+memory_line_id=79;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01010000;
+#60;
+// ------------- Current Time: 251690*(1ns)
+memory_line_id=80;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 252130*(1ns)
+memory_line_id=81;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 252190*(1ns)
+memory_line_id=82;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 252630*(1ns)
+memory_line_id=83;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000000;
+#60;
+// ------------- Current Time: 252690*(1ns)
+memory_line_id=84;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#440;
+// ------------- Current Time: 253130*(1ns)
+memory_line_id=85;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 253190*(1ns)
+memory_line_id=86;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 253630*(1ns)
+memory_line_id=87;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 254130*(1ns)
+memory_line_id=88;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 254190*(1ns)
+memory_line_id=89;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 254630*(1ns)
+memory_line_id=90;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 255130*(1ns)
+memory_line_id=91;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 255190*(1ns)
+memory_line_id=92;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 255630*(1ns)
+memory_line_id=93;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 256130*(1ns)
+memory_line_id=94;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 256190*(1ns)
+memory_line_id=95;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 256630*(1ns)
+memory_line_id=96;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 257130*(1ns)
+memory_line_id=97;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 257190*(1ns)
+memory_line_id=98;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 257630*(1ns)
+memory_line_id=99;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#60;
+// ------------- Current Time: 257690*(1ns)
+memory_line_id=100;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011100;
+#440;
+// ------------- Current Time: 258130*(1ns)
+memory_line_id=101;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#60;
+// ------------- Current Time: 258190*(1ns)
+memory_line_id=102;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101101;
+#440;
+// ------------- Current Time: 258630*(1ns)
+memory_line_id=103;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 258690*(1ns)
+memory_line_id=104;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#1440;
+// ------------- Current Time: 260130*(1ns)
+memory_line_id=105;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100001;
+#60;
+// ------------- Current Time: 260190*(1ns)
+memory_line_id=106;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010001;
+#440;
+// ------------- Current Time: 260630*(1ns)
+memory_line_id=107;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010000;
+#60;
+// ------------- Current Time: 260690*(1ns)
+memory_line_id=108;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 261130*(1ns)
+memory_line_id=109;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 261190*(1ns)
+memory_line_id=110;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 261630*(1ns)
+memory_line_id=111;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000000;
+#60;
+// ------------- Current Time: 261690*(1ns)
+memory_line_id=112;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#440;
+// ------------- Current Time: 262130*(1ns)
+memory_line_id=113;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 262190*(1ns)
+memory_line_id=114;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 262630*(1ns)
+memory_line_id=115;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 263130*(1ns)
+memory_line_id=116;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 263190*(1ns)
+memory_line_id=117;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 263630*(1ns)
+memory_line_id=118;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 264130*(1ns)
+memory_line_id=119;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 264190*(1ns)
+memory_line_id=120;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 264630*(1ns)
+memory_line_id=121;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 265130*(1ns)
+memory_line_id=122;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 265190*(1ns)
+memory_line_id=123;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 265630*(1ns)
+memory_line_id=124;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#60;
+// ------------- Current Time: 265690*(1ns)
+memory_line_id=125;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001100;
+#440;
+// ------------- Current Time: 266130*(1ns)
+memory_line_id=126;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001101;
+#60;
+// ------------- Current Time: 266190*(1ns)
+memory_line_id=127;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#440;
+// ------------- Current Time: 266630*(1ns)
+memory_line_id=128;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011000;
+#500;
+// ------------- Current Time: 267130*(1ns)
+memory_line_id=129;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011001;
+#60;
+// ------------- Current Time: 267190*(1ns)
+memory_line_id=130;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101001;
+#440;
+// ------------- Current Time: 267630*(1ns)
+memory_line_id=131;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 267690*(1ns)
+memory_line_id=132;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#940;
+// ------------- Current Time: 268630*(1ns)
+memory_line_id=133;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100100;
+#500;
+// ------------- Current Time: 269130*(1ns)
+memory_line_id=134;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100101;
+#60;
+// ------------- Current Time: 269190*(1ns)
+memory_line_id=135;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010101;
+#440;
+// ------------- Current Time: 269630*(1ns)
+memory_line_id=136;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010000;
+#60;
+// ------------- Current Time: 269690*(1ns)
+memory_line_id=137;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 270130*(1ns)
+memory_line_id=138;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 270190*(1ns)
+memory_line_id=139;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 270630*(1ns)
+memory_line_id=140;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000100;
+#60;
+// ------------- Current Time: 270690*(1ns)
+memory_line_id=141;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#440;
+// ------------- Current Time: 271130*(1ns)
+memory_line_id=142;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 271190*(1ns)
+memory_line_id=143;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 271630*(1ns)
+memory_line_id=144;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 272130*(1ns)
+memory_line_id=145;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 272190*(1ns)
+memory_line_id=146;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 272630*(1ns)
+memory_line_id=147;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 273130*(1ns)
+memory_line_id=148;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 273190*(1ns)
+memory_line_id=149;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 273630*(1ns)
+memory_line_id=150;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 274130*(1ns)
+memory_line_id=151;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 274190*(1ns)
+memory_line_id=152;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 274630*(1ns)
+memory_line_id=153;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#60;
+// ------------- Current Time: 274690*(1ns)
+memory_line_id=154;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001000;
+#440;
+// ------------- Current Time: 275130*(1ns)
+memory_line_id=155;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001001;
+#60;
+// ------------- Current Time: 275190*(1ns)
+memory_line_id=156;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011001;
+#440;
+// ------------- Current Time: 275630*(1ns)
+memory_line_id=157;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011100;
+#500;
+// ------------- Current Time: 276130*(1ns)
+memory_line_id=158;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#60;
+// ------------- Current Time: 276190*(1ns)
+memory_line_id=159;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101101;
+#440;
+// ------------- Current Time: 276630*(1ns)
+memory_line_id=160;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 276690*(1ns)
+memory_line_id=161;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#2740;
+// ------------- Current Time: 279430*(1ns)
+memory_line_id=162;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 284490*(1ns)
+memory_line_id=163;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 289550*(1ns)
+memory_line_id=164;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 294610*(1ns)
+memory_line_id=165;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 299670*(1ns)
+memory_line_id=166;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 304730*(1ns)
+memory_line_id=167;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 309790*(1ns)
+memory_line_id=168;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 314850*(1ns)
+memory_line_id=169;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 319910*(1ns)
+memory_line_id=170;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 324970*(1ns)
+memory_line_id=171;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 330030*(1ns)
+memory_line_id=172;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 335090*(1ns)
+memory_line_id=173;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 340150*(1ns)
+memory_line_id=174;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 345210*(1ns)
+memory_line_id=175;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 350270*(1ns)
+memory_line_id=176;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 355330*(1ns)
+memory_line_id=177;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 360390*(1ns)
+memory_line_id=178;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 365450*(1ns)
+memory_line_id=179;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 370510*(1ns)
+memory_line_id=180;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 375570*(1ns)
+memory_line_id=181;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 380630*(1ns)
+memory_line_id=182;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 385690*(1ns)
+memory_line_id=183;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 390750*(1ns)
+memory_line_id=184;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 395810*(1ns)
+memory_line_id=185;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 400870*(1ns)
+memory_line_id=186;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 405930*(1ns)
+memory_line_id=187;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 410990*(1ns)
+memory_line_id=188;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 416050*(1ns)
+memory_line_id=189;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 421110*(1ns)
+memory_line_id=190;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 426170*(1ns)
+memory_line_id=191;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 431230*(1ns)
+memory_line_id=192;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 436290*(1ns)
+memory_line_id=193;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 441350*(1ns)
+memory_line_id=194;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 446410*(1ns)
+memory_line_id=195;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 451470*(1ns)
+memory_line_id=196;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 456530*(1ns)
+memory_line_id=197;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 461590*(1ns)
+memory_line_id=198;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 466650*(1ns)
+memory_line_id=199;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 471710*(1ns)
+memory_line_id=200;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 476770*(1ns)
+memory_line_id=201;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 481830*(1ns)
+memory_line_id=202;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 486890*(1ns)
+memory_line_id=203;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 491950*(1ns)
+memory_line_id=204;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 497010*(1ns)
+memory_line_id=205;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 502070*(1ns)
+memory_line_id=206;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 507130*(1ns)
+memory_line_id=207;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 512190*(1ns)
+memory_line_id=208;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 517250*(1ns)
+memory_line_id=209;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 522310*(1ns)
+memory_line_id=210;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 527370*(1ns)
+memory_line_id=211;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 532430*(1ns)
+memory_line_id=212;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 537490*(1ns)
+memory_line_id=213;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 542550*(1ns)
+memory_line_id=214;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 547610*(1ns)
+memory_line_id=215;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 552670*(1ns)
+memory_line_id=216;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 557730*(1ns)
+memory_line_id=217;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 562790*(1ns)
+memory_line_id=218;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 567850*(1ns)
+memory_line_id=219;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 572910*(1ns)
+memory_line_id=220;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 577970*(1ns)
+memory_line_id=221;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 583030*(1ns)
+memory_line_id=222;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 588090*(1ns)
+memory_line_id=223;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 593150*(1ns)
+memory_line_id=224;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 598210*(1ns)
+memory_line_id=225;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 603270*(1ns)
+memory_line_id=226;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 608330*(1ns)
+memory_line_id=227;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 613390*(1ns)
+memory_line_id=228;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 618450*(1ns)
+memory_line_id=229;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 623510*(1ns)
+memory_line_id=230;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 628570*(1ns)
+memory_line_id=231;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 633630*(1ns)
+memory_line_id=232;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 638690*(1ns)
+memory_line_id=233;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 643750*(1ns)
+memory_line_id=234;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 648810*(1ns)
+memory_line_id=235;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 653870*(1ns)
+memory_line_id=236;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 658930*(1ns)
+memory_line_id=237;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 663990*(1ns)
+memory_line_id=238;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 669050*(1ns)
+memory_line_id=239;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 674110*(1ns)
+memory_line_id=240;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 679170*(1ns)
+memory_line_id=241;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 684230*(1ns)
+memory_line_id=242;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 689290*(1ns)
+memory_line_id=243;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 694350*(1ns)
+memory_line_id=244;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 699410*(1ns)
+memory_line_id=245;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 704470*(1ns)
+memory_line_id=246;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 709530*(1ns)
+memory_line_id=247;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 714590*(1ns)
+memory_line_id=248;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 719650*(1ns)
+memory_line_id=249;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 724710*(1ns)
+memory_line_id=250;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 729770*(1ns)
+memory_line_id=251;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 734830*(1ns)
+memory_line_id=252;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 739890*(1ns)
+memory_line_id=253;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 744950*(1ns)
+memory_line_id=254;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 750010*(1ns)
+$stop;
+end
+endmodule
+/*
+ORIGINAL CAPTURE DUMP
+memory_line_id=0: FD 02
+memory_line_id=1: 8A 02
+memory_line_id=2: FD 02
+memory_line_id=3: FD 02
+memory_line_id=4: FD 02
+memory_line_id=5: FD 02
+memory_line_id=6: FD 02
+memory_line_id=7: FD 02
+memory_line_id=8: FD 00
+memory_line_id=9: FD 00
+memory_line_id=10: AD 00
+memory_line_id=11: 19 04
+memory_line_id=12: 03 05
+memory_line_id=13: 16 15
+memory_line_id=14: 19 10
+memory_line_id=15: 03 11
+memory_line_id=16: 16 01
+memory_line_id=17: 19 00
+memory_line_id=18: 03 01
+memory_line_id=19: 16 11
+memory_line_id=20: 19 14
+memory_line_id=21: 03 15
+memory_line_id=22: 16 05
+memory_line_id=23: 19 04
+memory_line_id=24: 03 05
+memory_line_id=25: 16 15
+memory_line_id=26: 19 14
+memory_line_id=27: 03 15
+memory_line_id=28: 16 05
+memory_line_id=29: 19 04
+memory_line_id=30: 03 05
+memory_line_id=31: 16 15
+memory_line_id=32: 19 14
+memory_line_id=33: 03 15
+memory_line_id=34: 16 25
+memory_line_id=35: 03 20
+memory_line_id=36: FD E0
+memory_line_id=37: FD E0
+memory_line_id=38: FD E0
+memory_line_id=39: FD E0
+memory_line_id=40: FD E0
+memory_line_id=41: FD E0
+memory_line_id=42: FD E0
+memory_line_id=43: FD E0
+memory_line_id=44: FD E0
+memory_line_id=45: FD E0
+memory_line_id=46: FD E0
+memory_line_id=47: FD E0
+memory_line_id=48: FD E0
+memory_line_id=49: FD E0
+memory_line_id=50: FD E0
+memory_line_id=51: FD E0
+memory_line_id=52: FD E0
+memory_line_id=53: FD E0
+memory_line_id=54: FD E0
+memory_line_id=55: FD E0
+memory_line_id=56: FD E0
+memory_line_id=57: FD E0
+memory_line_id=58: FD E0
+memory_line_id=59: 43 E0
+memory_line_id=60: FD E2
+memory_line_id=61: FD E2
+memory_line_id=62: 22 E2
+memory_line_id=63: 03 E0
+memory_line_id=64: FD 60
+memory_line_id=65: FD 60
+memory_line_id=66: FD 60
+memory_line_id=67: FD 60
+memory_line_id=68: FD 60
+memory_line_id=69: FD 60
+memory_line_id=70: FD 60
+memory_line_id=71: FD 60
+memory_line_id=72: FD 60
+memory_line_id=73: FD 60
+memory_line_id=74: FD 60
+memory_line_id=75: FD 60
+memory_line_id=76: 64 60
+memory_line_id=77: 03 61
+memory_line_id=78: 16 51
+memory_line_id=79: 03 50
+memory_line_id=80: 16 90
+memory_line_id=81: 03 91
+memory_line_id=82: 16 81
+memory_line_id=83: 03 80
+memory_line_id=84: 16 00
+memory_line_id=85: 03 01
+memory_line_id=86: 16 11
+memory_line_id=87: 19 10
+memory_line_id=88: 03 11
+memory_line_id=89: 16 01
+memory_line_id=90: 19 04
+memory_line_id=91: 03 05
+memory_line_id=92: 16 15
+memory_line_id=93: 19 10
+memory_line_id=94: 03 11
+memory_line_id=95: 16 01
+memory_line_id=96: 19 04
+memory_line_id=97: 03 05
+memory_line_id=98: 16 15
+memory_line_id=99: 03 14
+memory_line_id=100: 16 1C
+memory_line_id=101: 03 1D
+memory_line_id=102: 16 2D
+memory_line_id=103: 03 28
+memory_line_id=104: 48 E0
+memory_line_id=105: 03 E1
+memory_line_id=106: 16 D1
+memory_line_id=107: 03 D0
+memory_line_id=108: 16 90
+memory_line_id=109: 03 91
+memory_line_id=110: 16 81
+memory_line_id=111: 03 80
+memory_line_id=112: 16 00
+memory_line_id=113: 03 01
+memory_line_id=114: 16 11
+memory_line_id=115: 19 10
+memory_line_id=116: 03 11
+memory_line_id=117: 16 01
+memory_line_id=118: 19 00
+memory_line_id=119: 03 01
+memory_line_id=120: 16 11
+memory_line_id=121: 19 10
+memory_line_id=122: 03 11
+memory_line_id=123: 16 01
+memory_line_id=124: 03 04
+memory_line_id=125: 16 0C
+memory_line_id=126: 03 0D
+memory_line_id=127: 16 1D
+memory_line_id=128: 19 18
+memory_line_id=129: 03 19
+memory_line_id=130: 16 29
+memory_line_id=131: 03 28
+memory_line_id=132: 2F E0
+memory_line_id=133: 19 E4
+memory_line_id=134: 03 E5
+memory_line_id=135: 16 D5
+memory_line_id=136: 03 D0
+memory_line_id=137: 16 90
+memory_line_id=138: 03 91
+memory_line_id=139: 16 81
+memory_line_id=140: 03 84
+memory_line_id=141: 16 04
+memory_line_id=142: 03 05
+memory_line_id=143: 16 15
+memory_line_id=144: 19 14
+memory_line_id=145: 03 15
+memory_line_id=146: 16 05
+memory_line_id=147: 19 00
+memory_line_id=148: 03 01
+memory_line_id=149: 16 11
+memory_line_id=150: 19 14
+memory_line_id=151: 03 15
+memory_line_id=152: 16 05
+memory_line_id=153: 03 00
+memory_line_id=154: 16 08
+memory_line_id=155: 03 09
+memory_line_id=156: 16 19
+memory_line_id=157: 19 1C
+memory_line_id=158: 03 1D
+memory_line_id=159: 16 2D
+memory_line_id=160: 03 28
+memory_line_id=161: 89 E0
+memory_line_id=162: FD E2
+memory_line_id=163: FD E2
+memory_line_id=164: FD E2
+memory_line_id=165: FD E2
+memory_line_id=166: FD E2
+memory_line_id=167: FD E2
+memory_line_id=168: FD E2
+memory_line_id=169: FD E2
+memory_line_id=170: FD E2
+memory_line_id=171: FD E2
+memory_line_id=172: FD E2
+memory_line_id=173: FD E2
+memory_line_id=174: FD E2
+memory_line_id=175: FD E2
+memory_line_id=176: FD E2
+memory_line_id=177: FD E2
+memory_line_id=178: FD E2
+memory_line_id=179: FD E2
+memory_line_id=180: FD E2
+memory_line_id=181: FD E2
+memory_line_id=182: FD E2
+memory_line_id=183: FD E2
+memory_line_id=184: FD E2
+memory_line_id=185: FD E2
+memory_line_id=186: FD E2
+memory_line_id=187: FD E2
+memory_line_id=188: FD E2
+memory_line_id=189: FD E2
+memory_line_id=190: FD E2
+memory_line_id=191: FD E2
+memory_line_id=192: FD E2
+memory_line_id=193: FD E2
+memory_line_id=194: FD E2
+memory_line_id=195: FD E2
+memory_line_id=196: FD E2
+memory_line_id=197: FD E2
+memory_line_id=198: FD E2
+memory_line_id=199: FD E2
+memory_line_id=200: FD E2
+memory_line_id=201: FD E2
+memory_line_id=202: FD E2
+memory_line_id=203: FD E2
+memory_line_id=204: FD E2
+memory_line_id=205: FD E2
+memory_line_id=206: FD E2
+memory_line_id=207: FD E2
+memory_line_id=208: FD E2
+memory_line_id=209: FD E2
+memory_line_id=210: FD E2
+memory_line_id=211: FD E2
+memory_line_id=212: FD E2
+memory_line_id=213: FD E2
+memory_line_id=214: FD E2
+memory_line_id=215: FD E2
+memory_line_id=216: FD E2
+memory_line_id=217: FD E2
+memory_line_id=218: FD E2
+memory_line_id=219: FD E2
+memory_line_id=220: FD E2
+memory_line_id=221: FD E2
+memory_line_id=222: FD E2
+memory_line_id=223: FD E2
+memory_line_id=224: FD E2
+memory_line_id=225: FD E2
+memory_line_id=226: FD E2
+memory_line_id=227: FD E2
+memory_line_id=228: FD E2
+memory_line_id=229: FD E2
+memory_line_id=230: FD E2
+memory_line_id=231: FD E2
+memory_line_id=232: FD E2
+memory_line_id=233: FD E2
+memory_line_id=234: FD E2
+memory_line_id=235: FD E2
+memory_line_id=236: FD E2
+memory_line_id=237: FD E2
+memory_line_id=238: FD E2
+memory_line_id=239: FD E2
+memory_line_id=240: FD E2
+memory_line_id=241: FD E2
+memory_line_id=242: FD E2
+memory_line_id=243: FD E2
+memory_line_id=244: FD E2
+memory_line_id=245: FD E2
+memory_line_id=246: FD E2
+memory_line_id=247: FD E2
+memory_line_id=248: FD E2
+memory_line_id=249: FD E2
+memory_line_id=250: FD E2
+memory_line_id=251: FD E2
+memory_line_id=252: FD E2
+memory_line_id=253: FD E2
+memory_line_id=254: FD E2
+memory_line_id=255: 00 01
+*/
Index: trunk/openverifla_2.3/java/capture_spi_slave_vhdl_20180824_1736.v
===================================================================
--- trunk/openverifla_2.3/java/capture_spi_slave_vhdl_20180824_1736.v (nonexistent)
+++ trunk/openverifla_2.3/java/capture_spi_slave_vhdl_20180824_1736.v (revision 38)
@@ -0,0 +1,1322 @@
+`timescale 1ns / 10ps
+
+module capture_20180824_1736_35(clk_of_verifla, la_trigger_matched, SCK, SSEL, MOSI, MISO, bitcnt_0, byte_received, byte_data_sent_10, memory_line_id);
+
+output clk_of_verifla;
+output la_trigger_matched;
+output [64:0] memory_line_id;
+output SCK;
+output SSEL;
+output MOSI;
+output MISO;
+output bitcnt_0;
+output byte_received;
+output [1:0] byte_data_sent_10;
+reg SCK;
+reg SSEL;
+reg MOSI;
+reg MISO;
+reg bitcnt_0;
+reg byte_received;
+reg [1:0] byte_data_sent_10;
+reg [64:0] memory_line_id;
+reg la_trigger_matched;
+reg clk_of_verifla;
+
+parameter PERIOD = 20;
+initial // Clock process for clk_of_verifla
+begin
+ forever
+ begin
+ clk_of_verifla = 1'b0;
+ #(10); clk_of_verifla = 1'b1;
+ #(10);
+ end
+end
+
+initial begin
+#(10);
+la_trigger_matched = 0;
+memory_line_id=7;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 5070*(1ns)
+memory_line_id=0;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 10130*(1ns)
+memory_line_id=1;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 15190*(1ns)
+memory_line_id=2;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 20250*(1ns)
+memory_line_id=3;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 25310*(1ns)
+memory_line_id=4;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 30370*(1ns)
+memory_line_id=5;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#5060;
+// ------------- Current Time: 35430*(1ns)
+memory_line_id=6;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000010;
+#4800;
+// ------------- Current Time: 40230*(1ns)
+memory_line_id=8;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+la_trigger_matched = 1;
+#5060;
+// ------------- Current Time: 45290*(1ns)
+memory_line_id=9;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#5060;
+// ------------- Current Time: 50350*(1ns)
+memory_line_id=10;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#3640;
+// ------------- Current Time: 53990*(1ns)
+memory_line_id=11;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 54490*(1ns)
+memory_line_id=12;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 54550*(1ns)
+memory_line_id=13;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 54990*(1ns)
+memory_line_id=14;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 55490*(1ns)
+memory_line_id=15;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 55550*(1ns)
+memory_line_id=16;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 55990*(1ns)
+memory_line_id=17;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 56490*(1ns)
+memory_line_id=18;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 56550*(1ns)
+memory_line_id=19;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 56990*(1ns)
+memory_line_id=20;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 57490*(1ns)
+memory_line_id=21;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 57550*(1ns)
+memory_line_id=22;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 57990*(1ns)
+memory_line_id=23;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 58490*(1ns)
+memory_line_id=24;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 58550*(1ns)
+memory_line_id=25;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 58990*(1ns)
+memory_line_id=26;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 59490*(1ns)
+memory_line_id=27;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 59550*(1ns)
+memory_line_id=28;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 59990*(1ns)
+memory_line_id=29;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 60490*(1ns)
+memory_line_id=30;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 60550*(1ns)
+memory_line_id=31;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 60990*(1ns)
+memory_line_id=32;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 61490*(1ns)
+memory_line_id=33;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 61550*(1ns)
+memory_line_id=34;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00100101;
+#440;
+// ------------- Current Time: 61990*(1ns)
+memory_line_id=35;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00100000;
+#60;
+// ------------- Current Time: 62050*(1ns)
+memory_line_id=36;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 67110*(1ns)
+memory_line_id=37;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 72170*(1ns)
+memory_line_id=38;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 77230*(1ns)
+memory_line_id=39;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 82290*(1ns)
+memory_line_id=40;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 87350*(1ns)
+memory_line_id=41;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 92410*(1ns)
+memory_line_id=42;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 97470*(1ns)
+memory_line_id=43;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 102530*(1ns)
+memory_line_id=44;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 107590*(1ns)
+memory_line_id=45;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 112650*(1ns)
+memory_line_id=46;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 117710*(1ns)
+memory_line_id=47;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 122770*(1ns)
+memory_line_id=48;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 127830*(1ns)
+memory_line_id=49;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 132890*(1ns)
+memory_line_id=50;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 137950*(1ns)
+memory_line_id=51;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 143010*(1ns)
+memory_line_id=52;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 148070*(1ns)
+memory_line_id=53;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 153130*(1ns)
+memory_line_id=54;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 158190*(1ns)
+memory_line_id=55;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 163250*(1ns)
+memory_line_id=56;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 168310*(1ns)
+memory_line_id=57;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 173370*(1ns)
+memory_line_id=58;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 178430*(1ns)
+memory_line_id=59;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#860;
+// ------------- Current Time: 179290*(1ns)
+memory_line_id=60;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 184350*(1ns)
+memory_line_id=61;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 189410*(1ns)
+memory_line_id=62;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#580;
+// ------------- Current Time: 189990*(1ns)
+memory_line_id=63;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#60;
+// ------------- Current Time: 190050*(1ns)
+memory_line_id=64;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#5060;
+// ------------- Current Time: 195110*(1ns)
+memory_line_id=65;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100000;
+#2500;
+// ------------- Current Time: 197610*(1ns)
+memory_line_id=66;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01100001;
+#60;
+// ------------- Current Time: 197670*(1ns)
+memory_line_id=67;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01010001;
+#440;
+// ------------- Current Time: 198110*(1ns)
+memory_line_id=68;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b01010000;
+#60;
+// ------------- Current Time: 198170*(1ns)
+memory_line_id=69;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 198610*(1ns)
+memory_line_id=70;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 198670*(1ns)
+memory_line_id=71;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 199110*(1ns)
+memory_line_id=72;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000000;
+#60;
+// ------------- Current Time: 199170*(1ns)
+memory_line_id=73;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#440;
+// ------------- Current Time: 199610*(1ns)
+memory_line_id=74;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 199670*(1ns)
+memory_line_id=75;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 200110*(1ns)
+memory_line_id=76;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 200610*(1ns)
+memory_line_id=77;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 200670*(1ns)
+memory_line_id=78;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 201110*(1ns)
+memory_line_id=79;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 201610*(1ns)
+memory_line_id=80;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 201670*(1ns)
+memory_line_id=81;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 202110*(1ns)
+memory_line_id=82;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 202610*(1ns)
+memory_line_id=83;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 202670*(1ns)
+memory_line_id=84;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 203110*(1ns)
+memory_line_id=85;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#500;
+// ------------- Current Time: 203610*(1ns)
+memory_line_id=86;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 203670*(1ns)
+memory_line_id=87;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 204110*(1ns)
+memory_line_id=88;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#60;
+// ------------- Current Time: 204170*(1ns)
+memory_line_id=89;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011100;
+#440;
+// ------------- Current Time: 204610*(1ns)
+memory_line_id=90;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#60;
+// ------------- Current Time: 204670*(1ns)
+memory_line_id=91;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101101;
+#440;
+// ------------- Current Time: 205110*(1ns)
+memory_line_id=92;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 205170*(1ns)
+memory_line_id=93;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#1440;
+// ------------- Current Time: 206610*(1ns)
+memory_line_id=94;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100001;
+#60;
+// ------------- Current Time: 206670*(1ns)
+memory_line_id=95;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010001;
+#440;
+// ------------- Current Time: 207110*(1ns)
+memory_line_id=96;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010000;
+#60;
+// ------------- Current Time: 207170*(1ns)
+memory_line_id=97;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 207610*(1ns)
+memory_line_id=98;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 207670*(1ns)
+memory_line_id=99;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 208110*(1ns)
+memory_line_id=100;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000000;
+#60;
+// ------------- Current Time: 208170*(1ns)
+memory_line_id=101;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#440;
+// ------------- Current Time: 208610*(1ns)
+memory_line_id=102;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 208670*(1ns)
+memory_line_id=103;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 209110*(1ns)
+memory_line_id=104;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 209610*(1ns)
+memory_line_id=105;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 209670*(1ns)
+memory_line_id=106;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 210110*(1ns)
+memory_line_id=107;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 210610*(1ns)
+memory_line_id=108;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 210670*(1ns)
+memory_line_id=109;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 211110*(1ns)
+memory_line_id=110;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010000;
+#500;
+// ------------- Current Time: 211610*(1ns)
+memory_line_id=111;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#60;
+// ------------- Current Time: 211670*(1ns)
+memory_line_id=112;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#440;
+// ------------- Current Time: 212110*(1ns)
+memory_line_id=113;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#60;
+// ------------- Current Time: 212170*(1ns)
+memory_line_id=114;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001100;
+#440;
+// ------------- Current Time: 212610*(1ns)
+memory_line_id=115;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001101;
+#60;
+// ------------- Current Time: 212670*(1ns)
+memory_line_id=116;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#440;
+// ------------- Current Time: 213110*(1ns)
+memory_line_id=117;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011000;
+#500;
+// ------------- Current Time: 213610*(1ns)
+memory_line_id=118;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011001;
+#60;
+// ------------- Current Time: 213670*(1ns)
+memory_line_id=119;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101001;
+#440;
+// ------------- Current Time: 214110*(1ns)
+memory_line_id=120;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 214170*(1ns)
+memory_line_id=121;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#940;
+// ------------- Current Time: 215110*(1ns)
+memory_line_id=122;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100100;
+#500;
+// ------------- Current Time: 215610*(1ns)
+memory_line_id=123;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100101;
+#60;
+// ------------- Current Time: 215670*(1ns)
+memory_line_id=124;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010101;
+#440;
+// ------------- Current Time: 216110*(1ns)
+memory_line_id=125;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11010000;
+#60;
+// ------------- Current Time: 216170*(1ns)
+memory_line_id=126;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010000;
+#440;
+// ------------- Current Time: 216610*(1ns)
+memory_line_id=127;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10010001;
+#60;
+// ------------- Current Time: 216670*(1ns)
+memory_line_id=128;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000001;
+#440;
+// ------------- Current Time: 217110*(1ns)
+memory_line_id=129;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b10000100;
+#60;
+// ------------- Current Time: 217170*(1ns)
+memory_line_id=130;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000100;
+#440;
+// ------------- Current Time: 217610*(1ns)
+memory_line_id=131;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#60;
+// ------------- Current Time: 217670*(1ns)
+memory_line_id=132;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#440;
+// ------------- Current Time: 218110*(1ns)
+memory_line_id=133;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 218610*(1ns)
+memory_line_id=134;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 218670*(1ns)
+memory_line_id=135;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 219110*(1ns)
+memory_line_id=136;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#500;
+// ------------- Current Time: 219610*(1ns)
+memory_line_id=137;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000001;
+#60;
+// ------------- Current Time: 219670*(1ns)
+memory_line_id=138;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010001;
+#440;
+// ------------- Current Time: 220110*(1ns)
+memory_line_id=139;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010100;
+#500;
+// ------------- Current Time: 220610*(1ns)
+memory_line_id=140;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00010101;
+#60;
+// ------------- Current Time: 220670*(1ns)
+memory_line_id=141;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000101;
+#440;
+// ------------- Current Time: 221110*(1ns)
+memory_line_id=142;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00000000;
+#60;
+// ------------- Current Time: 221170*(1ns)
+memory_line_id=143;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001000;
+#440;
+// ------------- Current Time: 221610*(1ns)
+memory_line_id=144;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00001001;
+#60;
+// ------------- Current Time: 221670*(1ns)
+memory_line_id=145;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011001;
+#440;
+// ------------- Current Time: 222110*(1ns)
+memory_line_id=146;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011100;
+#500;
+// ------------- Current Time: 222610*(1ns)
+memory_line_id=147;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00011101;
+#60;
+// ------------- Current Time: 222670*(1ns)
+memory_line_id=148;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101101;
+#440;
+// ------------- Current Time: 223110*(1ns)
+memory_line_id=149;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b00101000;
+#60;
+// ------------- Current Time: 223170*(1ns)
+memory_line_id=150;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 228230*(1ns)
+memory_line_id=151;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 233290*(1ns)
+memory_line_id=152;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 238350*(1ns)
+memory_line_id=153;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 243410*(1ns)
+memory_line_id=154;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 248470*(1ns)
+memory_line_id=155;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 253530*(1ns)
+memory_line_id=156;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 258590*(1ns)
+memory_line_id=157;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#5060;
+// ------------- Current Time: 263650*(1ns)
+memory_line_id=158;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100000;
+#4220;
+// ------------- Current Time: 267870*(1ns)
+memory_line_id=159;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 272930*(1ns)
+memory_line_id=160;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 277990*(1ns)
+memory_line_id=161;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 283050*(1ns)
+memory_line_id=162;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 288110*(1ns)
+memory_line_id=163;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 293170*(1ns)
+memory_line_id=164;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 298230*(1ns)
+memory_line_id=165;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 303290*(1ns)
+memory_line_id=166;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 308350*(1ns)
+memory_line_id=167;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 313410*(1ns)
+memory_line_id=168;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 318470*(1ns)
+memory_line_id=169;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 323530*(1ns)
+memory_line_id=170;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 328590*(1ns)
+memory_line_id=171;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 333650*(1ns)
+memory_line_id=172;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 338710*(1ns)
+memory_line_id=173;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 343770*(1ns)
+memory_line_id=174;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 348830*(1ns)
+memory_line_id=175;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 353890*(1ns)
+memory_line_id=176;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 358950*(1ns)
+memory_line_id=177;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 364010*(1ns)
+memory_line_id=178;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 369070*(1ns)
+memory_line_id=179;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 374130*(1ns)
+memory_line_id=180;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 379190*(1ns)
+memory_line_id=181;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 384250*(1ns)
+memory_line_id=182;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 389310*(1ns)
+memory_line_id=183;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 394370*(1ns)
+memory_line_id=184;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 399430*(1ns)
+memory_line_id=185;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 404490*(1ns)
+memory_line_id=186;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 409550*(1ns)
+memory_line_id=187;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 414610*(1ns)
+memory_line_id=188;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 419670*(1ns)
+memory_line_id=189;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 424730*(1ns)
+memory_line_id=190;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 429790*(1ns)
+memory_line_id=191;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 434850*(1ns)
+memory_line_id=192;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 439910*(1ns)
+memory_line_id=193;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 444970*(1ns)
+memory_line_id=194;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 450030*(1ns)
+memory_line_id=195;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 455090*(1ns)
+memory_line_id=196;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 460150*(1ns)
+memory_line_id=197;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 465210*(1ns)
+memory_line_id=198;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 470270*(1ns)
+memory_line_id=199;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 475330*(1ns)
+memory_line_id=200;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 480390*(1ns)
+memory_line_id=201;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 485450*(1ns)
+memory_line_id=202;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 490510*(1ns)
+memory_line_id=203;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 495570*(1ns)
+memory_line_id=204;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 500630*(1ns)
+memory_line_id=205;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 505690*(1ns)
+memory_line_id=206;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 510750*(1ns)
+memory_line_id=207;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 515810*(1ns)
+memory_line_id=208;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 520870*(1ns)
+memory_line_id=209;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 525930*(1ns)
+memory_line_id=210;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 530990*(1ns)
+memory_line_id=211;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 536050*(1ns)
+memory_line_id=212;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 541110*(1ns)
+memory_line_id=213;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 546170*(1ns)
+memory_line_id=214;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 551230*(1ns)
+memory_line_id=215;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 556290*(1ns)
+memory_line_id=216;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 561350*(1ns)
+memory_line_id=217;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 566410*(1ns)
+memory_line_id=218;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 571470*(1ns)
+memory_line_id=219;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 576530*(1ns)
+memory_line_id=220;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 581590*(1ns)
+memory_line_id=221;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 586650*(1ns)
+memory_line_id=222;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 591710*(1ns)
+memory_line_id=223;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 596770*(1ns)
+memory_line_id=224;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 601830*(1ns)
+memory_line_id=225;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 606890*(1ns)
+memory_line_id=226;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 611950*(1ns)
+memory_line_id=227;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 617010*(1ns)
+memory_line_id=228;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 622070*(1ns)
+memory_line_id=229;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 627130*(1ns)
+memory_line_id=230;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 632190*(1ns)
+memory_line_id=231;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 637250*(1ns)
+memory_line_id=232;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 642310*(1ns)
+memory_line_id=233;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 647370*(1ns)
+memory_line_id=234;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 652430*(1ns)
+memory_line_id=235;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 657490*(1ns)
+memory_line_id=236;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 662550*(1ns)
+memory_line_id=237;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 667610*(1ns)
+memory_line_id=238;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 672670*(1ns)
+memory_line_id=239;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 677730*(1ns)
+memory_line_id=240;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 682790*(1ns)
+memory_line_id=241;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 687850*(1ns)
+memory_line_id=242;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 692910*(1ns)
+memory_line_id=243;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 697970*(1ns)
+memory_line_id=244;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 703030*(1ns)
+memory_line_id=245;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 708090*(1ns)
+memory_line_id=246;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 713150*(1ns)
+memory_line_id=247;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 718210*(1ns)
+memory_line_id=248;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 723270*(1ns)
+memory_line_id=249;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 728330*(1ns)
+memory_line_id=250;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 733390*(1ns)
+memory_line_id=251;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 738450*(1ns)
+memory_line_id=252;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 743510*(1ns)
+memory_line_id=253;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 748570*(1ns)
+memory_line_id=254;
+{byte_data_sent_10,byte_received,bitcnt_0,MISO,MOSI,SSEL,SCK} = 8'b11100010;
+#5060;
+// ------------- Current Time: 753630*(1ns)
+$stop;
+end
+endmodule
+/*
+ORIGINAL CAPTURE DUMP
+memory_line_id=0: FD 02
+memory_line_id=1: FD 02
+memory_line_id=2: FD 02
+memory_line_id=3: FD 02
+memory_line_id=4: FD 02
+memory_line_id=5: FD 02
+memory_line_id=6: F0 02
+memory_line_id=7: FD 02
+memory_line_id=8: FD 00
+memory_line_id=9: FD 00
+memory_line_id=10: B6 00
+memory_line_id=11: 19 04
+memory_line_id=12: 03 05
+memory_line_id=13: 16 15
+memory_line_id=14: 19 10
+memory_line_id=15: 03 11
+memory_line_id=16: 16 01
+memory_line_id=17: 19 00
+memory_line_id=18: 03 01
+memory_line_id=19: 16 11
+memory_line_id=20: 19 14
+memory_line_id=21: 03 15
+memory_line_id=22: 16 05
+memory_line_id=23: 19 04
+memory_line_id=24: 03 05
+memory_line_id=25: 16 15
+memory_line_id=26: 19 14
+memory_line_id=27: 03 15
+memory_line_id=28: 16 05
+memory_line_id=29: 19 04
+memory_line_id=30: 03 05
+memory_line_id=31: 16 15
+memory_line_id=32: 19 14
+memory_line_id=33: 03 15
+memory_line_id=34: 16 25
+memory_line_id=35: 03 20
+memory_line_id=36: FD E0
+memory_line_id=37: FD E0
+memory_line_id=38: FD E0
+memory_line_id=39: FD E0
+memory_line_id=40: FD E0
+memory_line_id=41: FD E0
+memory_line_id=42: FD E0
+memory_line_id=43: FD E0
+memory_line_id=44: FD E0
+memory_line_id=45: FD E0
+memory_line_id=46: FD E0
+memory_line_id=47: FD E0
+memory_line_id=48: FD E0
+memory_line_id=49: FD E0
+memory_line_id=50: FD E0
+memory_line_id=51: FD E0
+memory_line_id=52: FD E0
+memory_line_id=53: FD E0
+memory_line_id=54: FD E0
+memory_line_id=55: FD E0
+memory_line_id=56: FD E0
+memory_line_id=57: FD E0
+memory_line_id=58: FD E0
+memory_line_id=59: 2B E0
+memory_line_id=60: FD E2
+memory_line_id=61: FD E2
+memory_line_id=62: 1D E2
+memory_line_id=63: 03 E0
+memory_line_id=64: FD 60
+memory_line_id=65: 7D 60
+memory_line_id=66: 03 61
+memory_line_id=67: 16 51
+memory_line_id=68: 03 50
+memory_line_id=69: 16 90
+memory_line_id=70: 03 91
+memory_line_id=71: 16 81
+memory_line_id=72: 03 80
+memory_line_id=73: 16 00
+memory_line_id=74: 03 01
+memory_line_id=75: 16 11
+memory_line_id=76: 19 10
+memory_line_id=77: 03 11
+memory_line_id=78: 16 01
+memory_line_id=79: 19 04
+memory_line_id=80: 03 05
+memory_line_id=81: 16 15
+memory_line_id=82: 19 10
+memory_line_id=83: 03 11
+memory_line_id=84: 16 01
+memory_line_id=85: 19 04
+memory_line_id=86: 03 05
+memory_line_id=87: 16 15
+memory_line_id=88: 03 14
+memory_line_id=89: 16 1C
+memory_line_id=90: 03 1D
+memory_line_id=91: 16 2D
+memory_line_id=92: 03 28
+memory_line_id=93: 48 E0
+memory_line_id=94: 03 E1
+memory_line_id=95: 16 D1
+memory_line_id=96: 03 D0
+memory_line_id=97: 16 90
+memory_line_id=98: 03 91
+memory_line_id=99: 16 81
+memory_line_id=100: 03 80
+memory_line_id=101: 16 00
+memory_line_id=102: 03 01
+memory_line_id=103: 16 11
+memory_line_id=104: 19 10
+memory_line_id=105: 03 11
+memory_line_id=106: 16 01
+memory_line_id=107: 19 00
+memory_line_id=108: 03 01
+memory_line_id=109: 16 11
+memory_line_id=110: 19 10
+memory_line_id=111: 03 11
+memory_line_id=112: 16 01
+memory_line_id=113: 03 04
+memory_line_id=114: 16 0C
+memory_line_id=115: 03 0D
+memory_line_id=116: 16 1D
+memory_line_id=117: 19 18
+memory_line_id=118: 03 19
+memory_line_id=119: 16 29
+memory_line_id=120: 03 28
+memory_line_id=121: 2F E0
+memory_line_id=122: 19 E4
+memory_line_id=123: 03 E5
+memory_line_id=124: 16 D5
+memory_line_id=125: 03 D0
+memory_line_id=126: 16 90
+memory_line_id=127: 03 91
+memory_line_id=128: 16 81
+memory_line_id=129: 03 84
+memory_line_id=130: 16 04
+memory_line_id=131: 03 05
+memory_line_id=132: 16 15
+memory_line_id=133: 19 14
+memory_line_id=134: 03 15
+memory_line_id=135: 16 05
+memory_line_id=136: 19 00
+memory_line_id=137: 03 01
+memory_line_id=138: 16 11
+memory_line_id=139: 19 14
+memory_line_id=140: 03 15
+memory_line_id=141: 16 05
+memory_line_id=142: 03 00
+memory_line_id=143: 16 08
+memory_line_id=144: 03 09
+memory_line_id=145: 16 19
+memory_line_id=146: 19 1C
+memory_line_id=147: 03 1D
+memory_line_id=148: 16 2D
+memory_line_id=149: 03 28
+memory_line_id=150: FD E0
+memory_line_id=151: FD E0
+memory_line_id=152: FD E0
+memory_line_id=153: FD E0
+memory_line_id=154: FD E0
+memory_line_id=155: FD E0
+memory_line_id=156: FD E0
+memory_line_id=157: FD E0
+memory_line_id=158: D3 E0
+memory_line_id=159: FD E2
+memory_line_id=160: FD E2
+memory_line_id=161: FD E2
+memory_line_id=162: FD E2
+memory_line_id=163: FD E2
+memory_line_id=164: FD E2
+memory_line_id=165: FD E2
+memory_line_id=166: FD E2
+memory_line_id=167: FD E2
+memory_line_id=168: FD E2
+memory_line_id=169: FD E2
+memory_line_id=170: FD E2
+memory_line_id=171: FD E2
+memory_line_id=172: FD E2
+memory_line_id=173: FD E2
+memory_line_id=174: FD E2
+memory_line_id=175: FD E2
+memory_line_id=176: FD E2
+memory_line_id=177: FD E2
+memory_line_id=178: FD E2
+memory_line_id=179: FD E2
+memory_line_id=180: FD E2
+memory_line_id=181: FD E2
+memory_line_id=182: FD E2
+memory_line_id=183: FD E2
+memory_line_id=184: FD E2
+memory_line_id=185: FD E2
+memory_line_id=186: FD E2
+memory_line_id=187: FD E2
+memory_line_id=188: FD E2
+memory_line_id=189: FD E2
+memory_line_id=190: FD E2
+memory_line_id=191: FD E2
+memory_line_id=192: FD E2
+memory_line_id=193: FD E2
+memory_line_id=194: FD E2
+memory_line_id=195: FD E2
+memory_line_id=196: FD E2
+memory_line_id=197: FD E2
+memory_line_id=198: FD E2
+memory_line_id=199: FD E2
+memory_line_id=200: FD E2
+memory_line_id=201: FD E2
+memory_line_id=202: FD E2
+memory_line_id=203: FD E2
+memory_line_id=204: FD E2
+memory_line_id=205: FD E2
+memory_line_id=206: FD E2
+memory_line_id=207: FD E2
+memory_line_id=208: FD E2
+memory_line_id=209: FD E2
+memory_line_id=210: FD E2
+memory_line_id=211: FD E2
+memory_line_id=212: FD E2
+memory_line_id=213: FD E2
+memory_line_id=214: FD E2
+memory_line_id=215: FD E2
+memory_line_id=216: FD E2
+memory_line_id=217: FD E2
+memory_line_id=218: FD E2
+memory_line_id=219: FD E2
+memory_line_id=220: FD E2
+memory_line_id=221: FD E2
+memory_line_id=222: FD E2
+memory_line_id=223: FD E2
+memory_line_id=224: FD E2
+memory_line_id=225: FD E2
+memory_line_id=226: FD E2
+memory_line_id=227: FD E2
+memory_line_id=228: FD E2
+memory_line_id=229: FD E2
+memory_line_id=230: FD E2
+memory_line_id=231: FD E2
+memory_line_id=232: FD E2
+memory_line_id=233: FD E2
+memory_line_id=234: FD E2
+memory_line_id=235: FD E2
+memory_line_id=236: FD E2
+memory_line_id=237: FD E2
+memory_line_id=238: FD E2
+memory_line_id=239: FD E2
+memory_line_id=240: FD E2
+memory_line_id=241: FD E2
+memory_line_id=242: FD E2
+memory_line_id=243: FD E2
+memory_line_id=244: FD E2
+memory_line_id=245: FD E2
+memory_line_id=246: FD E2
+memory_line_id=247: FD E2
+memory_line_id=248: FD E2
+memory_line_id=249: FD E2
+memory_line_id=250: FD E2
+memory_line_id=251: FD E2
+memory_line_id=252: FD E2
+memory_line_id=253: FD E2
+memory_line_id=254: FD E2
+memory_line_id=255: 00 06
+*/
Index: trunk/openverifla_2.3/java/compile.bat
===================================================================
--- trunk/openverifla_2.3/java/compile.bat (nonexistent)
+++ trunk/openverifla_2.3/java/compile.bat (revision 38)
@@ -0,0 +1,2 @@
+set CLASSPATH=jssc.jar;.
+javac *java
Index: trunk/openverifla_2.3/java/compile.sh
===================================================================
--- trunk/openverifla_2.3/java/compile.sh (nonexistent)
+++ trunk/openverifla_2.3/java/compile.sh (revision 38)
@@ -0,0 +1,2 @@
+export CLASSPATH="jssc.jar:."
+javac *java
trunk/openverifla_2.3/java/compile.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/java/jssc.jar
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream
Index: trunk/openverifla_2.3/java/jssc.jar
===================================================================
--- trunk/openverifla_2.3/java/jssc.jar (nonexistent)
+++ trunk/openverifla_2.3/java/jssc.jar (revision 38)
trunk/openverifla_2.3/java/jssc.jar
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: trunk/openverifla_2.3/java/run.bat
===================================================================
--- trunk/openverifla_2.3/java/run.bat (nonexistent)
+++ trunk/openverifla_2.3/java/run.bat (revision 38)
@@ -0,0 +1,2 @@
+set CLASSPATH=jssc.jar;.
+java %1 %2 %3 %4 %5
Index: trunk/openverifla_2.3/java/run.sh
===================================================================
--- trunk/openverifla_2.3/java/run.sh (nonexistent)
+++ trunk/openverifla_2.3/java/run.sh (revision 38)
@@ -0,0 +1,3 @@
+export CLASSPATH="jssc.jar:."
+echo "CLASSPATH=$CLASSPATH"
+java $1 $2 $3 $4 $5
trunk/openverifla_2.3/java/run.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/java/verifla_properties_keyboard.txt
===================================================================
--- trunk/openverifla_2.3/java/verifla_properties_keyboard.txt (nonexistent)
+++ trunk/openverifla_2.3/java/verifla_properties_keyboard.txt (revision 38)
@@ -0,0 +1,46 @@
+# VeriFLA Logic Analyzer Project File
+
+# Serial port
+# On Windows this would be COM5 or similar
+#/dev/ttyUSB0
+LA.portName=/dev/ttyUSB0
+LA.baudRate=115200
+
+# Memory
+# ====
+LA.memWords=64
+# Data input width and indentical samples bits (clones) must be multiple of 8.
+LA.dataWordLenBits=16
+LA.clonesWordLenBits=16
+LA.triggerMatchMemAddr=8
+
+
+# Generated verilog
+# ====
+LA.timescaleUnit=1ns
+LA.timescalePrecision=10ps
+# clockPeriod expressed in [timescaleUnit]
+LA.clockPeriod=20
+
+# User data signals
+LA.totalSignals=16
+# Big endian (1) or Little endian (0).
+LA.signalGroups=4
+# Group 0
+LA.groupName.0=KBD_KEY
+LA.groupSize.0=8
+LA.groupEndian.0=0
+# Group 1
+LA.groupName.1=kbd_clk_line
+LA.groupSize.1=1
+LA.groupEndian.1=0
+# Group 2
+LA.groupName.2=kbd_data_line
+LA.groupSize.2=1
+LA.groupEndian.2=0
+# Group 3
+LA.groupName.3=not_used
+LA.groupSize.3=6
+LA.groupEndian.3=0
+
+
trunk/openverifla_2.3/java/verifla_properties_keyboard.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/java/verifla_properties_spi_slave.txt
===================================================================
--- trunk/openverifla_2.3/java/verifla_properties_spi_slave.txt (nonexistent)
+++ trunk/openverifla_2.3/java/verifla_properties_spi_slave.txt (revision 38)
@@ -0,0 +1,61 @@
+# VeriFLA Logic Analyzer Project File
+
+# Serial port
+# On Windows this would be COM5 or similar
+#/dev/ttyUSB0
+LA.portName=/dev/ttyUSB0
+LA.baudRate=115200
+
+# Memory
+# ====
+LA.memWords=256
+# Data input width and indentical samples bits (clones) must be multiple of 8.
+LA.dataWordLenBits=8
+LA.clonesWordLenBits=8
+LA.triggerMatchMemAddr=8
+
+
+# Generated verilog
+# ====
+LA.timescaleUnit=1ns
+LA.timescalePrecision=10ps
+# clockPeriod expressed in [timescaleUnit]
+LA.clockPeriod=20
+
+
+# User data signals
+LA.totalSignals=8
+# Big endian (1) or Little endian (0).
+LA.signalGroups=7
+{byte_data_sent[1:0], byte_received, bitcnt[0], MISO, MOSI, SSEL, SCK}
+# Group 0
+LA.groupName.0=SCK
+LA.groupSize.0=1
+LA.groupEndian.0=0
+# Group 1
+LA.groupName.1=SSEL
+LA.groupSize.1=1
+LA.groupEndian.1=0
+# Group 2
+LA.groupName.2=MOSI
+LA.groupSize.2=1
+LA.groupEndian.2=0
+# Group 3
+LA.groupName.3=MISO
+LA.groupSize.3=1
+LA.groupEndian.3=0
+# Group 4
+LA.groupName.4=bitcnt_0
+LA.groupSize.4=1
+LA.groupEndian.4=0
+# Group 5
+LA.groupName.5=byte_received
+LA.groupSize.5=1
+LA.groupEndian.5=0
+# Group 6
+LA.groupName.6=byte_data_sent_10
+LA.groupSize.6=2
+LA.groupEndian.6=0
+
+
+
trunk/openverifla_2.3/java/verifla_properties_spi_slave.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/java/verifla_properties_xenomai_spi.txt
===================================================================
--- trunk/openverifla_2.3/java/verifla_properties_xenomai_spi.txt (nonexistent)
+++ trunk/openverifla_2.3/java/verifla_properties_xenomai_spi.txt (revision 38)
@@ -0,0 +1,56 @@
+# VeriFLA Logic Analyzer Project File
+
+# Serial port
+# On Windows this would be COM5 or similar
+#/dev/ttyUSB0
+LA.portName=/dev/ttyUSB0
+LA.baudRate=115200
+
+# Memory
+# ====
+LA.memWords=128
+# Data input width and indentical samples bits (clones) must be multiple of 8.
+LA.dataWordLenBits=8
+LA.clonesWordLenBits=8
+LA.triggerMatchMemAddr=8
+
+
+# Generated verilog
+# ====
+LA.timescaleUnit=1ns
+LA.timescalePrecision=10ps
+# clockPeriod expressed in [timescaleUnit]
+LA.clockPeriod=20
+
+# User data signals
+LA.totalSignals=8
+# Big endian (1) or Little endian (0).
+LA.signalGroups=7
+# Group 0
+LA.groupName.0=MISO
+LA.groupSize.0=1
+LA.groupEndian.0=0
+# Group 1
+LA.groupName.1=MOSI
+LA.groupSize.1=1
+LA.groupEndian.1=0
+# Group 2
+LA.groupName.2=SSEL
+LA.groupSize.2=1
+LA.groupEndian.2=0
+# Group 3
+LA.groupName.3=SCK
+LA.groupSize.3=1
+LA.groupEndian.3=0
+# Group 4
+LA.groupName.4=interrupt_ack
+LA.groupSize.4=1
+LA.groupEndian.4=0
+# Group 5
+LA.groupName.5=spi_output_valid_sing
+LA.groupSize.5=1
+LA.groupEndian.5=0
+# Group 6
+LA.groupName.6=int_spi_latency_cnt_9_8
+LA.groupSize.6=2
+LA.groupEndian.6=0
trunk/openverifla_2.3/java/verifla_properties_xenomai_spi.txt
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.ucf
===================================================================
--- trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.ucf (nonexistent)
+++ trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.ucf (revision 38)
@@ -0,0 +1,28 @@
+#NET "switch[0]" LOC="L13";
+#NET "switch[1]" LOC="L14";
+#NET "switch[2]" LOC="H18";
+#NET "switch[3]" LOC="N17";
+
+NET "clk" LOC = "C9";
+NET "reset" LOC = "L13";
+
+NET "kbd_data_line" LOC = "G13";
+NET "kbd_clk" LOC = "G14";
+
+#NET "J1_0" LOC = "N15";
+#NET "J1_1" LOC = "N14";
+#NET "J1_2" LOC = "E15";
+#NET "J1_3" LOC = "V7";
+
+#leds
+NET "kbd_key[0]" LOC="D4";
+NET "kbd_key[1]" LOC="C3";
+NET "kbd_key[2]" LOC="D6";
+NET "kbd_key[3]" LOC="E6";
+NET "kbd_key[4]" LOC="D13";
+NET "kbd_key[5]" LOC="A7";
+NET "kbd_key[6]" LOC="G9";
+NET "kbd_key[7]" LOC="A8";
+
+NET "uart_REC_dataH" LOC = "R13";
+NET "uart_XMIT_dataH" LOC = "P13";
trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.v
===================================================================
--- trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.v (revision 38)
@@ -0,0 +1,81 @@
+module keyboard(kbd_data_line, kbd_clk, kbd_key,
+ clk, reset,
+ //top_of_verifla transceiver
+ uart_XMIT_dataH, uart_REC_dataH
+);
+
+
+input clk, reset;
+//top_of_verifla transceiver
+input uart_REC_dataH;
+output uart_XMIT_dataH;
+
+// App. specific
+input kbd_data_line, kbd_clk;
+output [7:0] kbd_key; // register for storing keyboard data
+
+reg [7:0] kbd_key;
+reg [3:0] i; // initial value needs to be not equal to 0 through 7. set initial to 10.
+
+wire negedge_kbd_clk;
+
+
+// This is the keyboard driver logic (fsm).
+always @ (posedge clk or posedge reset)
+begin
+ if(reset)
+ begin
+ i=10;
+ kbd_key=8'h0; //{8'b00010010};//8'h0;
+ end
+ else begin
+ if(negedge_kbd_clk)
+ begin
+ if ((i >= 0) && (i <= 7))
+ // If i is pointing to a bit of data let us keep it.
+ begin
+ kbd_key = {kbd_data_line, kbd_key[7:1]};
+ i = i + 1;
+ end
+ else if ((i == 8) || (i == 9))
+ // Otherwise if i is pointing to the parity bit or the stop bit let us ignore it.
+ begin
+ i = i + 1;
+ end
+ else // Else we have a start bit
+ begin
+ i = 0;
+ end
+ end
+ end
+end
+
+
+reg [2:0] kbd_clk_buf=3'b000;
+always @ (posedge clk) kbd_clk_buf={kbd_clk_buf[1:0], kbd_clk};
+assign negedge_kbd_clk = kbd_clk_buf[2:1]==2'b10;
+
+
+// Simple counter
+reg [5:0] cnt=0;
+always @(posedge clk or posedge reset)
+begin
+ if(reset)
+ cnt = 0;
+ else
+ if(negedge_kbd_clk)
+ cnt = cnt+1;
+end
+
+// VeriFLA
+top_of_verifla verifla (.clk(clk), .rst_l(!reset), .sys_run(1'b1),
+ .data_in({cnt, kbd_data_line, kbd_clk, kbd_key}),
+ //{6'b0, kbd_data_line, kbd_clk, kbd_key},
+ // Transceiver
+ .uart_XMIT_dataH(uart_XMIT_dataH), .uart_REC_dataH(uart_REC_dataH));
+
+endmodule
+
+// Local Variables:
+// verilog-library-directories:(".", "../verifla")
+// End:
trunk/openverifla_2.3/verilog/keyboard-driver/keyboard.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/keyboard-driver/keyboard_driver_test.v
===================================================================
--- trunk/openverifla_2.3/verilog/keyboard-driver/keyboard_driver_test.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/keyboard-driver/keyboard_driver_test.v (revision 38)
@@ -0,0 +1,90 @@
+`timescale 1ns / 1ps
+module keyboard_driver_test(kbd_key);
+
+`include "../verifla/common_internal_verifla.v"
+
+// This test module is wrote
+// in the following scenario: the driver is on the FPGA and the keyboard
+// is attached to the FPGA development board
+
+// Declaration
+output [7:0] kbd_key;
+wire [7:0] kbd_key;
+// This signals must explicitly added to the simulation.
+// For debugging purposes, also add the register named "i" from the keyboard driver
+reg reset, clk;
+reg kbd_clk, kbd_data_line;
+wire uart_XMIT_dataH;
+reg uart_REC_dataH=1;
+
+reg [64:0] i;
+
+keyboard kd (kbd_data_line, kbd_clk, kbd_key,
+ clk, reset,
+ //top_of_verifla transceiver
+ uart_XMIT_dataH, uart_REC_dataH
+);
+
+always begin
+ clk = 0;
+ #5;
+ clk = 1;
+ #5;
+end
+
+// Reset the driver by using the reset button of the FPGA board.
+initial begin
+ $dumpfile("kbd.vcd");
+ $dumpvars;
+ reset = 0;
+ #10;
+ reset = 1;
+ #10;
+ reset = 0;
+end
+
+// Now, simulate the keyboard.
+// Consider the keyboard clock period to be about 10 units.
+initial begin
+ // At the begining, the line is idle for some periods.
+ kbd_clk=1; kbd_data_line=1; #2050; #2050;
+
+ // When a key is pressed, the keyboard sends its scan code
+ // on the data line. For the 'a' key, the scan code is 1Ch=00011100b.
+ // The order is LSb first, so the bits are sent in the following order: 00111000.
+ // Simulate pressing the 'a' key.
+ // Send start bit.
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ // Send the scan code
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ kbd_clk=1; #250; kbd_data_line=0; #250; kbd_clk=0; #500;
+ // Send the parity bit which is '1' for the 'a' key.
+ kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500;
+ // Send the stop bit.
+ kbd_clk=1; #250; kbd_data_line=1; #250; kbd_clk=0; #500;
+ // Put the line idle for two periods.
+ kbd_clk=1; kbd_data_line=1; #2050; #2050;
+ #1000;
+ // When the 'a' key - that is now pressed,
+ // will be released, then the keyboard will send F0h, 1Ch.
+ // We do not simulate this because the process is similar.
+
+`ifdef DEBUG_LA
+ //$display("value: %b", {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, {LA_DATA_INPUT_WORDLEN_BITS{1'b0}}});
+ for(i = 0; i <= LA_MEM_LAST_ADDR; i = i + 1) begin
+ //$display("i=%d m2[i]=%d m1[i]=%b", i, kd.verifla.mi.m2[i], kd.verifla.mi.m1[i]);
+ $display("%d %h %h %h %h", i, kd.verifla.mi.mem[i][31:24], kd.verifla.mi.mem[i][22:16],
+ kd.verifla.mi.mem[i][15:8], kd.verifla.mi.mem[i][7:0]);
+ end
+ //$display("m[%d]=%d", LA_MEM_LAST_ADDR, kd.verifla.mi.mem[LA_MEM_LAST_ADDR]);
+`endif
+ $stop;
+end
+
+endmodule
trunk/openverifla_2.3/verilog/keyboard-driver/keyboard_driver_test.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/baud_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/baud_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/baud_of_verifla.v (revision 38)
@@ -0,0 +1,45 @@
+
+module baud_of_verifla(
+ sys_clk,
+ sys_rst_l,
+ baud_clk_posedge
+ );
+
+
+`include "inc_of_verifla.v"
+
+
+input sys_clk;
+input sys_rst_l;
+output baud_clk_posedge;
+reg baud_clk;
+reg baud_clk_posedge;
+
+reg [BAUD_COUNTER_SIZE-1:0] counter=0; //{BAUD_COUNTER_SIZE{1'b0}};
+
+always @(posedge sys_clk or negedge sys_rst_l)
+begin
+ if(~sys_rst_l) begin
+ baud_clk <= 0;
+ baud_clk_posedge <= 0;
+ counter <= 0;
+ end else if (counter < T2_div_T1_div_2) begin
+ counter <= counter + 1;
+ baud_clk <= baud_clk;
+ baud_clk_posedge <= 0;
+ end else begin
+ if(~baud_clk) // baud_clk will become 1
+ baud_clk_posedge <= 1;
+ counter <= 0;
+ baud_clk <= ~baud_clk;
+ end
+end
+
+/*
+reg [2:0] baud_vec=3'b000;
+always @(posedge clk) baud_vec = {baud_vec[1:0], baud_clk};
+wire baud_clk_posedge=(baud_vec[2:1]=2'b01;
+wire baud_clk_negedge=(baud_vec[2:1]=2'b10;
+*/
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/baud_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/common_internal_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/common_internal_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/common_internal_verifla.v (revision 38)
@@ -0,0 +1,38 @@
+
+// Data input width and indentical samples bits must be multiple of 8.
+parameter LA_DATA_INPUT_WORDLEN_BITS=16;
+
+// Trigger
+parameter LA_TRIGGER_VALUE={LA_DATA_INPUT_WORDLEN_BITS{1'b0}},
+ LA_TRIGGER_MASK={{(LA_DATA_INPUT_WORDLEN_BITS - 10){1'b0}}, 2'b11, 8'h00},
+ LA_TRACE_MASK={LA_DATA_INPUT_WORDLEN_BITS{1'b1}};
+
+parameter LA_MEM_CLEAN_BEFORE_RUN=0;
+parameter LA_IDENTICAL_SAMPLES_BITS=16;
+parameter LA_MEM_WORDLEN_BITS=(LA_DATA_INPUT_WORDLEN_BITS+LA_IDENTICAL_SAMPLES_BITS);
+parameter LA_MEM_WORDLEN_OCTETS=((LA_MEM_WORDLEN_BITS+7)/8);
+parameter LA_MEM_ADDRESS_BITS=6;
+parameter LA_MEM_FIRST_ADDR=0,
+ LA_MEM_LAST_ADDR=((1<> 3),
+ LA_MEM_LAST_ADDR_BEFORE_TRIGGER=(LA_TRIGGER_MATCH_MEM_ADDR-1);
+parameter LA_MAX_SAMPLES_AFTER_TRIGGER_BITS=26,
+ LA_MAX_SAMPLES_AFTER_TRIGGER={1'b0, {(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1){1'b1}}};
+
+// Identical samples
+parameter LA_MAX_IDENTICAL_SAMPLES=((1 << LA_IDENTICAL_SAMPLES_BITS) - 2); //{LA_IDENTICAL_SAMPLES_BITS{1'b1}};
+
+/*
+Reserved mem words:
+ LA_MEM_EMPTY_SLOT which represents an empty and not used memory slot.
+It has sense if LA_MEM_CLEAN_BEFORE_RUN and
+ a) when the trigger event arrives before the filling of the full btqueue.
+ b) after the trigger event and after capturing LA_MAX_SAMPLES_AFTER_TRIGGER
+*/
+//`define LA_INIT_MEM_AT_RESET
+parameter LA_MEM_EMPTY_SLOT={LA_MEM_WORDLEN_BITS{1'b0}};
+
+//`define DEBUG_LA
trunk/openverifla_2.3/verilog/verifla/common_internal_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/computer_input_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/computer_input_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/computer_input_of_verifla.v (revision 38)
@@ -0,0 +1,90 @@
+/*
+file: computer_input_of_verifla.v
+license: GNU GPL
+
+Revision history
+- 20180827-1700
+allow only USERCMD_RUN.
+revision date: 2007/Sep/03; author: Laurentiu DUCA
+- USERCMD_RESET
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+module computer_input_of_verifla (clk, rst_l,
+ rec_dataH, rec_readyH, user_run);
+// user commands
+parameter USERCMD_RUN = 8'h01;
+// CI_states
+parameter CI_STATES_BITS=4,
+ CI_STATE_IDLE=0,
+ CI_STATE_START_OF_NEW_CMD=1;
+
+// input
+input clk, rst_l;
+input rec_readyH;
+input [7:0] rec_dataH;
+// output
+output user_run;
+reg user_run;
+// locals
+reg [CI_STATES_BITS-1:0] ci_state, next_ci_state;
+reg [7:0] ci_indata, next_ci_indata;
+wire ci_new_octet_received;
+
+// T(clk)<
trunk/openverifla_2.3/verilog/verifla/computer_input_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/inc_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/inc_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/inc_of_verifla.v (revision 38)
@@ -0,0 +1,17 @@
+parameter CLOCK_FREQUENCY = 50000000;
+// If CLOCK_FREQUENCY < 50 MHz then BAUDRATE must be < 115200 bps (for example 9600).
+parameter BAUDRATE = 115200;
+
+parameter T2_div_T1_div_2 = CLOCK_FREQUENCY / (BAUDRATE * 16 * 2);
+// Assert: BAUD_COUNTER_SIZE >= log2(T2_div_T1_div_2) bits
+parameter BAUD_COUNTER_SIZE = 15;
+//`define DEBUG
+/*
+1s ... 50000000 T1
+1bit ... 16 T2
+1s .. 115200 bits
+=>
+1s .. 115200 * 16 T2
+
+T2 = 5000000 T1 / (115200 * 16) = T1 * 50000000 / (115200 * 16)
+*/
trunk/openverifla_2.3/verilog/verifla/inc_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/memory_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/memory_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/memory_of_verifla.v (revision 38)
@@ -0,0 +1,69 @@
+/*
+20180814-1600
+- LA_MEM_CLEAN_BEFORE_RUN is not used here anymore;
+LA_INIT_MEM_AT_RESET is used instead.
+20180808-1700
+- ifdef LA_MEM_CLEAN_BEFORE_RUN
+Author: Laurentiu Duca
+License: GNU GPL
+*/
+
+module memory_of_verifla (
+ clk, rst_l, //clkb,
+ addra, wea, dina, addrb, doutb
+);
+
+`include "common_internal_verifla.v"
+
+input rst_l;
+input clk;
+//input clkb;
+input wea;
+input [LA_MEM_ADDRESS_BITS-1:0] addra;
+input [LA_MEM_ADDRESS_BITS-1:0] addrb;
+output [LA_MEM_WORDLEN_BITS-1:0] doutb;
+input [LA_MEM_WORDLEN_BITS-1:0] dina;
+
+reg [LA_MEM_WORDLEN_BITS-1:0] mem[LA_MEM_LAST_ADDR:0];
+
+//assign doutb = mem[addrb];
+// This works too as a consequence of send_capture_of_verifla architecture.
+reg [LA_MEM_WORDLEN_BITS-1:0] doutb;
+always @(posedge clk or negedge rst_l)
+if(~rst_l)
+ doutb <= LA_MEM_EMPTY_SLOT;
+else
+ doutb <= mem[addrb];
+
+`ifndef LA_INIT_MEM_AT_RESET
+always @(posedge clk)
+begin
+ if(wea) begin
+ mem[addra] <= dina;
+ end
+end
+`else
+//reg [LA_MEM_WORDLEN_BITS-1:0] i;
+always @(posedge clk or negedge rst_l)
+begin
+ if(~rst_l) begin:RESET_SECTON
+ integer i;
+ for(i=0; i<=LA_MEM_LAST_ADDR; i=i+1)
+ mem[i] <= LA_MEM_EMPTY_SLOT;
+ end else begin
+ if(wea) begin
+ mem[addra] <= dina;
+ end
+ end
+end
+`endif
+
+initial begin:INIT_SECTION
+ integer i;
+ for(i=0; i<=LA_MEM_LAST_ADDR; i=i+1)
+ mem[i] <= LA_MEM_EMPTY_SLOT;
+ //$readmemh("mem2018-2.mif", mem);
+end
+
+endmodule
+
trunk/openverifla_2.3/verilog/verifla/memory_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/monitor_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/monitor_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/monitor_of_verifla.v (revision 38)
@@ -0,0 +1,299 @@
+/*
+file: monitor_of_verifla.v
+license: GNU GPL
+Revision history
+20181016-1225
+- LA_TRACE_MASK
+20180827-1700
+- broke mon_run in sys_run and user_run
+- clean memory at user_run
+20180823-1435
+- mon_run_reg
+20180814-1600
+- LA_MEM_CLEAN_BEFORE_RUN is parameter now
+20180808-1700
+- ifdef LA_MEM_CLEAN_BEFORE_RUN
+revision date: 20180730-1500; Laurentiu Duca
+- redesign of mem struct
+- the bt_queue_tail_address is wrote at the end of capture.
+revision date: 2007/Sep/03; author: Laurentiu DUCA
+- the bt_queue_head_address is wrote at the end of capture.
+- zero all memory at a mon_run (if LA_MEM_CLEAN_BEFORE_RUN).
+- note that _at_ means after trigger event and _bt_ means before trigger event
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+module monitor_of_verifla (clk, rst_l,
+ sys_run, user_run, data_in,
+ mem_port_A_address, mem_port_A_data_in, mem_port_A_wen,
+ ack_sc_run, sc_done, sc_run);
+
+`include "common_internal_verifla.v"
+
+// MON_states
+parameter
+ MON_STATES_BITS=4,
+ MON_STATE_IDLE=0,
+ MON_STATE_DO_MEM_CLEAN=1,
+ MON_STATE_PREPARE_RUN=2,
+ MON_STATE_WAIT_TRIGGER_MATCH=3,
+ MON_STATE_AFTER_TRIGGER=4,
+ MON_STATE_DATA_CAPTURED=5,
+ MON_STATE_SC_RUN=6,
+ MON_STATE_WAIT_SC_DONE=7;
+
+// input
+input clk, rst_l;
+input [LA_DATA_INPUT_WORDLEN_BITS-1:0] data_in;
+input sys_run, user_run, ack_sc_run, sc_done;
+// output
+output [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address;
+output [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in;
+output mem_port_A_wen;
+output sc_run;
+reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address;
+reg [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in;
+reg mem_port_A_wen;
+reg sys_run_reg, sc_run, next_sc_run;
+
+// local
+reg [MON_STATES_BITS-1:0] mon_state, next_mon_state;
+reg [LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1:0]
+ next_mon_samples_after_trigger, mon_samples_after_trigger;
+reg [LA_MEM_ADDRESS_BITS-1:0] next_mon_write_address, mon_write_address;
+reg [LA_MEM_ADDRESS_BITS-1:0] next_bt_queue_tail_address, bt_queue_tail_address;
+reg [LA_DATA_INPUT_WORDLEN_BITS-1:0] mon_old_data_in,
+ mon_current_data_in; //={LA_DATA_INPUT_WORDLEN_BITS{1'b0}};
+reg [LA_IDENTICAL_SAMPLES_BITS-1:0] mon_clones_nr, next_mon_clones_nr;
+
+
+// Register the input data
+// such that mon_current_data_in is constant the full clock period.
+always @(posedge clk or negedge rst_l)
+begin
+ if(~rst_l)
+ begin
+ mon_old_data_in <= 0;
+ mon_current_data_in <= 0;
+ sys_run_reg <= 0;
+ end
+ else begin
+ mon_old_data_in <= mon_current_data_in;
+ mon_current_data_in <= data_in;
+ sys_run_reg <= sys_run;
+ end
+end
+
+// set new values
+always @(posedge clk or negedge rst_l)
+begin
+ if(~rst_l)
+ begin
+ mon_state <= MON_STATE_IDLE;
+ sc_run <= 0;
+ mon_write_address <= LA_MEM_FIRST_ADDR;
+ bt_queue_tail_address <= 0;
+ mon_samples_after_trigger <= 0;
+ mon_clones_nr <= 1;
+ end
+ else begin
+ mon_state <= next_mon_state;
+ sc_run <= next_sc_run;
+ mon_write_address <= next_mon_write_address;
+ bt_queue_tail_address <= next_bt_queue_tail_address;
+ mon_samples_after_trigger <= next_mon_samples_after_trigger;
+ mon_clones_nr <= next_mon_clones_nr;
+ end
+end
+
+
+// continuous assignments
+wire [LA_MEM_ADDRESS_BITS-1:0] one_plus_mon_write_address = (mon_write_address+1);
+wire [LA_IDENTICAL_SAMPLES_BITS-1:0] oneplus_mon_clones_nr = (mon_clones_nr+1);
+wire data_in_changed = ((mon_current_data_in & LA_TRACE_MASK) != (mon_old_data_in & LA_TRACE_MASK));
+wire last_mem_addr_before_trigger = (mon_write_address == LA_MEM_LAST_ADDR_BEFORE_TRIGGER);
+wire not_maximum_mon_clones_nr = (mon_clones_nr < LA_MAX_IDENTICAL_SAMPLES);
+
+
+// mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
+task mon_prepare_run;
+begin
+ // we share the same clock as memory.
+ mem_port_A_address=LA_MEM_FIRST_ADDR;
+ mem_port_A_data_in={{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
+ mem_port_A_wen=1;
+ next_mon_write_address=LA_MEM_FIRST_ADDR;
+ next_mon_clones_nr=2;
+ next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH;
+end
+endtask
+
+
+// state machine
+always @(*)
+/*
+ mon_state or sys_run_reg
+ or ack_sc_run or sc_done or sc_run
+ // eliminate warnings
+ or mon_write_address or bt_queue_tail_address or mon_samples_after_trigger
+ or mon_current_data_in or mon_old_data_in or mon_clones_nr
+ or data_in_changed or oneplus_mon_clones_nr or one_plus_mon_write_address
+ or not_maximum_mon_clones_nr
+ or last_mem_addr_before_trigger)
+*/
+begin
+ // implicit
+ next_mon_state=mon_state;
+ next_sc_run=sc_run;
+ next_mon_write_address=mon_write_address;
+ next_bt_queue_tail_address=bt_queue_tail_address;
+ next_mon_samples_after_trigger=mon_samples_after_trigger;
+ next_mon_clones_nr = mon_clones_nr;
+ mem_port_A_address=0;
+ mem_port_A_data_in=0;
+ mem_port_A_wen=0;
+
+ // state dependent
+ case(mon_state)
+ MON_STATE_IDLE:
+ begin
+ if(sys_run_reg || user_run)
+ begin
+ if(LA_MEM_CLEAN_BEFORE_RUN || user_run) begin
+ next_mon_write_address=LA_MEM_FIRST_ADDR;
+ next_mon_state=MON_STATE_DO_MEM_CLEAN;
+ end else
+ mon_prepare_run;
+ end
+ else
+ next_mon_state=MON_STATE_IDLE;
+ end
+
+ MON_STATE_DO_MEM_CLEAN:
+ begin
+ mem_port_A_address=mon_write_address;
+ mem_port_A_data_in=LA_MEM_EMPTY_SLOT;
+ mem_port_A_wen=1;
+ if(mon_write_address < LA_MEM_LAST_ADDR)
+ begin
+ next_mon_write_address=mon_write_address+1;
+ next_mon_state = MON_STATE_DO_MEM_CLEAN;
+ end
+ else
+ // at the new posedge clock, will clean memory at its last address
+ next_mon_state = MON_STATE_PREPARE_RUN;
+ end
+
+ MON_STATE_PREPARE_RUN:
+ begin
+ mon_prepare_run;
+ end
+
+ MON_STATE_WAIT_TRIGGER_MATCH:
+ begin
+ // circular queue
+ if((mon_current_data_in & LA_TRIGGER_MASK) !=
+ (LA_TRIGGER_VALUE & LA_TRIGGER_MASK))
+ begin
+ next_mon_state = MON_STATE_WAIT_TRIGGER_MATCH;
+ mem_port_A_wen = 1;
+ mem_port_A_address = data_in_changed ?
+ (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address) :
+ (not_maximum_mon_clones_nr ? mon_write_address :
+ (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address));
+ mem_port_A_data_in = data_in_changed ?
+ {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
+ (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} :
+ {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
+ next_mon_clones_nr = data_in_changed ? 2 :
+ (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2);
+ next_mon_write_address = data_in_changed ?
+ (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR: one_plus_mon_write_address) :
+ (not_maximum_mon_clones_nr ? mon_write_address :
+ (last_mem_addr_before_trigger ? LA_MEM_FIRST_ADDR : one_plus_mon_write_address));
+ end
+ else begin
+ // trigger matched
+ next_mon_state=MON_STATE_AFTER_TRIGGER;
+ mem_port_A_address=LA_TRIGGER_MATCH_MEM_ADDR;
+ mem_port_A_data_in = {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, mon_current_data_in};
+ mem_port_A_wen=1;
+ next_mon_write_address=LA_TRIGGER_MATCH_MEM_ADDR;
+ next_mon_clones_nr=2;
+ next_bt_queue_tail_address = mon_write_address;
+ next_mon_samples_after_trigger=1;
+ end
+ end
+
+ MON_STATE_AFTER_TRIGGER:
+ begin
+ if((mon_samples_after_trigger < LA_MAX_SAMPLES_AFTER_TRIGGER) &&
+ (mon_write_address < LA_MEM_LAST_ADDR))
+ begin
+ mem_port_A_wen = 1;
+ mem_port_A_address = data_in_changed ? one_plus_mon_write_address :
+ (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address);
+ mem_port_A_data_in = data_in_changed ? {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
+ (not_maximum_mon_clones_nr ? {mon_clones_nr, mon_current_data_in} :
+ {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
+ next_mon_clones_nr = data_in_changed ? 2 :
+ (not_maximum_mon_clones_nr ? oneplus_mon_clones_nr : 2);
+ next_mon_write_address = data_in_changed ? one_plus_mon_write_address :
+ (not_maximum_mon_clones_nr ? mon_write_address : one_plus_mon_write_address);
+ next_mon_samples_after_trigger=mon_samples_after_trigger+1;
+ next_mon_state=MON_STATE_AFTER_TRIGGER;
+ end
+ else begin
+ mem_port_A_wen=0;
+ next_mon_state=MON_STATE_DATA_CAPTURED;
+ end
+ end
+
+ MON_STATE_DATA_CAPTURED:
+ begin
+ // Save bt_queue_tail_address
+ mem_port_A_address = LA_BT_QUEUE_TAIL_ADDRESS;
+ mem_port_A_data_in =
+ {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}},
+ bt_queue_tail_address};
+ mem_port_A_wen = 1;
+ next_mon_state=MON_STATE_SC_RUN;
+ end
+
+ MON_STATE_SC_RUN:
+ begin
+ next_mon_state=MON_STATE_WAIT_SC_DONE;
+ next_sc_run=1;
+ end
+ MON_STATE_WAIT_SC_DONE:
+ begin
+ // sc_run must already be 1, when entering state MON_STATE_SEND_CAPTURE.
+ if(ack_sc_run)
+ next_sc_run=0;
+ if((sc_run == 0) && (sc_done))
+ next_mon_state=MON_STATE_IDLE;
+ else
+ next_mon_state=MON_STATE_WAIT_SC_DONE;
+ end
+
+
+ default: // should never get here
+ begin
+ next_mon_state=4'bxxxx;
+ next_sc_run=1'bx;
+ next_mon_write_address={LA_MEM_ADDRESS_BITS{1'bx}};
+ next_bt_queue_tail_address={(LA_MEM_ADDRESS_BITS){1'bx}};
+ next_mon_samples_after_trigger={LA_MAX_SAMPLES_AFTER_TRIGGER_BITS{1'bx}};
+ next_mon_clones_nr={LA_IDENTICAL_SAMPLES_BITS{1'bx}};
+ mem_port_A_address={LA_MEM_ADDRESS_BITS{1'bx}};
+ mem_port_A_data_in={LA_MEM_WORDLEN_BITS{1'bx}};
+ mem_port_A_wen=1'bx;
+ end
+ endcase
+end
+
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/monitor_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/send_capture_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/send_capture_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/send_capture_of_verifla.v (revision 38)
@@ -0,0 +1,167 @@
+/*
+file: send_capture_of_verifla.v
+license: GNU GPL
+Revision history
+revision date: 20180808-1540
+- include baud_clk_posedge
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+//`timescale 1ns/1ps
+module send_capture_of_verifla(clk, rst_l, baud_clk_posedge,
+ sc_run, ack_sc_run, sc_done,
+ mem_port_B_address, mem_port_B_dout,
+ xmit_doneH, xmitH, xmit_dataH);
+
+`include "common_internal_verifla.v"
+
+// SC_states
+parameter
+ SC_STATES_BITS=4,
+ SC_STATE_IDLE=0,
+ SC_STATE_ACK_SC_RUN=1,
+ SC_STATE_SET_MEMADDR_TO_READ_FROM=2,
+ SC_STATE_GET_MEM_OUTPUT_DATA=3,
+ SC_STATE_SEND_OCTET=4,
+ SC_STATE_WAIT_OCTET_SENT=5,
+ SC_STATE_WORD_SENT=6;
+
+// input
+input clk, rst_l;
+input baud_clk_posedge;
+input sc_run;
+input [LA_MEM_WORDLEN_BITS-1:0] mem_port_B_dout;
+input xmit_doneH;
+// output
+output [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address;
+output xmitH;
+output [7:0] xmit_dataH;
+output ack_sc_run, sc_done;
+reg [LA_MEM_ADDRESS_BITS-1:0] mem_port_B_address;
+reg xmitH;
+reg [7:0] xmit_dataH;
+reg ack_sc_run, sc_done;
+// local
+reg [SC_STATES_BITS-1:0] sc_state, next_sc_state;
+reg [LA_MEM_ADDRESS_BITS-1:0] sc_current_address, next_sc_current_address;
+reg [LA_MEM_WORDLEN_OCTETS-1:0] sc_octet_id, next_sc_octet_id;
+reg [LA_MEM_WORDLEN_BITS-1:0] sc_word_bits, next_sc_word_bits;
+
+// set up next value
+always @(posedge clk or negedge rst_l)
+begin
+ if(~rst_l)
+ begin
+ sc_state=SC_STATE_IDLE;
+ sc_current_address=0;
+ sc_word_bits=0;
+ sc_octet_id=0;
+ end
+ else
+ if (baud_clk_posedge)
+ begin
+ sc_state=next_sc_state;
+ sc_current_address=next_sc_current_address;
+ sc_word_bits=next_sc_word_bits;
+ sc_octet_id=next_sc_octet_id;
+ end
+end
+
+// state machine
+always @(sc_state or sc_run or xmit_doneH
+ // not important but xilinx warnings.
+ or sc_current_address or mem_port_B_dout or sc_word_bits or sc_octet_id)
+begin
+ // implicitly
+ next_sc_state=sc_state;
+ ack_sc_run=0;
+ sc_done=0;
+ xmit_dataH=0;
+ xmitH=0;
+ mem_port_B_address=sc_current_address;
+ next_sc_current_address=sc_current_address;
+ next_sc_word_bits=sc_word_bits;
+ next_sc_octet_id=sc_octet_id;
+
+ // state dependent
+ case(sc_state)
+ SC_STATE_IDLE:
+ begin
+ if(sc_run)
+ begin
+ next_sc_state = SC_STATE_ACK_SC_RUN;
+ next_sc_current_address=LA_MEM_LAST_ADDR;
+ end
+ else
+ next_sc_state = SC_STATE_IDLE;
+ end
+ SC_STATE_ACK_SC_RUN:
+ begin
+ ack_sc_run=1;
+ next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM;
+ end
+ SC_STATE_SET_MEMADDR_TO_READ_FROM:
+ begin
+ mem_port_B_address=sc_current_address;
+ // next clock cycle we have memory dout of our read.
+ next_sc_state = SC_STATE_GET_MEM_OUTPUT_DATA;
+ end
+ SC_STATE_GET_MEM_OUTPUT_DATA:
+ begin
+ next_sc_word_bits=mem_port_B_dout;
+ // LSB first
+ next_sc_octet_id=0;
+ next_sc_state = SC_STATE_SEND_OCTET;
+ end
+ SC_STATE_SEND_OCTET:
+ begin
+ xmit_dataH=sc_word_bits[7:0];
+ next_sc_word_bits={8'd0, sc_word_bits[LA_MEM_WORDLEN_BITS-1:8]}; //sc_word_bits>>8;
+ xmitH=1;
+ next_sc_octet_id=sc_octet_id+1;
+ next_sc_state = SC_STATE_WAIT_OCTET_SENT;
+ end
+ SC_STATE_WAIT_OCTET_SENT:
+ begin
+ if(xmit_doneH)
+ begin
+ if(sc_octet_id < LA_MEM_WORDLEN_OCTETS)
+ next_sc_state = SC_STATE_SEND_OCTET;
+ else
+ next_sc_state = SC_STATE_WORD_SENT;
+ end
+ else
+ next_sc_state = SC_STATE_WAIT_OCTET_SENT;
+ end
+ SC_STATE_WORD_SENT:
+ begin
+ if(sc_current_address > LA_MEM_FIRST_ADDR)
+ begin
+ next_sc_current_address=sc_current_address-1;
+ next_sc_state = SC_STATE_SET_MEMADDR_TO_READ_FROM;
+ end
+ else
+ begin
+ // done sending all captured data
+ sc_done = 1;
+ next_sc_state = SC_STATE_IDLE;
+ end
+ end
+ default: // should never get here
+ begin
+ next_sc_state=4'bxxxx;
+ sc_done=1'bx;
+ xmit_dataH=1'bx;
+ xmitH=1'bx;
+ mem_port_B_address={LA_MEM_ADDRESS_BITS{1'bx}};
+ next_sc_current_address={LA_MEM_ADDRESS_BITS{1'bx}};
+ next_sc_word_bits={LA_MEM_WORDLEN_BITS{1'bx}};
+ next_sc_octet_id={LA_MEM_WORDLEN_OCTETS{1'bx}};
+ end
+ endcase
+end
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/send_capture_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/single_pulse_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/single_pulse_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/single_pulse_of_verifla.v (revision 38)
@@ -0,0 +1,83 @@
+// Update: 20180814_1555, author: Laurentiu Duca
+// User readable form.
+// Create Date: 16:17:26 02/23/2007
+// Additional Comments: single pulse from a multi-periods-contiguos pulse
+// Author: Laurentiu Duca
+// License: GNU GPL
+
+`timescale 1ns / 1ps
+
+module single_pulse_of_verifla(clk, rst_l, ub, ubsing);
+input clk, rst_l;
+input ub;
+output ubsing;
+
+
+reg next_state, state;
+reg ubsing_reg, next_ubsing_reg;
+
+assign ubsing = ubsing_reg;
+
+always @(posedge clk or negedge rst_l)
+begin
+ if (~rst_l) begin
+ state <= 0;
+ ubsing_reg <= 0;
+ end else begin
+ state <= next_state;
+ ubsing_reg <= next_ubsing_reg;
+ end
+end
+
+always @(*)
+begin
+ next_state <= state;
+ next_ubsing_reg <= 0;
+ case (state)
+ 0: if (ub == 1) begin
+ next_state <= 1;
+ next_ubsing_reg <= 1;
+ end
+ 1: if (ub == 0)
+ next_state <= 0;
+ endcase
+end
+
+
+/*
+Truth table
+====
+before (posedge clk) | after (posedge clk)
+ub / state(q1q0) | state(q1q0) / ubsing
+0 / 00 | 00 / 0
+1 / 00 | 01 / 1
+x / 01 | 10 / 0
+0 / 10 | 00 / 0
+1 / 10 | 10 / 0
+
+Notes:
+- works only if the (posedge ub) comes 2 clk periods after the prevoius (negedge ub).
+- after rst_l, ub can be either 0 or 1.
+*/
+
+/*
+reg [1:0] q;
+assign ubsing = q[0];
+
+always @ (posedge clk or negedge rst_l)
+begin
+
+if(~rst_l)
+begin
+ q[0] <= 0;
+ q[1] <= 0;
+end
+else
+begin
+ q[0] <= ~q[0] && ub && ~q[1];
+ q[1] <= q[0] || (~q[0] && ub && q[1]);
+end
+end
+*/
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/single_pulse_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/top_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/top_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/top_of_verifla.v (revision 38)
@@ -0,0 +1,69 @@
+/*
+file: top_of_verifla.v
+license: GNU GPL
+Revision history
+revision date: 2007/Sep/03; author: Laurentiu DUCA
+- sys_run: an internal possible run command
+- combined_reset_low which allows the user to reset the monitor
+
+revision date: 2007/Jul/4; author: Laurentiu DUCA
+- v01
+*/
+
+
+module top_of_verifla(clk, rst_l, sys_run, data_in,
+ // Transceiver
+ uart_XMIT_dataH, uart_REC_dataH
+ );
+
+`include "common_internal_verifla.v"
+
+input clk, rst_l, sys_run;
+input [LA_DATA_INPUT_WORDLEN_BITS-1:0] data_in;
+output uart_XMIT_dataH;
+input uart_REC_dataH;
+
+// App. specific.
+wire [LA_MEM_WORDLEN_BITS-1:0] mem_port_A_data_in, mem_port_B_dout;
+wire [LA_MEM_ADDRESS_BITS-1:0] mem_port_A_address, mem_port_B_address;
+wire mem_port_A_wen;
+wire user_run;
+wire sc_run, ack_sc_run, sc_done;
+
+// Transceiver
+wire [7:0] xmit_dataH;
+wire xmit_doneH;
+wire xmitH;
+// Receiver
+wire [7:0] rec_dataH;
+wire rec_readyH;
+// Baud
+wire baud_clk_posedge;
+
+uart_of_verifla iUART (clk, rst_l, baud_clk_posedge,
+ // Transmitter
+ uart_XMIT_dataH, xmitH, xmit_dataH, xmit_doneH,
+ // Receiver
+ uart_REC_dataH, rec_dataH, rec_readyH);
+
+memory_of_verifla mi (
+ .addra(mem_port_A_address), .addrb(mem_port_B_address),
+ .clk(clk), .rst_l(rst_l),
+ .dina(mem_port_A_data_in), .doutb(mem_port_B_dout),
+ .wea(mem_port_A_wen));
+
+computer_input_of_verifla ci (clk, rst_l,
+ rec_dataH, rec_readyH, user_run);
+
+monitor_of_verifla mon (clk, rst_l,
+ sys_run, user_run, data_in,
+ mem_port_A_address, mem_port_A_data_in, mem_port_A_wen,
+ ack_sc_run, sc_done, sc_run);
+// send_capture_of_verifla must use the same reset as the uart.
+send_capture_of_verifla sc (clk, rst_l, baud_clk_posedge,
+ sc_run, ack_sc_run, sc_done,
+ mem_port_B_address, mem_port_B_dout,
+ xmit_doneH, xmitH, xmit_dataH);
+
+endmodule
+
trunk/openverifla_2.3/verilog/verifla/top_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/u_rec_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/u_rec_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/u_rec_of_verifla.v (revision 38)
@@ -0,0 +1,169 @@
+
+/*
+Update: Laurentiu Duca, 20180808_1200:
+ - consider baud_clk_posedge
+Update: Laurentiu Duca, 20180724_1550:
+ - removed "rdy_o <= 1'b0;" from idle state
+ and moved to STA_CHECK_START_BIT.
+ - sample in the middle of the data bit
+ - correct init values and sizes
+*/
+
+/////////////////////////////////////////////////////////////////////
+//// Author: Zhangfeifei ////
+//// ////
+//// Advance Test Technology Laboratory, ////
+//// Institute of Computing Technology, ////
+//// Chinese Academy of Sciences ////
+//// ////
+//// If you encountered any problem, please contact : ////
+//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org ////
+//// Tel: +86-10-6256 5533 ext. 5673 ////
+//// ////
+//// Downloaded from: ////
+//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2005-2006 Zhangfeifei ////
+//// zhangfeifei@ict.ac.cn ////
+//// ////
+//// ////
+//// This source file may be used and distributed freely without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and any derivative work contains the ////
+//// original copyright notice and the associated disclaimer. ////
+//// ////
+//// Please let the author know if it is used ////
+//// for commercial purpose. ////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// ////
+//// Date of Creation: 2005.12.3 ////
+//// ////
+//// Version: 0.0.1 ////
+//// ////
+//// Description: rx module of the uart module,data format is ////
+//// 8bits data,1 bits stop bit,and no parity check ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Change log: ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+module u_rec_of_verifla(
+ clk_i,rst_i,//system signal
+ baud_clk_posedge,
+ rxd_i,//serial data in
+ rdy_o,data_o //data ready and parallel data out signal
+ );
+
+ parameter // state difinition
+ STA_IDLE = 0,
+ STA_CHECK_START_BIT = 1,
+ STA_RECEIVE = 2;
+
+ input clk_i;
+ input rst_i;
+ input baud_clk_posedge;
+ input rxd_i;
+
+ output rdy_o;
+ output [7:0] data_o;
+
+ reg rdy_o;
+ reg [7:0] data_o;
+
+ reg [7:0] rsr;//reciving shift register
+ reg [3:0] num_of_rec;
+
+ reg [1:0] reg_sta;
+
+ //the counter to count the clk in
+ reg [3:0] count;
+ reg count_c;//the carry of count
+
+ always @(posedge clk_i or posedge rst_i)
+ begin
+ if(rst_i)
+ begin
+ data_o <= 8'b0;
+ rdy_o <= 1'b0;
+ rsr <= 8'h0;
+ num_of_rec <= 4'b0;
+ count <= 4'b0;
+ count_c <= 1'b0;
+ reg_sta <= STA_IDLE;
+ end
+ else begin
+ if(baud_clk_posedge)
+ case (reg_sta)
+ STA_IDLE:
+ begin
+ num_of_rec <= 4'd0;
+ count <= 4'd0;
+ if(!rxd_i)
+ reg_sta <= STA_CHECK_START_BIT;//recive a start bit
+ else
+ reg_sta <= STA_IDLE;
+ end
+ STA_CHECK_START_BIT:
+ begin
+ if(count >= 7)
+ begin
+ count <= 0;
+ if(!rxd_i) begin
+ //has passed 8 clk and rxd_i is still zero,then start bit has been confirmed
+ rdy_o <= 1'b0;
+ reg_sta <= STA_RECEIVE;
+ end
+ else
+ reg_sta <= STA_IDLE;
+ end
+ else begin
+ reg_sta <= STA_CHECK_START_BIT;
+ count <= count +1;
+ end
+ end
+ STA_RECEIVE:
+ begin
+ {count_c,count} <= count +1;
+ //has passed 16 clk after the last bit has been checked,sampling a bit
+ if(count_c)
+ begin
+ if(num_of_rec <=4'd7)
+ begin //sampling the received bit
+ rsr <= {rxd_i,rsr[7:1]};
+ num_of_rec <= num_of_rec +1;
+ reg_sta <= STA_RECEIVE;
+ end
+ else begin//sampling the stop bit
+ //if(rxd_i)//if stop bit exist
+ //begin
+ data_o <= rsr;
+ rdy_o <= 1'b1;
+ //end
+ reg_sta <= STA_IDLE;
+ end
+ end
+ end
+ endcase
+ end
+ end
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/u_rec_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/u_xmit_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/u_xmit_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/u_xmit_of_verifla.v (revision 38)
@@ -0,0 +1,157 @@
+/*
+Update: Laurentiu Duca, 20180808_1200:
+ - consider baud_clk_posedge
+Update: Laurentiu Duca, 20180724_1550:
+ - In state STA_TRANS, put num_of_trans <= 4'd8 instead of 7.
+ in order to send stop bit.
+ - correct init values and sizes
+*/
+
+
+/////////////////////////////////////////////////////////////////////
+//// Author: Zhangfeifei ////
+//// ////
+//// Advance Test Technology Laboratory, ////
+//// Institute of Computing Technology, ////
+//// Chinese Academy of Sciences ////
+//// ////
+//// If you encountered any problem, please contact : ////
+//// Email: zhangfeifei@ict.ac.cn or whitewill@opencores.org ////
+//// Tel: +86-10-6256 5533 ext. 5673 ////
+//// ////
+//// Downloaded from: ////
+//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2005-2006 Zhangfeifei ////
+//// zhangfeifei@ict.ac.cn ////
+//// ////
+//// ////
+//// This source file may be used and distributed freely without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and any derivative work contains the ////
+//// original copyright notice and the associated disclaimer. ////
+//// ////
+//// Please let the author know if it is used ////
+//// for commercial purpose. ////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// ////
+//// Date of Creation: 2005.12.3 ////
+//// ////
+//// Version: 0.0.1 ////
+//// ////
+//// Description: tx module of the uart module,data format is ////
+//// 8bits data,1 bits stop bit,and no parity check ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Change log: ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+module u_xmit_of_verifla(
+ clk_i,rst_i,//system signal
+ baud_clk_posedge,
+ data_i,wen_i,//parallel data in and enable signal
+ txd_o,//serial data out
+ tre_o// ready to transmit flag
+ );
+
+ parameter // state difinition
+ STA_IDLE = 0,
+ STA_TRANS = 1,
+ STA_FINISH = 2;
+
+ input clk_i;
+ input rst_i;
+ input baud_clk_posedge;
+ input [7:0] data_i;
+ input wen_i;
+
+ output txd_o;
+ output tre_o;
+
+ reg txd_o;
+ reg tre_o;
+
+ reg [7:0] tsr;//transmitting shift register
+ reg [3:0] num_of_trans;
+
+ reg [1:0] reg_sta;
+
+ //the counter to count the clk in
+ reg [3:0] count;
+ reg count_c;//the carry of count
+
+ always @(posedge clk_i or posedge rst_i)
+ begin
+ if(rst_i)
+ begin
+ tsr <= 8'b0;
+ txd_o <= 1'b1;
+ tre_o <= 1'b1;
+ num_of_trans <= 4'b0;
+ count_c <= 1'b0;
+ count <= 4'b0;
+ reg_sta <= STA_IDLE;
+ end
+ else begin
+ if(baud_clk_posedge)
+ case(reg_sta)
+ STA_IDLE:
+ begin
+ num_of_trans <= 4'd0;
+ count <= 4'd0;
+ count_c <= 1'b0;
+ if(wen_i)
+ begin
+ tsr <= data_i;
+ tre_o <= 1'b0;
+ txd_o <= 1'b0;// transmit the start bit
+ reg_sta <= STA_TRANS;
+ end
+ else
+ reg_sta <= STA_IDLE;
+ end
+ STA_TRANS:
+ begin
+ {count_c,count} <= count + 1;
+
+ if(count_c)
+ begin
+ if(num_of_trans <=4'd8)
+ begin
+ //note ,when num_of_trans==8 ,we transmit the stop bit
+ tsr <= {1'b1,tsr[7:1]};
+ txd_o <= tsr[0];
+ num_of_trans <= num_of_trans+1;
+ reg_sta <= STA_TRANS;
+ end
+ else begin
+ txd_o <= 1'b1;
+ tre_o <= 1'b1;
+ reg_sta <= STA_IDLE;
+ end
+ end
+ end
+ endcase
+ end
+ end
+
+endmodule
trunk/openverifla_2.3/verilog/verifla/u_xmit_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/verilog/verifla/uart_of_verifla.v
===================================================================
--- trunk/openverifla_2.3/verilog/verifla/uart_of_verifla.v (nonexistent)
+++ trunk/openverifla_2.3/verilog/verifla/uart_of_verifla.v (revision 38)
@@ -0,0 +1,101 @@
+/*
+Update: Laurentiu Duca, 20180808_1200:
+ - consider baud_clk_posedge
+*/
+module uart_of_verifla ( sys_clk,
+ sys_rst_l,
+ baud_clk_posedge,
+
+ // Transmitter
+ uart_XMIT_dataH,
+ xmitH,
+ xmit_dataH,
+ xmit_doneH,
+
+ // Receiver
+ uart_REC_dataH,
+ rec_dataH,
+ rec_readyH
+ );
+
+input sys_clk;
+input sys_rst_l;
+output baud_clk_posedge;
+
+// Trasmitter
+output uart_XMIT_dataH;
+input xmitH;
+input [7:0] xmit_dataH;
+output xmit_doneH;
+
+// Receiver
+input uart_REC_dataH;
+output [7:0] rec_dataH;
+output rec_readyH;
+
+wire baud_clk_posedge;
+wire [7:0] rec_dataH;
+wire rec_readyH;
+
+
+
+// Instantiate the Transmitter
+u_xmit_of_verifla txd1 (
+ .clk_i(sys_clk),
+ .rst_i(!sys_rst_l),
+ .baud_clk_posedge(baud_clk_posedge),
+ .data_i(xmit_dataH),
+ .wen_i(xmitH),
+ .txd_o(uart_XMIT_dataH),
+ .tre_o(xmit_doneH)
+ );
+/*
+u_xmit iXMIT( .sys_clk(baud_clk),
+ .sys_rst_l(sys_rst_l),
+
+ .uart_xmitH(uart_XMIT_dataH),
+ .xmitH(xmitH),
+ .xmit_dataH(xmit_dataH),
+ .xmit_doneH(xmit_doneH)
+ );
+*/
+
+// Instantiate the Receiver
+u_rec_of_verifla rxd1(
+ .clk_i(sys_clk),
+ .rst_i(!sys_rst_l),//system signal
+ .baud_clk_posedge(baud_clk_posedge),
+ .rxd_i(uart_REC_dataH),//serial data in
+ .rdy_o (rec_readyH), .data_o(rec_dataH) //data ready and parallel data out signal
+ );
+/*
+u_rec iRECEIVER (// system connections
+ .sys_rst_l(sys_rst_l),
+ .sys_clk(baud_clk),
+ // uart
+ .uart_dataH(uart_REC_dataH),
+ .rec_dataH(rec_dataH),
+ .rec_readyH(rec_readyH)
+ );
+*/
+
+// Instantiate the Baud Rate Generator
+
+baud_of_verifla baud1( .sys_clk(sys_clk),
+ .sys_rst_l(sys_rst_l),
+ .baud_clk_posedge(baud_clk_posedge)
+ );
+
+/*
+reg [2:0] baud_clk_vec=0;
+always @(posedge sys_clk or negedge sys_rst_l)
+begin
+ if(~sys_rst_l)
+ baud_clk_vec = 0;
+ else
+ baud_clk_vec = {baud_clk_vec[1:0], baud_clk};
+end
+wire baud_clk_posedge;
+assign baud_clk_posedge=baud_clk_vec[2:1]==2'b01;
+*/
+endmodule
trunk/openverifla_2.3/verilog/verifla/uart_of_verifla.v
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/keyboard/keyboard.ucf
===================================================================
--- trunk/openverifla_2.3/vhdl/keyboard/keyboard.ucf (nonexistent)
+++ trunk/openverifla_2.3/vhdl/keyboard/keyboard.ucf (revision 38)
@@ -0,0 +1,28 @@
+#NET "switch[0]" LOC="L13";
+#NET "switch[1]" LOC="L14";
+#NET "switch[2]" LOC="H18";
+#NET "switch[3]" LOC="N17";
+
+NET "clk" LOC = "C9";
+NET "reset" LOC = "L13";
+
+NET "kbd_data_line" LOC = "G13";
+NET "kbd_clk" LOC = "G14";
+
+#NET "J1_0" LOC = "N15";
+#NET "J1_1" LOC = "N14";
+#NET "J1_2" LOC = "E15";
+#NET "J1_3" LOC = "V7";
+
+#leds
+NET "kbd_key[0]" LOC="D4";
+NET "kbd_key[1]" LOC="C3";
+NET "kbd_key[2]" LOC="D6";
+NET "kbd_key[3]" LOC="E6";
+NET "kbd_key[4]" LOC="D13";
+NET "kbd_key[5]" LOC="A7";
+NET "kbd_key[6]" LOC="G9";
+NET "kbd_key[7]" LOC="A8";
+
+NET "uart_REC_dataH" LOC = "R13";
+NET "uart_XMIT_dataH" LOC = "P13";
trunk/openverifla_2.3/vhdl/keyboard/keyboard.ucf
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/keyboard/keyboard.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/keyboard/keyboard.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/keyboard/keyboard.vhd (revision 38)
@@ -0,0 +1,84 @@
+-- keyboad driver
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+-----------------------------------------------------
+
+entity keyboard is
+port( kbd_data_line, kbd_clk: in std_logic;
+ kbd_key: out std_logic_vector(7 downto 0);
+ clk, reset: in std_logic;
+ uart_XMIT_dataH: out std_logic;
+ uart_REC_dataH: in std_logic
+);
+end keyboard;
+
+-----------------------------------------------------
+
+architecture keyboard_arch of keyboard is
+
+ -- define the states of keyboard_arch model
+ signal i: std_logic_vector(3 downto 0);
+ signal kbd_clk_buf: std_logic_vector(2 downto 0) :="000";
+ signal negedge_kbd_clk: std_logic :='0';
+ signal kbd_key_reg: std_logic_vector(7 downto 0);
+ signal cnt: std_logic_vector(5 downto 0);
+ signal verifla_data_in : std_logic_vector(15 downto 0);
+begin
+
+ p1: process(clk) begin
+ if(rising_edge(clk)) then
+ kbd_clk_buf <= kbd_clk_buf(1 downto 0) & kbd_clk;
+ end if;
+ end process;
+ negedge_kbd_clk <= '1' when (kbd_clk_buf(2 downto 1) = "10") else '0';
+
+ -- process: state registers
+ state_reg: process(clk, reset)
+ begin
+ if (reset='1') then
+ i <= "1010";
+ kbd_key_reg <= x"00";
+ elsif (rising_edge(clk)) then
+ if (negedge_kbd_clk = '1') then
+ if ((i >= x"0") and (i <= x"7")) then
+ kbd_key_reg <= kbd_data_line & kbd_key_reg(7 downto 1);
+ i <= std_logic_vector((unsigned(i)+"0001"));
+ elsif ((i = x"8") or (i = x"9")) then
+ i <= std_logic_vector((unsigned(i)+"0001"));
+ else
+ i <= x"0";
+ end if;
+ end if;
+ end if;
+ end process;
+ kbd_key <= kbd_key_reg;
+
+ -- Simple counter
+ state_reg_cnt: process(clk, reset)
+ begin
+ if (reset='1') then
+ cnt <= "000000";
+ elsif (rising_edge(clk)) then
+ if(negedge_kbd_clk = '1') then
+ cnt <= std_logic_vector(unsigned(cnt)+"000001");
+ end if;
+ end if;
+ end process;
+
+ -- openVeriFLA
+ verifla_data_in <= cnt & kbd_data_line & kbd_clk & kbd_key_reg;
+ --(15 downto 10 => '0') & kbd_data_line & kbd_clk & kbd_key_reg;
+ verifla: entity work.top_of_verifla(top_of_verifla_arch)
+ port map (clk=>clk, rst_l=>not(reset), sys_run=>'1',
+ data_in=>verifla_data_in,
+ -- Transceiver
+ uart_XMIT_dataH => uart_XMIT_dataH,
+ uart_REC_dataH => uart_REC_dataH);
+
+end keyboard_arch;
Index: trunk/openverifla_2.3/vhdl/keyboard/keyboard_driver_test.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/keyboard/keyboard_driver_test.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/keyboard/keyboard_driver_test.vhd (revision 38)
@@ -0,0 +1,103 @@
+-----------------------------------------------------------------
+-- Booth algorithm for multiplication
+-- author: Laurentiu Duca
+-----------------------------------------------------------------
+
+library ieee;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+use ieee.std_logic_1164.all;
+
+entity keyboard_driver_test is -- entity declaration
+end keyboard_driver_test;
+
+-----------------------------------------------------------------
+
+architecture keyboard_driver_test_arch of keyboard_driver_test is
+
+-- This test module is wrote
+-- in the following scenario: the driver is on the FPGA and the keyboard
+-- is attached to the FPGA development board
+
+ signal kbd_key:std_logic_vector(7 downto 0);
+-- This signals must explicitly added to the simulation.
+-- For debugging purposes, also add the register named "i" from the keyboard driver
+ signal reset, clk: std_logic;
+ signal kbd_clk, kbd_data_line: std_logic;
+ signal uart_XMIT_dataH: std_logic;
+ signal uart_REC_dataH: std_logic :='1';
+ --signal i: std_logic_vector(64 downto 0);
+
+ signal stop_simulation: std_logic := '0';
+
+begin
+
+ keyboard1: entity work.keyboard(keyboard_arch)
+ port map(kbd_data_line=>kbd_data_line, kbd_clk=>kbd_clk, kbd_key=>kbd_key,
+ clk=>clk, reset=>reset,
+ --top_of_verifla transceiver
+ uart_XMIT_dataH=>uart_XMIT_dataH, uart_REC_dataH=>uart_REC_dataH);
+
+ process
+ begin
+ if stop_simulation = '0' then
+ clk <= '1'; -- clock cycle 10 ns
+ wait for 5 ns;
+ clk <= '0';
+ wait for 5 ns;
+ else
+ wait;
+ end if;
+ end process;
+
+ -- Reset the driver by using the reset button of the FPGA board.
+ process
+ begin
+ reset <= '1';
+ wait for 10 ns;
+ reset <= '0';
+ wait for 10 ns;
+ wait;
+ end process;
+
+ -- Now, simulate the keyboard.
+ -- Consider the keyboard clock period to be about 10 units.
+ process
+ begin
+ -- At the begining, the line is idle for some periods.
+ kbd_clk<='1'; kbd_data_line<='1'; wait for 2050 ns; wait for 2050 ns;
+
+ -- When a key is pressed, the keyboard sends its scan code
+ -- on the data line. For the 'a' key, the scan code is 1Ch=00011100b.
+ -- The order is LSb first, so the bits are sent in the following order: 00111000.
+ -- Simulate pressing the 'a' key.
+ -- Send start bit.
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ -- Send the scan code
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='1'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='1'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='1'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='0'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ -- Send the parity bit which is '1' for the 'a' key.
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='1'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ -- Send the stop bit.
+ kbd_clk<='1'; wait for 250 ns; kbd_data_line<='1'; wait for 250 ns; kbd_clk<='0'; wait for 500 ns;
+ -- Put the line idle for some periods.
+ kbd_clk<='1'; kbd_data_line<='1'; wait for 2050 ns; wait for 2050 ns;
+ wait for 1000 ns;
+ -- When the 'a' key - that is now pressed,
+ -- will be released, then the keyboard will send F0h, 1Ch.
+ -- We do not simulate this because the process is similar.
+
+ -- stop simulation.
+ -- assert false report "end of simulation" severity failure;
+ stop_simulation <= '1';
+ wait;
+
+ end process;
+
+end keyboard_driver_test_arch;
trunk/openverifla_2.3/vhdl/keyboard/keyboard_driver_test.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/baud_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/baud_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/baud_of_verifla.vhd (revision 38)
@@ -0,0 +1,67 @@
+-- 20180816-1450
+-- baud rate generator
+-- author: Laurentiu Duca
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use work.inc_of_verifla.all;
+
+-----------------------------------------------------
+
+entity baud_of_verifla is
+port( sys_clk, sys_rst_l:in std_logic;
+ baud_clk_posedge: out std_logic
+);
+end baud_of_verifla;
+
+-----------------------------------------------------
+
+architecture baud_of_verifla_arch of baud_of_verifla is
+
+ -- This were moved to inc_of_verifla.vhd
+ --constant CLOCK_FREQUENCY: integer := 50000000;
+ --constant BPS: integer := 115200;
+ -- 1s ... 50000000 T1
+ -- 1bit ... 16 T2
+ -- 1s .. 115200 bits
+ -- =>
+ -- 1s .. 115200 * 16 T2
+ --
+ -- T2 = 5000000 T1 / (115200 * 16) = T1 * 50000000 / (115200 * 16)
+ --constant T2_div_T1_div_2: integer := (CLOCK_FREQUENCY / (BPS * 16 * 2));
+ -- COUNTER_SIZE = log2(T2_T1_div_2) bits
+ --constant BAUD_COUNTER_SIZE: integer := 15;
+
+ signal counter: std_logic_vector((BAUD_COUNTER_SIZE-1) downto 0);
+ signal baud_clk, baud_clk_posedge_reg: std_logic;
+
+begin
+
+ baud_clk_posedge <= baud_clk_posedge_reg;
+
+ state_reg: process(sys_clk, sys_rst_l)
+ begin
+ if (sys_rst_l='0') then
+ baud_clk <= '0';
+ baud_clk_posedge_reg <= '0';
+ counter <= std_logic_vector(to_unsigned(0, BAUD_COUNTER_SIZE)); --x"00000000";
+ elsif (rising_edge(sys_clk)) then
+ if (counter < std_logic_vector(to_unsigned(T2_div_T1_div_2, BAUD_COUNTER_SIZE))) then
+ counter <= counter + std_logic_vector(to_unsigned(1, BAUD_COUNTER_SIZE));
+ baud_clk <= baud_clk;
+ baud_clk_posedge_reg <= '0';
+ else
+ if (baud_clk = '0') then
+ baud_clk_posedge_reg <= '1';
+ end if;
+ counter <= std_logic_vector(to_unsigned(0, BAUD_COUNTER_SIZE));
+ baud_clk <= not(baud_clk);
+ end if;
+ end if;
+ end process;
+
+end baud_of_verifla_arch;
\ No newline at end of file
trunk/openverifla_2.3/vhdl/verifla/baud_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/common_internal_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/common_internal_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/common_internal_verifla.vhd (revision 38)
@@ -0,0 +1,55 @@
+-- date: 20180821-1530
+-- author: Laurentiu Duca
+---------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+---------------------------------------------------------------------------
+
+package common_internal_verifla is
+
+-- Data input width and indentical samples bits must be multiple of 8.
+constant LA_DATA_INPUT_WORDLEN_BITS: integer :=16;
+
+-- Trigger
+constant LA_TRIGGER_VALUE: std_logic_vector((LA_DATA_INPUT_WORDLEN_BITS-1) downto 0)
+ :=(others => '0');
+constant LA_TRIGGER_MASK: std_logic_vector((LA_DATA_INPUT_WORDLEN_BITS-1) downto 0)
+ :=(LA_DATA_INPUT_WORDLEN_BITS-7 downto LA_DATA_INPUT_WORDLEN_BITS-8 => '1',
+ others => '0');
+constant LA_TRACE_MASK: std_logic_vector((LA_DATA_INPUT_WORDLEN_BITS-1) downto 0)
+ :=(others => '1');
+
+constant LA_MEM_CLEAN_BEFORE_RUN: integer :=1;
+constant LA_IDENTICAL_SAMPLES_BITS: integer :=16;
+constant LA_MEM_WORDLEN_BITS: integer :=(LA_DATA_INPUT_WORDLEN_BITS+LA_IDENTICAL_SAMPLES_BITS);
+constant LA_MEM_WORDLEN_OCTETS: integer :=((LA_MEM_WORDLEN_BITS+7)/8);
+constant LA_MEM_ADDRESS_BITS: integer :=6;
+constant LA_MEM_FIRST_ADDR: integer := 0;
+constant LA_MEM_LAST_ADDR: integer := 2 ** LA_MEM_ADDRESS_BITS - 1;
+
+constant LA_BT_QUEUE_TAIL_ADDRESS: integer :=LA_MEM_LAST_ADDR;
+-- constraint: (LA_MEM_FIRST_ADDR + 4) <= LA_TRIGGER_MATCH_MEM_ADDR <= (LA_MEM_LAST_ADDR - 4)
+constant LA_TRIGGER_MATCH_MEM_ADDR: integer := 2 ** (LA_MEM_ADDRESS_BITS - 3);
+constant LA_MEM_LAST_ADDR_BEFORE_TRIGGER: integer := LA_TRIGGER_MATCH_MEM_ADDR - 1;
+constant LA_MAX_SAMPLES_AFTER_TRIGGER_BITS: integer :=26;
+constant LA_MAX_SAMPLES_AFTER_TRIGGER: integer := 2 ** (LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1) - 1;
+
+-- Identical samples
+constant LA_MAX_IDENTICAL_SAMPLES: integer := 2 ** LA_IDENTICAL_SAMPLES_BITS - 2;
+
+--Reserved mem words
+-- LA_MEM_EMPTY_SLOT which represents an empty and not used memory slot.
+--It has sense if LA_MEM_CLEAN_BEFORE_RUN and
+-- a) when the trigger event arrives before the filling of the full btqueue.
+-- b) after the trigger event and after capturing LA_MAX_SAMPLES_AFTER_TRIGGER
+
+--`define LA_INIT_MEM_AT_RESET: instead of this verilog define we have two architectures for memory.
+constant LA_MEM_EMPTY_SLOT: std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0)
+ := (others => '0');
+
+end common_internal_verifla;
trunk/openverifla_2.3/vhdl/verifla/common_internal_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/computer_input_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/computer_input_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/computer_input_of_verifla.vhd (revision 38)
@@ -0,0 +1,79 @@
+-- 20180820-1740
+-- Author: Laurentiu Duca
+-- License: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use work.common_internal_verifla.all;
+
+-----------------------------------------------------
+
+entity computer_input_of_verifla is
+ port (clk, rst_l: in std_logic;
+ rec_dataH: in std_logic_vector(7 downto 0);
+ rec_readyH: in std_logic;
+ user_run: out std_logic);
+end computer_input_of_verifla;
+
+-----------------------------------------------------
+
+architecture computer_input_of_verifla_arch of computer_input_of_verifla is
+
+--constant USERCMD_RESET: std_logic_vector(7 downto 0) :=x"00";
+constant USERCMD_RUN: std_logic_vector(7 downto 0) :=x"01";
+type state_type is (CI_STATE_IDLE, CI_STATE_START_OF_NEW_CMD);
+signal ci_state, next_ci_state: state_type;
+signal ci_indata, next_ci_indata: std_logic_vector(7 downto 0);
+signal ci_new_octet_received:std_logic;
+signal next_user_run: std_logic;
+
+begin
+
+ -- T(clk)<clk, rst_l=>rst_l, ub=>rec_readyH, ubsing=>ci_new_octet_received);
+
+ -- set up next value
+ state_reg: process(clk, rst_l)
+ begin
+ if (rst_l='0') then
+ ci_state<=CI_STATE_IDLE;
+ ci_indata<=x"00";
+ user_run <= '0';
+ elsif (rising_edge(clk)) then
+ ci_state<=next_ci_state;
+ ci_indata<=next_ci_indata;
+ user_run <= next_user_run;
+ end if;
+ end process;
+
+ -- state machine
+ comb_logic: process(ci_new_octet_received, rec_dataH, ci_state, ci_indata)
+ begin
+ -- implicit
+ next_ci_state <= ci_state;
+ next_ci_indata <= x"00";
+ next_user_run <= '0';
+ case ci_state is
+ when CI_STATE_IDLE =>
+ if(ci_new_octet_received = '1') then
+ next_ci_indata <= rec_dataH;
+ next_ci_state <= CI_STATE_START_OF_NEW_CMD;
+ else
+ next_ci_state<=CI_STATE_IDLE;
+ end if;
+ when CI_STATE_START_OF_NEW_CMD =>
+ next_ci_state<=CI_STATE_IDLE;
+ if (ci_indata = USERCMD_RUN) then
+ next_user_run<='1';
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ end case;
+ end process;
+
+end computer_input_of_verifla_arch;
trunk/openverifla_2.3/vhdl/verifla/computer_input_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/inc_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/inc_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/inc_of_verifla.vhd (revision 38)
@@ -0,0 +1,30 @@
+--library IEEE;
+--use IEEE.STD_LOGIC_1164.ALL;
+--use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+---------------------------------------------------------------------------
+
+package inc_of_verifla is
+
+constant CLOCK_FREQUENCY: integer := 50000000;
+constant BAUDRATE: integer := 115200;
+
+constant T2_div_T1_div_2: integer := (CLOCK_FREQUENCY / (BAUDRATE * 16 * 2));
+-- Assert: BAUD_COUNTER_SIZE >= log2(T2_div_T1_div_2) bits
+constant BAUD_COUNTER_SIZE: integer := 15;
+
+-- 1s ... 50000000 T1
+-- 1bit ... 16 T2
+-- 1s .. 115200 bits
+-- =>
+-- 1s .. 115200 * 16 T2
+--
+-- T2 = 5000000 T1 / (115200 * 16) = T1 * 50000000 / (115200 * 16)
+
+end inc_of_verifla;
+
+package body inc_of_verifla is
+
+end inc_of_verifla;
Index: trunk/openverifla_2.3/vhdl/verifla/memory_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/memory_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/memory_of_verifla.vhd (revision 38)
@@ -0,0 +1,96 @@
+-- 20180820-1740
+-- Author: Laurentiu Duca
+-- License: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use work.common_internal_verifla.all;
+
+-----------------------------------------------------
+
+entity memory_of_verifla is port(
+ clk, rst_l: in std_logic;
+ addra: in std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ wea: in std_logic;
+ dina: in std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+ addrb: in std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ doutb: out std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0)
+);
+end memory_of_verifla;
+-----------------------------------------------------
+
+architecture memory_of_verifla_arch of memory_of_verifla is
+
+type reg_array is array (0 to LA_MEM_LAST_ADDR) of std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+
+impure function init_mem(n: in integer) return reg_array is
+ variable temp_mem : reg_array;
+begin
+ for i in reg_array'range loop
+ temp_mem(i) := LA_MEM_EMPTY_SLOT; --std_logic_vector(to_unsigned(0, LA_MEM_WORDLEN_BITS));
+ end loop;
+ return temp_mem;
+end function;
+
+signal mem: reg_array := init_mem(0);
+
+begin
+ -- doutb <= mem(to_integer(unsigned(addrb)));
+ -- This works too as a consequence of send_capture_of_verifla architecture.
+ p0: process(clk, rst_l)
+ begin
+ if(rst_l = '0') then
+ doutb <= LA_MEM_EMPTY_SLOT;
+ elsif(rising_edge(clk)) then
+ doutb <= mem(to_integer(unsigned(addrb)));
+ end if;
+ end process;
+
+ p1: process(clk)
+ begin
+ if(rising_edge(clk)) then
+ if(wea = '1') then
+ mem(to_integer(unsigned(addra))) <= dina;
+ end if;
+ end if;
+ end process;
+
+end memory_of_verifla_arch;
+-----------------------------------------------------
+
+architecture memory_of_verifla_clean_at_reset_arch of memory_of_verifla is
+
+type reg_array is array (0 to LA_MEM_LAST_ADDR) of std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+signal mem: reg_array;
+--signal i: integer;
+
+begin
+ -- doutb <= mem(to_integer(unsigned(addrb)));
+ -- This works too as a consequence of send_capture_of_verifla architecture.
+ p0: process(clk, rst_l)
+ begin
+ if(rst_l = '0') then
+ doutb <= LA_MEM_EMPTY_SLOT;
+ elsif(rising_edge(clk)) then
+ doutb <= mem(to_integer(unsigned(addrb)));
+ end if;
+ end process;
+
+ p1: process(clk, rst_l)
+ begin
+ if(rst_l = '0') then
+ for i in 0 to LA_MEM_LAST_ADDR loop
+ mem(i) <= LA_MEM_EMPTY_SLOT;
+ end loop;
+ elsif(rising_edge(clk)) then
+ if(wea = '1') then
+ mem(to_integer(unsigned(addra))) <= dina;
+ end if;
+ end if;
+ end process;
+
+end memory_of_verifla_clean_at_reset_arch;
trunk/openverifla_2.3/vhdl/verifla/memory_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/monitor_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/monitor_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/monitor_of_verifla.vhd (revision 38)
@@ -0,0 +1,337 @@
+-- Author: Laurentiu Duca
+-- License: GNU GPL
+-- 20181016-1225
+-- LA_TRACE_MASK
+-- 20180826-1740
+-- split mon_run in sys_run and user_run
+-- 20180820-1500
+-- first source
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+use work.common_internal_verifla.all;
+
+-----------------------------------------------------
+
+entity monitor_of_verifla is
+ port (clk, rst_l: in std_logic;
+ sys_run, user_run: in std_logic;
+ data_in: in std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0);
+ mem_port_A_address: out std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ mem_port_A_data_in: out std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+ mem_port_A_wen: out std_logic;
+ ack_sc_run, sc_done: in std_logic;
+ sc_run: out std_logic);
+end monitor_of_verifla;
+
+-----------------------------------------------------
+
+architecture monitor_of_verifla_arch of monitor_of_verifla is
+
+ constant LA_MEM_FIRST_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS));
+ constant LA_MEM_LAST_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := std_logic_vector(to_unsigned(LA_MEM_LAST_ADDR, LA_MEM_ADDRESS_BITS));
+ constant LA_BT_QUEUE_TAIL_ADDRESS_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := LA_MEM_LAST_ADDR_SLV;
+ constant LA_TRIGGER_MATCH_MEM_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := std_logic_vector(to_unsigned(LA_TRIGGER_MATCH_MEM_ADDR, LA_MEM_ADDRESS_BITS));
+ constant LA_MEM_LAST_ADDR_BEFORE_TRIGGER_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := std_logic_vector(to_unsigned(LA_MEM_LAST_ADDR_BEFORE_TRIGGER, LA_MEM_ADDRESS_BITS));
+
+ --type state_type is (MON_STATE_IDLE, MON_STATE_DO_MEM_CLEAN, MON_STATE_PREPARE_RUN,
+ --MON_STATE_WAIT_TRIGGER_MATCH, MON_STATE_AFTER_TRIGGER, MON_STATE_DATA_CAPTURED,
+ --MON_STATE_SC_RUN, MON_STATE_WAIT_SC_DONE);
+ -- This way, at reset we can set any start state.
+ constant MON_STATE_IDLE: integer :=0;
+ constant MON_STATE_DO_MEM_CLEAN: integer :=1;
+ constant MON_STATE_PREPARE_RUN: integer :=2;
+ constant MON_STATE_WAIT_TRIGGER_MATCH: integer :=3;
+ constant MON_STATE_AFTER_TRIGGER: integer :=4;
+ constant MON_STATE_DATA_CAPTURED: integer :=5;
+ constant MON_STATE_SC_RUN: integer :=6;
+ constant MON_STATE_WAIT_SC_DONE: integer :=7;
+
+ signal sys_run_reg: std_logic;
+ signal sc_run_aux, next_sc_run_aux: std_logic;
+ signal mon_state, next_mon_state: integer; -- state_type;
+ signal next_mon_samples_after_trigger, mon_samples_after_trigger:
+ std_logic_vector(LA_MAX_SAMPLES_AFTER_TRIGGER_BITS-1 downto 0);
+ signal next_mon_write_address, mon_write_address:
+ std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ signal next_bt_queue_tail_address, bt_queue_tail_address: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ signal mon_old_data_in, mon_current_data_in: std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0);
+ signal mon_clones_nr, next_mon_clones_nr: std_logic_vector(LA_IDENTICAL_SAMPLES_BITS-1 downto 0);
+ signal one_plus_mon_write_address:std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ signal oneplus_mon_clones_nr:std_logic_vector(LA_IDENTICAL_SAMPLES_BITS-1 downto 0);
+ signal data_in_changed: std_logic;
+ signal last_mem_addr_before_trigger: std_logic;
+ signal not_maximum_mon_clones_nr: std_logic;
+
+begin
+
+ -- Register the input data
+ -- such that mon_current_data_in is constant the full clock period.
+ register_input_data: process(clk, rst_l)
+ begin
+ if (rst_l='0') then
+ mon_old_data_in <= (others => '0');
+ mon_current_data_in <= (others => '0');
+ sys_run_reg <= '0';
+ elsif (rising_edge(clk)) then
+ mon_old_data_in <= mon_current_data_in;
+ mon_current_data_in <= data_in;
+ sys_run_reg <= sys_run;
+ end if;
+ end process;
+
+ -- set new values
+ state_reg: process(clk, rst_l)
+ begin
+ if (rst_l='0') then
+ mon_state <= MON_STATE_IDLE;
+ sc_run_aux <= '0';
+ mon_write_address <= std_logic_vector(to_unsigned(LA_MEM_FIRST_ADDR, LA_MEM_ADDRESS_BITS));
+ bt_queue_tail_address <= (others => '0');
+ mon_samples_after_trigger <= (others => '0');
+ mon_clones_nr <= ((LA_IDENTICAL_SAMPLES_BITS-1) downto 1 => '0', others => '1');
+ elsif (rising_edge(clk)) then
+ mon_state <= next_mon_state;
+ sc_run_aux <= next_sc_run_aux;
+ mon_write_address <= next_mon_write_address;
+ bt_queue_tail_address <= next_bt_queue_tail_address;
+ mon_samples_after_trigger <= next_mon_samples_after_trigger;
+ mon_clones_nr <= next_mon_clones_nr;
+ end if;
+ end process;
+
+ -- continuous assignments
+ one_plus_mon_write_address <=
+ std_logic_vector(to_unsigned(to_integer(unsigned(mon_write_address)) + 1, LA_MEM_ADDRESS_BITS));
+ oneplus_mon_clones_nr <=
+ std_logic_vector(to_unsigned(to_integer(unsigned(mon_clones_nr)) + 1, LA_IDENTICAL_SAMPLES_BITS));
+ data_in_changed <= '1' when ((mon_current_data_in and LA_TRACE_MASK) /= (mon_old_data_in and LA_TRACE_MASK)) else '0';
+ last_mem_addr_before_trigger <=
+ '1' when (to_integer(unsigned(mon_write_address)) = LA_MEM_LAST_ADDR_BEFORE_TRIGGER) else '0';
+ not_maximum_mon_clones_nr <=
+ '1' when (to_integer(unsigned(mon_clones_nr)) < LA_MAX_IDENTICAL_SAMPLES) else '0';
+ sc_run <= sc_run_aux;
+
+ -- state machine
+ comb_logic: process(mon_state, sys_run_reg, user_run, ack_sc_run, sc_done, sc_run_aux,
+ mon_write_address, bt_queue_tail_address, mon_samples_after_trigger,
+ mon_current_data_in, mon_old_data_in, mon_clones_nr,
+ data_in_changed, oneplus_mon_clones_nr, one_plus_mon_write_address,
+ not_maximum_mon_clones_nr, last_mem_addr_before_trigger)
+ begin
+ -- implicit
+ next_mon_state <= mon_state;
+ next_sc_run_aux <= sc_run_aux;
+ next_mon_write_address <= mon_write_address;
+ next_bt_queue_tail_address <= bt_queue_tail_address;
+ next_mon_samples_after_trigger <= mon_samples_after_trigger;
+ next_mon_clones_nr <= mon_clones_nr;
+ mem_port_A_address <= (others => '0');
+ mem_port_A_data_in <= (others => '0');
+ mem_port_A_wen <= '0';
+ case mon_state is
+ when MON_STATE_IDLE =>
+ if((sys_run_reg = '1') or (user_run = '1')) then
+ if((LA_MEM_CLEAN_BEFORE_RUN = 1) or (user_run = '1')) then
+ next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
+ next_mon_state <= MON_STATE_DO_MEM_CLEAN;
+ else
+ -- mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
+ -- we share the same clock as memory.
+ mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ --{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
+ mem_port_A_wen <= '1';
+ next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
+ end if;
+ else
+ next_mon_state <= MON_STATE_IDLE;
+ end if;
+ when MON_STATE_DO_MEM_CLEAN =>
+ mem_port_A_address <= mon_write_address;
+ mem_port_A_data_in <= LA_MEM_EMPTY_SLOT;
+ mem_port_A_wen <= '1';
+ if(to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR) then
+ next_mon_write_address <= std_logic_vector(to_unsigned(to_integer(unsigned(mon_write_address)) + 1,
+ LA_MEM_ADDRESS_BITS));
+ next_mon_state <= MON_STATE_DO_MEM_CLEAN;
+ else
+ -- at the new posedge clock, will clean memory at its last address
+ next_mon_state <= MON_STATE_PREPARE_RUN;
+ end if;
+ when MON_STATE_PREPARE_RUN =>
+ -- mon_prepare_run is called from states MON_STATE_IDLE and MON_STATE_PREPARE_RUN
+ -- we share the same clock as memory.
+ mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ --{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in};
+ mem_port_A_wen <= '1';
+ next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
+ when MON_STATE_WAIT_TRIGGER_MATCH =>
+ -- circular queue
+ if((mon_current_data_in and LA_TRIGGER_MASK) /= (LA_TRIGGER_VALUE and LA_TRIGGER_MASK)) then
+ next_mon_state <= MON_STATE_WAIT_TRIGGER_MATCH;
+ mem_port_A_wen <= '1';
+ if(data_in_changed = '1') then
+ if(last_mem_addr_before_trigger = '1') then
+ mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
+ else
+ mem_port_A_address <= one_plus_mon_write_address;
+ end if;
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ mem_port_A_address <= mon_write_address;
+ else
+ if(last_mem_addr_before_trigger = '1') then
+ mem_port_A_address <= LA_MEM_FIRST_ADDR_SLV;
+ else
+ mem_port_A_address <= one_plus_mon_write_address;
+ end if;
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ --{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ mem_port_A_data_in <= mon_clones_nr & mon_current_data_in;
+ else
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ -- {{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in}
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ next_mon_clones_nr <= oneplus_mon_clones_nr;
+ else
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ if(last_mem_addr_before_trigger = '1') then
+ next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
+ else
+ next_mon_write_address <= one_plus_mon_write_address;
+ end if;
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ next_mon_write_address <= mon_write_address;
+ else
+ if(last_mem_addr_before_trigger = '1') then
+ next_mon_write_address <= LA_MEM_FIRST_ADDR_SLV;
+ else
+ next_mon_write_address <= one_plus_mon_write_address;
+ end if;
+ end if;
+ end if;
+ else
+ -- trigger matched
+ next_mon_state <= MON_STATE_AFTER_TRIGGER;
+ mem_port_A_address <= LA_TRIGGER_MATCH_MEM_ADDR_SLV;
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ -- {{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1}, mon_current_data_in};
+ mem_port_A_wen <= '1';
+ next_mon_write_address <= LA_TRIGGER_MATCH_MEM_ADDR_SLV;
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ next_bt_queue_tail_address <= mon_write_address;
+ next_mon_samples_after_trigger <= std_logic_vector(to_unsigned(1, LA_MAX_SAMPLES_AFTER_TRIGGER_BITS));
+ end if;
+ when MON_STATE_AFTER_TRIGGER =>
+ if((to_integer(unsigned(mon_samples_after_trigger)) < LA_MAX_SAMPLES_AFTER_TRIGGER) and
+ (to_integer(unsigned(mon_write_address)) < LA_MEM_LAST_ADDR)) then
+ mem_port_A_wen <= '1';
+ if(data_in_changed = '1') then
+ mem_port_A_address <= one_plus_mon_write_address;
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ mem_port_A_address <= mon_write_address;
+ else
+ mem_port_A_address <= one_plus_mon_write_address;
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ --{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in} :
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ mem_port_A_data_in <= mon_clones_nr & mon_current_data_in;
+ else
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_IDENTICAL_SAMPLES_BITS-1)) & '1' & mon_current_data_in;
+ --{{(LA_IDENTICAL_SAMPLES_BITS-1){1'b0}}, 1'b1, mon_current_data_in});
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ next_mon_clones_nr <= oneplus_mon_clones_nr;
+ else
+ next_mon_clones_nr <= std_logic_vector(to_unsigned(2, LA_IDENTICAL_SAMPLES_BITS));
+ end if;
+ end if;
+ if(data_in_changed = '1') then
+ next_mon_write_address <= one_plus_mon_write_address;
+ else
+ if(not_maximum_mon_clones_nr = '1') then
+ next_mon_write_address <= mon_write_address;
+ else
+ next_mon_write_address <= one_plus_mon_write_address;
+ end if;
+ end if;
+ next_mon_samples_after_trigger <=
+ std_logic_vector(to_unsigned(to_integer(unsigned(mon_samples_after_trigger)+1),
+ LA_MAX_SAMPLES_AFTER_TRIGGER_BITS));
+ next_mon_state <= MON_STATE_AFTER_TRIGGER;
+ else
+ mem_port_A_wen <= '0';
+ next_mon_state <= MON_STATE_DATA_CAPTURED;
+ end if;
+ when MON_STATE_DATA_CAPTURED =>
+ -- Save bt_queue_tail_address
+ mem_port_A_address <= LA_BT_QUEUE_TAIL_ADDRESS_SLV;
+ mem_port_A_data_in <=
+ std_logic_vector(to_unsigned(0, LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS)) & bt_queue_tail_address;
+ -- {{(LA_MEM_WORDLEN_BITS-LA_MEM_ADDRESS_BITS){1'b0}}, bt_queue_tail_address};
+ mem_port_A_wen <= '1';
+ next_mon_state <= MON_STATE_SC_RUN;
+ when MON_STATE_SC_RUN =>
+ next_mon_state <= MON_STATE_WAIT_SC_DONE;
+ next_sc_run_aux <= '1';
+ when MON_STATE_WAIT_SC_DONE =>
+ -- sc_run must already be 1.
+ if(ack_sc_run = '1') then
+ next_sc_run_aux <= '0';
+ end if;
+ if((sc_run_aux = '0') and (sc_done = '1')) then
+ next_mon_state <= MON_STATE_IDLE;
+ else
+ next_mon_state <= MON_STATE_WAIT_SC_DONE;
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ end case;
+ end process;
+
+end monitor_of_verifla_arch;
trunk/openverifla_2.3/vhdl/verifla/monitor_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/send_capture_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/send_capture_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/send_capture_of_verifla.vhd (revision 38)
@@ -0,0 +1,130 @@
+-- 20180820-1740
+-- Author: Laurentiu Duca
+-- License: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+use work.common_internal_verifla.all;
+
+-----------------------------------------------------
+
+entity send_capture_of_verifla is
+ port (clk, rst_l, baud_clk_posedge: in std_logic;
+ sc_run: in std_logic;
+ ack_sc_run, sc_done: out std_logic;
+ mem_port_B_address: out std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ mem_port_B_dout: in std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+ xmit_doneH: in std_logic;
+ xmitH: out std_logic;
+ xmit_dataH: out std_logic_vector(7 downto 0));
+end send_capture_of_verifla;
+
+-----------------------------------------------------
+
+architecture send_capture_of_verifla_arch of send_capture_of_verifla is
+
+ constant LA_MEM_LAST_ADDR_SLV: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0)
+ := std_logic_vector(to_unsigned(LA_MEM_LAST_ADDR, LA_MEM_ADDRESS_BITS));
+ constant USERCMD_RESET: std_logic_vector(7 downto 0) :=x"00";
+ constant USERCMD_RUN: std_logic_vector(7 downto 0) :=x"01";
+ type state_type is (SC_STATE_IDLE, SC_STATE_ACK_SC_RUN,
+ SC_STATE_SET_MEMADDR_TO_READ_FROM, SC_STATE_GET_MEM_OUTPUT_DATA,
+ SC_STATE_SEND_OCTET, SC_STATE_WAIT_OCTET_SENT, SC_STATE_WORD_SENT);
+
+ signal sc_state, next_sc_state: state_type;
+ signal sc_current_address, next_sc_current_address: std_logic_vector(LA_MEM_ADDRESS_BITS-1 downto 0);
+ signal sc_octet_id, next_sc_octet_id:std_logic_vector(LA_MEM_WORDLEN_OCTETS-1 downto 0);
+ signal sc_word_bits, next_sc_word_bits: std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+
+begin
+
+ -- set up next value
+ state_reg: process(clk, rst_l)
+ begin
+ if (rst_l='0') then
+ sc_state<=SC_STATE_IDLE;
+ sc_current_address<=(others => '0');
+ sc_word_bits<=(others => '0');
+ sc_octet_id<= (others => '0');
+ elsif (rising_edge(clk)) then
+ if (baud_clk_posedge = '1') then
+ sc_state <= next_sc_state;
+ sc_current_address <= next_sc_current_address;
+ sc_word_bits <= next_sc_word_bits;
+ sc_octet_id <= next_sc_octet_id;
+ end if;
+ end if;
+ end process;
+
+ -- state machine
+ comb_logic: process(sc_state, sc_run, xmit_doneH,
+ sc_current_address, sc_word_bits, sc_octet_id, mem_port_B_dout)
+ begin
+ -- implicit
+ next_sc_state<=sc_state;
+ ack_sc_run<='0';
+ sc_done<='0';
+ xmit_dataH<=(others => '0');
+ xmitH<='0';
+ mem_port_B_address<=sc_current_address;
+ next_sc_current_address<=sc_current_address;
+ next_sc_word_bits<=sc_word_bits;
+ next_sc_octet_id<=sc_octet_id;
+ case sc_state is
+ when SC_STATE_IDLE =>
+ if(sc_run = '1') then
+ next_sc_state <= SC_STATE_ACK_SC_RUN;
+ next_sc_current_address <= LA_MEM_LAST_ADDR_SLV;
+ else
+ next_sc_state <= SC_STATE_IDLE;
+ end if;
+ when SC_STATE_ACK_SC_RUN =>
+ ack_sc_run <= '1';
+ next_sc_state <= SC_STATE_SET_MEMADDR_TO_READ_FROM;
+ when SC_STATE_SET_MEMADDR_TO_READ_FROM =>
+ mem_port_B_address <= sc_current_address;
+ -- next clock cycle we have memory dout of our read.
+ next_sc_state <= SC_STATE_GET_MEM_OUTPUT_DATA;
+ when SC_STATE_GET_MEM_OUTPUT_DATA =>
+ next_sc_word_bits <= mem_port_B_dout;
+ -- LSB first
+ next_sc_octet_id <= (others => '0');
+ next_sc_state <= SC_STATE_SEND_OCTET;
+ when SC_STATE_SEND_OCTET =>
+ xmit_dataH <= sc_word_bits(7 downto 0);
+ next_sc_word_bits <= x"00" & sc_word_bits(LA_MEM_WORDLEN_BITS-1 downto 8);
+ -- shift_right(unsigned(sc_word_bits),8);
+ xmitH <= '1';
+ next_sc_octet_id <= std_logic_vector(to_unsigned(
+ to_integer(unsigned(sc_octet_id))+1, LA_MEM_WORDLEN_OCTETS));
+ next_sc_state <= SC_STATE_WAIT_OCTET_SENT;
+ when SC_STATE_WAIT_OCTET_SENT =>
+ if(xmit_doneH = '1') then
+ if(to_integer(unsigned(sc_octet_id)) < LA_MEM_WORDLEN_OCTETS) then
+ next_sc_state <= SC_STATE_SEND_OCTET;
+ else
+ next_sc_state <= SC_STATE_WORD_SENT;
+ end if;
+ else
+ next_sc_state <= SC_STATE_WAIT_OCTET_SENT;
+ end if;
+ when SC_STATE_WORD_SENT =>
+ if(to_integer(unsigned(sc_current_address)) > LA_MEM_FIRST_ADDR) then
+ next_sc_current_address <= std_logic_vector(to_unsigned(
+ to_integer(unsigned(sc_current_address))-1, LA_MEM_ADDRESS_BITS));
+ next_sc_state <= SC_STATE_SET_MEMADDR_TO_READ_FROM;
+ else
+ -- done sending all captured data
+ sc_done <= '1';
+ next_sc_state <= SC_STATE_IDLE;
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ end case;
+ end process;
+
+end send_capture_of_verifla_arch;
trunk/openverifla_2.3/vhdl/verifla/send_capture_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/single_pulse_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/single_pulse_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/single_pulse_of_verifla.vhd (revision 38)
@@ -0,0 +1,66 @@
+-----------------------------------------------------
+-- single pulse from a multi-periods-contiguous pulse
+-- date: 20180820-1700
+-- author: Laurentiu Duca
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+-----------------------------------------------------
+
+entity single_pulse_of_verifla is
+port( clk, rst_l: in std_logic;
+ ub: in std_logic;
+ ubsing: out std_logic
+);
+end single_pulse_of_verifla;
+
+-----------------------------------------------------
+
+architecture single_pulse_of_verifla_arch of single_pulse_of_verifla is
+
+ signal next_state, state: std_logic;
+ signal ubsing_reg, next_ubsing_reg: std_logic;
+
+begin
+ ubsing <= ubsing_reg;
+
+ state_reg: process(clk, rst_l)
+ begin
+ if (rst_l='0') then
+ state <= '0';
+ ubsing_reg <= '0';
+ elsif (rising_edge(clk)) then
+ state <= next_state;
+ ubsing_reg <= next_ubsing_reg;
+ end if;
+ end process;
+
+ comb_logic: process(state, ub)
+ begin
+ next_state <= state;
+ next_ubsing_reg <= '0';
+ case state is
+ when '0' =>
+ if (ub = '1') then
+ next_state <= '1';
+ next_ubsing_reg <= '1';
+ end if;
+ when '1' =>
+ if (ub = '0') then
+ next_state <= '0';
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ --next_state <= '0';
+ --next_ubsing_reg <= '0';
+ end case;
+ end process;
+
+end single_pulse_of_verifla_arch;
+
+-----------------------------------------------------
Index: trunk/openverifla_2.3/vhdl/verifla/top_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/top_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/top_of_verifla.vhd (revision 38)
@@ -0,0 +1,71 @@
+-- 20180820-1740
+-- Author: Laurentiu Duca
+-- License: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+use work.common_internal_verifla.all;
+
+-----------------------------------------------------
+
+entity top_of_verifla is
+ port (clk, rst_l, sys_run: in std_logic;
+ data_in: in std_logic_vector(LA_DATA_INPUT_WORDLEN_BITS-1 downto 0);
+ -- Transceiver
+ uart_XMIT_dataH: out std_logic;
+ uart_REC_dataH: in std_logic);
+end top_of_verifla;
+
+-----------------------------------------------------
+
+architecture top_of_verifla_arch of top_of_verifla is
+
+ signal mem_port_A_data_in, mem_port_B_dout: std_logic_vector(LA_MEM_WORDLEN_BITS-1 downto 0);
+ signal mem_port_A_address, mem_port_B_address: std_logic_vector (LA_MEM_ADDRESS_BITS-1 downto 0) ;
+ signal mem_port_A_wen: std_logic;
+ signal user_run: std_logic;
+ signal sc_run, ack_sc_run, sc_done: std_logic;
+ -- Transmitter
+ signal xmit_dataH: std_logic_vector(7 downto 0);
+ signal xmit_doneH, xmitH: std_logic;
+ -- Receiver
+ signal rec_dataH: std_logic_vector(7 downto 0);
+ signal rec_readyH: std_logic;
+ -- Baud
+ signal baud_clk_posedge: std_logic;
+
+begin
+ iUART: entity work.uart_of_verifla(uart_of_verifla_arch)
+ port map(clk, rst_l, baud_clk_posedge,
+ -- Transmitter
+ uart_XMIT_dataH, xmitH, xmit_dataH, xmit_doneH,
+ -- Receiver
+ uart_REC_dataH, rec_dataH, rec_readyH);
+ mi: entity work.memory_of_verifla(memory_of_verifla_arch)
+ port map (addra => mem_port_A_address, addrb => mem_port_B_address,
+ clk=>clk, rst_l=>rst_l,
+ dina=>mem_port_A_data_in, doutb=>mem_port_B_dout,
+ wea=>mem_port_A_wen);
+
+ ci: entity work.computer_input_of_verifla(computer_input_of_verifla_arch)
+ port map (clk, rst_l, rec_dataH, rec_readyH, user_run);
+
+ mon: entity work.monitor_of_verifla(monitor_of_verifla_arch)
+ port map (clk, rst_l,
+ sys_run, user_run, data_in,
+ mem_port_A_address, mem_port_A_data_in, mem_port_A_wen,
+ ack_sc_run, sc_done, sc_run);
+
+ -- send_capture_of_verifla must use the same reset as the uart.
+ sc: entity work.send_capture_of_verifla(send_capture_of_verifla_arch)
+ port map (clk, rst_l, baud_clk_posedge,
+ sc_run, ack_sc_run, sc_done,
+ mem_port_B_address, mem_port_B_dout,
+ xmit_doneH, xmitH, xmit_dataH);
+
+end top_of_verifla_arch;
+
trunk/openverifla_2.3/vhdl/verifla/top_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/u_rec_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/u_rec_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/u_rec_of_verifla.vhd (revision 38)
@@ -0,0 +1,98 @@
+-- date: 20180816_1740
+-- author: Laurentiu Duca
+-- license: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+-----------------------------------------------------
+
+
+entity u_rec_of_verifla is
+port( clk_i, rst_i, baud_clk_posedge: in std_logic;
+ rxd_i: in std_logic; -- serial data in
+ rdy_o: out std_logic;
+ data_o:out std_logic_vector(7 downto 0)
+);
+end u_rec_of_verifla;
+
+-----------------------------------------------------
+
+architecture u_rec_of_verifla_arch of u_rec_of_verifla is
+
+ type state_type is (STA_IDLE, STA_CHECK_START_BIT, STA_RECEIVE);
+ signal rdy_o_reg: std_logic;
+ signal data_o_reg: std_logic_vector(7 downto 0);
+ signal rsr: std_logic_vector(7 downto 0); -- receiving shift reg
+ signal num_of_rec: std_logic_vector(3 downto 0);
+ signal reg_sta: state_type;
+ signal count: std_logic_vector(4 downto 0); -- the counter to count the clk in
+ --signal count_c: std_logic; -- the carry of count
+
+begin
+
+ rdy_o <= rdy_o_reg;
+ data_o <= data_o_reg;
+
+ state_reg: process(clk_i, rst_i)
+ begin
+ if (rst_i='1') then
+ data_o_reg <= x"00";
+ rdy_o_reg <= '0';
+ rsr <= x"00";
+ num_of_rec <= "0000";
+ count <= "00000";
+ --count_c <= '0';
+ reg_sta <= STA_IDLE;
+ elsif (rising_edge(clk_i)) then
+ if(baud_clk_posedge = '1') then
+ case reg_sta is
+ when STA_IDLE =>
+ num_of_rec <= x"0";
+ count <= "00000";
+ if(rxd_i = '0') then
+ reg_sta <= STA_CHECK_START_BIT;
+ else
+ reg_sta <= STA_IDLE;
+ end if;
+ when STA_CHECK_START_BIT =>
+ if(count >= "00111") then
+ count <= "00000";
+ if(rxd_i = '0') then
+ -- has passed 8 clk and rxd_i is still zero,then start bit has been confirmed
+ rdy_o_reg <= '0';
+ reg_sta <= STA_RECEIVE;
+ else
+ reg_sta <= STA_IDLE;
+ end if;
+ else
+ reg_sta <= STA_CHECK_START_BIT;
+ count <= std_logic_vector(unsigned(count)+"00001");
+ end if;
+ when STA_RECEIVE =>
+ count <= std_logic_vector(unsigned('0' & count(3 downto 0))+"00001");
+ if(count(4) = '1') then
+ -- has passed 16 clk after the last bit has been checked,sampling a bit
+ if(num_of_rec <= x"7") then
+ -- sampling the received bit
+ rsr <= rxd_i & rsr(7 downto 1);
+ num_of_rec <= std_logic_vector(unsigned(num_of_rec)+"0001");
+ reg_sta <= STA_RECEIVE;
+ else
+ -- sample the stop bit
+ data_o_reg <= rsr;
+ rdy_o_reg <= '1';
+ reg_sta <= STA_IDLE;
+ end if;
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ end case;
+ end if;
+ end if;
+ end process;
+end u_rec_of_verifla_arch;
trunk/openverifla_2.3/vhdl/verifla/u_rec_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/u_xmit_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/u_xmit_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/u_xmit_of_verifla.vhd (revision 38)
@@ -0,0 +1,87 @@
+-- 20180816-1600
+-- author: Laurentiu Duca
+-- license: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+-----------------------------------------------------
+
+
+entity u_xmit_of_verifla is
+port( clk_i, rst_i, baud_clk_posedge: in std_logic;
+ data_i:in std_logic_vector(7 downto 0);
+ wen_i: in std_logic;
+ txd_o, tre_o: out std_logic
+);
+end u_xmit_of_verifla;
+
+-----------------------------------------------------
+
+architecture u_xmit_of_verifla_arch of u_xmit_of_verifla is
+
+ type state_type is (STA_IDLE, STA_TRANS, STA_FINISH);
+ signal txd_o_reg, tre_o_reg: std_logic;
+ signal tsr: std_logic_vector(7 downto 0); -- transmitting shift register
+ signal num_of_trans: std_logic_vector(3 downto 0);
+ signal reg_sta: state_type;
+ signal count: std_logic_vector(4 downto 0); -- the counter to count the clk in
+ --signal count_c: std_logic; -- the carry of count
+
+begin
+
+ txd_o <= txd_o_reg;
+ tre_o <= tre_o_reg;
+
+ state_reg: process(clk_i, rst_i)
+ begin
+ if (rst_i='1') then
+ tsr <= x"00";
+ txd_o_reg <= '1';
+ tre_o_reg <= '1';
+ num_of_trans <= "0000";
+ --count_c <= '0';
+ count <= "00000";
+ reg_sta <= STA_IDLE;
+ elsif (rising_edge(clk_i)) then
+ if(baud_clk_posedge = '1') then
+ case reg_sta is
+ when STA_IDLE =>
+ num_of_trans <= "0000";
+ count <= "00000";
+ --count_c <= '0';
+ if (wen_i = '1') then
+ tsr <= data_i;
+ tre_o_reg <= '0';
+ txd_o_reg <= '0';
+ reg_sta <= STA_TRANS;
+ else
+ reg_sta <= STA_IDLE;
+ end if;
+ when STA_TRANS =>
+ count <= std_logic_vector(unsigned('0' & count(3 downto 0)) + "00001");
+ if(count(4) = '1') then
+ if(num_of_trans <= x"8") then
+ -- note ,when num_of_trans==8 ,we transmit the stop bit
+ tsr <= '1' & tsr(7 downto 1);
+ txd_o_reg <= tsr(0);
+ num_of_trans <= std_logic_vector(unsigned(num_of_trans) + "0001");
+ reg_sta <= STA_TRANS;
+ else
+ txd_o_reg <= '1';
+ tre_o_reg <= '1';
+ reg_sta <= STA_IDLE;
+ end if;
+ end if;
+ when others =>
+ -- this is forced by the vhdl compiler
+ end case;
+ end if;
+ end if;
+ end process;
+
+end u_xmit_of_verifla_arch;
\ No newline at end of file
trunk/openverifla_2.3/vhdl/verifla/u_xmit_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: trunk/openverifla_2.3/vhdl/verifla/uart_of_verifla.vhd
===================================================================
--- trunk/openverifla_2.3/vhdl/verifla/uart_of_verifla.vhd (nonexistent)
+++ trunk/openverifla_2.3/vhdl/verifla/uart_of_verifla.vhd (revision 38)
@@ -0,0 +1,50 @@
+-- uart_of_verifla
+-- date: 20180816_1740
+-- author: Laurentiu Duca
+-- license: GNU GPL
+-----------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+-----------------------------------------------------
+
+entity uart_of_verifla is
+port( sys_clk, sys_rst_l: in std_logic;
+ baud_clk_posedge: out std_logic;
+ uart_XMIT_dataH: out std_logic;
+ xmitH: in std_logic;
+ xmit_dataH: in std_logic_vector(7 downto 0);
+ xmit_doneH: out std_logic;
+ uart_REC_dataH: in std_logic;
+ rec_dataH: out std_logic_vector(7 downto 0);
+ rec_readyH: out std_logic
+);
+end uart_of_verifla;
+
+-----------------------------------------------------
+
+architecture uart_of_verifla_arch of uart_of_verifla is
+
+ signal sys_rst: std_logic;
+ signal baud_clk_posedge_wire: std_logic;
+
+begin
+ sys_rst <= not sys_rst_l;
+ baud_clk_posedge <= baud_clk_posedge_wire;
+
+ txd1: entity work.u_xmit_of_verifla(u_xmit_of_verifla_arch)
+ port map(clk_i => sys_clk, rst_i =>sys_rst, baud_clk_posedge => baud_clk_posedge_wire,
+ data_i => xmit_dataH, wen_i => xmitH, txd_o => uart_XMIT_dataH, tre_o => xmit_doneH);
+
+ rxd1: entity work.u_rec_of_verifla(u_rec_of_verifla_arch)
+ port map(clk_i => sys_clk, rst_i => sys_rst, baud_clk_posedge => baud_clk_posedge_wire,
+ rxd_i => uart_REC_dataH, rdy_o => rec_readyH, data_o => rec_dataH);
+
+ baud1: entity work.baud_of_verifla(baud_of_verifla_arch)
+ port map(sys_clk => sys_clk, sys_rst_l => sys_rst_l, baud_clk_posedge => baud_clk_posedge_wire);
+
+end uart_of_verifla_arch;
trunk/openverifla_2.3/vhdl/verifla/uart_of_verifla.vhd
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property