OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

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  • This comparison shows the changes necessary to convert path 
    /or1200_soc/trunk/boards/de1_board/sim/tests/boot_rom_2
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/boot_rom_2.mpf
356,43 → 356,43
Project_SortMethod = unused
Project_Files_Count = 19
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
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Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
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Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
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Project_File_4 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
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Project_File_5 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_6 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239905312 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_7 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1239838062 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
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Project_File_8 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
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Project_File_9 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
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Project_File_10 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
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Project_File_11 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
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Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
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Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238115510 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
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Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
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Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838052 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239838051 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
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Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
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Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1265135404 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1219274282 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1265136509 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_2/tb_dut.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1265140756 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
/tb_dut.v
11,7 → 11,7
input tb_rst
);
wire [3:0] boot_strap = 4'b0010;
wire [3:0] boot_strap = 4'b1100;
// --------------------------------------------------------------------
/boot_rom_2.cr.mti
41,13 → 41,6
Top level modules:
soc_mem_bank_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_top
 
Top level modules:
soc_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_2
76,19 → 69,19
Top level modules:
tb_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_1
-- Compiling module soc_peripherals
 
Top level modules:
boot_rom_1
soc_peripherals
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_peripherals
-- Compiling module boot_rom_1
 
Top level modules:
soc_peripherals
boot_rom_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
97,19 → 90,19
Top level modules:
boot_rom_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module top
-- Compiling module boot_vector_rom
 
Top level modules:
top
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_vector_rom
-- Compiling module top
 
Top level modules:
boot_vector_rom
top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
118,7 → 111,7
Top level modules:
IS61LV25616
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_2/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_2/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 

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