OpenCores
URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

Subversion Repositories or1200_soc

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /or1200_soc/trunk/boards/de1_board/sim/tests/debug
    from Rev 23 to Rev 24
    ↔ Reverse comparison
  •

Rev 23 → Rev 24

/debug.cr.mti
1,5 → 1,12
C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_vector_rom/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_vector_rom/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_system
 
Top level modules:
20,13 → 27,6
Top level modules:
soc_gpio
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_ram
97,6 → 97,13
Top level modules:
boot_rom_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_adv_dbg.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_adv_dbg.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_adv_dbg
 
Top level modules:
soc_adv_dbg
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_2
111,13 → 118,6
Top level modules:
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module top
 
Top level modules:
top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module IS61LV25616
/wave.do
1,71 → 1,117
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic -radix hexadecimal /tb_top/tb_clk
add wave -noupdate -format Logic -radix hexadecimal /tb_top/tb_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r0
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r1
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r2
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r3
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r4
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r5
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r6
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r7
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r8
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r9
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r10
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r11
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r12
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r13
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r14
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r15
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r16
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r17
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r18
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r19
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r20
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r21
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r22
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r23
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r24
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r25
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r26
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r27
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r28
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r29
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r30
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r31
add wave -noupdate -divider OR1200
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_ack_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_err_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_dat_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_cyc_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_we_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_cab_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_ack_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_err_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_dat_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_cyc_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_we_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_cab_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_ack_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_adr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_bte_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_cab_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_cti_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_cyc_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_err_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_sel_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_stb_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/adbg_wb_we_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/cpu0_rst_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_ack_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_adr_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_bp_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_dat_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_is_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_lss_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_stall_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_stb_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_we_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dbg_wp_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_ack_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_cab_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_cyc_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_err_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_remap_adr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_remap_nibble
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_remap_select
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_sel_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_stb_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/dwb_we_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_ack_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_cab_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_cyc_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_dat_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_err_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_remap_adr_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_remap_nibble
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_remap_select
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_sel_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_stb_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/iwb_we_o
add wave -noupdate -divider {New Divider}
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/capture_dr
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/capture_dr_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_ack_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_addr_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_bp_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_clk_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_data_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_data_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_rst_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_stall_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_stb_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/cpu0_we_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/debug_rst
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/debug_select
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/debug_select_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/debug_tdi
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/debug_tdo
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/drck
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/jtag_tck
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/jtag_tdi
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/jtag_tdo
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/jtag_tms
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/jtag_trst
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/pause_dr_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/rst_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/shift_dr
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/shift_dr_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/tck2
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/tck_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/tdi_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/tdo_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/update2
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/update_dr
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/update_dr_i
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_ack_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_adr_o
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_bte_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_cab_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_clk_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_cti_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_cyc_o
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_dat_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_dat_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_err_i
add wave -noupdate -format Literal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_sel_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_stb_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/wb_we_o
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/xcapture
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/xselect
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/xshift
add wave -noupdate -format Logic /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_soc_adv_dbg/xupdate
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {12201000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
WaveRestoreCursors {{Cursor 1} {4517800 ps} 0}
configure wave -namecolwidth 226
configure wave -valuecolwidth 115
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
76,5 → 122,6
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom {10012500 ps} {15262500 ps}
WaveRestoreZoom {0 ps} {21 us}
/debug.mpf
46,6 → 46,8
 
 
work = work
adv_debug_sys = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/libs/adv_debug_sys
altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
158,7 → 160,7
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
resolution = 1ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
354,45 → 356,47
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 19
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838063 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1118235516 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238545534 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1239838051 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Files_Count = 20
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_vector_rom/tb_dut.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1265139252 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838063 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1118235516 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238115511 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1265136600 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1239905312 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1265222099 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1239838062 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1265220405 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838063 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838063 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238111450 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238115510 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838052 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1219274282 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238111450 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_adv_dbg.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1265232852 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 19 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238115510 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1265221383 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1219274282 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1265136509 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
/do_sim.do
1,6 → 1,6
vsim -f ../../../libs/library_files.txt work.tb_top
 
view wave
do ./wave.do
# view wave
# do ./wave.do
 
run 20us

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