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URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

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Rev 22 → Rev 23

/de1_board/sim/tests/boot_rom_0/boot_rom_0.mpf
0,0 → 1,430
; Copyright 1991-2007 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
 
; Xilinx Primitive Libraries
;
; VHDL Section
; unisim = $MODEL_TECH/../xilinx/vhdl/unisim
; unimacro = $MODEL_TECH/../xilinx/vhdl/unimacro
; simprim = $MODEL_TECH/../xilinx/vhdl/simprim
; xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
; aim = $MODEL_TECH/../xilinx/vhdl/aim
; pls = $MODEL_TECH/../xilinx/vhdl/pls
; cpld = $MODEL_TECH/../xilinx/vhdl/cpld
 
; Verilog Section
; unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
; unimacro_ver = $MODEL_TECH/../xilinx/verilog/unimacro_ver
; uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
; simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
; xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
; aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
; cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
 
; or1200_soc libraries
gpio = ../../../libs/gpio
or1200 = ../../../libs/or1200
sim = ../../../libs/sim
uart16550 = ../../../libs/uart16550
wb_conmax = ../../../libs/wb_conmax
wb_size_bridge = ../../../libs/wb_size_bridge
 
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 20 us
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
 
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = hexadecimal
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript.txt
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
[lmc]
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
 
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 19
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838063 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1118235516 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238115511 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239905312 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1239838062 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838063 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238111450 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238115510 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838052 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_0/tb_dut.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1264815912 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1219274282 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238545534 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
Project_Major_Version = 6
Project_Minor_Version = 5
/de1_board/sim/tests/boot_rom_0/tb_dut.v
0,0 → 1,233
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`include "timescale.v"
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
wire [3:0] boot_strap = 4'b0000;
// --------------------------------------------------------------------
// de1 wires
wire [1:0] clock_24;
wire [1:0] clock_27;
wire clock_50;
wire ext_clock;
wire [3:0] key;
wire [9:0] sw;
wire [6:0] hex0;
wire [6:0] hex1;
wire [6:0] hex2;
wire [6:0] hex3;
wire [7:0] ledg;
wire [9:0] ledr;
wire uart_txd;
wire uart_rxd;
wire [15:0] dram_dq;
wire [11:0] dram_addr;
wire dram_ldqm;
wire dram_udqm;
wire dram_we_n;
wire dram_cas_n;
wire dram_ras_n;
wire dram_cs_n;
wire dram_ba_0;
wire dram_ba_1;
wire dram_clk;
wire dram_cke;
wire [7:0] fl_dq;
wire [21:0] fl_addr;
wire fl_we_n;
wire fl_rst_n;
wire fl_oe_n;
wire fl_ce_n;
wire [15:0] sram_dq;
wire [17:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire sd_dat;
wire sd_dat3;
wire sd_cmd;
wire sd_clk;
wire i2c_sdat;
wire i2c_sclk;
wire ps2_dat;
wire ps2_clk;
wire tdi;
wire tck;
wire tcs;
wire tdo;
wire vga_hs;
wire vga_vs;
wire [3:0] vga_r;
wire [3:0] vga_g;
wire [3:0] vga_b;
wire aud_adclrck;
wire aud_adcdat;
wire aud_daclrck;
wire aud_dacdat;
wire aud_bclk;
wire aud_xck;
wire [35:0] gpio_0;
wire [35:0] gpio_1;
// --------------------------------------------------------------------
// fpga top
assign clock_24 = {1'b0, tb_clk};
assign sw = {6'b000000, boot_strap};
assign key = {3'b000, ~tb_rst};
top
i_top(
//////////////////////// Clock Input ////////////////////////
.clock_24( clock_24 ), // 24 MHz
.clock_27(clock_27), // 27 MHz
.clock_50(clock_50), // 50 MHz
.ext_clock(ext_clock), // External Clock
//////////////////////// Push Button ////////////////////////
.key( key ), // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
.sw( sw ), // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
.hex0(hex0), // Seven Segment Digit 0
.hex1(hex1), // Seven Segment Digit 1
.hex2(hex2), // Seven Segment Digit 2
.hex3(hex3), // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
.ledg(ledg), // LED Green[7:0]
.ledr(ledr), // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
.uart_txd(uart_txd), // UART Transmitter
.uart_rxd(uart_rxd), // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
.dram_dq(dram_dq), // SDRAM Data bus 16 Bits
.dram_addr(dram_addr), // SDRAM Address bus 12 Bits
.dram_ldqm(dram_ldqm), // SDRAM Low-byte Data Mask
.dram_udqm(dram_udqm), // SDRAM High-byte Data Mask
.dram_we_n(dram_we_n), // SDRAM Write Enable
.dram_cas_n(dram_cas_n), // SDRAM Column Address Strobe
.dram_ras_n(dram_ras_n), // SDRAM Row Address Strobe
.dram_cs_n(dram_cs_n), // SDRAM Chip Select
.dram_ba_0(dram_ba_0), // SDRAM Bank Address 0
.dram_ba_1(dram_ba_1), // SDRAM Bank Address 0
.dram_clk(dram_clk), // SDRAM Clock
.dram_cke(dram_cke), // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
.fl_dq(fl_dq), // FLASH Data bus 8 Bits
.fl_addr(fl_addr), // FLASH Address bus 22 Bits
.fl_we_n(fl_we_n), // FLASH Write Enable
.fl_rst_n(fl_rst_n), // FLASH Reset
.fl_oe_n(fl_oe_n), // FLASH Output Enable
.fl_ce_n(fl_ce_n), // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
.sram_dq(sram_dq), // SRAM Data bus 16 Bits
.sram_addr(sram_addr), // SRAM Address bus 18 Bits
.sram_ub_n(sram_ub_n), // SRAM High-byte Data Mask
.sram_lb_n(sram_lb_n), // SRAM Low-byte Data Mask
.sram_we_n(sram_we_n), // SRAM Write Enable
.sram_ce_n(sram_ce_n), // SRAM Chip Enable
.sram_oe_n(sram_oe_n), // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
.sd_dat(sd_dat), // SD Card Data
.sd_dat3(sd_dat3), // SD Card Data 3
.sd_cmd(sd_cmd), // SD Card Command Signal
.sd_clk(sd_clk), // SD Card Clock
//////////////////////// I2C ////////////////////////////////
.i2c_sdat(i2c_sdat), // I2C Data
.i2c_sclk(i2c_sclk), // I2C Clock
//////////////////////// PS2 ////////////////////////////////
.ps2_dat(ps2_dat), // PS2 Data
.ps2_clk(ps2_clk), // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
.tdi(tdi), // CPLD -> FPGA (data in)
.tck(tck), // CPLD -> FPGA (clk)
.tcs(tcs), // CPLD -> FPGA (CS)
.tdo(tdo), // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
.vga_hs(vga_hs), // VGA H_SYNC
.vga_vs(vga_vs), // VGA V_SYNC
.vga_r(vga_r), // VGA Red[3:0]
.vga_g(vga_g), // VGA Green[3:0]
.vga_b(vga_b), // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
.aud_adclrck(aud_adclrck), // Audio CODEC ADC LR Clock
.aud_adcdat(aud_adcdat), // Audio CODEC ADC Data
.aud_daclrck(aud_daclrck), // Audio CODEC DAC LR Clock
.aud_dacdat(aud_dacdat), // Audio CODEC DAC Data
.aud_bclk(aud_bclk), // Audio CODEC Bit-Stream Clock
.aud_xck(aud_xck), // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
.gpio_0(gpio_0), // GPIO Connection 0
.gpio_1(gpio_1) // GPIO Connection 1
);
 
// --------------------------------------------------------------------
// IS61LV25616
IS61LV25616 i_IS61LV25616 (
.A(sram_addr),
.IO(sram_dq),
.CE_(sram_ce_n),
.OE_(sram_oe_n),
.WE_(sram_we_n),
.LB_(sram_lb_n),
.UB_(sram_ub_n)
);
// --------------------------------------------------------------------
// s29al032d_00
s29al032d_00 #( .UserPreload(1'b1), .mem_file_name( "../../../sw/load_this_to_ram/boot_rom_2.txt" ) )
i_s29al032d_00(
.A21(fl_addr[21]),
.A20(fl_addr[20]),
.A19(fl_addr[19]),
.A18(fl_addr[18]),
.A17(fl_addr[17]),
.A16(fl_addr[16]),
.A15(fl_addr[15]),
.A14(fl_addr[14]),
.A13(fl_addr[13]),
.A12(fl_addr[12]),
.A11(fl_addr[11]),
.A10(fl_addr[10]),
.A9(fl_addr[9]),
.A8(fl_addr[8]),
.A7(fl_addr[7]),
.A6(fl_addr[6]),
.A5(fl_addr[5]),
.A4(fl_addr[4]),
.A3(fl_addr[3]),
.A2(fl_addr[2]),
.A1(fl_addr[1]),
.A0(fl_addr[0]),
 
.DQ7(fl_dq[7]),
.DQ6(fl_dq[6]),
.DQ5(fl_dq[5]),
.DQ4(fl_dq[4]),
.DQ3(fl_dq[3]),
.DQ2(fl_dq[2]),
.DQ1(fl_dq[1]),
.DQ0(fl_dq[0]),
 
.CENeg(fl_ce_n),
.OENeg(fl_oe_n),
.WENeg(fl_we_n),
.RESETNeg(fl_rst_n),
.ACC(),
.RY()
);
endmodule
 
/de1_board/sim/tests/boot_rom_0/boot_rom_0.cr.mti
0,0 → 1,135
C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_system
 
Top level modules:
soc_system
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module s29al032d_00
-- Compiling module BUFFER
 
Top level modules:
s29al032d_00
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_gpio
 
Top level modules:
soc_gpio
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_ram
 
Top level modules:
soc_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_registers
 
Top level modules:
soc_registers
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_1
 
Top level modules:
soc_mem_bank_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_top
 
Top level modules:
soc_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_2
 
Top level modules:
soc_mem_bank_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_3
 
Top level modules:
soc_mem_bank_3
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_0
 
Top level modules:
boot_rom_0
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_top
 
Top level modules:
tb_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_peripherals
 
Top level modules:
soc_peripherals
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_1
 
Top level modules:
boot_rom_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_2
 
Top level modules:
boot_rom_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_vector_rom
 
Top level modules:
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module top
 
Top level modules:
top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module IS61LV25616
 
Top level modules:
IS61LV25616
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_0/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/boot_rom_0/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_boot
 
Top level modules:
soc_boot
 
} {} {}}
/de1_board/sim/tests/boot_rom_0/do_sim.do
0,0 → 1,6
vsim -f ../../../libs/library_files.txt work.tb_top
 
view wave
do ./wave.do
 
run 20us
/de1_board/sim/tests/boot_rom_2/boot_rom_2.mpf
0,0 → 1,430
; Copyright 1991-2007 Mentor Graphics Corporation
;
; All Rights Reserved.
;
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
;
 
[Library]
std = $MODEL_TECH/../std
ieee = $MODEL_TECH/../ieee
verilog = $MODEL_TECH/../verilog
vital2000 = $MODEL_TECH/../vital2000
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
 
; Xilinx Primitive Libraries
;
; VHDL Section
; unisim = $MODEL_TECH/../xilinx/vhdl/unisim
; unimacro = $MODEL_TECH/../xilinx/vhdl/unimacro
; simprim = $MODEL_TECH/../xilinx/vhdl/simprim
; xilinxcorelib = $MODEL_TECH/../xilinx/vhdl/xilinxcorelib
; aim = $MODEL_TECH/../xilinx/vhdl/aim
; pls = $MODEL_TECH/../xilinx/vhdl/pls
; cpld = $MODEL_TECH/../xilinx/vhdl/cpld
 
; Verilog Section
; unisims_ver = $MODEL_TECH/../xilinx/verilog/unisims_ver
; unimacro_ver = $MODEL_TECH/../xilinx/verilog/unimacro_ver
; uni9000_ver = $MODEL_TECH/../xilinx/verilog/uni9000_ver
; simprims_ver = $MODEL_TECH/../xilinx/verilog/simprims_ver
; xilinxcorelib_ver = $MODEL_TECH/../xilinx/verilog/xilinxcorelib_ver
; aim_ver = $MODEL_TECH/../xilinx/verilog/aim_ver
; cpld_ver = $MODEL_TECH/../xilinx/verilog/cpld_ver
 
; or1200_soc libraries
gpio = ../../../libs/gpio
or1200 = ../../../libs/or1200
sim = ../../../libs/sim
uart16550 = ../../../libs/uart16550
wb_conmax = ../../../libs/wb_conmax
wb_size_bridge = ../../../libs/wb_size_bridge
 
 
work = work
[vcom]
; VHDL93 variable selects language version as the default.
; Default is VHDL-2002.
; Value of 0 or 1987 for VHDL-1987.
; Value of 1 or 1993 for VHDL-1993.
; Default or value of 2 or 2002 for VHDL-2002.
VHDL93 = 2002
 
; Show source line containing error. Default is off.
; Show_source = 1
 
; Turn off unbound-component warnings. Default is on.
; Show_Warning1 = 0
 
; Turn off process-without-a-wait-statement warnings. Default is on.
; Show_Warning2 = 0
 
; Turn off null-range warnings. Default is on.
; Show_Warning3 = 0
 
; Turn off no-space-in-time-literal warnings. Default is on.
; Show_Warning4 = 0
 
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
; Show_Warning5 = 0
 
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
; Optimize_1164 = 0
 
; Turn on resolving of ambiguous function overloading in favor of the
; "explicit" function declaration (not the one automatically created by
; the compiler for each type declaration). Default is off.
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
; will match the behavior of synthesis tools.
Explicit = 1
 
; Turn off acceleration of the VITAL packages. Default is to accelerate.
; NoVital = 1
 
; Turn off VITAL compliance checking. Default is checking on.
; NoVitalCheck = 1
 
; Ignore VITAL compliance checking errors. Default is to not ignore.
; IgnoreVitalErrors = 1
 
; Turn off VITAL compliance checking warnings. Default is to show warnings.
; Show_VitalChecksWarnings = 0
 
; Keep silent about case statement static warnings.
; Default is to give a warning.
; NoCaseStaticError = 1
 
; Keep silent about warnings caused by aggregates that are not locally static.
; Default is to give a warning.
; NoOthersStaticError = 1
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "Loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on some limited synthesis rule compliance checking. Checks only:
; -- signals used (read) by a process must be in the sensitivity list
; CheckSynthesis = 1
 
; Activate optimizations on expressions that do not involve signals,
; waits, or function/procedure/task invocations. Default is off.
; ScalarOpts = 1
 
; Require the user to specify a configuration for all bindings,
; and do not generate a compile time default binding for the
; component. This will result in an elaboration error of
; 'component not bound' if the user fails to do so. Avoids the rare
; issue of a false dependency upon the unused default binding.
; RequireConfigForAllDefaultBinding = 1
 
; Inhibit range checking on subscripts of arrays. Range checking on
; scalars defined with subtypes is inhibited by default.
; NoIndexCheck = 1
 
; Inhibit range checks on all (implicit and explicit) assignments to
; scalar objects defined with subtypes.
; NoRangeCheck = 1
 
[vlog]
 
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
; NoDebug = 1
 
; Turn off "loading..." messages. Default is messages on.
; Quiet = 1
 
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
; Default is off.
; Hazard = 1
 
; Turn on converting regular Verilog identifiers to uppercase. Allows case
; insensitivity for module names. Default is no conversion.
; UpCase = 1
 
; Turn on incremental compilation of modules. Default is off.
; Incremental = 1
 
; Turns on lint-style checking.
; Show_Lint = 1
 
[vsim]
; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps
 
; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default
 
; Default run length
RunLength = 20 us
 
; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000
 
; Directive to license manager:
; vhdl Immediately reserve a VHDL license
; vlog Immediately reserve a Verilog license
; plus Immediately reserve a VHDL and Verilog license
; nomgc Do not look for Mentor Graphics Licenses
; nomti Do not look for Model Technology Licenses
; noqueue Do not wait in the license queue when a license isn't available
; viewsim Try for viewer license but accept simulator license(s) instead
; of queuing for viewer license
; License = plus
 
; Stop the simulator after a VHDL/Verilog assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 3
 
; Assertion Message Format
; %S - Severity Level
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %% - print '%' character
; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
 
; Assertion File - alternate file for storing VHDL/Verilog assertion messages
; AssertFile = assert.log
 
; Default radix for all windows and commands...
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = hexadecimal
 
; VSIM Startup command
; Startup = do startup.do
 
; File for saving command transcript
TranscriptFile = transcript.txt
 
; File for saving command history
; CommandHistory = cmdhist.log
 
; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /
 
; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example, sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :
 
; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1
 
; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze
 
; If zero, open files when elaborated; otherwise, open files on
; first read or write. Default is 0.
; DelayFileOpen = 1
 
; Control VHDL files opened for write.
; 0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0
 
; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
; 0 = unlimited
ConcurrentFileLimit = 40
 
; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0
 
; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1
 
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1
 
; Control the format of the (VHDL) FOR generate statement label
; for each iteration. Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes. The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type). Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d
 
; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0
 
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
 
; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave
; DefaultRestartOptions = -force
 
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000
 
; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0
 
; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1
 
; WLF file time limit. Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time. When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0
 
; WLF file size limit. Limit WLF file size, as closely as possible,
; to the specified number of megabytes. If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000
 
; Specify whether or not a WLF file should be deleted when the
; simulation ends. A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1
 
[lmc]
 
[msg_system]
; Change a message severity or suppress a message.
; The format is: <msg directive> = <msg number>[,<msg number>...]
; Examples:
; note = 3009
; warning = 3033
; error = 3010,3016
; fatal = 3016,3033
; suppress = 3009,3016,3043
; The command verror <msg number> can be used to get the complete
; description of a message.
 
; Control transcripting of elaboration/runtime messages.
; The default is to have messages appear in the transcript and
; recorded in the wlf file (messages that are recorded in the
; wlf file can be viewed in the MsgViewer). The other settings
; are to send messages only to the transcript or only to the
; wlf file. The valid values are
; both {default}
; tran {transcript only}
; wlf {wlf file only}
; msgmode = both
 
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 19
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838063 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1118235516 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1238115511 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239905312 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1239838062 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838063 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238111450 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238019418 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238115510 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238534422 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838052 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239838051 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1219274282 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238545534 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
SYSTEMVERILOG_DoubleClick = Edit
SYSTEMVERILOG_CustomDoubleClick =
VHDL_DoubleClick = Edit
VHDL_CustomDoubleClick =
PSL_DoubleClick = Edit
PSL_CustomDoubleClick =
TEXT_DoubleClick = Edit
TEXT_CustomDoubleClick =
SYSTEMC_DoubleClick = Edit
SYSTEMC_CustomDoubleClick =
TCL_DoubleClick = Edit
TCL_CustomDoubleClick =
MACRO_DoubleClick = Edit
MACRO_CustomDoubleClick =
VCD_DoubleClick = Edit
VCD_CustomDoubleClick =
SDF_DoubleClick = Edit
SDF_CustomDoubleClick =
XML_DoubleClick = Edit
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
Project_Major_Version = 6
Project_Minor_Version = 5
/de1_board/sim/tests/boot_rom_2/wave.do
0,0 → 1,80
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic -radix hexadecimal /tb_top/tb_clk
add wave -noupdate -format Logic -radix hexadecimal /tb_top/tb_rst
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r0
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r1
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r2
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r3
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r4
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r5
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r6
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r7
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r8
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r9
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r10
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r11
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r12
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r13
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r14
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r15
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r16
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r17
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r18
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r19
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r20
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r21
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r22
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r23
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r24
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r25
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r26
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r27
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r28
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r29
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r30
add wave -noupdate -format Literal -radix hexadecimal /tb_top/r31
add wave -noupdate -divider OR1200
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_ack_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_err_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_dat_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_cyc_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_we_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/iwb_cab_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_clk_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_rst_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_ack_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_err_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_rty_i
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_dat_i
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_cyc_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_stb_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_adr_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_we_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_sel_o
add wave -noupdate -format Literal -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_dat_o
add wave -noupdate -format Logic -radix hexadecimal /tb_top/i_tb_dut/i_top/i_or1200_soc_top/i_or1200_top/dwb_cab_o
add wave -noupdate -divider {New Divider}
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {12201000 ps} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
update
WaveRestoreZoom {10012500 ps} {15262500 ps}
/de1_board/sim/tests/boot_rom_2/tb_dut.v
0,0 → 1,233
// --------------------------------------------------------------------
//
// --------------------------------------------------------------------
 
 
`include "timescale.v"
 
 
module tb_dut(
input tb_clk,
input tb_rst
);
wire [3:0] boot_strap = 4'b0010;
// --------------------------------------------------------------------
// de1 wires
wire [1:0] clock_24;
wire [1:0] clock_27;
wire clock_50;
wire ext_clock;
wire [3:0] key;
wire [9:0] sw;
wire [6:0] hex0;
wire [6:0] hex1;
wire [6:0] hex2;
wire [6:0] hex3;
wire [7:0] ledg;
wire [9:0] ledr;
wire uart_txd;
wire uart_rxd;
wire [15:0] dram_dq;
wire [11:0] dram_addr;
wire dram_ldqm;
wire dram_udqm;
wire dram_we_n;
wire dram_cas_n;
wire dram_ras_n;
wire dram_cs_n;
wire dram_ba_0;
wire dram_ba_1;
wire dram_clk;
wire dram_cke;
wire [7:0] fl_dq;
wire [21:0] fl_addr;
wire fl_we_n;
wire fl_rst_n;
wire fl_oe_n;
wire fl_ce_n;
wire [15:0] sram_dq;
wire [17:0] sram_addr;
wire sram_ub_n;
wire sram_lb_n;
wire sram_we_n;
wire sram_ce_n;
wire sram_oe_n;
wire sd_dat;
wire sd_dat3;
wire sd_cmd;
wire sd_clk;
wire i2c_sdat;
wire i2c_sclk;
wire ps2_dat;
wire ps2_clk;
wire tdi;
wire tck;
wire tcs;
wire tdo;
wire vga_hs;
wire vga_vs;
wire [3:0] vga_r;
wire [3:0] vga_g;
wire [3:0] vga_b;
wire aud_adclrck;
wire aud_adcdat;
wire aud_daclrck;
wire aud_dacdat;
wire aud_bclk;
wire aud_xck;
wire [35:0] gpio_0;
wire [35:0] gpio_1;
// --------------------------------------------------------------------
// fpga top
assign clock_24 = {1'b0, tb_clk};
assign sw = {6'b000000, boot_strap};
assign key = {3'b000, ~tb_rst};
top
i_top(
//////////////////////// Clock Input ////////////////////////
.clock_24( clock_24 ), // 24 MHz
.clock_27(clock_27), // 27 MHz
.clock_50(clock_50), // 50 MHz
.ext_clock(ext_clock), // External Clock
//////////////////////// Push Button ////////////////////////
.key( key ), // Pushbutton[3:0]
//////////////////////// DPDT Switch ////////////////////////
.sw( sw ), // Toggle Switch[9:0]
//////////////////////// 7-SEG Dispaly ////////////////////////
.hex0(hex0), // Seven Segment Digit 0
.hex1(hex1), // Seven Segment Digit 1
.hex2(hex2), // Seven Segment Digit 2
.hex3(hex3), // Seven Segment Digit 3
//////////////////////////// LED ////////////////////////////
.ledg(ledg), // LED Green[7:0]
.ledr(ledr), // LED Red[9:0]
//////////////////////////// UART ////////////////////////////
.uart_txd(uart_txd), // UART Transmitter
.uart_rxd(uart_rxd), // UART Receiver
/////////////////////// SDRAM Interface ////////////////////////
.dram_dq(dram_dq), // SDRAM Data bus 16 Bits
.dram_addr(dram_addr), // SDRAM Address bus 12 Bits
.dram_ldqm(dram_ldqm), // SDRAM Low-byte Data Mask
.dram_udqm(dram_udqm), // SDRAM High-byte Data Mask
.dram_we_n(dram_we_n), // SDRAM Write Enable
.dram_cas_n(dram_cas_n), // SDRAM Column Address Strobe
.dram_ras_n(dram_ras_n), // SDRAM Row Address Strobe
.dram_cs_n(dram_cs_n), // SDRAM Chip Select
.dram_ba_0(dram_ba_0), // SDRAM Bank Address 0
.dram_ba_1(dram_ba_1), // SDRAM Bank Address 0
.dram_clk(dram_clk), // SDRAM Clock
.dram_cke(dram_cke), // SDRAM Clock Enable
//////////////////////// Flash Interface ////////////////////////
.fl_dq(fl_dq), // FLASH Data bus 8 Bits
.fl_addr(fl_addr), // FLASH Address bus 22 Bits
.fl_we_n(fl_we_n), // FLASH Write Enable
.fl_rst_n(fl_rst_n), // FLASH Reset
.fl_oe_n(fl_oe_n), // FLASH Output Enable
.fl_ce_n(fl_ce_n), // FLASH Chip Enable
//////////////////////// SRAM Interface ////////////////////////
.sram_dq(sram_dq), // SRAM Data bus 16 Bits
.sram_addr(sram_addr), // SRAM Address bus 18 Bits
.sram_ub_n(sram_ub_n), // SRAM High-byte Data Mask
.sram_lb_n(sram_lb_n), // SRAM Low-byte Data Mask
.sram_we_n(sram_we_n), // SRAM Write Enable
.sram_ce_n(sram_ce_n), // SRAM Chip Enable
.sram_oe_n(sram_oe_n), // SRAM Output Enable
//////////////////// SD Card Interface ////////////////////////
.sd_dat(sd_dat), // SD Card Data
.sd_dat3(sd_dat3), // SD Card Data 3
.sd_cmd(sd_cmd), // SD Card Command Signal
.sd_clk(sd_clk), // SD Card Clock
//////////////////////// I2C ////////////////////////////////
.i2c_sdat(i2c_sdat), // I2C Data
.i2c_sclk(i2c_sclk), // I2C Clock
//////////////////////// PS2 ////////////////////////////////
.ps2_dat(ps2_dat), // PS2 Data
.ps2_clk(ps2_clk), // PS2 Clock
//////////////////// USB JTAG link ////////////////////////////
.tdi(tdi), // CPLD -> FPGA (data in)
.tck(tck), // CPLD -> FPGA (clk)
.tcs(tcs), // CPLD -> FPGA (CS)
.tdo(tdo), // FPGA -> CPLD (data out)
//////////////////////// VGA ////////////////////////////
.vga_hs(vga_hs), // VGA H_SYNC
.vga_vs(vga_vs), // VGA V_SYNC
.vga_r(vga_r), // VGA Red[3:0]
.vga_g(vga_g), // VGA Green[3:0]
.vga_b(vga_b), // VGA Blue[3:0]
//////////////////// Audio CODEC ////////////////////////////
.aud_adclrck(aud_adclrck), // Audio CODEC ADC LR Clock
.aud_adcdat(aud_adcdat), // Audio CODEC ADC Data
.aud_daclrck(aud_daclrck), // Audio CODEC DAC LR Clock
.aud_dacdat(aud_dacdat), // Audio CODEC DAC Data
.aud_bclk(aud_bclk), // Audio CODEC Bit-Stream Clock
.aud_xck(aud_xck), // Audio CODEC Chip Clock
//////////////////////// GPIO ////////////////////////////////
.gpio_0(gpio_0), // GPIO Connection 0
.gpio_1(gpio_1) // GPIO Connection 1
);
 
// --------------------------------------------------------------------
// IS61LV25616
IS61LV25616 i_IS61LV25616 (
.A(sram_addr),
.IO(sram_dq),
.CE_(sram_ce_n),
.OE_(sram_oe_n),
.WE_(sram_we_n),
.LB_(sram_lb_n),
.UB_(sram_ub_n)
);
// --------------------------------------------------------------------
// s29al032d_00
s29al032d_00 #( .UserPreload(1'b1), .mem_file_name( "../../../sw/load_this_to_ram/boot_rom_2.txt" ) )
i_s29al032d_00(
.A21(fl_addr[21]),
.A20(fl_addr[20]),
.A19(fl_addr[19]),
.A18(fl_addr[18]),
.A17(fl_addr[17]),
.A16(fl_addr[16]),
.A15(fl_addr[15]),
.A14(fl_addr[14]),
.A13(fl_addr[13]),
.A12(fl_addr[12]),
.A11(fl_addr[11]),
.A10(fl_addr[10]),
.A9(fl_addr[9]),
.A8(fl_addr[8]),
.A7(fl_addr[7]),
.A6(fl_addr[6]),
.A5(fl_addr[5]),
.A4(fl_addr[4]),
.A3(fl_addr[3]),
.A2(fl_addr[2]),
.A1(fl_addr[1]),
.A0(fl_addr[0]),
 
.DQ7(fl_dq[7]),
.DQ6(fl_dq[6]),
.DQ5(fl_dq[5]),
.DQ4(fl_dq[4]),
.DQ3(fl_dq[3]),
.DQ2(fl_dq[2]),
.DQ1(fl_dq[1]),
.DQ0(fl_dq[0]),
 
.CENeg(fl_ce_n),
.OENeg(fl_oe_n),
.WENeg(fl_we_n),
.RESETNeg(fl_rst_n),
.ACC(),
.RY()
);
endmodule
 
/de1_board/sim/tests/boot_rom_2/do_sim.do
0,0 → 1,6
vsim -f ../../../libs/library_files.txt work.tb_top
 
view wave
do ./wave.do
 
run 20us
/de1_board/sim/tests/boot_rom_2/boot_rom_2.cr.mti
0,0 → 1,135
C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_system
 
Top level modules:
soc_system
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module s29al032d_00
-- Compiling module BUFFER
 
Top level modules:
s29al032d_00
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_gpio
 
Top level modules:
soc_gpio
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_ram
 
Top level modules:
soc_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_registers
 
Top level modules:
soc_registers
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_1
 
Top level modules:
soc_mem_bank_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_top
 
Top level modules:
soc_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_2
 
Top level modules:
soc_mem_bank_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_3
 
Top level modules:
soc_mem_bank_3
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_0
 
Top level modules:
boot_rom_0
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_top
 
Top level modules:
tb_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_1
 
Top level modules:
boot_rom_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_peripherals
 
Top level modules:
soc_peripherals
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_2
 
Top level modules:
boot_rom_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module top
 
Top level modules:
top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_vector_rom
 
Top level modules:
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module IS61LV25616
 
Top level modules:
IS61LV25616
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/tests/uboot_test/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_boot
 
Top level modules:
soc_boot
 
} {} {}}
/de1_board/sim/tests/debug/debug.cr.mti
1,5 → 1,5
C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_system
 
Top level modules:
6,7 → 6,7
soc_system
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module s29al032d_00
-- Compiling module BUFFER
 
14,7 → 14,7
s29al032d_00
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_gpio
 
Top level modules:
21,7 → 21,7
soc_gpio
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_dut
 
Top level modules:
28,7 → 28,7
tb_dut
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_ram
 
Top level modules:
35,7 → 35,7
soc_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_registers
 
Top level modules:
42,7 → 42,7
soc_registers
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_1
 
Top level modules:
49,7 → 49,7
soc_mem_bank_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_top
 
Top level modules:
56,7 → 56,7
soc_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_2
 
Top level modules:
63,7 → 63,7
soc_mem_bank_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_mem_bank_3
 
Top level modules:
70,7 → 70,7
soc_mem_bank_3
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_0
 
Top level modules:
77,49 → 77,49
boot_rom_0
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module tb_top
 
Top level modules:
tb_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_peripherals
 
Top level modules:
soc_peripherals
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_1
 
Top level modules:
boot_rom_1
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module soc_peripherals
 
Top level modules:
soc_peripherals
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_rom_2
 
Top level modules:
boot_rom_2
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module boot_vector_rom
 
Top level modules:
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v {1 {vlog -work work +incdir+../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module top
 
Top level modules:
top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module boot_vector_rom
 
Top level modules:
boot_vector_rom
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v {1 {vlog -work work -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module IS61LV25616
 
Top level modules:
126,7 → 126,7
IS61LV25616
 
} {} {}} C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v {1 {vlog -work work +incdir+../../../src +incdir+../../../../../src -nocovercells C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module soc_boot
 
Top level modules:
/de1_board/sim/tests/debug/debug.mpf
346,48 → 346,53
; msgmode = both
 
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 19
Project_File_0 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_system.v
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Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239838063 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/S29al032d_00/model/s29al032d_00.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1118235516 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 18 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1118235516 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 18 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_gpio.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238538756 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238545534 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_dut.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1239837089 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1239838051 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_ram.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238113682 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238115511 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_registers.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237926731 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 10 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_1.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237926732 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_top.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1239905061 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1239905312 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_2.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1239827647 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1239838062 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_mem_bank_3.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239826999 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838063 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_0.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238533579 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 14 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1236190413 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238533575 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237926732 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238111450 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_peripherals.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238019418 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_1.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_rom_2.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1238113375 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 16 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1238533559 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1239830918 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1238115510 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 16 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/top.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1239838052 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/src/boot_vector_rom.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238534422 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/models/sram/IS61LV25616AL.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1219274280 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to work vlog_upper 0 cover_noshort 0 compile_order 17 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1219274282 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 17 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1200_soc/src/soc_boot.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1238539174 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options +incdir+../../../src+incdir+../../../../../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238545534 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../../../src+incdir+../../../../../src compile_to work vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
394,8 → 399,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
423,6 → 426,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState = {tabbed horizontal 1} {C:/qaz/_CVS_WORK/units/or1200_soc/boards/de1_board/sim/src/tb_top.v 0 1}
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/gpio.mpf
278,12 → 278,17
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = gpio
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 1
Project_File_0 = C:/qaz/_CVS_WORK/units/gpio/rtl/verilog/gpio_top.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1089968226 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to gpio vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236702934 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to gpio vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
290,8 → 295,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
319,6 → 322,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/gpio.cr.mti
1,5 → 1,5
C:/qaz/_CVS_WORK/units/gpio/rtl/verilog/gpio_top.v {1 {vlog -work gpio +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/gpio/rtl/verilog/gpio_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module gpio_top
 
Top level modules:
/de1_board/libs/libs.do
0,0 → 1,10
 
vlib gpio
vlib or1200
vlib sim
vlib uart16550
vlib wb_conmax
vlib wb_size_bridge
 
 
 
/de1_board/libs/uart16550.mpf
278,30 → 278,35
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = uart16550
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 10
Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} last_compile 1236708645 cover_fsm 0 cover_branch 0 vlog_noload 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085139805 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1027977378 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 9 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1101115319 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1087569975 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1085142915 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 9 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1057947626 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1027977378 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to uart16550 vlog_options +incdir+../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1236708645 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to uart16550 vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
308,8 → 313,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
337,6 → 340,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/wb_conmax.mpf
278,26 → 278,31
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = wb_conmax
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 8
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1033623607 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_conmax vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1033623609 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to wb_conmax vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
304,8 → 309,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
333,6 → 336,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/wb_size_bridge.mpf
278,16 → 278,21
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = wb_size_bridge
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 3
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1237927188 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_size_bridge vlog_options {} compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1237927188 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_size_bridge vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238018693 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to wb_size_bridge vlog_upper 0 cover_noshort 0 compile_order 1 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238018693 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to wb_size_bridge vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 folder {Top Level} cover_branch 0 cover_fsm 0 last_compile 1237927188 vlog_noload 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to wb_size_bridge vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 last_compile 1238018693 vlog_noload 0 cover_branch 0 folder {Top Level} vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options {} compile_to wb_size_bridge vlog_upper 0 cover_noshort 0 compile_order 0 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
294,8 → 299,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
323,6 → 326,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/or1200.mpf
278,126 → 278,131
; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl
[Project]
; Warning -- Do not edit the project properties directly.
; Property names are dynamic in nature and property
; values have special syntax. Changing property data directly
; can result in a corrupt MPF file. All project properties
; can be modified through project window dialogs.
Project_Version = 6
Project_DefaultLib = or1200
Project_DefaultLib = work
Project_SortMethod = unused
Project_Files_Count = 58
Project_File_0 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 11 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_0 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 39 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_1 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_256x32.v
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 13 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 39 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 49 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 41 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 13 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_2 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 11 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_3 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 41 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_4 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 49 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_5 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_iwb_biu.v
Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 26 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_6 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
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Project_File_7 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v
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Project_File_6 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v
Project_File_P_6 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 27 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_7 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
Project_File_P_7 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 10 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_8 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 12 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
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Project_File_10 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_top.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 22 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 12 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_9 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_top.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 22 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_10 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 47 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_11 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_reg2mem.v
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 34 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 34 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_12 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rf.v
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 35 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 35 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_13 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x14.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 40 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 40 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_14 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mult_mac.v
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 29 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 29 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_15 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_fsm.v
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 6 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_16 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 50 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_16 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 50 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_17 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pm.v
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 32 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_17 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 32 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_18 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_tag.v
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 21 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_18 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 21 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_19 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cpu.v
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 4 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_19 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 4 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_20 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_top.v
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 53 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_20 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 53 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_21 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rfram_generic.v
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 36 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_21 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 36 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_22 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 54 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_22 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 54 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_23 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_ram.v
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 7 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_23 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 7 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_24 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_freeze.v
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Project_File_25 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v
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Project_File_26 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pic.v
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Project_File_27 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_genpc.v
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Project_File_28 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb.v
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Project_File_29 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wb_biu.v
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Project_File_30 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb_fifo.v
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Project_File_31 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
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Project_File_32 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_qmem_top.v
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Project_File_33 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x24.v
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Project_File_34 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_operandmuxes.v
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Project_File_35 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
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Project_File_36 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_if.v
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Project_File_37 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mem2reg.v
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Project_File_38 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tt.v
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Project_File_39 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_top.v
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Project_File_40 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_du.v
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Project_File_41 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_fsm.v
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Project_File_42 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_alu.v
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Project_File_43 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_top.v
Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 25 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_43 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 25 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_44 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_128x32.v
Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 43 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_44 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 43 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_45 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_512x20.v
Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 45 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_45 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 45 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_46 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ctrl.v
Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 5 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_46 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 5 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_47 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sprs.v
Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 52 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_48 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
Project_File_P_48 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 24 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_49 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
Project_File_P_49 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 46 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_50 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_tag.v
Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 8 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_51 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v
Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 3 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_52 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wbmux.v
Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 57 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_53 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v
Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 20 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_54 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 48 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_55 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935658 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 2 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_47 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 52 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_48 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
Project_File_P_48 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 46 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_49 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
Project_File_P_49 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 24 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_50 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v
Project_File_P_50 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 3 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_51 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_tag.v
Project_File_P_51 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 8 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_52 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v
Project_File_P_52 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 20 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_53 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wbmux.v
Project_File_P_53 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 57 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_54 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
Project_File_P_54 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 2 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_55 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
Project_File_P_55 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 48 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_56 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_except.v
Project_File_P_56 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 15 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_56 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 15 dont_compile 0 cover_expr 0 cover_stmt 0
Project_File_57 = C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_256x21.v
Project_File_P_57 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1237935659 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to or1200 vlog_options +incdir+../src compile_order 44 cover_expr 0 dont_compile 0 cover_stmt 0
Project_File_P_57 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 last_compile 1237935660 folder {Top Level} cover_branch 0 cover_fsm 0 vlog_enable0In 0 cover_excludedefault 0 vlog_disableopt 0 cover_covercells 0 vlog_hazard 0 vlog_showsource 0 cover_optlevel 3 voptflow 1 ood 0 vlog_0InOptions {} toggle - vlog_options +incdir+../src compile_to or1200 vlog_upper 0 cover_noshort 0 compile_order 44 dont_compile 0 cover_expr 0 cover_stmt 0
Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
404,8 → 409,6
Save_Compile_Report = 1
Project_Opt_Count = 0
ForceSoftPaths = 0
ReOpenSourceFiles = 1
CloseSourceFiles = 1
ProjectStatusDelay = 5000
VERILOG_DoubleClick = Edit
VERILOG_CustomDoubleClick =
433,6 → 436,5
LOGFILE_CustomDoubleClick =
UCDB_DoubleClick = Edit
UCDB_CustomDoubleClick =
EditorState =
Project_Major_Version = 6
Project_Minor_Version = 4
Project_Minor_Version = 5
/de1_board/libs/uart16550.cr.mti
1,61 → 1,61
C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_tfifo
C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module raminfr
 
Top level modules:
uart_tfifo
raminfr
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_sync_flops.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_sync_flops
 
Top level modules:
uart_sync_flops
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/raminfr.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module raminfr
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_tfifo.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_tfifo
 
Top level modules:
raminfr
uart_tfifo
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_transmitter
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_wb
 
Top level modules:
uart_transmitter
uart_wb
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_regs
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_debug_if
 
Top level modules:
uart_regs
uart_debug_if
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_receiver.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_receiver
 
Top level modules:
uart_receiver
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_debug_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_debug_if
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_regs.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_regs
 
Top level modules:
uart_debug_if
uart_regs
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_wb.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module uart_wb
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_transmitter.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_transmitter
 
Top level modules:
uart_wb
uart_transmitter
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_rfifo.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_rfifo
 
Top level modules:
62,7 → 62,7
uart_rfifo
 
} {} {}} C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v {1 {vlog -work uart16550 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/uart16550/rtl/verilog/uart_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module uart_top
 
Top level modules:
/de1_board/libs/wb_conmax.cr.mti
1,57 → 1,57
C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module wb_conmax_slave_if
C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_arb
 
Top level modules:
wb_conmax_slave_if
wb_conmax_arb
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_msel.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_msel
 
Top level modules:
wb_conmax_msel
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_arb.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module wb_conmax_arb
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_slave_if
 
Top level modules:
wb_conmax_arb
wb_conmax_slave_if
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_master_if
 
Top level modules:
wb_conmax_master_if
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_pri_dec
 
Top level modules:
wb_conmax_pri_dec
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_master_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module wb_conmax_master_if
 
Top level modules:
wb_conmax_master_if
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_top
 
Top level modules:
wb_conmax_top
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_pri_enc
 
Top level modules:
wb_conmax_pri_enc
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_rf.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_conmax_rf
 
Top level modules:
wb_conmax_rf
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v {1 {vlog -work wb_conmax +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module wb_conmax_pri_enc
 
Top level modules:
wb_conmax_pri_enc
 
} {} {}}
/de1_board/libs/wb_size_bridge.cr.mti
1,19 → 1,19
C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module async_mem_if
C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module asram_if
 
Top level modules:
async_mem_if
asram_if
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/asram_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module asram_if
} {} {}} C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/async_mem_if.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module async_mem_if
 
Top level modules:
asram_if
async_mem_if
 
} {} {}} C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v {1 {vlog -work wb_size_bridge -nocovercells C:/qaz/_CVS_WORK/units/wb_size_bridge/src/wb_size_bridge.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module wb_size_bridge
 
Top level modules:
/de1_board/libs/or1200.cr.mti
1,82 → 1,82
C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_dmmu_top
C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_32x24
 
Top level modules:
or1200_dmmu_top
or1200_spram_32x24
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_256x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_256x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dpram_256x32
 
Top level modules:
or1200_dpram_256x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_32x24.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_spram_32x24
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_top.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dmmu_top
 
Top level modules:
or1200_spram_32x24
or1200_dmmu_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_64x22
 
Top level modules:
or1200_spram_64x22
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x8.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_2048x8
 
Top level modules:
or1200_spram_2048x8
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x22.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_spram_64x22
 
Top level modules:
or1200_spram_64x22
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_iwb_biu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_iwb_biu.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_iwb_biu
 
Top level modules:
or1200_iwb_biu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_lsu
 
Top level modules:
or1200_lsu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dmmu_tlb.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dmmu_tlb
 
Top level modules:
or1200_dmmu_tlb
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_lsu.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_lsu
 
Top level modules:
or1200_lsu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dpram_32x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dpram_32x32
 
Top level modules:
or1200_dpram_32x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_1024x32
 
Top level modules:
or1200_spram_1024x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_ic_top
 
Top level modules:
or1200_ic_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_spram_1024x32
 
Top level modules:
or1200_spram_1024x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_reg2mem.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_reg2mem.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_reg2mem
 
Top level modules:
83,7 → 83,7
or1200_reg2mem
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rf.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rf.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_rf
 
Top level modules:
90,7 → 90,7
or1200_rf
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x14.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x14.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_64x14
 
Top level modules:
97,7 → 97,7
or1200_spram_64x14
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mult_mac.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mult_mac.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_mult_mac
 
Top level modules:
104,7 → 104,7
or1200_mult_mac
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_fsm.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_fsm.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dc_fsm
 
Top level modules:
111,7 → 111,7
or1200_dc_fsm
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_2048x32
 
Top level modules:
118,7 → 118,7
or1200_spram_2048x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pm.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pm.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_pm
 
Top level modules:
125,7 → 125,7
or1200_pm
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_tag.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_tag.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_ic_tag
 
Top level modules:
132,7 → 132,7
or1200_ic_tag
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cpu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cpu.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_cpu
 
Top level modules:
139,7 → 139,7
or1200_cpu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_top
 
Top level modules:
146,7 → 146,7
or1200_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rfram_generic.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_rfram_generic.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_rfram_generic
 
Top level modules:
153,7 → 153,7
or1200_rfram_generic
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tpram_32x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_tpram_32x32
 
Top level modules:
160,7 → 160,7
or1200_tpram_32x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_ram.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_ram.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dc_ram
 
Top level modules:
167,7 → 167,7
or1200_dc_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_freeze.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_freeze.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_freeze
 
Top level modules:
174,7 → 174,7
or1200_freeze
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_gmultp2_32x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_gmultp2_32x32
 
Top level modules:
181,7 → 181,7
or1200_gmultp2_32x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pic.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_pic.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_pic
 
Top level modules:
188,7 → 188,7
or1200_pic
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_genpc.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_genpc.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_genpc
 
Top level modules:
195,7 → 195,7
or1200_genpc
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_sb
 
Top level modules:
202,7 → 202,7
or1200_sb
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wb_biu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wb_biu.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_wb_biu
 
Top level modules:
209,7 → 209,7
or1200_wb_biu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb_fifo.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sb_fifo.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_sb_fifo
 
Top level modules:
216,10 → 216,10
or1200_sb_fifo
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_xcv_ram32x8d.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_qmem_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_qmem_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_qmem_top
 
Top level modules:
226,7 → 226,7
or1200_qmem_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x24.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_64x24.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_64x24
 
Top level modules:
233,7 → 233,7
or1200_spram_64x24
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_operandmuxes.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_operandmuxes.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_operandmuxes
 
Top level modules:
240,7 → 240,7
or1200_operandmuxes
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_2048x32_bw
 
Top level modules:
247,7 → 247,7
or1200_spram_2048x32_bw
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_if.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_if.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_if
 
Top level modules:
254,7 → 254,7
or1200_if
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mem2reg.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_mem2reg.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_mem2reg
 
Top level modules:
261,7 → 261,7
or1200_mem2reg
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tt.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_tt.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_tt
 
Top level modules:
268,7 → 268,7
or1200_tt
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dc_top
 
Top level modules:
275,7 → 275,7
or1200_dc_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_du.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_du.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_du
 
Top level modules:
282,7 → 282,7
or1200_du
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_fsm.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_fsm.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_ic_fsm
 
Top level modules:
289,7 → 289,7
or1200_ic_fsm
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_alu.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_alu.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_alu
 
Top level modules:
296,7 → 296,7
or1200_alu
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_top.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_top.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_immu_top
 
Top level modules:
303,7 → 303,7
or1200_immu_top
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_128x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_128x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_128x32
 
Top level modules:
310,7 → 310,7
or1200_spram_128x32
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_512x20.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_512x20.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_512x20
 
Top level modules:
317,7 → 317,7
or1200_spram_512x20
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ctrl.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ctrl.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_ctrl
 
Top level modules:
324,66 → 324,66
or1200_ctrl
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sprs.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_sprs.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_sprs
 
Top level modules:
or1200_sprs
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_1024x8
 
Top level modules:
or1200_spram_1024x8
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_tlb.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_immu_tlb.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_immu_tlb
 
Top level modules:
or1200_immu_tlb
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x8.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_spram_1024x8
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_cfgr
 
Top level modules:
or1200_spram_1024x8
or1200_cfgr
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_tag.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_dc_tag.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_dc_tag
 
Top level modules:
or1200_dc_tag
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_cfgr.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_cfgr
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_ic_ram
 
Top level modules:
or1200_cfgr
or1200_ic_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wbmux.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_wbmux.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_wbmux
 
Top level modules:
or1200_wbmux
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_ic_ram.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
-- Compiling module or1200_ic_ram
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
 
Top level modules:
or1200_ic_ram
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_1024x32_bw
 
Top level modules:
or1200_spram_1024x32_bw
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_amultp2_32x32.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_except.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_except.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_except
 
Top level modules:
390,7 → 390,7
or1200_except
 
} {} {}} C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_256x21.v {1 {vlog -work or1200 +incdir+../src -nocovercells C:/qaz/_CVS_WORK/units/or1k/or1200/rtl/verilog/or1200_spram_256x21.v
Model Technology ModelSim ALTERA vlog 6.4a Compiler 2008.08 Oct 22 2008
Model Technology ModelSim ALTERA vlog 6.5b Compiler 2009.10 Oct 1 2009
-- Compiling module or1200_spram_256x21
 
Top level modules:
/de1_board/sw/load_this_to_ram/boot_rom_0.txt
17,416 → 17,65
15000000
 
@00000006
9c21fff4
1860ab11
 
@00000007
d4014800
18803000
 
@00000008
d4015004
a86322ef
 
@00000009
d4016008
a8a40001
 
@0000000a
18802000
d4041800
 
@0000000b
9ce0ffba
a8c40002
 
@0000000c
a8640100
84640000
 
@0000000d
a8a40104
9c60ffba
 
@0000000e
84630000
d8051800
 
@0000000f
a8c40108
9c60ffbe
 
@00000010
84650000
d8061800
 
@00000011
84660000
84640000
 
@00000012
a8a40040
1860cea5
 
@00000013
a8c40044
a883e0ff
 
@00000014
84650000
18605fff
 
@00000015
a8840048
a863fffc
 
@00000016
84660000
d4032000
 
@00000017
18a06000
00000000
 
@00000018
84640000
15000000
 
@00000019
a9050014
44004800
 
@0000001a
1860ab11
 
@0000001b
18803000
 
@0000001c
a86322ef
 
@0000001d
a8c40001
 
@0000001e
d4041800
 
@0000001f
84640000
 
@00000020
d8063800
 
@00000021
a8640002
 
@00000022
9ce0ffbe
 
@00000023
a8c50008
 
@00000024
d8033800
 
@00000025
84640000
 
@00000026
9ce000ff
 
@00000027
84650000
 
@00000028
18806100
 
@00000029
d4063800
 
@0000002a
d4083800
 
@0000002b
a8c40014
 
@0000002c
84650000
 
@0000002d
9ce0ffff
 
@0000002e
84640000
 
@0000002f
a9040008
 
@00000030
d4063800
 
@00000031
d4083800
 
@00000032
a8c50028
 
@00000033
84640000
 
@00000034
a8e5002c
 
@00000035
18606600
 
@00000036
a8850040
 
@00000037
84630000
 
@00000038
84660000
 
@00000039
84670000
 
@0000003a
84640000
 
@0000003b
18606040
 
@0000003c
84630000
 
@0000003d
18605fff
 
@0000003e
a943fffc
 
@0000003f
18606f00
 
@00000040
84630000
 
@00000041
1860cea5
 
@00000042
a983e0ff
 
@00000043
d40a6000
 
@00000044
04000018
 
@00000045
15000000
 
@00000046
04000026
 
@00000047
9c600071
 
@00000048
04000024
 
@00000049
9c600061
 
@0000004a
04000022
 
@0000004b
9c60007a
 
@0000004c
04000020
 
@0000004d
9c60000a
 
@0000004e
0400001e
 
@0000004f
9c60000d
 
@00000050
18600400
 
@00000051
a8630230
 
@00000052
04000026
 
@00000053
15000000
 
@00000054
d40a6000
 
@00000055
00000000
 
@00000056
15000000
 
@00000057
85210000
 
@00000058
85410004
 
@00000059
85810008
 
@0000005a
44004800
 
@0000005b
9c21000c
 
@0000005c
18605000
 
@0000005d
9cc0ff83
 
@0000005e
a8a30003
 
@0000005f
a8830001
 
@00000060
d8053000
 
@00000061
9cc00000
 
@00000062
d8043000
 
@00000063
9c80001a
 
@00000064
9cc00003
 
@00000065
d8032000
 
@00000066
a8630002
 
@00000067
d8053000
 
@00000068
9c800001
 
@00000069
d8032000
 
@0000006a
44004800
 
@0000006b
15000000
 
@0000006c
b8630018
 
@0000006d
18c05000
 
@0000006e
b8630098
 
@0000006f
a8a60005
 
@00000070
8c850000
 
@00000071
a4840020
 
@00000072
bc240000
 
@00000073
0ffffffd
 
@00000074
15000000
 
@00000075
d8061800
 
@00000076
44004800
 
@00000077
15000000
 
@00000078
9c21fff8
 
@00000079
d4014800
 
@0000007a
d4015004
 
@0000007b
a9430000
 
@0000007c
8c630000
 
@0000007d
b8630018
 
@0000007e
bc030000
 
@0000007f
10000009
 
@00000080
b8630098
 
@00000081
07ffffeb
 
@00000082
9d4a0001
 
@00000083
8c6a0000
 
@00000084
b8630018
 
@00000085
bc230000
 
@00000086
13fffffb
 
@00000087
b8630098
 
@00000088
85210000
 
@00000089
85410004
 
@0000008a
44004800
 
@0000008b
9c210008
 
@0000008c
61727267
 
@0000008d
21206172
 
@0000008e
72672121
 
@0000008f
0a0d0000
 

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