URL
https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk
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/or1200_soc/trunk/src
- from Rev 12 to Rev 2
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Rev 12 → Rev 2
/ram/ram_1p_32x65536.v
0,0 → 1,41
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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module ram_1p_32x65536( data, addr, we, clk, q ); |
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parameter DATA_WIDTH = 32; |
parameter ADDR_WIDTH = 16; |
parameter MEM_INIT = 0; |
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input [(DATA_WIDTH-1):0] data; |
input [(ADDR_WIDTH-1):0] addr; |
input we; |
input clk; |
output [(DATA_WIDTH-1):0] q; |
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// Declare the RAM variable |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; |
reg [ADDR_WIDTH-1:0] addr_reg; |
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always @ (posedge clk) |
begin |
// Write |
if (we) ram[addr] <= data; |
addr_reg <= addr; |
end |
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// Read returns NEW data at addr if we == 1'b1. This is the |
// natural behavior of TriMatrix memory blocks in Single Port |
// mode |
assign q = ram[addr_reg]; |
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generate |
if( MEM_INIT != 0 ) |
initial |
$readmemh( MEM_INIT, ram ); |
endgenerate |
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endmodule |
/ram/ram_1p_32x2048.v
0,0 → 1,41
// -------------------------------------------------------------------- |
// |
// -------------------------------------------------------------------- |
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module ram_1p_32x2048( data, addr, we, clk, q ); |
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parameter DATA_WIDTH = 32; |
parameter ADDR_WIDTH = 11; |
parameter MEM_INIT = "../../sw/load_this_to_ram/qmem.txt"; |
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input [(DATA_WIDTH-1):0] data; |
input [(ADDR_WIDTH-1):0] addr; |
input we; |
input clk; |
output [(DATA_WIDTH-1):0] q; |
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// Declare the RAM variable |
reg [DATA_WIDTH-1:0] ram[2**ADDR_WIDTH-1:0]; |
reg [ADDR_WIDTH-1:0] addr_reg; |
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always @ (posedge clk) |
begin |
// Write |
if (we) ram[addr] <= data; |
addr_reg <= addr; |
end |
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// Read returns NEW data at addr if we == 1'b1. This is the |
// natural behavior of TriMatrix memory blocks in Single Port |
// mode |
assign q = ram[addr_reg]; |
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generate |
if( MEM_INIT != 0 ) |
initial |
$readmemh( MEM_INIT, ram ); |
endgenerate |
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endmodule |