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URL https://opencores.org/ocsvn/or1200_soc/or1200_soc/trunk

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    /or1200_soc/trunk/src
    from Rev 22 to Rev 24
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Rev 22 → Rev 24

/soc_mem_bank_2.v
2,17 → 2,17
 
 
module soc_mem_bank_2(
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
input [31:0] mem_data_i,
output [31:0] mem_data_o,
input [31:0] mem_addr_i,
input [3:0] mem_sel_i,
input mem_we_i,
input mem_cyc_i,
input mem_stb_i,
output mem_ack_o,
output mem_err_o,
output mem_rty_o,
inout [7:0] fl_dq,
output [21:0] fl_addr,
output fl_we_n,
19,16 → 19,16
output fl_rst_n,
output fl_oe_n,
output fl_ce_n,
input mem_clk_i,
input mem_rst_i
);
input mem_clk_i,
input mem_rst_i
);
parameter USE_NOR_FLASH = 1;
parameter USE_NOR_FLASH = 1;
generate
if( USE_NOR_FLASH )
begin
generate
if( USE_NOR_FLASH )
begin
//---------------------------------------------------
// nor flash
async_mem_if #( .AW(22), .DW(8) )
58,7 → 58,7
);
//---------------------------------------------------
// outputs for stub
// outputs for nor flash
assign mem_err_o = 1'b0;
assign mem_rty_o = 1'b0;
assign fl_rst_n = ~mem_rst_i;
74,7 → 74,7
assign mem_rty_o = 1'b0;
end
 
endgenerate
endgenerate
endmodule
 
/soc_top.v
42,40 → 42,40
output sram_ce_n, // sram chip enable
output sram_oe_n, // sram output enable
input [31:0] gpio_a_aux_i,
input [31:0] gpio_a_ext_pad_i,
output [31:0] gpio_a_ext_pad_o,
output [31:0] gpio_a_ext_padoe_o,
input [31:0] gpio_a_aux_i,
input [31:0] gpio_a_ext_pad_i,
output [31:0] gpio_a_ext_pad_o,
output [31:0] gpio_a_ext_padoe_o,
 
input [31:0] gpio_b_aux_i,
input [31:0] gpio_b_ext_pad_i,
output [31:0] gpio_b_ext_pad_o,
output [31:0] gpio_b_ext_padoe_o,
input [31:0] gpio_b_aux_i,
input [31:0] gpio_b_ext_pad_i,
output [31:0] gpio_b_ext_pad_o,
output [31:0] gpio_b_ext_padoe_o,
 
input [31:0] gpio_c_aux_i,
input [31:0] gpio_c_ext_pad_i,
output [31:0] gpio_c_ext_pad_o,
output [31:0] gpio_c_ext_padoe_o,
input [31:0] gpio_c_aux_i,
input [31:0] gpio_c_ext_pad_i,
output [31:0] gpio_c_ext_pad_o,
output [31:0] gpio_c_ext_padoe_o,
 
input [31:0] gpio_d_aux_i,
input [31:0] gpio_d_ext_pad_i,
output [31:0] gpio_d_ext_pad_o,
output [31:0] gpio_d_ext_padoe_o,
input [31:0] gpio_d_aux_i,
input [31:0] gpio_d_ext_pad_i,
output [31:0] gpio_d_ext_pad_o,
output [31:0] gpio_d_ext_padoe_o,
 
input [31:0] gpio_e_aux_i,
input [31:0] gpio_e_ext_pad_i,
output [31:0] gpio_e_ext_pad_o,
output [31:0] gpio_e_ext_padoe_o,
input [31:0] gpio_e_aux_i,
input [31:0] gpio_e_ext_pad_i,
output [31:0] gpio_e_ext_pad_o,
output [31:0] gpio_e_ext_padoe_o,
 
input [31:0] gpio_f_aux_i,
input [31:0] gpio_f_ext_pad_i,
output [31:0] gpio_f_ext_pad_o,
output [31:0] gpio_f_ext_padoe_o,
input [31:0] gpio_f_aux_i,
input [31:0] gpio_f_ext_pad_i,
output [31:0] gpio_f_ext_pad_o,
output [31:0] gpio_f_ext_padoe_o,
 
input [31:0] gpio_g_aux_i,
input [31:0] gpio_g_ext_pad_i,
output [31:0] gpio_g_ext_pad_o,
output [31:0] gpio_g_ext_padoe_o,
input [31:0] gpio_g_aux_i,
input [31:0] gpio_g_ext_pad_i,
output [31:0] gpio_g_ext_pad_o,
output [31:0] gpio_g_ext_padoe_o,
 
input [3:0] boot_strap,
82,6 → 82,13
`ifdef USE_DEBUG_0
output [255:0] debug_0,
`endif
 
`ifdef USE_EXT_JTAG
input jtag_tck_i,
input jtag_tms_i,
input jtag_tdo_i,
output jtag_tdi_o,
`endif
input sys_clk,
input sys_rst
96,7 → 103,9
 
 
// System
wire cpu0_rst_o;
wire clk_i = sys_clk;
// wire rst_i = sys_rst | cpu0_rst_o;
wire rst_i = sys_rst;
 
//---------------------------------------------------
130,6 → 139,19
wire [3:0] dwb_sel_o;
wire [dw-1:0] dwb_dat_o;
wire dwb_cab_o;
//---------------------------------------------------
// External Debug Interface
wire dbg_stall_i;
wire [3:0] dbg_lss_o; // External Load/Store Unit Status
wire [1:0] dbg_is_o; // External Insn Fetch Status
wire [10:0] dbg_wp_o; // Watchpoints Outputs
wire dbg_bp_o; // Breakpoint Output
wire dbg_stb_i; // External Address/Data Strobe
wire dbg_we_i; // External Write Enable
wire [aw-1:0] dbg_adr_i; // External Address Input
wire [dw-1:0] dbg_dat_i; // External Data Input
wire [dw-1:0] dbg_dat_o; // External Data Output
wire dbg_ack_o; // External Data Acknowledge (not WB compatible)
 
or1200_top i_or1200_top(
//---------------------------------------------------
178,18 → 200,18
 
//---------------------------------------------------
// External Debug Interface
.dbg_stall_i(1'b0), // External Stall Input
// .dbg_ewt_i(dbg_ewt_i), // External Watchpoint Trigger Input
.dbg_stall_i(dbg_stall_i), // External Stall Input
.dbg_ewt_i(1'b0), // External Watchpoint Trigger Input
// .dbg_lss_o(dbg_lss_o), // External Load/Store Unit Status
// .dbg_is_o(dbg_is_o), // External Insn Fetch Status
// .dbg_wp_o(dbg_wp_o), // Watchpoints Outputs
// .dbg_bp_o(dbg_bp_o), // Breakpoint Output
// .dbg_stb_i(dbg_stb_i), // External Address/Data Strobe
// .dbg_we_i(dbg_we_i), // External Write Enable
// .dbg_adr_i(dbg_adr_i), // External Address Input
// .dbg_dat_i(dbg_dat_i), // External Data Input
// .dbg_dat_o(dbg_dat_o), // External Data Output
// .dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
.dbg_bp_o(dbg_bp_o), // Breakpoint Output
.dbg_stb_i(dbg_stb_i), // External Address/Data Strobe
.dbg_we_i(dbg_we_i), // External Write Enable
.dbg_adr_i(dbg_adr_i), // External Address Input
.dbg_dat_i(dbg_dat_i), // External Data Input
.dbg_dat_o(dbg_dat_o), // External Data Output
.dbg_ack_o(dbg_ack_o), // External Data Acknowledge (not WB compatible)
 
 
//---------------------------------------------------
221,7 → 243,67
.rst_i(rst_i)
);
 
//---------------------------------------------------
// adbg_top
wire [31:0] adbg_wb_adr_o;
wire [31:0] adbg_wb_dat_o;
wire [31:0] adbg_wb_dat_i;
wire adbg_wb_cyc_o;
wire adbg_wb_stb_o;
wire [3:0] adbg_wb_sel_o;
wire adbg_wb_we_o;
wire adbg_wb_ack_i;
wire adbg_wb_cab_o;
wire adbg_wb_err_i;
wire [2:0] adbg_wb_cti_o;
wire [1:0] adbg_wb_bte_o;
`ifdef USE_ADV_DEBUG_SYS
soc_adv_dbg
i_soc_adv_dbg(
`ifdef USE_EXT_JTAG
.jtag_tck_i(jtag_tck_i),
.jtag_tms_i(jtag_tms_i),
.jtag_tdo_i(jtag_tdo_i),
.jtag_tdi_o(jtag_tdi_o),
`endif
.wb_clk_i(dwb_clk_i), // WISHBONE common signals
.wb_adr_o(adbg_wb_adr_o), // WISHBONE master interface
.wb_dat_o(adbg_wb_dat_o),
.wb_dat_i(adbg_wb_dat_i),
.wb_cyc_o(adbg_wb_cyc_o),
.wb_stb_o(adbg_wb_stb_o),
.wb_sel_o(adbg_wb_sel_o),
.wb_we_o(adbg_wb_we_o),
.wb_ack_i(adbg_wb_ack_i),
.wb_cab_o(adbg_wb_cab_o),
.wb_err_i(adbg_wb_err_i),
.wb_cti_o(adbg_wb_cti_o),
.wb_bte_o(adbg_wb_bte_o),
.cpu0_clk_i(dwb_clk_i), // CPU signals
.cpu0_addr_o(dbg_adr_i),
.cpu0_data_i(dbg_dat_o),
.cpu0_data_o(dbg_dat_i),
.cpu0_bp_i(dbg_bp_o),
.cpu0_stall_o(dbg_stall_i),
.cpu0_stb_o(dbg_stb_i),
.cpu0_we_o(dbg_we_i),
.cpu0_ack_i(dbg_ack_o),
.cpu0_rst_o(cpu0_rst_o)
);
`else
assign dbg_stall_i = 1'b0;
assign adbg_wb_dat_o = 32'h0000_0000;
assign adbg_wb_adr_o = 32'h0000_0000;
assign adbg_wb_sel_o = 4'h0;
assign adbg_wb_we_o = 1'b0;
assign adbg_wb_cyc_o = 1'b0;
assign adbg_wb_stb_o = 1'b0;
`endif
//---------------------------------------------------
// remap mux
wire [1:0] boot_remap;
361,7 → 443,6
.m0_data_i(iwb_dat_o),
.m0_data_o(iwb_dat_i),
.m0_addr_i( iwb_remap_adr_o ),
// .m0_addr_i( iwb_adr_o ),
.m0_sel_i(iwb_sel_o),
.m0_we_i(iwb_we_o),
.m0_cyc_i(iwb_cyc_o),
373,7 → 454,6
.m1_data_i(dwb_dat_o),
.m1_data_o(dwb_dat_i),
.m1_addr_i(dwb_remap_adr_o),
// .m1_addr_i(dwb_adr_o),
.m1_sel_i(dwb_sel_o),
.m1_we_i(dwb_we_o),
.m1_cyc_i(dwb_cyc_o),
382,12 → 462,16
.m1_err_o(dwb_err_i),
.m1_rty_o(dwb_rty_i),
// Master 2 Interface
.m2_data_i(32'h0000_0000),
.m2_addr_i(32'h0000_0000),
.m2_sel_i(4'h0),
.m2_we_i(1'b0),
.m2_cyc_i(1'b0),
.m2_stb_i(1'b0),
.m2_data_i(adbg_wb_dat_o),
.m2_data_o(adbg_wb_dat_i),
.m2_addr_i(adbg_wb_adr_o),
.m2_sel_i(adbg_wb_sel_o),
.m2_we_i(adbg_wb_we_o),
.m2_cyc_i(adbg_wb_cyc_o),
.m2_stb_i(adbg_wb_stb_o),
.m2_ack_o(adbg_wb_ack_i),
.m2_err_o(adbg_wb_err_i),
.m2_rty_o(),
// Master 3 Interface
.m3_data_i(32'h0000_0000),
.m3_addr_i(32'h0000_0000),
706,46 → 790,46
.gpio_err_o(s6_err_i),
.gpio_rty_o(s6_rty_i),
.gpio_a_aux_i(gpio_a_aux_i),
.gpio_a_ext_pad_i(gpio_a_ext_pad_i),
.gpio_a_ext_pad_o(gpio_a_ext_pad_o),
.gpio_a_ext_padoe_o(gpio_a_ext_padoe_o),
.gpio_a_aux_i(gpio_a_aux_i),
.gpio_a_ext_pad_i(gpio_a_ext_pad_i),
.gpio_a_ext_pad_o(gpio_a_ext_pad_o),
.gpio_a_ext_padoe_o(gpio_a_ext_padoe_o),
.gpio_a_inta_o(),
.gpio_b_aux_i(gpio_b_aux_i),
.gpio_b_ext_pad_i(gpio_b_ext_pad_i),
.gpio_b_ext_pad_o(gpio_b_ext_pad_o),
.gpio_b_ext_padoe_o(gpio_b_ext_padoe_o),
.gpio_b_aux_i(gpio_b_aux_i),
.gpio_b_ext_pad_i(gpio_b_ext_pad_i),
.gpio_b_ext_pad_o(gpio_b_ext_pad_o),
.gpio_b_ext_padoe_o(gpio_b_ext_padoe_o),
.gpio_b_inta_o(),
 
.gpio_c_aux_i(gpio_c_aux_i),
.gpio_c_ext_pad_i(gpio_c_ext_pad_i),
.gpio_c_ext_pad_o(gpio_c_ext_pad_o),
.gpio_c_ext_padoe_o(gpio_c_ext_padoe_o),
.gpio_c_aux_i(gpio_c_aux_i),
.gpio_c_ext_pad_i(gpio_c_ext_pad_i),
.gpio_c_ext_pad_o(gpio_c_ext_pad_o),
.gpio_c_ext_padoe_o(gpio_c_ext_padoe_o),
.gpio_c_inta_o(),
 
.gpio_d_aux_i(gpio_d_aux_i),
.gpio_d_ext_pad_i(gpio_d_ext_pad_i),
.gpio_d_ext_pad_o(gpio_d_ext_pad_o),
.gpio_d_ext_padoe_o(gpio_d_ext_padoe_o),
.gpio_d_aux_i(gpio_d_aux_i),
.gpio_d_ext_pad_i(gpio_d_ext_pad_i),
.gpio_d_ext_pad_o(gpio_d_ext_pad_o),
.gpio_d_ext_padoe_o(gpio_d_ext_padoe_o),
.gpio_d_inta_o(),
 
.gpio_e_aux_i(gpio_e_aux_i),
.gpio_e_ext_pad_i(gpio_e_ext_pad_i),
.gpio_e_ext_pad_o(gpio_e_ext_pad_o),
.gpio_e_ext_padoe_o(gpio_e_ext_padoe_o),
.gpio_e_aux_i(gpio_e_aux_i),
.gpio_e_ext_pad_i(gpio_e_ext_pad_i),
.gpio_e_ext_pad_o(gpio_e_ext_pad_o),
.gpio_e_ext_padoe_o(gpio_e_ext_padoe_o),
.gpio_e_inta_o(),
 
.gpio_f_aux_i(gpio_f_aux_i),
.gpio_f_ext_pad_i(gpio_f_ext_pad_i),
.gpio_f_ext_pad_o(gpio_f_ext_pad_o),
.gpio_f_ext_padoe_o(gpio_f_ext_padoe_o),
.gpio_f_aux_i(gpio_f_aux_i),
.gpio_f_ext_pad_i(gpio_f_ext_pad_i),
.gpio_f_ext_pad_o(gpio_f_ext_pad_o),
.gpio_f_ext_padoe_o(gpio_f_ext_padoe_o),
.gpio_f_inta_o(),
 
.gpio_g_aux_i(gpio_g_aux_i),
.gpio_g_ext_pad_i(gpio_g_ext_pad_i),
.gpio_g_ext_pad_o(gpio_g_ext_pad_o),
.gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
.gpio_g_aux_i(gpio_g_aux_i),
.gpio_g_ext_pad_i(gpio_g_ext_pad_i),
.gpio_g_ext_pad_o(gpio_g_ext_pad_o),
.gpio_g_ext_padoe_o(gpio_g_ext_padoe_o),
.gpio_g_inta_o(),
 
.gpio_clk_i(clk_i),

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