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/or1k/tags/final_interface/gdb-5.0/sim/h8300
```
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/acconfig.h

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/configure

0,0 → 1,4013

configure Property changes : Added: svn:executable ## -0,0 +1 ## +* \ No newline at end of property Index: Makefile.in =================================================================== --- Makefile.in (nonexistent) +++ Makefile.in (revision 1765) @@ -0,0 +1,25 @@ +# Makefile template for Configure for the h8300 sim library. +# Copyright (C) 1990, 91, 92, 95, 96, 1997 Free Software Foundation, Inc. +# Written by Cygnus Support. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + +## COMMON_PRE_CONFIG_FRAG + +SIM_OBJS = compile.o sim-load.o + +## COMMON_POST_CONFIG_FRAG + +compile.o: compile.c config.h Index: inst.h =================================================================== --- inst.h (nonexistent) +++ inst.h (revision 1765) @@ -0,0 +1,89 @@ +#define DEBUG + +/* These define the size of main memory for the simulator. + + Note the size of main memory for the H8/300H is only 256k. Keeping it + small makes the simulator run much faster and consume less memory. + + The linker knows about the limited size of the simulator's main memory + on the H8/300H (via the h8300h.sc linker script). So if you change + H8300H_MSIZE, be sure to fix the linker script too. + + Also note that there's a separate "eightbit" area aside from main + memory. For simplicity, the simulator assumes any data memory reference + outside of main memory refers to the eightbit area (in theory, this + can only happen when simulating H8/300H programs). We make no attempt + to catch overlapping addresses, wrapped addresses, etc etc. */ +#define H8300_MSIZE (1<<16) +#define H8300H_MSIZE (1<<18) + +#define CSIZE 1000 + +/* Local register names */ +typedef enum +{ + R0, R1, R2, R3, R4, R5, R6, R7, + R_ZERO, + R_PC, + R_CCR, + R_HARD_0, + R_LAST, +} reg_type; + + +/* Structure used to describe addressing */ + +typedef struct +{ + int type; + int reg; + int literal; +} ea_type; + + + +typedef struct +{ + ea_type src; + ea_type dst; + int opcode; + int next_pc; + int oldpc; + int cycles; +#ifdef DEBUG +struct h8_opcode *op; +#endif +} +decoded_inst; + +enum h8300_sim_state { + SIM_STATE_RUNNING, SIM_STATE_EXITED, SIM_STATE_SIGNALLED, SIM_STATE_STOPPED +}; + +typedef struct +{ + enum h8300_sim_state state; + int exception; + unsigned int regs[9]; + int pc; + int ccr; + + + unsigned char *memory; + unsigned char *eightbit; + unsigned short *cache_idx; + int cache_top; + int maximum; + int csize; + int mask; + + decoded_inst *cache; + int cycles; + int insts; + int ticks; + int compiles; +#ifdef ADEBUG + int stats[O_LAST]; +#endif +} +cpu_state_type; Index: configure.in =================================================================== --- configure.in (nonexistent) +++ configure.in (revision 1765) @@ -0,0 +1,10 @@ +dnl Process this file with autoconf to produce a configure script. +sinclude(../common/aclocal.m4) +AC_PREREQ(2.5)dnl +AC_INIT(Makefile.in) + +SIM_AC_COMMON + +AC_CHECK_HEADERS(stdlib.h time.h sys/param.h) + +SIM_AC_OUTPUT Index: writecode.c =================================================================== --- writecode.c (nonexistent) +++ writecode.c (revision 1765) @@ -0,0 +1,1033 @@ +/* Code generator for the Hitachi H8/300 architecture simulator. + + Written by Steve Chamberlain of Cygnus Support. + sac@cygnus.com + + This file is part of H8/300 sim + + + THIS SOFTWARE IS NOT COPYRIGHTED + + Cygnus offers the following for use in the public domain. Cygnus + makes no warranty with regard to the software or it's performance + and the user accepts the software "AS IS" with all faults. + + CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO + THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. + +*/ + +/* This program reads the H8/300 opcode table and writes out + a large switch statement to understand the opcodes (with ifs if + there is more than one opcode per case) and code to do the stuff */ + +#include + +#define DEFINE_TABLE +#define INSIM +#include"opcode/h8300.h" + +#define MAXSAME 140 + +#define PTWO 256 +static struct h8_opcode *h8_opcodes_sorted[PTWO][MAXSAME]; + +char *cs = "/*"; +char *ce = "*/"; + +/* How to get at nibble n from the instruction */ +char *nibs[] = +{ + "foo", + "(b0&0xf)", + "((b1>>4)&0xf)", + "((b1)&0xf)", + "((pc[1]>>12)&0xf)", + "((pc[1]>>8)&0xf)", + "((pc[1]>>4)&0xf)", + "((pc[1])&0xf)", + 0, 0}; + +/* how to get at the 3 bit immediate in the instruction */ +char *imm3[] = +{"foo", + "foo", + "((b1>>4)&0x7)", + "foo", + "foo", + "foo", + "(pc[1]>>4)&0x7"}; + +/* How to get at a byte register from an index in the instruction at + nibble n */ +char *breg[] = +{"foo", + "*(blow[b0])", + "*(bhigh[b1])", + "*(blow[b1])", + 0, 0, + "*(bhigh[pc[1]>>8])"}; + +/* How to get at a word register from an index in the instruction at + nibble n */ + +char *wreg[] = +{"foo", + "*(wlow[b0])", + "*(whigh[b1])", + "*(wlow[b1])"}; + +#define sorted_key noperands + +/* sort the opcode table into h8_opcodes_sorted[0..255] */ +static void +init () +{ + unsigned int i; + struct h8_opcode *p; + + for (p = h8_opcodes; p->name; p++) + { + int n1 = 0; + int n2 = 0; + int j; +#if 0 + for (j = 0; p->data.nib[j] != E; j++) + { + if ((int) p->data.nib[j] == ABS16ORREL8SRC) + p->data.nib[j] = ABS16SRC; + if ((int) p->data.nib[j] == ABS16OR8SRC) + p->data.nib[j] = ABS16SRC; + if ((int) p->data.nib[j] == ABS16OR8DST) + p->data.nib[j] = ABS16DST; + } +#endif + + if ((int) p->data.nib[0] < 16) + { + n1 = (int) p->data.nib[0]; + } + else + n1 = 0; + if ((int) p->data.nib[1] < 16) + { + n2 = (int) p->data.nib[1]; + } + else + n2 = 0; + for (i = 0; i < MAXSAME; i++) + { + int j = /* ((n3 >> 3) * 512) + ((n4 >> 3) * 256) + */ n1 * 16 + n2; + + if (h8_opcodes_sorted[j][i] == (struct h8_opcode *) NULL) + { + h8_opcodes_sorted[j][i] = p; + p->sorted_key = j; + break; + } + } + + if (i == MAXSAME) + abort (); + + /* Just make sure there are an even number of nibbles in it, and + that the count is the same s the length */ + for (i = 0; p->data.nib[i] != E; i++) + /*EMPTY*/ ; + if (i & 1) + abort (); + p->length = i / 2; + } + for (i = 0; i < PTWO; i++) + { + if (h8_opcodes_sorted[i][0]) + p = h8_opcodes_sorted[i][0]; + else + h8_opcodes_sorted[i][0] = p; + } +} + +/* decode the lvalues, creating a pointer in real space to object - + remember if the thing has to be swapped out of where it is */ + + +int swap[2]; + +lval (p) + struct h8_opcode *p; +{ + int i; + + for (i = 0; p->data.nib[i] != E; i++) + { + int x = p->data.nib[i]; + int size; + int op; + op = (x & DST) ? 1 : 0; + + switch (x & SIZE) + { + case L_32: + size = 32; + break; + case L_16: + size = 16; + break; + case L_8: + size = 8; + break; + default: + size = 1234; + } + + if (x & REG) + { + printf ("ir%d = GET_LVAL_%d_REG(%d);\n", op, size, i); + } + else if (x & IMM) + { + printf ("/* Imm has no lvalue */\n"); + } + + } + + + +} + +void +decode (p, fetch, size) + struct h8_opcode *p; + int fetch; + int size; +{ + if (fetch) + { + lval (p); + } + +} + + + +static void +esleep () +{ + printf ("saved_state.exception = SIGSTOP;\n"); +} + +static void +mov (p, s, sz) + struct h8_opcode *p; + char *s; + int sz; +{ + printf ("dst = srca;\n"); +} + +static void +andc (p) + struct h8_opcode *p; +{ + printf ("SET_CCR(GET_CCR() & srca);\n"); +} + +static void +addx (p) + struct h8_opcode *p; +{ + printf ("dst = srca + srcb+ (c != 0);\n"); +} + +static void +subx (p) + struct h8_opcode *p; +{ + printf ("dst = srcb - srca - (c != 0);\n"); +} + +static void +add (p, s, sz) + struct h8_opcode *p; + char *s; + int sz; +{ + printf ("%s;\n", s); +} + +static void +adds (p, s) + struct h8_opcode *p; + char *s; +{ + printf ("%s;\n", s); +} + +static void +bra (p, a) + struct h8_opcode *p; + char *a; +{ + printf ("if (%s) npc += ((char )b1)>>1;\n", a); +} + +static void +bsr (p, a) + struct h8_opcode *p; + char *a; +{ + printf ("reg[7]-=2;\n"); + printf ("tmp = reg[7];\n"); + printf ("SET_WORD_MEM(tmp, (npc-saved_state.mem)*2);\n"); + printf ("npc += ((char)b1)>>1;\n"); +} + +static void +cmp (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + decode (p, 1, s); + printf ("srca = -srca;\n"); + printf ("dst = srca + srcb;\n"); +} + +static +void +jsr (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("if (b1 == 0xc4) {\n"); + printf ("printf(\"%%c\", reg[2]);\n"); + printf ("}\n"); + printf ("else {\n"); + printf ("reg[7]-=2;\n"); + printf ("tmp = reg[7];\n"); + printf ("SET_WORD_MEM(tmp, (npc-saved_state.mem)*2);\n"); + printf ("npc = (lval>>1) + saved_state.mem;\n"); + printf ("}"); +} + +static void +jmp (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("npc = (lval>>1) + saved_state.mem;\n"); +} + +static void +rts (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("tmp = reg[7];\n"); + printf ("reg[7]+=2;\n"); + printf ("npc = saved_state.mem + (WORD_MEM(tmp)>>1);\n"); +} + +static void +rte (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("reg[7]+=2;\n"); + printf ("tmp = reg[7];\n"); + printf ("reg[7]+=2;\n"); + printf ("SET_CCR(tmp);\n"); + printf ("npc = saved_state.mem + (WORD_MEM(tmp)>>1);\n"); +} + +static void +setf (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("tmp = GET_CCR();\n"); + printf ("tmp %s= srca;\n", a); +} + +static void +bpt (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("saved_state.exception = SIGTRAP;\n"); + printf ("npc = pc;\n"); +} + +static void +log (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("dst = srcb %s srca;\n", a); +} + +static void +ulog (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("dst = %s srcb ;\n", a); +} + +static void +nop () +{ +} + +static void +rotl () +{ + printf ("c = srcb & 0x80;\n"); + printf ("dst = srcb << 1;\n"); + printf ("if (c) dst|=1;\n"); +} + +static void +rotr () +{ + printf ("c = srcb & 1;\n"); + printf ("dst = srcb >> 1;\n"); + printf ("if (c) dst|=0x80;\n"); +} + +static void +rotxl () +{ + printf ("tmp = srcb & 0x80;\n"); + printf ("dst = srcb << 1;\n"); + printf ("if (c) dst|=1;\n"); + printf ("c = tmp;\n"); +} + +static void +rotxr () +{ + printf ("tmp = srcb & 1;\n"); + printf ("dst = srcb >> 1;\n"); + printf ("if (c) dst|=0x80;\n"); + printf ("c = tmp;\n"); +} + +static void +shal () +{ + printf ("c = srcb&0x80;\n"); + printf ("dst = srcb << 1;\n"); +} + +static +void +shar () +{ + printf ("c = srcb&0x1;\n"); + printf ("if (srcb&0x80) dst = (srcb>>1) | 0x80;\n"); + printf ("else dst = (srcb>>1) &~ 0x80;\n"); +} + +static +void +shll () +{ + printf ("c = srcb&0x80;\n"); + printf ("dst = srcb << 1;\n"); +} + +static +void +shlr () +{ + printf ("c = srcb&0x1;\n"); + printf ("dst = (srcb>>1) &~ 0x80;\n"); +} + +static +void +divxu () +{ + printf ("srca = %s;\n", breg[2]); + printf ("srcb = %s;\n", wreg[3]); + printf ("n = srca & 0x80;\n"); + printf ("z = !srca;\n"); + printf ("if (srca) dst = srcb / srca;tmp = srcb %% srca;\n"); + printf ("%s = (dst & 0xff) | (tmp << 8);\n", wreg[3]); +} + +static +void +mulxu () +{ + printf ("srca = %s;\n", breg[2]); + printf ("srcb = %s;\n", wreg[3]); + + printf ("dst = (srcb&0xff) * srca;\n"); + printf ("%s = dst;\n", wreg[3]); +} + +static +void +inc () +{ + printf ("dst = %s;\n", breg[3]); + printf ("v = (dst==0x7f);\n"); + printf ("dst++;\n"); + printf ("%s= dst;\n", breg[3]); +} + +static +void +bit (p, a, s) + struct h8_opcode *p; + char *a; + int s; +{ + printf ("%s\n", a); +} + +static +void +dec () +{ + printf ("dst = %s;\n", breg[3]); + printf ("v = (dst==0x80);\n"); + printf ("dst--;\n"); + printf ("%s = dst;\n", breg[3]); +} + +char saf[] = "goto setflags;"; +char sf[] = "goto shiftflags;"; +char af8[] = "goto aluflags8;"; +char af16[] = "goto aluflags16;"; +char lf[] = "goto logflags;"; +char icf[] = "goto incflags;"; +char mf8[] = "goto movflags8;"; +char mf16[] = "goto movflags16;"; +char nx[] = "goto next;"; + +struct +{ + char *ftype; + int decode; + char *name; + void (*func) (); + char *arg; + int size; + +} + +table[] = +{ + { + nx, 1, "bld", bit, "dst = srcb; c = (srcb>>srca)&1;", 8 + } + , + { + nx, 1, "bild", bit, "dst = srcb; c = !((srcb>>srca)&1);", 8 + } + , + { + nx, 1, "band", bit, "dst = srcb; c = C &&((srcb>>srca)&1);", 8 + } + , + { + nx, 1, "biand", bit, "dst = srcb; c = C &&(!((srcb>>srca)&1));", 8 + } + , + { + nx, 1, "bior", bit, "dst = srcb; c = C ||(!((srcb>>srca)&1));", 8 + } + , + { + nx, 1, "bor", bit, "dst = srcb; c = C ||(((srcb>>srca)&1));", 8 + } + , + { + nx, 1, "bixor", bit, "dst = srcb; c = C ^(!((srcb>>srca)&1));", 8 + } + , + { + nx, 1, "bxor", bit, "dst = srcb; c = C ^(((srcb>>srca)&1));", 8 + } + , + { + nx, 1, "bnot", bit, "dst = srcb ^ (1<>srca)&1);", 8 + } + , + { + icf, 0, "dec", dec, 0, 0 + } + , + { + icf, 0, "inc", inc, 0, 0 + } + , + { + saf, 1, "orc", setf, "|", 0 + } + , + { + saf, 1, "xorc", setf, "^", 0 + } + , + { + saf, 1, "andc", setf, "&", 0 + } + , + { + nx, 1, "nop", nop, 0, 0 + } + , + { + nx, 1, "bra", bra, "1", 0 + } + , + { + nx, 1, "brn", bra, "0", 0 + } + , + { + nx, 1, "bhi", bra, "(C||Z)==0", 0 + } + , + { + nx, 1, "bls", bra, "(C||Z)==1", 0 + } + , + { + nx, 1, "bcs", bra, "C==1", 0 + } + , + { + nx, 1, "bcc", bra, "C==0", 0 + } + , + { + nx, 1, "bpl", bra, "N==0", 0 + } + , + { + nx, 1, "bmi", bra, "N==1", 0 + } + , + { + nx, 1, "bvs", bra, "V==1", 0 + } + , + { + nx, 1, "bvc", bra, "V==0", 0 + } + , + { + nx, 1, "bge", bra, "(N^V)==0", 0 + } + , + { + nx, 1, "bgt", bra, "(Z|(N^V))==0", 0 + } + , + { + nx, 1, "blt", bra, "(N^V)==1", 0 + } + , + { + nx, 1, "ble", bra, "(Z|(N^V))==1", 0 + } + , + { + nx, 1, "beq", bra, "Z==1", 0 + } + , + { + nx, 1, "bne", bra, "Z==0", 0 + } + , + { + nx, 1, "bsr", bsr, "", 0 + } + , + { + nx, 1, "jsr", jsr, 0, 0 + } + , + { + nx, 1, "jmp", jmp, 0, 0 + } + , + { + nx, 0, "rts", rts, 0, 0 + } + , + { + nx, 0, "rte", rte, 0, 0 + } + , + { + nx, 1, "andc", andc, 0, 0 + } + , + { + sf, 1, "shal", shal, 0, 0 + } + , + { + sf, 1, "shar", shar, 0, 0 + } + , + { + sf, 1, "shll", shll, 0, 0 + } + , + { + sf, 1, "shlr", shlr, 0, 0 + } + , + { + sf, 1, "rotxl", rotxl, 0, 0 + } + , + { + sf, 1, "rotxr", rotxr, 0, 0 + } + , + { + sf, 1, "rotl", rotl, 0, 0 + } + , + { + sf, 1, "rotr", rotr, 0, 0 + } + , + { + lf, 1, "xor", log, "^", 0 + } + , + { + lf, 1, "and", log, "&", 0 + } + , + { + lf, 1, "or", log, "|", 0 + } + , + { + lf, 1, "not", ulog, " ~", 0 + } + , + { + lf, 1, "neg", ulog, " - ", 0 + } + , + { + nx, 1, "adds", adds, "dst = srca + srcb", 0 + } + , + { + nx, 1, "subs", adds, "srca = -srca; dst = srcb + srca", 0 + } + , + { + af8, 1, "add.b", add, "dst = srca + srcb", 8 + } + , + { + af16, 1, "add.w", add, "dst = srca + srcb", 16 + } + , + { + af16, 1, "sub.w", add, "srca = -srca; dst = srcb + srca", 16 + } + , + { + af8, 1, "sub.b", add, "srca = -srca; dst = srcb + srca", 8 + } + , + { + af8, 1, "addx", addx, 0, 8 + } + , + { + af8, 1, "subx", subx, 0, 8 + } + , + { + af8, 0, "cmp.b", cmp, 0, 8 + } + , + { + af16, 0, "cmp.w", cmp, 0, 16 + } + , + { + nx, 1, "sleep", esleep, 0, 0 + } + , + { + nx, 0, "bpt", bpt, 0, 8 + } + , + { + nx, 0, "divxu", divxu, 0, 0 + } + , + { + nx, 0, "mulxu", mulxu, 0, 0 + } + , + { + mf8, 1, "mov.b", mov, 0, 8 + } + , + { + mf8, 1, "movtpe", mov, 0, 8 + } + , + { + mf8, 1, "movfpe", mov, 0, 8 + } + , + { + mf16, 1, "mov.w", mov, 0, 16 + } + , + { + 0 + } +}; + +static +void +edo (p) + struct h8_opcode *p; +{ + int i; + + printf ("%s %s %s\n", cs, p->name, ce); + + for (i = 0; table[i].name; i++) + { + if (strcmp (table[i].name, p->name) == 0) + { + printf ("{\n"); + if (table[i].decode) + decode (p, 1, table[i].size); + printf ("cycles += %d;\n", p->time); + printf ("npc = pc + %d;\n", p->length / 2); + table[i].func (p, table[i].arg, table[i].size); + if (table[i].decode) + decode (p, 0, table[i].size); + if (table[i].ftype) + printf (table[i].ftype); + else + printf ("goto next;\n"); + printf ("}\n"); + return; + } + } + printf ("%s not found %s\n", cs, ce); + printf ("saved_state.exception = SIGILL;\n"); + printf ("break;\n"); +} + +static +int +owrite (i) + int i; +{ + /* write if statements to select the right opcode */ + struct h8_opcode **p; + int needand = 1; + + p = h8_opcodes_sorted[i]; + printf ("case 0x%03x:\n", i); + + if (p[1] == 0) + { + /* See if the next few also match */ + while (h8_opcodes_sorted[i + 1][0] == *p) + { + i++; + printf ("case 0x%03x:\n", i); + } + + /* Dont need any if's this is the only one */ + edo (*p); + } + else + { + while (*p) + { + /* start two nibbles in since we know we match in the first byte */ + int c; + int nib = 2; + int byte = 1; + int mask1[5]; + int mask0[5]; + int nibshift = 4; + int any = 0; + + for (c = 0; c < 5; c++) + { + mask1[c] = 0; + mask0[c] = 0; + } + printf ("%s %x%x", cs, (*p)->data.nib[0], (*p)->data.nib[1]); + while ((c = (*p)->data.nib[nib]) != E) + { + if (c & B30) + { + /* bit 3 must be zero */ + mask0[byte] |= 0x8 << nibshift; + printf ("0"); + any = 1; + } + else if (c & B31) + { + /* bit 3 must be one */ + mask1[byte] |= 0x8 << nibshift; + printf ("8"); + any = 1; + } + else if (c <= HexF) + { + mask0[byte] |= ((~c) & 0xf) << nibshift; + mask1[byte] |= (c & 0xf) << nibshift; + printf ("%x", c); + any = 1; + } + else + { + printf ("x"); + } + nib++; + if (nibshift == 4) + { + nibshift = 0; + } + else + { + byte++; + nibshift = 4; + } + } + printf ("*/\n"); + if (any) + { + printf ("if ("); + needand = 0; + for (c = 1; c < byte; c++) + { + if (mask0[c] | mask1[c]) + { + int sh; + + if (needand) + printf ("\n&&"); + if (c & 1) + sh = 0; + else + sh = 8; + if (c / 2 == 0 && sh == 0) + printf ("((b1&0x%x)==0x%x)", mask0[c] | mask1[c], + mask1[c]); + else + { + printf ("((pc[%d]&(0x%02x<<%d))==(0x%x<<%d))", + c / 2, mask0[c] | mask1[c], sh, + mask1[c], sh); + } + + needand = 1; + } + } + printf (")\n"); + } + edo (*p); + p++; + + } + } + return i; +} + +static +void +remove_dups () +{ + struct h8_opcode *s; + struct h8_opcode *d; + + for (d = s = h8_opcodes; s->name; s++) + { + int doit = 1; + + if (strcmp (s->name, "push") == 0) + doit = 0; + if (strcmp (s->name, "bhs") == 0) + doit = 0; + if (strcmp (s->name, "blo") == 0) + doit = 0; + if (strcmp (s->name, "bt") == 0) + doit = 0; + if (strcmp (s->name, "bf") == 0) + doit = 0; + if (strcmp (s->name, "pop") == 0) + doit = 0; + if (doit) + { + *d++ = *s; + } + } + *d++ = *s++; +} + +int +main () +{ + int i; + + remove_dups (); + init (); + + printf ("%s do the operation %s\n", cs, ce); + printf ("switch (b0) \n{\n"); + for (i = 0; i < PTWO; i++) + { + i = owrite (i); + } + printf ("}\n"); + + return 0; +} Index: ChangeLog =================================================================== --- ChangeLog (nonexistent) +++ ChangeLog (revision 1765) @@ -0,0 +1,605 @@ +Thu Sep 2 18:15:53 1999 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-05-08 Felix Lee + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +1999-04-02 Keith Seitz + + * compile.c (POLL_QUIT_INTERVAL): Define. Used to tweak the + frequency at which the poll_quit callback is used. + (sim_resume): Use POLL_QUIT_INTERVAL instead of hard-coded value. + +Tue Apr 28 18:33:31 1998 Geoffrey Noer + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sun Apr 26 15:31:55 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Sun Apr 26 15:20:14 1998 Tom Tromey + + * acconfig.h: New file. + * configure.in: Reverted change of Apr 24; use sinclude again. + +Fri Apr 24 14:16:40 1998 Tom Tromey + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Fri Apr 24 11:19:46 1998 Tom Tromey + + * configure.in: Don't call sinclude. + +Sat Apr 4 20:36:25 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Mar 27 16:15:52 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 25 12:35:29 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 18 12:38:12 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Feb 17 12:42:18 1998 Andrew Cagney + + * compile.c (sim_store_register, sim_fetch_register): Pass in + length parameter. Return -1. + +Sun Feb 1 16:47:51 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Sat Jan 31 18:15:41 1998 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Jan 19 22:26:29 1998 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Dec 15 23:17:11 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Thu Dec 4 09:21:05 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Nov 11 16:52:07 1997 Angela Marie Thomas (angela@cygnus.com) + + * compile.c: #include stdio.h for definition of NULL on + some platforms. + +Wed Oct 22 14:43:00 1997 Andrew Cagney + + * compile.c (sim_load): Pass lma_p and sim_write args to + sim_load_file. + +Fri Oct 3 09:28:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 24 17:38:57 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 23 11:04:38 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Sep 22 11:46:20 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Sep 19 17:45:25 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Sep 17 12:00:57 1997 Andrew Cagney + + * Makefile.in (compile.o): Depend on config.h in local directory. + +Mon Sep 15 17:36:15 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Tue Sep 9 22:17:26 1997 Felix Lee + + * inst.h (sim_state): rename to h8300_sim_state, to avoid conflict + with sim/common. + * configure.in: check for sys/param.h + * compile.c: #ifdef HAVE_SYS_PARAM_H. + #define SIGTRAP for wingdb. + (sim_resume): poll keyboard at least once per call. + (sim_resume): use host_callback instead of printf for syscall + output. + +Thu Sep 4 17:21:23 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Aug 27 18:13:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Tue Aug 26 10:38:43 1997 Andrew Cagney + + * compile.c (sim_kill): Delete. + (sim_create_inferior): Add ABFD argument. + (sim_load): Move setting of PC from here. + (sim_create_inferior): To here. + (sim_open, sim_load, set_h8300h): Add fixme explaining why much of + the sim_load code should be moved to sim_open. + +Mon Aug 25 17:50:22 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Mon Aug 25 15:47:41 1997 Andrew Cagney + + * compile.c (sim_open): Add ABFD argument. + +Tue May 20 10:16:48 1997 Andrew Cagney + + * compile.c (sim_open): Add callback argument. + (sim_set_callbacks): Delete SIM_DESC argument. + +Wed Apr 30 10:22:29 1997 Doug Evans + + * compile.c (sim_load): Call bfd_get_mach instead of examining + bfd fields directly. + * tconfig.in (SIM_PRE_LOAD): Delete, no longer used. + +Thu Apr 24 00:39:51 1997 Doug Evans + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Fri Apr 18 14:30:09 1997 Andrew Cagney + + * compile.c (sim_resume): Use poll_quit callback. + (sim_stop): New function. + +Thu Apr 17 03:06:39 1997 Doug Evans + + * Makefile.in (SIM_OBJS): Add sim-load.o. + * compile.c (sim_kind, myname): New static locals. + (sim_open): Set sim_kind, myname. + (sim_load): Return SIM_RC. New arg abfd. Update test for h8300h. + Call sim_load_file to load file into simulator. Set start address + from bfd. + (sim_create_inferior): Return SIM_RC. Delete arg start_address. + +Mon Apr 7 15:45:02 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + * config.in: Ditto. + +Wed Apr 2 15:06:28 1997 Doug Evans + + * compile.c (sim_open): New arg `kind'. + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Apr 2 14:34:19 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Wed Mar 19 01:14:00 1997 Andrew Cagney + + * configure: Regenerated to track ../common/aclocal.m4 changes. + +Mon Mar 17 15:10:07 1997 Andrew Cagney + + * configure: Re-generate. + +Fri Mar 14 10:34:11 1997 Michael Meissner + + * configure: Regenerate to track ../common/aclocal.m4 changes. + +Thu Mar 13 12:48:05 1997 Doug Evans + + * compile.c (sim_open): New SIM_DESC result. Argument is now in + argv form. + (other sim_*): New SIM_DESC argument. + +Tue Feb 4 13:36:29 1997 Doug Evans + + * Makefile.in (@COMMON_MAKEFILE_FRAG): Use + COMMON_{PRE,POST}_CONFIG_FRAG instead. + * configure.in: sinclude ../common/aclocal.m4. + * configure: Regenerated. + +Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) + + * configure configure.in Makefile.in: Update to new configure + scheme which is more compatible with WinGDB builds. + * configure.in: Improve comment on how to run autoconf. + * configure: Re-run autoconf to get new ../common/aclocal.m4. + * Makefile.in: Use autoconf substitution to install common + makefile fragment. + +Wed Nov 20 01:39:12 1996 Doug Evans + + * Makefile.in: Delete stuff moved to ../common/Make-common.in. + (SIM_OBJS): Define. + * configure.in: Simplify using macros in ../common/aclocal.m4. + * configure: Regenerated. + * inst.h (enum sim_state): Define. + (cpu_state_type): New member `state'. Set it whenever `exception' + is set. + * compile.c (sim_callback): New global. + (sim_set_simcache_size): Renamed from sim_csize. + (sim_resume, case O_SLEEP): Add right way to decode r0 but #if 0 out + 'cus it can't work. Change main loop exit test to use cpu.state. + (sim_trace): New function. + (sim_stop_reason): Add right way to set results, but #if 0 out. + (sim_size): New function. + (sim_info): Redirect calls to printf_filtered through callback. + (sim_set_callbacks): Record callback. + * run.c: Deleted, using one in ../common now. + * tconfig.in: New file. + +Thu Oct 3 16:13:18 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (mostlyclean): Don't remove config.log here. + +Fri Aug 9 22:59:11 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): rts, sleep, bpt and nop have + no associated "size". + +Tue Jul 9 22:15:39 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Fix all rotate-by-2-bits insns. + +Tue Jul 2 23:08:45 1996 Jeffrey A Law (law@cygnus.com) + + * run.c (main): Don't "load" sections which don't have + SEC_LOAD set. + * compile.c (sim_resume, case "O_NOT"): Use ONOT instead + of OSHIFTS. + (ONOT): Define. + (sim_resume, shift/rotate cases): Add support for shift/rotate + by two bits. + (OSHIFTS): Corresponding changes. + +Tue Jul 2 01:37:27 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Handle "ldm.l" and "stm.l". + +Wed Jun 26 08:58:53 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (h8300smode): Declare. + +Wed Jun 26 12:20:56 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) + + * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, + INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. + (docdir): Removed. + * configure.in (AC_PREREQ): autoconf 2.5 or higher. + (AC_PROG_INSTALL): Added. + * configure: Rebuilt. + +Tue Jun 18 16:31:10 1996 Jeffrey A. Law + + * compile.c (sim_load): Treat the H8/S like the H8/300H for now. + * run.c (main): Treat the H8/S like the H8/300H for now. + +Fri May 24 10:35:25 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (SEXTCHAR): Clear upper bits when sign + bit is clear. + +Wed May 22 22:23:37 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Correctly handle divu. + +Tue May 7 02:13:05 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Never allow the PC to have an + odd value. + +Fri Apr 12 16:50:37 1996 Jeffrey A Law (law@cygnus.com) + + * inst.h: Expand on comments regarding H8300H_MSIZE. Note + separate memory is allocate for the 8-bit area. + (struct cpu_state_type): Add new "eightbit' field. + * compile.c (GET_MEMORY_L): Handle access into the 8-bit + area. + (GET_MEMORY_W, GET_MEMORY_B): Likewise. + (SET_MEMORY_L, SET_MEMORY_W, SET_MEMORY_B): Likewise. + (init_pointers): Initialize space for the 8-bit area. + (sim_write): Handle writing into the 8-bit area. + (sim_read): Handle reading from the 8-bit area. + (sim_load): Reallocate space for the 8-bit area. + + * compile.c (sim_load): Re-allocate memory for the simulator + here. + +Fri Apr 12 09:39:56 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Fix and simplify overflow and carry + handling for 32bit ALU insns. + +Mon Apr 8 23:58:49 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (sim_resume): Fix overflow checks for ALU insns. + +Fri Apr 5 17:20:59 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (decode): Use "bit" to hold L_3 immediates instead + of holding them in "abs". Handle ABS8MEM memory references aka + 8-bit area. Replace ABSMOV references with ABS8MEM. + +Wed Mar 13 17:43:56 1996 Jeffrey A Law (law@cygnus.com) + + * compile.c (fetch): Handle accesses to the exception/function + vectors. + +Mon Mar 11 09:53:25 1996 Doug Evans + + * compile.c: #include "wait.h". + (sim_resume, sleep insn): Check program exit status in r0. + (sim_resume, shift insns): Fix setting of overflow flag for shal. + * run.c: #include . + (main): Abort if program got SIGILL. + Print error message if argument is invalid. + (usage): Improve text. + +Wed Feb 21 12:15:00 1996 Ian Lance Taylor + + * configure: Regenerate with autoconf 2.7. + +Thu Jan 4 11:52:53 1996 Doug Evans + + * inst.h (MPOWER,MSIZE): Deleted. + (H8300{,H}_MSIZE): Define. + * compile.c (memory_size): New static global. + (init_pointers): Set memory size from one of H8300{,H}_MSIZE. + (sim_write,sim_read): Use memory_size. + +Fri Oct 13 15:03:19 1995 steve chamberlain + + * compile.c (sim_set_callbacks): New. + +Tue Oct 10 11:11:26 1995 Fred Fish + + * Makefile.in (BISON): Remove macro. + +Wed Sep 20 13:35:02 1995 Ian Lance Taylor + + * Makefile.in (maintainer-clean): New synonym for realclean. + +Fri Sep 8 12:18:53 1995 Ian Lance Taylor + + * Makefile.in (install): Don't install in $(tooldir). + + * configure.in: Call AC_CONFIG_HEADER. Don't try to use + bfd/hosts/*.h file or bfd/config/*.mh file. Call AC_PROG_CC and + AC_PROG_RANLIB. Substitute in values for CFLAGS, HDEFINES and AR. + Call AC_CHECK_HEADERS for stdlib.h and time.h. Touch stamp.h if + creating config.h. + * configure: Rebuild. + * config.in: New file, created by autoheader. + * Makefile.in (AR): Define as @AR@. + (CC): New variable, defined as @CC@. + (CFLAGS): Define as @CFLAGS@. + (RANLIB): Define as @RANLIB@. + (HDEFINES, TDEFINES): New variables. + (@host_makefile_frag@): Remove. + (compile.o, run.o): Depend upon config.h. + (mostlyclean): Make the same as clean, not distclean. + (clean): Remove config.log. + (distclean): Remove config.h and stamp-h. + (Makefile): Don't depend upon @frags@. Just rebuild Makefile when + invoking config.status. + (config.h, stamp-h): New targets. + * compile.c: Include "config.h". Don't include . + Include and if they exist. Don't include + "sysdep.h". + (get_now): Remove unused local b. + * run.c: Include "config.h". Include if it exists. + Don't include "sysdep.h". + * writecode.c: Don't include "bfd.h" or "sysdep.h". Include + . + +Thu Aug 3 10:45:37 1995 Fred Fish + + * Update all FSF addresses except those in COPYING* files. + +Wed Jul 5 14:32:54 1995 J.T. Conklin + + * Makefile.in (clean): Remove run. + (distclean): Remove Makefile. + + * h8300.mt: Removed. + + * Makefile.in, configure.in: converted to autoconf. + * configure: New file, generated with autconf 2.4. + +Fri Jun 30 16:50:24 1995 Stan Shebs + + * compile.c (sim_do_command): New function. + +Tue Jun 20 16:18:13 1995 Steve Chamberlain + + * compile.c (get_now): Don't do if win32. + (sim_resume): Poll in win32 too. + +Wed May 24 16:31:38 1995 Jim Wilson + + * configure.in: Fix typo in last change. + +Mon Mar 27 10:32:34 1995 J.T. Conklin + + * run.c: parse arguments with getopt(). + +Tue Feb 28 17:30:08 1995 Ian Lance Taylor + + * configure.in: Use ../../bfd/hosts/std-host.h if specific + host unavailable. + +Sun Jan 22 12:35:43 1995 Steve Chamberlain + + * compile.c (sim_resume): Initialize cpu.mask. + +Thu Sep 8 16:53:00 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * inst.h (MPOWER): Bump simulated memory size to 2^18 bytes. + +Wed May 18 13:47:58 1994 Doug Evans (dje@canuck.cygnus.com) + + * compile.c: #include "bfd.h". + (sim_*): Set result type to void where there isn't one. + (sim_resume, default case): Set cpu.exception to SIGILL. + (sim_trace): Delete. + (sim_set_pc): Delete. + (sim_info): Delete printf_fn arg, all callers changed. + Call printf_filtered. + (set_h8300h): New arg `flag', all callers changed. + (sim_close): New function. + (sim_load): New function. + (sim_create_inferior): Renamed from sim_set_args, all callers changed. + * run.c: #include , "remote-sim.h". + (printf_filtered): New function. + +Fri May 13 18:32:27 1994 Doug Evans (dje@canuck.cygnus.com) + + * compile.c (decode): Fix typo (16 bit branches). + (*): Some white space clean up. + +Fri May 6 13:44:01 1994 Steve Chamberlain (sac@jonny.cygnus.com) + + * compile.c (decode): Compile 16bit branches properly. + +Sat Dec 11 16:32:36 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * compile.c: Tidy up formatting. (sim_resume): Add orc, xorc, + andc. Poll for interrupts. + +Thu Oct 28 19:29:34 1993 Doug Evans (dje@canuck.cygnus.com) + + * compile.c: #include "ansidecl.h" for remote-sim.h. + +Tue Oct 26 09:43:36 1993 Doug Evans (dje@canuck.cygnus.com) + + * Makefile.in (CSEARCH): Add -I$(srcdir)/../../gdb + * compile.c: #include "remote-sim.h". + (sim_resume): New arg siggnal. + (sim_write): Use SIM_ADDR for type of arg addr. + Always return a value. + (sim_read): Ditto. + (sim_store_register): Result is type int. + (sim_fetch_register): Ditto. + (sim_stop_reason): Renamed from sim_stop_signal. + (sim_set_pc): Use SIM_ADDR for type of arg pc. + (sim_info): int result, new arg printf_fn. + (sim_kill): int result. + (sim_open): int result, new arg name. + * run.c (main): Use sim_set_pc to set pc. + Update call to sim_info. + +Sat Oct 23 15:01:18 1993 Doug Evans (dje@canuck.cygnus.com) + + * compile.c (sim_stop_signal): Result is now enum sim_stop. + +Fri Oct 15 23:49:27 1993 Jim Kingdon (kingdon@lioth.cygnus.com) + + * compile.c (sim_kill, sim_open, sim_set_args): New functions. + +Thu Oct 7 16:24:10 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * compile.c (sim_set_pc): Write to the pc direcly. + (sim_store_register): Now value is passed by reference. (sim_read, + sim_write): Return number of bytes copied. + +Tue Aug 17 07:16:15 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * compile.c (mop): New function to do multiplies. + +Fri Jul 16 13:53:53 1993 Doug Evans (dje@canuck.cygnus.com) + + * compile.c (sim_resume): Add support for nop insn. + +Thu Jul 15 09:59:01 1993 Doug Evans (dje@canuck.cygnus.com) + + * compile.c: Reset HMODE back to zero (accidently set it to 1). + + * run.c (main): If h8/300h binary detected, call set_h8300h. + * compile.c (sim_resume): Fix O_NEG insn. + +Fri Jul 9 14:36:48 1993 Doug Evans (dje@canuck.cygnus.com) + + * run.c (main): Add -h flag to enable h8/300h emulation. + * compile.c: Rename Hmode to HMODE (consistency with gdb). + (set_h8300h): New function. + (sim_resume): Add support for extu,exts insns. + (sim_resume): Fix logical right shifting. + (sim_resume, label alu32): Fix setting of carry flag. + +Sun Jul 4 00:35:41 1993 Doug Evans (dje@canuck.cygnus.com) + + * compile.c (sim_csize): Initialize cpu.cache. + +Fri Jul 2 17:42:59 1993 Doug Evans (dje@canuck.cygnus.com) + + * Makefile.in: Add -I../../bfd to pick up bfd.h. + +Thu Jun 24 13:40:12 1993 Doug Evans (dje@canuck.cygnus.com) + + * run.c (main): Fix parsing of args. + + * compile.c (sim_resume): Fix shll insn. + +Tue Jun 8 14:16:46 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) + + * compile.c: New file, supports H8/300H. + * p1,p3, gencode.c, state.h, writecode.c All dead and obsolete. + +Tue Jun 1 11:14:59 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * run.c (main): Add -v to print info. + * p3.c (sim_info): New function. + +Mon Mar 15 15:48:31 1993 Ian Lance Taylor (ian@cygnus.com) + + * h8300.mt (DO_INSTALL): Renamed from INSTALL. + +Wed Mar 3 15:06:53 1993 Steve Chamberlain (sac@poseidon.cygnus.com) + + * Makefile.in: Don't use cb or indent + * p1.c, state.h, writecode.c: lint + +Mon Feb 1 16:44:58 1993 John Gilmore (gnu@cygnus.com) + + * Makefile.in: Make SunOS halfdone VPATH work. + * p1.c: Lint picked up by HP native compiler. + +Mon Jan 4 12:32:35 1993 Steve Chamberlain (sac@wahini.cygnus.com) + + * p1.c (sim_resume): when running on dos, any character typed to + the keyboard will cause a simulated exception. + +Sun Jan 3 14:15:07 1993 Steve Chamberlain (sac@thepub.cygnus.com) + + * p1.c, p3.c, run.c, writecode.c: all used h8/300 opcodes in and + running + +Tue Dec 22 13:56:48 1992 Steve Chamberlain (sac@thepub.cygnus.com) + + * new + Index: compile.c =================================================================== --- compile.c (nonexistent) +++ compile.c (revision 1765) @@ -0,0 +1,2173 @@ +/* + * Simulator for the Hitachi H8/300 architecture. + * + * Written by Steve Chamberlain of Cygnus Support. sac@cygnus.com + * + * This file is part of H8/300 sim + * + * + * THIS SOFTWARE IS NOT COPYRIGHTED + * + * Cygnus offers the following for use in the public domain. Cygnus makes no + * warranty with regard to the software or its performance and the user + * accepts the software "AS IS" with all faults. + * + * CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO THIS + * SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#include "config.h" + +#include +#include +#ifdef HAVE_TIME_H +#include +#endif +#ifdef HAVE_STDLIB_H +#include +#endif +#ifdef HAVE_SYS_PARAM_H +#include +#endif +#include "wait.h" +#include "ansidecl.h" +#include "bfd.h" +#include "callback.h" +#include "remote-sim.h" + +#ifndef SIGTRAP +# define SIGTRAP 5 +#endif + +int debug; + +host_callback *sim_callback; + +static SIM_OPEN_KIND sim_kind; +static char *myname; + +/* FIXME: Needs to live in header file. + This header should also include the things in remote-sim.h. + One could move this to remote-sim.h but this function isn't needed + by gdb. */ +void sim_set_simcache_size PARAMS ((int)); + +#define X(op, size) op*4+size + +#define SP (h8300hmode ? SL:SW) +#define SB 0 +#define SW 1 +#define SL 2 +#define OP_REG 1 +#define OP_DEC 2 +#define OP_DISP 3 +#define OP_INC 4 +#define OP_PCREL 5 +#define OP_MEM 6 +#define OP_CCR 7 +#define OP_IMM 8 +#define OP_ABS 10 +#define h8_opcodes ops +#define DEFINE_TABLE +#include "opcode/h8300.h" + +#include "inst.h" + +/* The rate at which to call the host's poll_quit callback. */ + +#define POLL_QUIT_INTERVAL 0x80000 + +#define LOW_BYTE(x) ((x) & 0xff) +#define HIGH_BYTE(x) (((x)>>8) & 0xff) +#define P(X,Y) ((X<<8) | Y) + +#define BUILDSR() cpu.ccr = (N << 3) | (Z << 2) | (V<<1) | C; + +#define GETSR() \ + c = (cpu.ccr >> 0) & 1;\ + v = (cpu.ccr >> 1) & 1;\ + nz = !((cpu.ccr >> 2) & 1);\ + n = (cpu.ccr >> 3) & 1; + +#ifdef __CHAR_IS_SIGNED__ +#define SEXTCHAR(x) ((char)(x)) +#endif + +#ifndef SEXTCHAR +#define SEXTCHAR(x) ((x & 0x80) ? (x | ~0xff): x & 0xff) +#endif + +#define UEXTCHAR(x) ((x) & 0xff) +#define UEXTSHORT(x) ((x) & 0xffff) +#define SEXTSHORT(x) ((short)(x)) + +static cpu_state_type cpu; + +int h8300hmode = 0; +int h8300smode = 0; + +static int memory_size; + + +static int +get_now () +{ +#ifndef WIN32 + return time (0); +#endif + return 0; +} + +static int +now_persec () +{ + return 1; +} + + +static int +bitfrom (x) +{ + switch (x & SIZE) + { + case L_8: + return SB; + case L_16: + return SW; + case L_32: + return SL; + case L_P: + return h8300hmode ? SL : SW; + } +} + +static +unsigned int +lvalue (x, rn) +{ + switch (x / 4) + { + case OP_DISP: + if (rn == 8) + { + return X (OP_IMM, SP); + } + return X (OP_REG, SP); + + case OP_MEM: + + return X (OP_MEM, SP); + default: + abort (); + } +} + +static unsigned int +decode (addr, data, dst) + int addr; + unsigned char *data; + decoded_inst *dst; + +{ + int rs = 0; + int rd = 0; + int rdisp = 0; + int abs = 0; + int plen = 0; + int bit = 0; + + struct h8_opcode *q = h8_opcodes; + int size = 0; + dst->dst.type = -1; + dst->src.type = -1; + /* Find the exact opcode/arg combo */ + while (q->name) + { + op_type *nib; + unsigned int len = 0; + + nib = q->data.nib; + + while (1) + { + op_type looking_for = *nib; + int thisnib = data[len >> 1]; + + thisnib = (len & 1) ? (thisnib & 0xf) : ((thisnib >> 4) & 0xf); + + if (looking_for < 16 && looking_for >= 0) + { + if (looking_for != thisnib) + goto fail; + } + else + { + if ((int) looking_for & (int) B31) + { + if (!(((int) thisnib & 0x8) != 0)) + goto fail; + looking_for = (op_type) ((int) looking_for & ~(int) + B31); + thisnib &= 0x7; + } + if ((int) looking_for & (int) B30) + { + if (!(((int) thisnib & 0x8) == 0)) + goto fail; + looking_for = (op_type) ((int) looking_for & ~(int) B30); + } + if (looking_for & DBIT) + { + if ((looking_for & 5) != (thisnib & 5)) + goto fail; + abs = (thisnib & 0x8) ? 2 : 1; + } + else if (looking_for & (REG | IND | INC | DEC)) + { + if (looking_for & REG) + { + /* + * Can work out size from the + * register + */ + size = bitfrom (looking_for); + } + if (looking_for & SRC) + { + rs = thisnib; + } + else + { + rd = thisnib; + } + } + else if (looking_for & L_16) + { + abs = (data[len >> 1]) * 256 + data[(len + 2) >> 1]; + plen = 16; + if (looking_for & (PCREL | DISP)) + { + abs = (short) (abs); + } + } + else if (looking_for & ABSJMP) + { + abs = + (data[1] << 16) + | (data[2] << 8) + | (data[3]); + } + else if (looking_for & MEMIND) + { + abs = data[1]; + } + else if (looking_for & L_32) + { + int i = len >> 1; + abs = (data[i] << 24) + | (data[i + 1] << 16) + | (data[i + 2] << 8) + | (data[i + 3]); + + plen = 32; + } + else if (looking_for & L_24) + { + int i = len >> 1; + abs = (data[i] << 16) | (data[i + 1] << 8) | (data[i + 2]); + plen = 24; + } + else if (looking_for & IGNORE) + { + /* nothing to do */ + } + else if (looking_for & DISPREG) + { + rdisp = thisnib & 0x7; + } + else if (looking_for & KBIT) + { + switch (thisnib) + { + case 9: + abs = 4; + break; + case 8: + abs = 2; + break; + case 0: + abs = 1; + break; + } + } + else if (looking_for & L_8) + { + plen = 8; + + if (looking_for & PCREL) + { + abs = SEXTCHAR (data[len >> 1]); + } + else if (looking_for & ABS8MEM) + { + plen = 8; + abs = h8300hmode ? ~0xff0000ff : ~0xffff00ff; + abs |= data[len >> 1] & 0xff ; + } + else + { + abs = data[len >> 1] & 0xff; + } + } + else if (looking_for & L_3) + { + plen = 3; + + bit = thisnib; + } + else if (looking_for == E) + { + dst->op = q; + + /* Fill in the args */ + { + op_type *args = q->args.nib; + int hadone = 0; + + while (*args != E) + { + int x = *args; + int rn = (x & DST) ? rd : rs; + ea_type *p; + + if (x & DST) + { + p = &(dst->dst); + } + else + { + p = &(dst->src); + } + + if (x & (L_3)) + { + p->type = X (OP_IMM, size); + p->literal = bit; + } + else if (x & (IMM | KBIT | DBIT)) + { + p->type = X (OP_IMM, size); + p->literal = abs; + } + else if (x & REG) + { + /* Reset the size, some + ops (like mul) have two sizes */ + + size = bitfrom (x); + p->type = X (OP_REG, size); + p->reg = rn; + } + else if (x & INC) + { + p->type = X (OP_INC, size); + p->reg = rn & 0x7; + } + else if (x & DEC) + { + p->type = X (OP_DEC, size); + p->reg = rn & 0x7; + } + else if (x & IND) + { + p->type = X (OP_DISP, size); + p->reg = rn & 0x7; + p->literal = 0; + } + else if (x & (ABS | ABSJMP | ABS8MEM)) + { + p->type = X (OP_DISP, size); + p->literal = abs; + p->reg = 8; + } + else if (x & MEMIND) + { + p->type = X (OP_MEM, size); + p->literal = abs; + } + else if (x & PCREL) + { + p->type = X (OP_PCREL, size); + p->literal = abs + addr + 2; + if (x & L_16) + p->literal += 2; + } + else if (x & ABSJMP) + { + p->type = X (OP_IMM, SP); + p->literal = abs; + } + else if (x & DISP) + { + p->type = X (OP_DISP, size); + p->literal = abs; + p->reg = rdisp & 0x7; + } + else if (x & CCR) + { + p->type = OP_CCR; + } + else + printf ("Hmmmm %x", x); + + args++; + } + } + + /* + * But a jmp or a jsr gets + * automagically lvalued, since we + * branch to their address not their + * contents + */ + if (q->how == O (O_JSR, SB) + || q->how == O (O_JMP, SB)) + { + dst->src.type = lvalue (dst->src.type, dst->src.reg); + } + + if (dst->dst.type == -1) + dst->dst = dst->src; + + dst->opcode = q->how; + dst->cycles = q->time; + + /* And a jsr to 0xc4 is turned into a magic trap */ + + if (dst->opcode == O (O_JSR, SB)) + { + if (dst->src.literal == 0xc4) + { + dst->opcode = O (O_SYSCALL, SB); + } + } + + dst->next_pc = addr + len / 2; + return; + } + else + { + printf ("Dont understand %x \n", looking_for); + } + } + + len++; + nib++; + } + + fail: + q++; + } + + dst->opcode = O (O_ILL, SB); +} + + +static void +compile (pc) +{ + int idx; + + /* find the next cache entry to use */ + + idx = cpu.cache_top + 1; + cpu.compiles++; + if (idx >= cpu.csize) + { + idx = 1; + } + cpu.cache_top = idx; + + /* Throw away its old meaning */ + cpu.cache_idx[cpu.cache[idx].oldpc] = 0; + + /* set to new address */ + cpu.cache[idx].oldpc = pc; + + /* fill in instruction info */ + decode (pc, cpu.memory + pc, cpu.cache + idx); + + /* point to new cache entry */ + cpu.cache_idx[pc] = idx; +} + + +static unsigned char *breg[18]; +static unsigned short *wreg[18]; +static unsigned int *lreg[18]; + +#define GET_B_REG(x) *(breg[x]) +#define SET_B_REG(x,y) (*(breg[x])) = (y) +#define GET_W_REG(x) *(wreg[x]) +#define SET_W_REG(x,y) (*(wreg[x])) = (y) + +#define GET_L_REG(x) *(lreg[x]) +#define SET_L_REG(x,y) (*(lreg[x])) = (y) + +#define GET_MEMORY_L(x) \ + (x < memory_size \ + ? ((cpu.memory[x+0] << 24) | (cpu.memory[x+1] << 16) \ + | (cpu.memory[x+2] << 8) | cpu.memory[x+3]) \ + : ((cpu.eightbit[(x+0) & 0xff] << 24) | (cpu.eightbit[(x+1) & 0xff] << 16) \ + | (cpu.eightbit[(x+2) & 0xff] << 8) | cpu.eightbit[(x+3) & 0xff])) + +#define GET_MEMORY_W(x) \ + (x < memory_size \ + ? ((cpu.memory[x+0] << 8) | (cpu.memory[x+1] << 0)) \ + : ((cpu.eightbit[(x+0) & 0xff] << 8) | (cpu.eightbit[(x+1) & 0xff] << 0))) + + +#define GET_MEMORY_B(x) \ + (x < memory_size ? (cpu.memory[x]) : (cpu.eightbit[x & 0xff])) + +#define SET_MEMORY_L(x,y) \ +{ register unsigned char *_p; register int __y = y; \ + _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ + _p[0] = (__y)>>24; _p[1] = (__y)>>16; \ + _p[2] = (__y)>>8; _p[3] = (__y)>>0;} + +#define SET_MEMORY_W(x,y) \ +{ register unsigned char *_p; register int __y = y; \ + _p = (x < memory_size ? cpu.memory+x : cpu.eightbit + (x & 0xff)); \ + _p[0] = (__y)>>8; _p[1] =(__y);} + +#define SET_MEMORY_B(x,y) \ + (x < memory_size ? (cpu.memory[(x)] = y) : (cpu.eightbit[x & 0xff] = y)) + +int +fetch (arg, n) + ea_type *arg; +{ + int rn = arg->reg; + int abs = arg->literal; + int r; + int t; + + switch (arg->type) + { + case X (OP_REG, SB): + return GET_B_REG (rn); + case X (OP_REG, SW): + return GET_W_REG (rn); + case X (OP_REG, SL): + return GET_L_REG (rn); + case X (OP_IMM, SB): + case X (OP_IMM, SW): + case X (OP_IMM, SL): + return abs; + case X (OP_DEC, SB): + abort (); + + case X (OP_INC, SB): + t = GET_L_REG (rn); + t &= cpu.mask; + r = GET_MEMORY_B (t); + t++; + t = t & cpu.mask; + SET_L_REG (rn, t); + return r; + break; + case X (OP_INC, SW): + t = GET_L_REG (rn); + t &= cpu.mask; + r = GET_MEMORY_W (t); + t += 2; + t = t & cpu.mask; + SET_L_REG (rn, t); + return r; + case X (OP_INC, SL): + t = GET_L_REG (rn); + t &= cpu.mask; + r = GET_MEMORY_L (t); + + t += 4; + t = t & cpu.mask; + SET_L_REG (rn, t); + return r; + + case X (OP_DISP, SB): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + return GET_MEMORY_B (t); + + case X (OP_DISP, SW): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + return GET_MEMORY_W (t); + + case X (OP_DISP, SL): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + return GET_MEMORY_L (t); + + case X (OP_MEM, SL): + t = GET_MEMORY_L (abs); + t &= cpu.mask; + return t; + + case X (OP_MEM, SW): + t = GET_MEMORY_W (abs); + t &= cpu.mask; + return t; + + default: + abort (); + + } +} + + +static +void +store (arg, n) + ea_type *arg; + int n; +{ + int rn = arg->reg; + int abs = arg->literal; + int t; + + switch (arg->type) + { + case X (OP_REG, SB): + SET_B_REG (rn, n); + break; + case X (OP_REG, SW): + SET_W_REG (rn, n); + break; + case X (OP_REG, SL): + SET_L_REG (rn, n); + break; + + case X (OP_DEC, SB): + t = GET_L_REG (rn) - 1; + t &= cpu.mask; + SET_L_REG (rn, t); + SET_MEMORY_B (t, n); + + break; + case X (OP_DEC, SW): + t = (GET_L_REG (rn) - 2) & cpu.mask; + SET_L_REG (rn, t); + SET_MEMORY_W (t, n); + break; + + case X (OP_DEC, SL): + t = (GET_L_REG (rn) - 4) & cpu.mask; + SET_L_REG (rn, t); + SET_MEMORY_L (t, n); + break; + + case X (OP_DISP, SB): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + SET_MEMORY_B (t, n); + break; + + case X (OP_DISP, SW): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + SET_MEMORY_W (t, n); + break; + + case X (OP_DISP, SL): + t = GET_L_REG (rn) + abs; + t &= cpu.mask; + SET_MEMORY_L (t, n); + break; + default: + abort (); + } +} + + +static union +{ + short int i; + struct + { + char low; + char high; + } + u; +} + +littleendian; + +static +void +init_pointers () +{ + static int init; + + if (!init) + { + int i; + + init = 1; + littleendian.i = 1; + + if (h8300hmode) + memory_size = H8300H_MSIZE; + else + memory_size = H8300_MSIZE; + cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); + cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); + cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); + + /* `msize' must be a power of two */ + if ((memory_size & (memory_size - 1)) != 0) + abort (); + cpu.mask = memory_size - 1; + + for (i = 0; i < 9; i++) + { + cpu.regs[i] = 0; + } + + for (i = 0; i < 8; i++) + { + unsigned char *p = (unsigned char *) (cpu.regs + i); + unsigned char *e = (unsigned char *) (cpu.regs + i + 1); + unsigned short *q = (unsigned short *) (cpu.regs + i); + unsigned short *u = (unsigned short *) (cpu.regs + i + 1); + cpu.regs[i] = 0x00112233; + while (p < e) + { + if (*p == 0x22) + { + breg[i] = p; + } + if (*p == 0x33) + { + breg[i + 8] = p; + } + p++; + } + while (q < u) + { + if (*q == 0x2233) + { + wreg[i] = q; + } + if (*q == 0x0011) + { + wreg[i + 8] = q; + } + q++; + } + cpu.regs[i] = 0; + lreg[i] = &cpu.regs[i]; + } + + lreg[8] = &cpu.regs[8]; + + /* initialize the seg registers */ + if (!cpu.cache) + sim_set_simcache_size (CSIZE); + } +} + +static void +control_c (sig, code, scp, addr) + int sig; + int code; + char *scp; + char *addr; +{ + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGINT; +} + +#define C (c != 0) +#define Z (nz == 0) +#define V (v != 0) +#define N (n != 0) + +static int +mop (code, bsize, sign) + decoded_inst *code; + int bsize; + int sign; +{ + int multiplier; + int multiplicand; + int result; + int n, nz; + + if (sign) + { + multiplicand = + bsize ? SEXTCHAR (GET_W_REG (code->dst.reg)) : + SEXTSHORT (GET_W_REG (code->dst.reg)); + multiplier = + bsize ? SEXTCHAR (GET_B_REG (code->src.reg)) : + SEXTSHORT (GET_W_REG (code->src.reg)); + } + else + { + multiplicand = bsize ? UEXTCHAR (GET_W_REG (code->dst.reg)) : + UEXTSHORT (GET_W_REG (code->dst.reg)); + multiplier = + bsize ? UEXTCHAR (GET_B_REG (code->src.reg)) : + UEXTSHORT (GET_W_REG (code->src.reg)); + + } + result = multiplier * multiplicand; + + if (sign) + { + n = result & (bsize ? 0x8000 : 0x80000000); + nz = result & (bsize ? 0xffff : 0xffffffff); + } + if (bsize) + { + SET_W_REG (code->dst.reg, result); + } + else + { + SET_L_REG (code->dst.reg, result); + } +/* return ((n==1) << 1) | (nz==1); */ + +} + +#define ONOT(name, how) \ +case O(name, SB): \ +{ \ + int t; \ + int hm = 0x80; \ + rd = GET_B_REG (code->src.reg); \ + how; \ + goto shift8; \ +} \ +case O(name, SW): \ +{ \ + int t; \ + int hm = 0x8000; \ + rd = GET_W_REG (code->src.reg); \ + how; \ + goto shift16; \ +} \ +case O(name, SL): \ +{ \ + int t; \ + int hm = 0x80000000; \ + rd = GET_L_REG (code->src.reg); \ + how; \ + goto shift32; \ +} + +#define OSHIFTS(name, how1, how2) \ +case O(name, SB): \ +{ \ + int t; \ + int hm = 0x80; \ + rd = GET_B_REG (code->src.reg); \ + if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ + { \ + how1; \ + } \ + else \ + { \ + how2; \ + } \ + goto shift8; \ +} \ +case O(name, SW): \ +{ \ + int t; \ + int hm = 0x8000; \ + rd = GET_W_REG (code->src.reg); \ + if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ + { \ + how1; \ + } \ + else \ + { \ + how2; \ + } \ + goto shift16; \ +} \ +case O(name, SL): \ +{ \ + int t; \ + int hm = 0x80000000; \ + rd = GET_L_REG (code->src.reg); \ + if ((GET_MEMORY_B (pc + 1) & 0x40) == 0) \ + { \ + how1; \ + } \ + else \ + { \ + how2; \ + } \ + goto shift32; \ +} + +#define OBITOP(name,f, s, op) \ +case O(name, SB): \ +{ \ + int m; \ + int b; \ + if (f) ea = fetch (&code->dst); \ + m=1<< fetch(&code->src); \ + op; \ + if(s) store (&code->dst,ea); goto next; \ +} + +int +sim_stop (sd) + SIM_DESC sd; +{ + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGINT; + return 1; +} + +void +sim_resume (sd, step, siggnal) + SIM_DESC sd; +{ + static int init1; + int cycles = 0; + int insts = 0; + int tick_start = get_now (); + void (*prev) (); + int poll_count = 0; + int res; + int tmp; + int rd; + int ea; + int bit; + int pc; + int c, nz, v, n; + int oldmask; + init_pointers (); + + prev = signal (SIGINT, control_c); + + if (step) + { + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGTRAP; + } + else + { + cpu.state = SIM_STATE_RUNNING; + cpu.exception = 0; + } + + pc = cpu.pc; + + /* The PC should never be odd. */ + if (pc & 0x1) + abort (); + + GETSR (); + oldmask = cpu.mask; + if (!h8300hmode) + cpu.mask = 0xffff; + do + { + int cidx; + decoded_inst *code; + + top: + cidx = cpu.cache_idx[pc]; + code = cpu.cache + cidx; + + +#define ALUOP(STORE, NAME, HOW) \ + case O(NAME,SB): HOW; if(STORE)goto alu8;else goto just_flags_alu8; \ + case O(NAME, SW): HOW; if(STORE)goto alu16;else goto just_flags_alu16; \ + case O(NAME,SL): HOW; if(STORE)goto alu32;else goto just_flags_alu32; + + +#define LOGOP(NAME, HOW) \ + case O(NAME,SB): HOW; goto log8;\ + case O(NAME, SW): HOW; goto log16;\ + case O(NAME,SL): HOW; goto log32; + + + +#if ADEBUG + if (debug) + { + printf ("%x %d %s\n", pc, code->opcode, + code->op ? code->op->name : "**"); + } + cpu.stats[code->opcode]++; + +#endif + + cycles += code->cycles; + insts++; + switch (code->opcode) + { + case 0: + /* + * This opcode is a fake for when we get to an + * instruction which hasnt been compiled + */ + compile (pc); + goto top; + break; + + + case O (O_SUBX, SB): + rd = fetch (&code->dst); + ea = fetch (&code->src); + ea = -(ea + C); + res = rd + ea; + goto alu8; + + case O (O_ADDX, SB): + rd = fetch (&code->dst); + ea = fetch (&code->src); + ea = C + ea; + res = rd + ea; + goto alu8; + +#define EA ea = fetch(&code->src); +#define RD_EA ea = fetch(&code->src); rd = fetch(&code->dst); + + ALUOP (1, O_SUB, RD_EA; + ea = -ea; + res = rd + ea); + ALUOP (1, O_NEG, EA; + ea = -ea; + rd = 0; + res = rd + ea); + + case O (O_ADD, SB): + rd = GET_B_REG (code->dst.reg); + ea = fetch (&code->src); + res = rd + ea; + goto alu8; + case O (O_ADD, SW): + rd = GET_W_REG (code->dst.reg); + ea = fetch (&code->src); + res = rd + ea; + goto alu16; + case O (O_ADD, SL): + rd = GET_L_REG (code->dst.reg); + ea = fetch (&code->src); + res = rd + ea; + goto alu32; + + + LOGOP (O_AND, RD_EA; + res = rd & ea); + + LOGOP (O_OR, RD_EA; + res = rd | ea); + + LOGOP (O_XOR, RD_EA; + res = rd ^ ea); + + + case O (O_MOV_TO_MEM, SB): + res = GET_B_REG (code->src.reg); + goto log8; + case O (O_MOV_TO_MEM, SW): + res = GET_W_REG (code->src.reg); + goto log16; + case O (O_MOV_TO_MEM, SL): + res = GET_L_REG (code->src.reg); + goto log32; + + + case O (O_MOV_TO_REG, SB): + res = fetch (&code->src); + SET_B_REG (code->dst.reg, res); + goto just_flags_log8; + case O (O_MOV_TO_REG, SW): + res = fetch (&code->src); + SET_W_REG (code->dst.reg, res); + goto just_flags_log16; + case O (O_MOV_TO_REG, SL): + res = fetch (&code->src); + SET_L_REG (code->dst.reg, res); + goto just_flags_log32; + + + case O (O_ADDS, SL): + SET_L_REG (code->dst.reg, + GET_L_REG (code->dst.reg) + + code->src.literal); + + goto next; + + case O (O_SUBS, SL): + SET_L_REG (code->dst.reg, + GET_L_REG (code->dst.reg) + - code->src.literal); + goto next; + + case O (O_CMP, SB): + rd = fetch (&code->dst); + ea = fetch (&code->src); + ea = -ea; + res = rd + ea; + goto just_flags_alu8; + + case O (O_CMP, SW): + rd = fetch (&code->dst); + ea = fetch (&code->src); + ea = -ea; + res = rd + ea; + goto just_flags_alu16; + + case O (O_CMP, SL): + rd = fetch (&code->dst); + ea = fetch (&code->src); + ea = -ea; + res = rd + ea; + goto just_flags_alu32; + + + case O (O_DEC, SB): + rd = GET_B_REG (code->src.reg); + ea = -1; + res = rd + ea; + SET_B_REG (code->src.reg, res); + goto just_flags_inc8; + + case O (O_DEC, SW): + rd = GET_W_REG (code->dst.reg); + ea = -code->src.literal; + res = rd + ea; + SET_W_REG (code->dst.reg, res); + goto just_flags_inc16; + + case O (O_DEC, SL): + rd = GET_L_REG (code->dst.reg); + ea = -code->src.literal; + res = rd + ea; + SET_L_REG (code->dst.reg, res); + goto just_flags_inc32; + + + case O (O_INC, SB): + rd = GET_B_REG (code->src.reg); + ea = 1; + res = rd + ea; + SET_B_REG (code->src.reg, res); + goto just_flags_inc8; + + case O (O_INC, SW): + rd = GET_W_REG (code->dst.reg); + ea = code->src.literal; + res = rd + ea; + SET_W_REG (code->dst.reg, res); + goto just_flags_inc16; + + case O (O_INC, SL): + rd = GET_L_REG (code->dst.reg); + ea = code->src.literal; + res = rd + ea; + SET_L_REG (code->dst.reg, res); + goto just_flags_inc32; + + +#define GET_CCR(x) BUILDSR();x = cpu.ccr + + case O (O_ANDC, SB): + GET_CCR (rd); + ea = code->src.literal; + res = rd & ea; + goto setc; + + case O (O_ORC, SB): + GET_CCR (rd); + ea = code->src.literal; + res = rd | ea; + goto setc; + + case O (O_XORC, SB): + GET_CCR (rd); + ea = code->src.literal; + res = rd ^ ea; + goto setc; + + + case O (O_BRA, SB): + if (1) + goto condtrue; + goto next; + + case O (O_BRN, SB): + if (0) + goto condtrue; + goto next; + + case O (O_BHI, SB): + if ((C || Z) == 0) + goto condtrue; + goto next; + + + case O (O_BLS, SB): + if ((C || Z)) + goto condtrue; + goto next; + + case O (O_BCS, SB): + if ((C == 1)) + goto condtrue; + goto next; + + case O (O_BCC, SB): + if ((C == 0)) + goto condtrue; + goto next; + + case O (O_BEQ, SB): + if (Z) + goto condtrue; + goto next; + case O (O_BGT, SB): + if (((Z || (N ^ V)) == 0)) + goto condtrue; + goto next; + + + case O (O_BLE, SB): + if (((Z || (N ^ V)) == 1)) + goto condtrue; + goto next; + + case O (O_BGE, SB): + if ((N ^ V) == 0) + goto condtrue; + goto next; + case O (O_BLT, SB): + if ((N ^ V)) + goto condtrue; + goto next; + case O (O_BMI, SB): + if ((N)) + goto condtrue; + goto next; + case O (O_BNE, SB): + if ((Z == 0)) + goto condtrue; + goto next; + + case O (O_BPL, SB): + if (N == 0) + goto condtrue; + goto next; + case O (O_BVC, SB): + if ((V == 0)) + goto condtrue; + goto next; + case O (O_BVS, SB): + if ((V == 1)) + goto condtrue; + goto next; + + case O (O_SYSCALL, SB): + { + char c = cpu.regs[2]; + sim_callback->write_stdout (sim_callback, &c, 1); + } + goto next; + + ONOT (O_NOT, rd = ~rd; v = 0;); + OSHIFTS (O_SHLL, + c = rd & hm; v = 0; rd <<= 1, + c = rd & (hm >> 1); v = 0; rd <<= 2); + OSHIFTS (O_SHLR, + c = rd & 1; v = 0; rd = (unsigned int) rd >> 1, + c = rd & 2; v = 0; rd = (unsigned int) rd >> 2); + OSHIFTS (O_SHAL, + c = rd & hm; v = (rd & hm) != ((rd & (hm >> 1)) << 1); rd <<= 1, + c = rd & (hm >> 1); v = (rd & (hm >> 1)) != ((rd & (hm >> 2)) << 2); rd <<= 2); + OSHIFTS (O_SHAR, + t = rd & hm; c = rd & 1; v = 0; rd >>= 1; rd |= t, + t = rd & hm; c = rd & 2; v = 0; rd >>= 2; rd |= t | t >> 1 ); + OSHIFTS (O_ROTL, + c = rd & hm; v = 0; rd <<= 1; rd |= C, + c = rd & hm; v = 0; rd <<= 1; rd |= C; c = rd & hm; rd <<= 1; rd |= C); + OSHIFTS (O_ROTR, + c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm, + c = rd & 1; v = 0; rd = (unsigned int) rd >> 1; if (c) rd |= hm; c = rd & 1; rd = (unsigned int) rd >> 1; if (c) rd |= hm); + OSHIFTS (O_ROTXL, + t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0, + t = rd & hm; rd <<= 1; rd |= C; c = t; v = 0; t = rd & hm; rd <<= 1; rd |= C; c = t); + OSHIFTS (O_ROTXR, + t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0, + t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t; v = 0; t = rd & 1; rd = (unsigned int) rd >> 1; if (C) rd |= hm; c = t); + + case O (O_JMP, SB): + { + pc = fetch (&code->src); + goto end; + + } + + case O (O_JSR, SB): + { + int tmp; + pc = fetch (&code->src); + call: + tmp = cpu.regs[7]; + + if (h8300hmode) + { + tmp -= 4; + SET_MEMORY_L (tmp, code->next_pc); + } + else + { + tmp -= 2; + SET_MEMORY_W (tmp, code->next_pc); + } + cpu.regs[7] = tmp; + + goto end; + } + case O (O_BSR, SB): + pc = code->src.literal; + goto call; + + case O (O_RTS, SN): + { + int tmp; + + tmp = cpu.regs[7]; + + if (h8300hmode) + { + pc = GET_MEMORY_L (tmp); + tmp += 4; + } + else + { + pc = GET_MEMORY_W (tmp); + tmp += 2; + } + + cpu.regs[7] = tmp; + goto end; + } + + case O (O_ILL, SB): + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGILL; + goto end; + case O (O_SLEEP, SN): + /* The format of r0 is defined by devo/include/wait.h. */ +#if 0 /* FIXME: Ugh. A breakpoint is the sleep insn. */ + if (WIFEXITED (cpu.regs[0])) + { + cpu.state = SIM_STATE_EXITED; + cpu.exception = WEXITSTATUS (cpu.regs[0]); + } + else if (WIFSTOPPED (cpu.regs[0])) + { + cpu.state = SIM_STATE_STOPPED; + cpu.exception = WSTOPSIG (cpu.regs[0]); + } + else + { + cpu.state = SIM_STATE_SIGNALLED; + cpu.exception = WTERMSIG (cpu.regs[0]); + } +#else + /* FIXME: Doesn't this break for breakpoints when r0 + contains just the right (er, wrong) value? */ + cpu.state = SIM_STATE_STOPPED; + if (! WIFEXITED (cpu.regs[0]) && WIFSIGNALED (cpu.regs[0])) + cpu.exception = SIGILL; + else + cpu.exception = SIGTRAP; +#endif + goto end; + case O (O_BPT, SN): + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGTRAP; + goto end; + + OBITOP (O_BNOT, 1, 1, ea ^= m); + OBITOP (O_BTST, 1, 0, nz = ea & m); + OBITOP (O_BCLR, 1, 1, ea &= ~m); + OBITOP (O_BSET, 1, 1, ea |= m); + OBITOP (O_BLD, 1, 0, c = ea & m); + OBITOP (O_BILD, 1, 0, c = !(ea & m)); + OBITOP (O_BST, 1, 1, ea &= ~m; + if (C) ea |= m); + OBITOP (O_BIST, 1, 1, ea &= ~m; + if (!C) ea |= m); + OBITOP (O_BAND, 1, 0, c = (ea & m) && C); + OBITOP (O_BIAND, 1, 0, c = !(ea & m) && C); + OBITOP (O_BOR, 1, 0, c = (ea & m) || C); + OBITOP (O_BIOR, 1, 0, c = !(ea & m) || C); + OBITOP (O_BXOR, 1, 0, c = (ea & m) != C); + OBITOP (O_BIXOR, 1, 0, c = !(ea & m) != C); + + +#define MOP(bsize, signed) mop(code, bsize,signed); goto next; + + case O (O_MULS, SB): + MOP (1, 1); + break; + case O (O_MULS, SW): + MOP (0, 1); + break; + case O (O_MULU, SB): + MOP (1, 0); + break; + case O (O_MULU, SW): + MOP (0, 0); + break; + + + case O (O_DIVU, SB): + { + rd = GET_W_REG (code->dst.reg); + ea = GET_B_REG (code->src.reg); + if (ea) + { + tmp = (unsigned)rd % ea; + rd = (unsigned)rd / ea; + } + SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); + n = ea & 0x80; + nz = ea & 0xff; + + goto next; + } + case O (O_DIVU, SW): + { + rd = GET_L_REG (code->dst.reg); + ea = GET_W_REG (code->src.reg); + n = ea & 0x8000; + nz = ea & 0xffff; + if (ea) + { + tmp = (unsigned)rd % ea; + rd = (unsigned)rd / ea; + } + SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); + goto next; + } + + case O (O_DIVS, SB): + { + + rd = SEXTSHORT (GET_W_REG (code->dst.reg)); + ea = SEXTCHAR (GET_B_REG (code->src.reg)); + if (ea) + { + tmp = (int) rd % (int) ea; + rd = (int) rd / (int) ea; + n = rd & 0x8000; + nz = 1; + } + else + nz = 0; + SET_W_REG (code->dst.reg, (rd & 0xff) | (tmp << 8)); + goto next; + } + case O (O_DIVS, SW): + { + rd = GET_L_REG (code->dst.reg); + ea = SEXTSHORT (GET_W_REG (code->src.reg)); + if (ea) + { + tmp = (int) rd % (int) ea; + rd = (int) rd / (int) ea; + n = rd & 0x80000000; + nz = 1; + } + else + nz = 0; + SET_L_REG (code->dst.reg, (rd & 0xffff) | (tmp << 16)); + goto next; + } + case O (O_EXTS, SW): + rd = GET_B_REG (code->src.reg + 8) & 0xff; /* Yes, src, not dst. */ + ea = rd & 0x80 ? -256 : 0; + res = rd + ea; + goto log16; + case O (O_EXTS, SL): + rd = GET_W_REG (code->src.reg) & 0xffff; + ea = rd & 0x8000 ? -65536 : 0; + res = rd + ea; + goto log32; + case O (O_EXTU, SW): + rd = GET_B_REG (code->src.reg + 8) & 0xff; + ea = 0; + res = rd + ea; + goto log16; + case O (O_EXTU, SL): + rd = GET_W_REG (code->src.reg) & 0xffff; + ea = 0; + res = rd + ea; + goto log32; + + case O (O_NOP, SN): + goto next; + + case O (O_STM, SL): + { + int nregs, firstreg, i; + + nregs = GET_MEMORY_B (pc + 1); + nregs >>= 4; + nregs &= 0xf; + firstreg = GET_MEMORY_B (pc + 3); + firstreg &= 0xf; + for (i = firstreg; i <= firstreg + nregs; i++) + { + cpu.regs[7] -= 4; + SET_MEMORY_L (cpu.regs[7], cpu.regs[i]); + } + } + goto next; + + case O (O_LDM, SL): + { + int nregs, firstreg, i; + + nregs = GET_MEMORY_B (pc + 1); + nregs >>= 4; + nregs &= 0xf; + firstreg = GET_MEMORY_B (pc + 3); + firstreg &= 0xf; + for (i = firstreg; i >= firstreg - nregs; i--) + { + cpu.regs[i] = GET_MEMORY_L (cpu.regs[7]); + cpu.regs[7] += 4; + } + } + goto next; + + default: + cpu.state = SIM_STATE_STOPPED; + cpu.exception = SIGILL; + goto end; + + } + abort (); + + setc: + cpu.ccr = res; + GETSR (); + goto next; + + condtrue: + /* When a branch works */ + pc = code->src.literal; + goto end; + + /* Set the cond codes from res */ + bitop: + + /* Set the flags after an 8 bit inc/dec operation */ + just_flags_inc8: + n = res & 0x80; + nz = res & 0xff; + v = (rd & 0x7f) == 0x7f; + goto next; + + + /* Set the flags after an 16 bit inc/dec operation */ + just_flags_inc16: + n = res & 0x8000; + nz = res & 0xffff; + v = (rd & 0x7fff) == 0x7fff; + goto next; + + + /* Set the flags after an 32 bit inc/dec operation */ + just_flags_inc32: + n = res & 0x80000000; + nz = res & 0xffffffff; + v = (rd & 0x7fffffff) == 0x7fffffff; + goto next; + + + shift8: + /* Set flags after an 8 bit shift op, carry,overflow set in insn */ + n = (rd & 0x80); + nz = rd & 0xff; + SET_B_REG (code->src.reg, rd); + goto next; + + shift16: + /* Set flags after an 16 bit shift op, carry,overflow set in insn */ + n = (rd & 0x8000); + nz = rd & 0xffff; + SET_W_REG (code->src.reg, rd); + goto next; + + shift32: + /* Set flags after an 32 bit shift op, carry,overflow set in insn */ + n = (rd & 0x80000000); + nz = rd & 0xffffffff; + SET_L_REG (code->src.reg, rd); + goto next; + + log32: + store (&code->dst, res); + just_flags_log32: + /* flags after a 32bit logical operation */ + n = res & 0x80000000; + nz = res & 0xffffffff; + v = 0; + goto next; + + log16: + store (&code->dst, res); + just_flags_log16: + /* flags after a 16bit logical operation */ + n = res & 0x8000; + nz = res & 0xffff; + v = 0; + goto next; + + + log8: + store (&code->dst, res); + just_flags_log8: + n = res & 0x80; + nz = res & 0xff; + v = 0; + goto next; + + alu8: + SET_B_REG (code->dst.reg, res); + just_flags_alu8: + n = res & 0x80; + nz = res & 0xff; + c = (res & 0x100); + switch (code->opcode / 4) + { + case O_ADD: + v = ((rd & 0x80) == (ea & 0x80) + && (rd & 0x80) != (res & 0x80)); + break; + case O_SUB: + case O_CMP: + v = ((rd & 0x80) != (-ea & 0x80) + && (rd & 0x80) != (res & 0x80)); + break; + case O_NEG: + v = (rd == 0x80); + break; + } + goto next; + + alu16: + SET_W_REG (code->dst.reg, res); + just_flags_alu16: + n = res & 0x8000; + nz = res & 0xffff; + c = (res & 0x10000); + switch (code->opcode / 4) + { + case O_ADD: + v = ((rd & 0x8000) == (ea & 0x8000) + && (rd & 0x8000) != (res & 0x8000)); + break; + case O_SUB: + case O_CMP: + v = ((rd & 0x8000) != (-ea & 0x8000) + && (rd & 0x8000) != (res & 0x8000)); + break; + case O_NEG: + v = (rd == 0x8000); + break; + } + goto next; + + alu32: + SET_L_REG (code->dst.reg, res); + just_flags_alu32: + n = res & 0x80000000; + nz = res & 0xffffffff; + switch (code->opcode / 4) + { + case O_ADD: + v = ((rd & 0x80000000) == (ea & 0x80000000) + && (rd & 0x80000000) != (res & 0x80000000)); + c = ((unsigned) res < (unsigned) rd) || ((unsigned) res < (unsigned) ea); + break; + case O_SUB: + case O_CMP: + v = ((rd & 0x80000000) != (-ea & 0x80000000) + && (rd & 0x80000000) != (res & 0x80000000)); + c = (unsigned) rd < (unsigned) -ea; + break; + case O_NEG: + v = (rd == 0x80000000); + c = res != 0; + break; + } + goto next; + + next:; + pc = code->next_pc; + + end: + ; + /* if (cpu.regs[8] ) abort(); */ + + if (--poll_count < 0) + { + poll_count = POLL_QUIT_INTERVAL; + if ((*sim_callback->poll_quit) != NULL + && (*sim_callback->poll_quit) (sim_callback)) + sim_stop (sd); + } + + } + while (cpu.state == SIM_STATE_RUNNING); + cpu.ticks += get_now () - tick_start; + cpu.cycles += cycles; + cpu.insts += insts; + + cpu.pc = pc; + BUILDSR (); + cpu.mask = oldmask; + signal (SIGINT, prev); +} + +int +sim_trace (sd) + SIM_DESC sd; +{ + /* FIXME: unfinished */ + abort (); +} + +int +sim_write (sd, addr, buffer, size) + SIM_DESC sd; + SIM_ADDR addr; + unsigned char *buffer; + int size; +{ + int i; + + init_pointers (); + if (addr < 0) + return 0; + for (i = 0; i < size; i++) + { + if (addr < memory_size) + { + cpu.memory[addr + i] = buffer[i]; + cpu.cache_idx[addr + i] = 0; + } + else + cpu.eightbit[(addr + i) & 0xff] = buffer[i]; + } + return size; +} + +int +sim_read (sd, addr, buffer, size) + SIM_DESC sd; + SIM_ADDR addr; + unsigned char *buffer; + int size; +{ + init_pointers (); + if (addr < 0) + return 0; + if (addr < memory_size) + memcpy (buffer, cpu.memory + addr, size); + else + memcpy (buffer, cpu.eightbit + (addr & 0xff), size); + return size; +} + + +#define R0_REGNUM 0 +#define R1_REGNUM 1 +#define R2_REGNUM 2 +#define R3_REGNUM 3 +#define R4_REGNUM 4 +#define R5_REGNUM 5 +#define R6_REGNUM 6 +#define R7_REGNUM 7 + +#define SP_REGNUM R7_REGNUM /* Contains address of top of stack */ +#define FP_REGNUM R6_REGNUM /* Contains address of executing + * stack frame */ + +#define CCR_REGNUM 8 /* Contains processor status */ +#define PC_REGNUM 9 /* Contains program counter */ + +#define CYCLE_REGNUM 10 +#define INST_REGNUM 11 +#define TICK_REGNUM 12 + + +int +sim_store_register (sd, rn, value, length) + SIM_DESC sd; + int rn; + unsigned char *value; + int length; +{ + int longval; + int shortval; + int intval; + longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; + shortval = (value[0] << 8) | (value[1]); + intval = h8300hmode ? longval : shortval; + + init_pointers (); + switch (rn) + { + case PC_REGNUM: + cpu.pc = intval; + break; + default: + abort (); + case R0_REGNUM: + case R1_REGNUM: + case R2_REGNUM: + case R3_REGNUM: + case R4_REGNUM: + case R5_REGNUM: + case R6_REGNUM: + case R7_REGNUM: + cpu.regs[rn] = intval; + break; + case CCR_REGNUM: + cpu.ccr = intval; + break; + case CYCLE_REGNUM: + cpu.cycles = longval; + break; + + case INST_REGNUM: + cpu.insts = longval; + break; + + case TICK_REGNUM: + cpu.ticks = longval; + break; + } + return -1; +} + +int +sim_fetch_register (sd, rn, buf, length) + SIM_DESC sd; + int rn; + unsigned char *buf; + int length; +{ + int v; + int longreg = 0; + + init_pointers (); + + switch (rn) + { + default: + abort (); + case 8: + v = cpu.ccr; + break; + case 9: + v = cpu.pc; + break; + case R0_REGNUM: + case R1_REGNUM: + case R2_REGNUM: + case R3_REGNUM: + case R4_REGNUM: + case R5_REGNUM: + case R6_REGNUM: + case R7_REGNUM: + v = cpu.regs[rn]; + break; + case 10: + v = cpu.cycles; + longreg = 1; + break; + case 11: + v = cpu.ticks; + longreg = 1; + break; + case 12: + v = cpu.insts; + longreg = 1; + break; + } + if (h8300hmode || longreg) + { + buf[0] = v >> 24; + buf[1] = v >> 16; + buf[2] = v >> 8; + buf[3] = v >> 0; + } + else + { + buf[0] = v >> 8; + buf[1] = v; + } + return -1; +} + +void +sim_stop_reason (sd, reason, sigrc) + SIM_DESC sd; + enum sim_stop *reason; + int *sigrc; +{ +#if 0 /* FIXME: This should work but we can't use it. + grep for SLEEP above. */ + switch (cpu.state) + { + case SIM_STATE_EXITED : *reason = sim_exited; break; + case SIM_STATE_SIGNALLED : *reason = sim_signalled; break; + case SIM_STATE_STOPPED : *reason = sim_stopped; break; + default : abort (); + } +#else + *reason = sim_stopped; +#endif + *sigrc = cpu.exception; +} + +/* FIXME: Rename to sim_set_mem_size. */ + +void +sim_size (n) + int n; +{ + /* Memory size is fixed. */ +} + +void +sim_set_simcache_size (n) +{ + if (cpu.cache) + free (cpu.cache); + if (n < 2) + n = 2; + cpu.cache = (decoded_inst *) malloc (sizeof (decoded_inst) * n); + memset (cpu.cache, 0, sizeof (decoded_inst) * n); + cpu.csize = n; +} + + +void +sim_info (sd, verbose) + SIM_DESC sd; + int verbose; +{ + double timetaken = (double) cpu.ticks / (double) now_persec (); + double virttime = cpu.cycles / 10.0e6; + + (*sim_callback->printf_filtered) (sim_callback, + "\n\n#instructions executed %10d\n", + cpu.insts); + (*sim_callback->printf_filtered) (sim_callback, + "#cycles (v approximate) %10d\n", + cpu.cycles); + (*sim_callback->printf_filtered) (sim_callback, + "#real time taken %10.4f\n", + timetaken); + (*sim_callback->printf_filtered) (sim_callback, + "#virtual time taked %10.4f\n", + virttime); + if (timetaken != 0.0) + (*sim_callback->printf_filtered) (sim_callback, + "#simulation ratio %10.4f\n", + virttime / timetaken); + (*sim_callback->printf_filtered) (sim_callback, + "#compiles %10d\n", + cpu.compiles); + (*sim_callback->printf_filtered) (sim_callback, + "#cache size %10d\n", + cpu.csize); + +#ifdef ADEBUG + /* This to be conditional on `what' (aka `verbose'), + however it was never passed as non-zero. */ + if (1) + { + int i; + for (i = 0; i < O_LAST; i++) + { + if (cpu.stats[i]) + (*sim_callback->printf_filtered) (sim_callback, + "%d: %d\n", i, cpu.stats[i]); + } + } +#endif +} + +/* Indicate whether the cpu is an h8/300 or h8/300h. + FLAG is non-zero for the h8/300h. */ + +void +set_h8300h (flag) + int flag; +{ + /* FIXME: Much of the code in sim_load can be moved to sim_open. + This function being replaced by a sim_open:ARGV configuration + option */ + h8300hmode = flag; +} + +SIM_DESC +sim_open (kind, ptr, abfd, argv) + SIM_OPEN_KIND kind; + struct host_callback_struct *ptr; + struct _bfd *abfd; + char **argv; +{ + /* FIXME: Much of the code in sim_load can be moved here */ + + sim_kind = kind; + myname = argv[0]; + sim_callback = ptr; + /* fudge our descriptor */ + return (SIM_DESC) 1; +} + +void +sim_close (sd, quitting) + SIM_DESC sd; + int quitting; +{ + /* nothing to do */ +} + +/* Called by gdb to load a program into memory. */ + +SIM_RC +sim_load (sd, prog, abfd, from_tty) + SIM_DESC sd; + char *prog; + bfd *abfd; + int from_tty; +{ + bfd *prog_bfd; + + /* FIXME: The code below that sets a specific variant of the h8/300 + being simulated should be moved to sim_open(). */ + + /* See if the file is for the h8/300 or h8/300h. */ + /* ??? This may not be the most efficient way. The z8k simulator + does this via a different mechanism (INIT_EXTRA_SYMTAB_INFO). */ + if (abfd != NULL) + prog_bfd = abfd; + else + prog_bfd = bfd_openr (prog, "coff-h8300"); + if (prog_bfd != NULL) + { + /* Set the cpu type. We ignore failure from bfd_check_format + and bfd_openr as sim_load_file checks too. */ + if (bfd_check_format (prog_bfd, bfd_object)) + { + unsigned long mach = bfd_get_mach (prog_bfd); + set_h8300h (mach == bfd_mach_h8300h + || mach == bfd_mach_h8300s); + } + } + + /* If we're using gdb attached to the simulator, then we have to + reallocate memory for the simulator. + + When gdb first starts, it calls fetch_registers (among other + functions), which in turn calls init_pointers, which allocates + simulator memory. + + The problem is when we do that, we don't know whether we're + debugging an h8/300 or h8/300h program. + + This is the first point at which we can make that determination, + so we just reallocate memory now; this will also allow us to handle + switching between h8/300 and h8/300h programs without exiting + gdb. */ + if (h8300hmode) + memory_size = H8300H_MSIZE; + else + memory_size = H8300_MSIZE; + + if (cpu.memory) + free (cpu.memory); + if (cpu.cache_idx) + free (cpu.cache_idx); + if (cpu.eightbit) + free (cpu.eightbit); + + cpu.memory = (unsigned char *) calloc (sizeof (char), memory_size); + cpu.cache_idx = (unsigned short *) calloc (sizeof (short), memory_size); + cpu.eightbit = (unsigned char *) calloc (sizeof (char), 256); + + /* `msize' must be a power of two */ + if ((memory_size & (memory_size - 1)) != 0) + abort (); + cpu.mask = memory_size - 1; + + if (sim_load_file (sd, myname, sim_callback, prog, prog_bfd, + sim_kind == SIM_OPEN_DEBUG, + 0, sim_write) + == NULL) + { + /* Close the bfd if we opened it. */ + if (abfd == NULL && prog_bfd != NULL) + bfd_close (prog_bfd); + return SIM_RC_FAIL; + } + + /* Close the bfd if we opened it. */ + if (abfd == NULL && prog_bfd != NULL) + bfd_close (prog_bfd); + return SIM_RC_OK; +} + +SIM_RC +sim_create_inferior (sd, abfd, argv, env) + SIM_DESC sd; + struct _bfd *abfd; + char **argv; + char **env; +{ + if (abfd != NULL) + cpu.pc = bfd_get_start_address (abfd); + else + cpu.pc = 0; + return SIM_RC_OK; +} + +void +sim_do_command (sd, cmd) + SIM_DESC sd; + char *cmd; +{ + (*sim_callback->printf_filtered) (sim_callback, + "This simulator does not accept any commands.\n"); +} + +void +sim_set_callbacks (ptr) + struct host_callback_struct *ptr; +{ + sim_callback = ptr; +} Index: config.in =================================================================== --- config.in (nonexistent) +++ config.in (revision 1765) @@ -0,0 +1,158 @@ +/* config.in. Generated automatically from configure.in by autoheader. */ + +/* Define if using alloca.c. */ +#undef C_ALLOCA + +/* Define to empty if the keyword does not work. */ +#undef const + +/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems. + This function is required for alloca.c support on those systems. */ +#undef CRAY_STACKSEG_END + +/* Define if you have alloca, as a function or macro. */ +#undef HAVE_ALLOCA + +/* Define if you have and it should be used (not on Ultrix). */ +#undef HAVE_ALLOCA_H + +/* Define if you have a working `mmap' system call. */ +#undef HAVE_MMAP + +/* Define as __inline if that's what the C compiler calls it. */ +#undef inline + +/* Define to `long' if doesn't define. */ +#undef off_t + +/* Define if you need to in order for stat and other things to work. */ +#undef _POSIX_SOURCE + +/* Define as the return type of signal handlers (int or void). */ +#undef RETSIGTYPE + +/* Define to `unsigned' if doesn't define. */ +#undef size_t + +/* If using the C implementation of alloca, define if you know the + direction of stack growth for your system; otherwise it will be + automatically deduced at run-time. + STACK_DIRECTION > 0 => grows toward higher addresses + STACK_DIRECTION < 0 => grows toward lower addresses + STACK_DIRECTION = 0 => direction of growth unknown + */ +#undef STACK_DIRECTION + +/* Define if you have the ANSI C header files. */ +#undef STDC_HEADERS + +/* Define to 1 if NLS is requested. */ +#undef ENABLE_NLS + +/* Define as 1 if you have gettext and don't want to use GNU gettext. */ +#undef HAVE_GETTEXT + +/* Define as 1 if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if your locale.h file contains LC_MESSAGES. */ +#undef HAVE_LC_MESSAGES + +/* Define if you have the __argz_count function. */ +#undef HAVE___ARGZ_COUNT + +/* Define if you have the __argz_next function. */ +#undef HAVE___ARGZ_NEXT + +/* Define if you have the __argz_stringify function. */ +#undef HAVE___ARGZ_STRINGIFY + +/* Define if you have the __setfpucw function. */ +#undef HAVE___SETFPUCW + +/* Define if you have the dcgettext function. */ +#undef HAVE_DCGETTEXT + +/* Define if you have the getcwd function. */ +#undef HAVE_GETCWD + +/* Define if you have the getpagesize function. */ +#undef HAVE_GETPAGESIZE + +/* Define if you have the getrusage function. */ +#undef HAVE_GETRUSAGE + +/* Define if you have the munmap function. */ +#undef HAVE_MUNMAP + +/* Define if you have the putenv function. */ +#undef HAVE_PUTENV + +/* Define if you have the setenv function. */ +#undef HAVE_SETENV + +/* Define if you have the setlocale function. */ +#undef HAVE_SETLOCALE + +/* Define if you have the sigaction function. */ +#undef HAVE_SIGACTION + +/* Define if you have the stpcpy function. */ +#undef HAVE_STPCPY + +/* Define if you have the strcasecmp function. */ +#undef HAVE_STRCASECMP + +/* Define if you have the strchr function. */ +#undef HAVE_STRCHR + +/* Define if you have the time function. */ +#undef HAVE_TIME + +/* Define if you have the header file. */ +#undef HAVE_ARGZ_H + +/* Define if you have the header file. */ +#undef HAVE_FCNTL_H + +/* Define if you have the header file. */ +#undef HAVE_FPU_CONTROL_H + +/* Define if you have the header file. */ +#undef HAVE_LIMITS_H + +/* Define if you have the header file. */ +#undef HAVE_LOCALE_H + +/* Define if you have the header file. */ +#undef HAVE_MALLOC_H + +/* Define if you have the header file. */ +#undef HAVE_NL_TYPES_H + +/* Define if you have the header file. */ +#undef HAVE_STDLIB_H + +/* Define if you have the header file. */ +#undef HAVE_STRING_H + +/* Define if you have the header file. */ +#undef HAVE_STRINGS_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_PARAM_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_RESOURCE_H + +/* Define if you have the header file. */ +#undef HAVE_SYS_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_TIME_H + +/* Define if you have the header file. */ +#undef HAVE_UNISTD_H + +/* Define if you have the header file. */ +#undef HAVE_VALUES_H Index: tconfig.in =================================================================== --- tconfig.in (nonexistent) +++ tconfig.in (revision 1765) @@ -0,0 +1,17 @@ +/* h8300 target configuration file. */ + +/* Define this if the simulator supports profiling. + See the mips simulator for an example. + This enables the `-p foo' and `-s bar' options. + The target is required to provide sim_set_profile{,_size}. */ +/* #define SIM_HAVE_PROFILE */ + +/* Define this if the simulator uses an instruction cache. + See the h8/300 simulator for an example. + This enables the `-c size' option to set the size of the cache. + The target is required to provide sim_set_simcache_size. */ +#define SIM_HAVE_SIMCACHE + +/* FIXME: This is a quick hack for run.c so it can support the `-h' option. + It will eventually be replaced by a more general facility. */ +#define SIM_H8300

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