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Index: models/codec_model.v
===================================================================
--- models/codec_model.v (nonexistent)
+++ models/codec_model.v (revision 1765)
@@ -0,0 +1,66 @@
+///////////////////////////////////////////////////////////////////
+// Codec model for EK4520
+//
+// The model simulated only mode that is found in Xess board which
+// is defined by:
+// CMODE = 0
+// DIF0 = 0
+// DIF1 = 1
+// This mode represent MCLK = 256fs
+// 20 bit in/out MSB justified, SCLK = 64fs
+//
+// Functionality:
+// - The model takes the input channel and dumps the samples to
+// an output file.
+// - The model creates activity on the input channel according to
+// an input file. (not yet implemented)
+
+`include "timescale.v"
+
+module codec_model (
+ mclk, lrclk, sclk, sdin, sdout
+ );
+
+input mclk;
+input lrclk;
+input sclk;
+input sdin;
+output sdout;
+
+reg [19:0] left_data;
+reg [19:0] right_data;
+integer left_count, right_count;
+
+// The file descriptors
+integer left_file, right_file;
+
+ assign sdout = 1'b0;
+
+// Opening the files for output data
+initial
+ begin
+ left_file = $fopen("../out/left.dat");
+ right_file = $fopen("../out/right.dat");
+ end // of opening files
+
+always @(negedge lrclk)
+ begin
+ left_count = 19;
+ right_count = 19;
+ $fdisplay(left_file, left_data);
+ $fdisplay(right_file, right_data);
+ end
+
+always @(negedge sclk)
+ begin
+ if ((left_count > 0) & (lrclk == 1'b0)) begin
+ left_data[left_count] <= sdin;
+ left_count <= left_count - 1;
+ end
+ if ((right_count > 0) & (lrclk == 1'b1)) begin
+ right_data[right_count] <= sdin;
+ right_count <= right_count - 1;
+ end
+ end
+
+endmodule
Index: models/vga_model.v
===================================================================
--- models/vga_model.v (nonexistent)
+++ models/vga_model.v (revision 1765)
@@ -0,0 +1,18 @@
+`include "timescale.v"
+
+module vga_model (
+ pclk,
+ hsyncn,
+ vsyncn,
+ r,g,b
+ );
+
+input pclk;
+input hsyncn;
+input vsyncn;
+input [1:0] r;
+input [1:0] g;
+input [1:0] b;
+
+
+endmodule
Index: models/idt71256sa15.v
===================================================================
--- models/idt71256sa15.v (nonexistent)
+++ models/idt71256sa15.v (revision 1765)
@@ -0,0 +1,295 @@
+
+/*******************************************************************************
+ * Copyright 1991, 1992, 1993 Integrated Device Technology Corp.
+ * All right reserved.
+ *
+ * This program is proprietary and confidential information of
+ * IDT Corp. and may be used and disclosed only as authorized
+ * in a license agreement controlling such use and disclosure.
+ *
+ * IDT reserves the right to make any changes to
+ * the product herein to improve function or design.
+ * IDT does not assume any liability arising out of
+ * the application or use of the product herein.
+ *
+ * WARNING: The unlicensed shipping, mailing, or carring of this
+ * technical data outside the United States, or the unlicensed
+ * disclosure, by whatever means, through visits abroad, or the
+ * unlicensed disclosure to foreign national in the United States,
+ * may violate the United States criminal law.
+ *
+ * File Name : idt71256sa15.v
+ * Function : 32Kx8-bit Asynchronous Static RAM
+ * Simulation Tool/Version : Verilog 2.0
+ *
+ ******************************************************************************/
+
+/*+ **************************** Internal Use Only *****************************
+ *+ Revision History
+ *+ Name Version dd-mmm-yy Notes
+ *+ William Lam 0.1 Mar-94 Based on IDT71B256SA part
+ *+ Martin Mueller 0.2 2-Sep-94 Updated to reflect IDT71256SA15 timing
+ *+ Martin Mueller 0.3 6-Sep-94 Changed to 0.1nS time scale
+ *+ ***************************************************************************/
+
+/*******************************************************************************
+ * Module Name: idt71256sa15
+ * Description: 32Kx8 15nS Asynchronous Static RAM
+ *
+ *******************************************************************************/
+`timescale 1ns/100ps
+//`timescale 10ps/10ps
+
+module idt71256sa15(data, addr, we_, oe_, cs_);
+inout [7:0] data;
+input [14:0] addr;
+input we_, oe_, cs_;
+
+//Read Cycle Parameters
+parameter Taa = 15; // address access time
+parameter Tacs = 15; // cs_ access time
+parameter Tclz = 4; // cs_ to output low Z time
+parameter Tchz = 7; // cs_ to output high Z time
+parameter Toe = 7; // oe_ to output time
+parameter Tohz = 6; // oe_ to output Z time
+parameter Toh = 4; // data hold from adr change time
+
+//Write Cycle Parameters
+parameter Taw = 10; // adr valid to end of write time
+parameter Tcw = 10; // cs_ to end of write time
+parameter Tas = 0; // address set up time
+parameter Twp = 10; // write pulse width min
+parameter Tdw = 7; // data valid to end of writ time
+parameter Tow = 4; // data act from end of writ time
+parameter Twhz = 6; // we_ to output in high Z time
+
+reg [7:0] mem[0:32767];
+
+time adr_chng,da_chng,we_fall,we_rise;
+time cs_fall,cs_rise,oe_fall,oe_rise;
+
+wire [7:0] data_in;
+reg [7:0] data_out;
+reg [7:0] temp1,temp2,temp3;
+reg outen, out_en, in_en;
+
+//integer i;
+//initial begin
+// for (i=0; i<32768 ; i=i+4) begin
+// mem[i] = 8'haa;
+// mem[i+1] = 8'hbb;
+// mem[i+2] = 8'hcc;
+// mem[i+3] = 8'hdd;
+// end
+//end
+
+initial
+ begin
+ in_en = 1'b1;
+ if (cs_)
+ out_en = 1'b0;
+ end
+
+// input/output control logic
+//---------------------------
+assign data = out_en ? data_out : 'hz;
+assign data_in = in_en ? data : 'hz;
+
+// read access
+//------------
+always @(addr)
+ if (cs_==0 & we_==1) //read
+ #Taa data_out = mem[addr];
+
+always @(addr)
+ begin
+ adr_chng = $time;
+
+ outen = 1'b0;
+ #Toh out_en = outen;
+
+//---------------------------------------------
+ if (cs_==0 & we_==1) //read
+ begin
+ if (oe_==0)
+ begin
+ outen = 1'b1;
+ out_en = 1'b1;
+ end
+ end
+//---------------------------------------------
+ if (cs_==0 & we_==0) //write
+ begin
+ if (oe_==0)
+ begin
+ outen = 1'b0;
+ out_en = 1'b0;
+ temp1 = data_in;
+ #Tdw mem[addr] = temp1;
+ end
+ else
+ begin
+ outen = 1'b0;
+ out_en = 1'b0;
+ temp1 = data_in;
+ #(Tdw-Toh) mem[addr] = temp1;
+ end
+
+ data_out = mem[addr];
+ end
+ end
+
+always @(negedge cs_)
+ begin
+ cs_fall = $time;
+
+ if (cs_fall - adr_chng < Tas)
+ $display($time, " Adr setup time is not enough Tas");
+
+ if (we_==1 & oe_==0)
+ outen = 1'b1;
+ #Tclz out_en = outen;
+
+ if (we_==1)
+ #(Tacs-Tclz) data_out = mem[addr];
+
+ if (we_==0)
+ begin
+ outen = 1'b0;
+ out_en = 1'b0;
+ temp2 = data_in;
+ #Tdw mem[addr] = temp2;
+ end
+
+ end
+
+always @(posedge cs_)
+ begin
+ cs_rise = $time;
+
+ if (we_==0)
+ begin
+ if (cs_rise - adr_chng < Taw)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " Adr valid to end of write is not enough Taw");
+ end
+
+ if (cs_rise - cs_fall < Tcw)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " cs_ to end of write is not enough Tcw");
+ end
+
+ if (cs_rise - da_chng < Tdw)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " Data setup is not enough");
+ end
+ end
+
+ outen = 1'b0;
+ #Tchz out_en = outen;
+
+ end
+
+always @(negedge oe_)
+ begin
+ oe_fall = $time;
+
+ data_out = mem[addr];
+
+ if (we_==1 & cs_==0)
+ outen = 1'b1;
+ #Toe out_en = outen;
+ end
+
+always @(posedge oe_)
+ begin
+ oe_rise = $time;
+
+ outen = 1'b0;
+ #Tohz out_en = outen;
+ end
+
+// write to ram
+//-------------
+always @(negedge we_)
+ begin
+ we_fall = $time;
+
+ if (we_fall - adr_chng < Tas)
+ $display($time, " Address set-up to WE low is not enough");
+
+ if (cs_==0 & oe_==0)
+ begin
+ outen = 1'b0;
+ #Twhz out_en = outen;
+ temp3 = data_in;
+ #Tdw mem[addr] = temp3;
+
+ data_out = mem[addr];
+ end
+
+ if (cs_==0 & oe_==1)
+ begin
+ outen = 1'b0;
+ out_en = 1'b0;
+ temp3 = data_in;
+ #Tdw mem[addr] = temp3;
+
+ data_out = mem[addr];
+ end
+ end
+
+always @(posedge we_)
+ begin
+ we_rise = $time;
+
+ if (cs_==0)
+ begin
+ if (we_rise - da_chng < Tdw)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " Data setup is not enough");
+ end
+ if (we_rise - adr_chng < Taw)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " Addr setup is not enough");
+ end
+ end
+ if (cs_==0 & oe_==0)
+ begin
+ if (we_rise - we_fall < (Twhz+Tdw) )
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " WE pulse width needs to be Twhz+Tdw");
+ end
+
+ outen = 1'b1;
+ #Tow out_en = outen;
+ end
+ if (cs_==0 & oe_==1)
+ begin
+ if (we_rise - we_fall < Twp)
+ begin
+ mem[addr] = 8'hxx;
+ $display($time, " WE pulse width needs to be Twp");
+ end
+ end
+ end
+
+always @ (data)
+ begin
+ da_chng = $time;
+
+ if (we_==0 & cs_==0)
+ begin
+ #Tdw mem[addr] = data_in;
+
+ data_out = mem[addr];
+ end
+ end
+
+endmodule
Index: models/512Kx8.v
===================================================================
--- models/512Kx8.v (nonexistent)
+++ models/512Kx8.v (revision 1765)
@@ -0,0 +1,323 @@
+// This model is the property of Cypress Semiconductor Corp and is protected
+
+// by the US copyright laws, any unauthorized copying and distribution is prohibited.
+
+// Cypress reserves the right to change any of the functional specifications without
+
+// any prior notice.
+
+// Cypress is not liable for any damages which may result from the use of this
+
+// functional model.
+
+//This model checks for all the timimg violations and if any timing specifications
+//are violated,the output might be undefined or go to a high impedance state while
+//reading.Please note that the variable "tsim" in this model has to be changed as
+//per your convenience for the simulation time.
+
+// Model: 512Kx8
+
+
+// Contact: mpd_apps@cypress.com
+
+//******************************************************************************
+`timescale 1 ns/1 ps
+
+
+module A512Kx8(Address,dataIO ,OE_bar,CE_bar,WE_bar);
+
+`define tsim 30000
+
+
+
+input [18:0] Address;
+inout [7:0] dataIO ;
+input OE_bar,CE_bar,WE_bar;
+reg [7:0] temp_array [524287:0];
+reg [7:0] mem_array [524287:0];
+reg [7:0] data_temp;
+reg [18:0] Address1,Address2,Address3,Address4 ;
+reg [7:0] dataIO1;
+reg ini_cebar,ini_webar,ini_wecebar;
+reg initiate_write1,initiate_write2,initiate_write3;
+reg initiate_read1,initiate_read2;
+reg delayed_WE;
+
+integer fsram1;
+
+time twc ;
+time tpwe;
+time tsce;
+time tsd ;
+time trc;
+time thzwe;
+time tdoe;
+
+
+time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;
+time write_CE_bar_start,write_WE_bar_start,write_address,write_data;
+time read_address,read_CE_bar_start,read_WE_bar_start;
+
+initial
+ begin
+ initiate_write1 = 1'b0;
+ initiate_write2 = 1'b0;
+ initiate_write3 = 1'b0;
+ initiate_read1 =1'b0;
+ initiate_read2 =1'b0;
+ read_address =0;
+ twc =10 ;
+ tpwe =7;
+ tsce =7 ;
+ tsd = 5 ;
+ trc =10 ;
+ thzwe = 5;
+ tdoe = 5;
+// fsram1 = $fopen("sram1.log");
+
+ end
+
+// Added thzwe for WE_bar going low
+
+wire [7:0] dataIO = (!OE_bar && delayed_WE) ? data_temp[7:0] : 8'bz ;
+
+always@(CE_bar or WE_bar or OE_bar or Address or dataIO )
+ begin
+
+ if ((CE_bar==1'b0) && (WE_bar ==1'b0))
+ begin
+ Address1 <= Address;
+ Address2 <= Address1;
+ dataIO1 <= dataIO;
+ temp_array[Address1] <= dataIO1[7:0] ;
+ end
+ end
+
+always@(negedge CE_bar)
+ begin
+ write_CE_bar_start <= $time;
+ read_CE_bar_start <=$time;
+ ini_cebar <= 1'b0;
+ ini_wecebar<=1'b0;
+ end
+
+//*******************Write_cycle**********************
+
+always@(posedge CE_bar)
+ begin
+ if (($time - write_CE_bar_start) >= tsce)
+ begin
+ if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )
+ begin
+ Address2 <= Address1;
+ temp_array[Address1] <= dataIO1[7:0];
+ ini_cebar <= 1'b1;
+ end
+ else
+ ini_cebar <= 1'b0;
+ end
+ else
+ begin
+ ini_cebar <= 1'b0;
+ end
+ end
+
+always@(negedge WE_bar)
+ begin
+ write_WE_bar_start <= $time;
+ ini_webar <= 1'b0;
+ ini_wecebar<=1'b0;
+#thzwe delayed_WE <= WE_bar;
+
+ end
+
+always@(posedge WE_bar )
+ begin
+ delayed_WE <= WE_bar;
+ read_WE_bar_start <=$time;
+ if (($time - write_WE_bar_start) >=tpwe)
+ begin
+ if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )
+ begin
+ Address2 <= Address1;
+ temp_array[Address1] <= dataIO1[7:0];
+ ini_webar <= 1'b1;
+ end
+ else
+ ini_webar <= 1'b0;
+ end
+ else
+ begin
+ ini_webar <= 1'b0;
+ end
+end
+
+always@(CE_bar && WE_bar)
+ begin
+ if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))
+ ini_wecebar <=1'b1;
+ else
+ ini_wecebar <= 1'b0 ;
+ end
+ else
+ ini_wecebar <=1'b0;
+ end
+
+always@(dataIO)
+ begin
+ write_data <= $time;
+ write_data1 <=write_data;
+ write_WE_bar_start1 <=$time;
+ write_CE_bar_start1 <=$time;
+ if ( ($time - write_data) >= tsd)
+ begin
+ if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))
+ begin
+ if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )
+ initiate_write2 <= 1'b1;
+ else
+ initiate_write2 <= 1'b0;
+ end
+ end
+ end
+
+always@(Address)
+ begin
+ write_address <= $time;
+ write_address1 <= write_address;
+ write_WE_bar_start1 <=$time;
+ write_CE_bar_start1 <=$time;
+ if ( ($time - write_address) >= twc)
+ begin
+ if ( (WE_bar == 1'b0) && (CE_bar ==1'b0))
+ begin
+ if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )
+ initiate_write3 <= 1'b1;
+ else
+ initiate_write3 <= 1'b0;
+ end
+ else
+ initiate_write3 <= 1'b0;
+ end
+ else
+ initiate_write3 <= 1'b0;
+ end
+
+always@(ini_cebar or ini_webar or ini_wecebar)
+ begin
+ if ( (ini_cebar == 1'b1) || (ini_webar == 1'b1) || (ini_wecebar == 1'b1) )
+ begin
+ if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )
+ initiate_write1 <= 1'b1;
+ else
+ initiate_write1 <= 1'b0;
+ end
+ else
+ initiate_write1 <= 1'b0;
+ end
+
+//Removed address change completing a write
+//removed initiate_write3
+//always@(initiate_write2 or initiate_write3)
+
+always @(initiate_write2)
+ begin
+ if ( (initiate_write2==1'b1) || (initiate_write3==1'b1))
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))
+ begin
+// $fdisplay(fsram1, "%t initiate_write2 [%h] <- %h", $time, Address2, temp_array[Address2]);
+ mem_array[Address2] <= temp_array[Address2];
+ end
+ end
+ initiate_write2 <=1'b0;
+ initiate_write3 <=1'b0;
+ end
+
+always@( initiate_write1 )
+ begin
+ if (initiate_write1==1'b1)
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce)) begin
+//&& (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))
+// $fdisplay(fsram1, "%t initiate_write1 [%h] <- %h", $time, Address2, temp_array[Address2]);
+ mem_array[Address2] <= temp_array[Address2];
+ end
+ end
+ initiate_write1 <=1'b0;
+ end
+
+//*********************Read_cycle******************
+
+always@(Address)
+ begin
+ read_address <=$time;
+ Address3 <=Address;
+ Address4 <=Address3;
+ if ( ($time - read_address) == trc)
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
+ initiate_read1 <= 1'b1;
+ else
+ initiate_read1 <= 1'b0;
+ end
+ else
+ initiate_read1 <= 1'b0;
+ end
+
+always
+ #1
+ begin
+ if ( ($time - read_address) >= trc)
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
+ begin
+ Address4 <=Address3;
+ initiate_read2 <= 1'b1;
+ end
+ else
+ initiate_read2 <= 1'b0;
+ end
+ else
+ initiate_read2 <= 1'b0;
+ end
+// initial # `tsim $finish;
+
+always@(initiate_read1 or initiate_read2)
+ begin
+ if ( (initiate_read1 == 1'b1) || (initiate_read2 == 1'b1) )
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )
+ begin
+ if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) ) begin
+// $fdisplay(fsram1, "%t initiate_read1/2 [%h] -> %h", $time, Address4, mem_array[Address4]);
+ data_temp[7:0] <= mem_array[Address4];
+ end
+ end
+ else
+ #thzwe data_temp <=8'bzz;
+ end
+ initiate_read1 <=1'b0;
+ initiate_read2 <=1'b0;
+ end
+
+always @(Address)
+ begin
+ if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin
+ #tdoe data_temp[7:0] <= mem_array[Address];
+// $fdisplay(fsram1, "%m %t Address [%h] -> %h", $time, Address, mem_array[Address]);
+ end
+ end
+
+always @(WE_bar or OE_bar or CE_bar)
+ begin
+ if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0) begin
+// $fdisplay(fsram1, "%t WE_bar/OE_bar/CE_bar [%h] -> %h", $time, Address3, mem_array[Address3]);
+ #tdoe data_temp[7:0] <= mem_array[Address3];
+ end
+ end
+
+
+endmodule
Index: models/256Kx16.v
===================================================================
--- models/256Kx16.v (nonexistent)
+++ models/256Kx16.v (revision 1765)
@@ -0,0 +1,346 @@
+// This model is the property of Cypress Semiconductor Corp and is protected
+
+// by the US copyright laws, any unauthorized copying and distribution is prohibited.
+
+// Cypress reserves the right to change any of the functional specifications without
+
+// any prior notice.
+
+// Cypress is not liable for any damages which may result from the use of this
+
+// functional model.
+
+//This model checks for all the timimg violations and if any timing specifications are violated,the output might be undefined or go to a high impedance state while reading.Please note that the variable "tsim" in this model has to be changed as per your convenience for the simulation time.
+
+// Model: 256Kx16 model
+
+// Contact: mpd_apps@cypress.com
+
+//******************************************************************************
+`timescale 1 ns/1 ps
+
+
+module A256Kx16(Address,dataIO ,OE_bar,CE_bar,WE_bar,BLE_bar, BHE_bar);
+
+`define tsim 30000
+
+
+
+input [17:0] Address;
+inout [15:0] dataIO ;
+input OE_bar,CE_bar,WE_bar, BLE_bar, BHE_bar;
+reg [7:0] temp_array0 [262143:0];
+reg [15:8] temp_array1 [262143:0];
+reg [7:0] mem_array0 [262143:0];
+reg [15:8] mem_array1 [262143:0];
+reg [15:0] data_temp;
+reg [17:0] Address1,Address2,Address3,Address4 ;
+reg [15:0] dataIO1;
+reg ini_cebar,ini_webar,ini_wecebar;
+reg initiate_write1,initiate_write2,initiate_write3;
+reg initiate_read1,initiate_read2;
+reg delayed_WE;
+
+time twc ;
+time tpwe;
+time tsce;
+time tsd ;
+time trc;
+time thzwe;
+time tdoe;
+
+
+time write_address1,write_data1,write_CE_bar_start1,write_WE_bar_start1;
+time write_CE_bar_start,write_WE_bar_start,write_address,write_data;
+time read_address,read_CE_bar_start,read_WE_bar_start;
+
+initial
+ begin
+ initiate_write1 = 1'b0;
+ initiate_write2 = 1'b0;
+ initiate_write3 = 1'b0;
+ initiate_read1 =1'b0;
+ initiate_read2 =1'b0;
+ read_address =0;
+ twc =10 ;
+ tpwe =7;
+ tsce =7 ;
+ tsd = 5 ;
+ trc =10 ;
+ thzwe = 5;
+ tdoe = 5;
+ end
+
+// Added thzwe for WE_bar going low
+
+wire [15:0] dataIO = (!OE_bar && delayed_WE) ? data_temp[15:0] : 16'bz ;
+
+always@(CE_bar or WE_bar or OE_bar or Address or dataIO )
+ begin
+
+ if ((CE_bar==1'b0) && (WE_bar ==1'b0))
+ begin
+ Address1 <= Address;
+ Address2 <= Address1;
+ dataIO1 <= dataIO;
+ temp_array0[Address1] <= dataIO1[7:0] ;
+ temp_array1[Address1] <= dataIO1[15:8] ;
+ end
+ end
+
+always@(negedge CE_bar)
+ begin
+ write_CE_bar_start <= $time;
+ read_CE_bar_start <=$time;
+ ini_cebar <= 1'b0;
+ ini_wecebar<=1'b0;
+ end
+
+//*******************Write_cycle**********************
+
+always@(posedge CE_bar)
+ begin
+ if (($time - write_CE_bar_start) >= tsce)
+ begin
+ if ( (WE_bar == 1'b0) && ( ($time - write_WE_bar_start) >=tpwe) )
+ begin
+ Address2 <= Address1;
+ temp_array0[Address1] <= dataIO1[7:0];
+ temp_array1[Address1] <= dataIO1[15:8] ;
+ ini_cebar <= 1'b1;
+ end
+ else
+ ini_cebar <= 1'b0;
+ end
+ else
+ begin
+ ini_cebar <= 1'b0;
+ end
+ end
+
+always@(negedge WE_bar)
+ begin
+ write_WE_bar_start <= $time;
+ ini_webar <= 1'b0;
+ ini_wecebar<=1'b0;
+#thzwe delayed_WE <= WE_bar;
+
+ end
+
+always@(posedge WE_bar )
+ begin
+ delayed_WE <= WE_bar;
+ read_WE_bar_start <=$time;
+ if (($time - write_WE_bar_start) >=tpwe)
+ begin
+ if ( (CE_bar == 1'b0) && ( ($time - write_CE_bar_start) >= tsce) )
+ begin
+ Address2 <= Address1;
+ temp_array0[Address1] <= dataIO1[7:0];
+ temp_array1[Address1] <= dataIO1[15:8] ;
+ ini_webar <= 1'b1;
+ end
+ else
+ ini_webar <= 1'b0;
+ end
+ else
+ begin
+ ini_webar <= 1'b0;
+ end
+end
+
+always@(CE_bar && WE_bar)
+ begin
+ if ( (CE_bar ==1'b1) && (WE_bar ==1'b1) )
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && (($time-write_CE_bar_start) >=tsce))
+ ini_wecebar <=1'b1;
+ else
+ ini_wecebar <= 1'b0 ;
+ end
+ else
+ ini_wecebar <=1'b0;
+ end
+
+always@(dataIO)
+ begin
+ write_data <= $time;
+ write_data1 <=write_data;
+ write_WE_bar_start1 <=$time;
+ write_CE_bar_start1 <=$time;
+ if ( ($time - write_data) >= tsd)
+ begin
+ if ( (WE_bar == 1'b0) && (CE_bar == 1'b0))
+ begin
+ if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_address) >=twc) )
+ initiate_write2 <= 1'b1;
+ else
+ initiate_write2 <= 1'b0;
+ end
+ end
+ end
+
+always@(Address)
+ begin
+ write_address <= $time;
+ write_address1 <= write_address;
+ write_WE_bar_start1 <=$time;
+ write_CE_bar_start1 <=$time;
+ if ( ($time - write_address) >= twc)
+ begin
+ if ( (WE_bar == 1'b0) && (CE_bar ==1'b0))
+ begin
+ if ( ( ($time - write_CE_bar_start) >=tsce) && ( ($time - write_WE_bar_start) >=tpwe) && (($time - write_data) >=tsd) )
+ initiate_write3 <= 1'b1;
+ else
+ initiate_write3 <= 1'b0;
+ end
+ else
+ initiate_write3 <= 1'b0;
+ end
+ else
+ initiate_write3 <= 1'b0;
+ end
+
+always@(ini_cebar or ini_webar or ini_wecebar)
+ begin
+ if ( (ini_cebar == 1'b1) || (ini_webar == 1'b1) || (ini_wecebar == 1'b1) )
+ begin
+ if ( ( ($time - write_data1) >= tsd) && ( ($time - write_address1) >= twc) )
+ initiate_write1 <= 1'b1;
+ else
+ initiate_write1 <= 1'b0;
+ end
+ else
+ initiate_write1 <= 1'b0;
+ end
+
+//Removed address change completing a write
+// removed initiate_write3
+
+//always@(initiate_write2 or initiate_write3)
+ always @(initiate_write2)
+begin
+ if ( (initiate_write2==1'b1) || (initiate_write3==1'b1))
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce))
+ begin
+ if (BLE_bar == 1'b0)
+ mem_array0[Address2] <= temp_array0[Address2];
+ if(BHE_bar == 1'b0)
+ mem_array1[Address2] <= temp_array1[Address2];
+ end
+ end
+ initiate_write2 <=1'b0;
+ initiate_write3 <=1'b0;
+ end
+
+always@( initiate_write1 )
+ begin
+ if (initiate_write1==1'b1)
+ begin
+ if ( ( ($time - write_WE_bar_start) >=tpwe) && ( ($time - write_CE_bar_start) >=tsce) && (($time - write_WE_bar_start1) >=tpwe) && (($time - write_CE_bar_start1) >=tsce))
+ begin
+ if (BLE_bar == 1'b0)
+ mem_array0[Address2] <= temp_array0[Address2];
+
+ if(BHE_bar == 1'b0)
+ mem_array1[Address2] <= temp_array1[Address2];
+ end
+ end
+ initiate_write1 <=1'b0;
+ end
+
+//*********************Read_cycle******************
+
+always@(Address)
+ begin
+ read_address <=$time;
+ Address3 <=Address;
+ Address4 <=Address3;
+ if ( ($time - read_address) == trc)
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
+ initiate_read1 <= 1'b1;
+ else
+ initiate_read1 <= 1'b0;
+ end
+ else
+ initiate_read1 <= 1'b0;
+ end
+
+always
+ #1
+ begin
+ if ( ($time - read_address) >= trc)
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar == 1'b1) )
+ begin
+ Address4 <=Address3;
+ initiate_read2 <= 1'b1;
+ end
+ else
+ initiate_read2 <= 1'b0;
+ end
+ else
+ initiate_read2 <= 1'b0;
+ end
+initial # `tsim $finish;
+
+always@(initiate_read1 or initiate_read2)
+ begin
+ if ( (initiate_read1 == 1'b1) || (initiate_read2 == 1'b1) )
+ begin
+ if ( (CE_bar == 1'b0) && (WE_bar ==1'b1) )
+ begin
+ if ( ( ($time - read_WE_bar_start) >=trc) && ( ($time -read_CE_bar_start) >=trc) )
+ begin
+ if(BLE_bar == 1'b0)
+ data_temp[7:0] <= mem_array0[Address4];
+ else
+ data_temp[7:0] <= 8'bzz;
+
+ if(BHE_bar == 1'b0)
+ data_temp[15:8] <= mem_array1[Address4];
+ else
+ data_temp[15:8] <= 8'bzz;
+ end
+ else
+ #thzwe data_temp <= 8'bzz;
+ end
+ else
+ #thzwe data_temp <=8'bzz;
+ end
+ initiate_read1 <=1'b0;
+ initiate_read2 <=1'b0;
+ end
+
+always @(Address)
+ begin
+ if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)
+ begin
+ if (BLE_bar == 1'b0)
+ #tdoe data_temp[7:0] <= mem_array0[Address];
+ else
+ data_temp[7:0] <= 8'bzz;
+
+ if (BHE_bar == 1'b0)
+ #tdoe data_temp[15:8] <= mem_array1[Address];
+ else
+ data_temp[15:8] <= 8'bzz;
+ end
+ end
+
+always @(WE_bar or OE_bar or CE_bar)
+ begin
+ if (CE_bar == 1'b0 && WE_bar == 1'b1 && OE_bar == 1'b0)
+ begin
+ if (BLE_bar == 1'b0)
+ #tdoe data_temp[7:0] <= mem_array0[Address3];
+ if (BHE_bar == 1'b0)
+ #tdoe data_temp[15:8] <= mem_array1[Address3];
+ end
+ end
+
+
+endmodule
Index: models/28f016s3/bwsvff.v
===================================================================
--- models/28f016s3/bwsvff.v (nonexistent)
+++ models/28f016s3/bwsvff.v (revision 1765)
@@ -0,0 +1,1477 @@
+
+ /*
+ 3-Jul-97 - the VCS simulator does not allow overwriting parameters. I
+ changed then to integers and inited them in the initial clause.
+ This should make the model better suited for all Verilog simulators.
+ 3-Jul-97 - Stretch size of OpBlock, CmdAdd_1 and CmdAdd_2 for 32 block parts.
+ 11-Jul-97 - added variable flash_cycle. Only check TAVAV timing when CEn is
+ asserted. This avoids errorious ERRORS when the address toggles
+ to fast when CEn is disabled.
+ */
+
+ /*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+ BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+ THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+ AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+ TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ ANY ACCOMPANYING ITEMS.
+
+ IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+ AGREEMENT
+
+ LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+ to use the enclosed software program ("Software"). You will not use,
+ copy, modify, rent, sell or transfer the Software or any portion
+ thereof, except as provided in this Agreement.
+
+ System OEM Developers may:
+ 1. Copy the Software for support, backup or archival purposes;
+ 2. Install, use, or distribute Intel owned Software in object code
+ only;
+ 3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+ 4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+ RESTRICTIONS:
+
+ YOU WILL NOT:
+ 1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+ 2. Decompile or reverse engineer any Software provided in object
+ code format;
+ 3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+ TRANSFER: You may transfer the Software to another OEM Developer if the
+ receiving party agrees to the terms of this Agreement at the sole risk
+ of any receiving party.
+
+ OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+ copies thereof remain with Intel or its vendors. The Software is
+ copyrighted and is protected by United States and international
+ copyright laws. You will not remove the copyright notice from the
+ Software. You agree to prevent any unauthorized copying of the
+ Software.
+
+ DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+ not be required to provide Intel with a copy of the source or object
+ code. OEM Developers shall be authorized to use, market, sell, and/or
+ distribute Derivatives to other OEM Developers at their own risk and
+ expense. Title to Derivatives and all copies thereof shall be in the
+ particular OEM Developer creating the Derivative. Such OEMs shall
+ remove the Intel copyright notice from all Derivatives if such notice is
+ contained in the Software source code.
+
+ DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+ you may only use the medium appropriate for your system.
+
+ WARRANTY: Intel warrants that it has the right to license you to use,
+ modify, or distribute the Software as provided in this Agreement. The
+ Software is provided "AS IS". Intel makes no representations to
+ upgrade, maintain, or support the Software at any time. Intel warrants
+ that the media on which the Software is furnished will be free from
+ defects in material and workmanship for a period of one (1) year from
+ the date of purchase. Upon return of such defective media, Intel's
+ entire liability and your exclusive remedy shall be the replacement of
+ the Software.
+
+ THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+ OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+ PARTICULAR PURPOSE.
+
+ LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+ BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+ INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+ CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+ OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+ TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+ conducted audits to verify your compliance with this Agreement. Intel
+ may terminate this Agreement at any time if you are in breach of any of
+ its terms and conditions. Upon termination, you will immediately
+ destroy, and certify in writing the destruction of, the Software or
+ return all copies of the Software and documentation to Intel.
+
+ U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+ developed at private expense and are provided with "RESTRICTED RIGHTS".
+ Use, duplication or disclosure by the Government is subject to
+ restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+ or its successor.
+
+ EXPORT LAWS: You agree that the distribution and export/re-export of the
+ Software is in compliance with the laws, regulations, orders or other
+ restrictions of the U.S. Export Administration Regulations.
+
+ APPLICABLE LAW: This Agreement is governed by the laws of the State of
+ California and the United States, including patent and copyright laws.
+ Any claim arising out of this Agreement will be brought in Santa Clara
+ County, California.
+ */
+
+ // This model is representative of the flash device described in the
+ // Byte-Wide Smart 3 FlashFile(tm) Memory Family datasheet (Order
+ // Number 290598).
+
+ `timescale 1ns/1ns
+
+ //generic defines for readability (already defined!)
+ `define FALSE 1'b0
+ `define TRUE 1'b1
+
+ `define Byte 7:0
+
+ `define VIL 1'b0
+ `define VIH 1'b1
+
+ `define rpb_vil 2'b00
+ `define rpb_vih 2'b01
+ `define rpb_vhh 2'b10
+
+ `define Ready 1'b1
+ `define Busy 1'b0
+
+ // These constants are the actual command codes
+ `define ClearCSRCmd 8'h50
+ `define ProgramCmd 8'h10
+ `define Program2Cmd 8'h40
+ `define EraseBlockCmd 8'h20
+ `define ReadArrayCmd 8'hFF
+ `define ReadCSRCmd 8'h70
+ `define ReadIDCmd 8'h90
+ `define SuspendCmd 8'hB0 //Valid for both erase
+ `define ResumeCmd 8'hD0 //and write suspend
+ `define ConfirmCmd 8'hD0
+ `define LBSetupCmd 8'h60
+ `define SetBlockLBCmd 8'h01
+ `define SetMasterLBCmd 8'hF1
+ `define ClearLBCmd 8'hD0
+
+ `define ReadMode_T 2:0
+ `define rdARRAY 3'b000
+ `define rdCSR 3'b011
+ `define rdID 3'b100
+
+ `define Program 2'b00
+ `define Erase 2'b01
+ `define Lock 2'b10
+
+ // Cmd_T record
+ `define Cmd_T 157:0
+ `define CmdAdd_1 157:137
+ `define CmdAdd_2 136:116
+ `define Add 115:96
+ `define CmdData_1 95:88
+ `define CmdData_2 87:78
+ `define Cmd 79:72
+ `define Count 71:40
+ `define Time 39:8
+ `define Confirm 7
+ `define OpBlock 6:2
+ `define OpType 1:0
+
+ `define WritePtr_T 1:0
+ `define NewCmd 2'b01
+ `define CmdField 2'b10
+
+ `define Locked 1'b1
+ `define Unlocked 1'b0
+
+ `define Vcc2700 3'b100
+ `define Vcc3300 3'b010
+ `define Vcc5000 3'b001
+
+ `include "dp016s3.v"
+
+ // device specific
+
+ //module definition for Intel Smartvoltage FlashFile(tm) Flash
+ //
+ //vpp and vcc are are 32 bit vectors which are treated as unsigned int
+ //scale for vpp and vcc is millivolts. ie. 0 = 0V, 5000 = 5V
+ //
+
+ module i28f016s3(dq, addr, ceb, oeb, web, rpb, ryby, vpp, vcc, rpblevel);
+
+ inout [`MaxOutputs-1:0] dq; //8 outputs
+
+ input [`AddrSize-1:0] addr; //address pins.
+
+ input ceb, //CE# - chip enable bar
+ oeb, //OE# - output enable bar
+ web, //WE# - write enable bar
+ rpb; //RP# - reset bar, powerdown
+
+ output ryby; //RY/BY# - Ready/Busy signal
+
+ input [31:0] vpp, //vpp in millivolts
+ vcc; //vcc in millivolts
+
+ input [1:0] rpblevel; //rpb at vil or vih or vhh
+
+ reg [`Byte] MainArray[`MainArraySize]; //flash array
+
+ // Flag to show that a Cmd has been written
+ // and needs predecoding
+ reg CmdValid ;
+
+ // This points to where data written to the part will
+ // go. By default it is to NewCmd. CmdField means the
+ // chip is waiting on more data for the cmd (ie confirm)
+
+ reg [`WritePtr_T] WriteToPtr ;
+
+ // Contains the current executing command and all its
+ // support information.
+ reg [`Cmd_T] Cmd ;
+
+ reg [`Cmd_T] Algorithm;
+
+ reg [`Cmd_T] SuspendedAlg;
+
+ // Output of Data
+ reg [7:0] ArrayOut ;
+
+ // Current output of the Compatible status register
+ reg [7:0] CSROut ;
+
+ // Current output of the ID register
+ reg [7:0] IDOut ;
+
+ // Startup Flag phase
+ reg StartUpFlag ;
+
+ // Global Reset Flag
+ reg Reset ;
+
+ // Variable to see if chip can only be read -- 2.7V Vcc
+ reg ReadOnly;
+
+ // Vpp Monitoring
+ reg VppFlag ;
+ reg VppError ;
+ reg VppErrFlag ;
+ reg ClearVppFlag ;
+
+ // Internal representation of the CSR SR.1 bit
+ reg Protected;
+ // Internal representation of the CSR SR.4 bit
+ reg Program_SetLBError ;
+ // Internal representation of the CSR SR.5 bit
+ reg Erase_ClearLBError ;
+
+ // Internal representation of GSR bit
+ reg [`ReadMode_T] ReadMode ;
+
+ // Current value of the CSR
+ wire [`Byte] CSR ;
+
+ // Flag that determines if the chip is driving
+ // the outputs
+ reg DriveOutputs ;
+
+ // Internal value of the out data. If DriveOutputs
+ // is active this value will be placed on the
+ // outputs. -1 == Unknown or XXXX
+ reg [`MaxOutputs-1:0] InternalOutput ;
+
+ // Number of addition writes necessary to
+ // supply the current command information.
+ // When it hits zero it goes to Decode
+ integer DataPtr ;
+
+ // Master internal write enable
+ wire Internal_WE ;
+
+ // Master internal output enable
+ wire Internal_OE ;
+ wire Internal_OE2 ;
+ wire Internal_OE3 ;
+
+ // Master internal read enable
+ wire Internal_RE ;
+
+ // Internal flag to tell if an algorithm is running
+ reg ReadyBusy ;
+
+ // Flag to represent if the chip is write suspended
+ reg WriteSuspended ;
+ // Flag to represent if the chip is erase suspended
+ reg EraseSuspended ;
+ // Flag to represent the chip should be suspended
+ reg Suspend ;
+ // Variable to hold which algorithm (program or erase)
+ // is to be suspended
+ reg [1:0] ToBeSuspended;
+
+ // Array to hold block lock-bit information
+ reg BlockLockBit[`NumberOfBlocks-1:0];
+ // Variable for block number to be locked
+ integer WhichBlock;
+ // Flag to represent state of master lock-bit
+ reg MasterLock;
+
+ // Algorithm Timer
+ reg TimerClk ;
+
+ // Flag to show the running algorithm is done.
+ reg AlgDone ;
+
+ // Number of timer cycles remaining for the
+ // current algorithm
+ integer AlgTime;
+
+ // Number of timer cycles remaining for erase operation
+ // when erase suspended and program operation in progress
+ integer TimeLeft;
+
+ // Generic temporary varible
+ integer LoopCntr ;
+ reg Other ;
+
+ //Block begin and end address
+ reg [`AddrSize-1:0] BlocksBegin[0:`NumberOfBlocks-1];
+ reg [`AddrSize-1:0] BlocksEnd[0:`NumberOfBlocks-1];
+ reg [31:0] BlocksEraseCount[0:`NumberOfBlocks-1];
+
+ // states the flash is in a cycle
+ reg flash_cycle;
+
+
+ //**********************************************************************
+ //TIMING VALUES
+ //**********************************************************************
+
+ time ToOut ;
+ time last_addr_time ,curr_addr_time;
+ time last_oe_time, curr_oe_time;
+ time last_ce_time, curr_ce_time;
+ time last_rp_time, curr_rp_time;
+ time last_ReadMode_time, curr_ReadMode_time ;
+ time last_Internal_RE_time, curr_Internal_RE_time ;
+ time last_Internal_WE_time, curr_Internal_WE_time ;
+ time last_dq_time ,curr_dq_time;
+ time last_rpb_time, curr_rpb_time ;
+ time WriteRecovery ;
+ time TempTime;
+
+ time Program_Time_Byte;
+ time Block_Erase_Time;
+ time Set_LockBit_Time;
+ time Clear_LockBit_Time;
+ time Program_Suspend_Time; // latency time
+ time Erase_Suspend_Time; // latency time
+
+ //**********************************************************************
+ //input configuration
+
+ parameter
+ LoadOnPowerup = 1, //load array from file
+`ifdef DAMJAN
+ LoadFileName = "../src/damjan_flash.in", //File to load array with
+`else
+ LoadFileName = "../src/flash.in", //File to load array with
+`endif
+ SaveOnPowerdown = `TRUE, //save array to file
+ SaveFileName = "../out/flash.out"; //save file name
+
+ //TIMING PARAMETERS
+ integer
+ TAVAV ,
+ TPHQV ,
+ TELQV ,
+ TGLQV ,
+ TAVQV ,
+ TGLQX ,
+ TGHQZ ,
+ TEHQZ ,
+ TOH ,
+ TWPH ,
+ TWP ,
+ TPHWL ,
+ TPHHWH ,
+ TAVWH ,
+ TDVWH ,
+ TWHDX ,
+ TWHAX ,
+ TimerPeriod ;
+
+
+ //**********************************************************************
+
+ initial begin
+ flash_cycle = 0 ;
+ Other = `FALSE ;
+ AlgDone = `FALSE ;
+ Reset = 1'bx ;
+ Reset <= `TRUE ;
+ StartUpFlag = `TRUE ;
+ StartUpFlag <= #2 `FALSE ;
+ DriveOutputs = `FALSE ;
+ ToOut = 0 ;
+ VppError = `FALSE ;
+ VppErrFlag = `FALSE ;
+ ClearVppFlag = `FALSE ;
+ VppFlag = `FALSE ;
+ WriteSuspended = `FALSE ;
+ EraseSuspended = `FALSE ;
+ Suspend = `FALSE ;
+ ToBeSuspended = `Program;
+ MasterLock = `Unlocked;
+ Erase_ClearLBError = `FALSE ;
+ Protected = `FALSE ;
+ TimerClk = 1'b0 ;
+ ArrayOut = `MaxOutputs'hxx ;
+ CSROut = 0 ;
+ IDOut = 0 ;
+ CmdValid = `FALSE ;
+ WriteToPtr = `NewCmd ;
+ last_addr_time = 0 ;
+ curr_addr_time = 0 ;
+ last_ce_time = 0 ;
+ curr_ce_time = 0 ;
+ last_oe_time = 0 ;
+ curr_oe_time = 0 ;
+ last_rp_time = 0 ;
+ curr_rp_time = 0 ;
+ last_ReadMode_time = 0 ;
+ curr_ReadMode_time = 0 ;
+ last_dq_time = 0 ;
+ curr_dq_time = 0 ;
+ last_rpb_time = 0 ;
+ curr_rpb_time = 0 ;
+ WriteRecovery = 0 ;
+ last_Internal_RE_time = 0 ;
+ curr_Internal_RE_time = 0 ;
+ InternalOutput = `MaxOutputs'hxx ;
+ last_Internal_WE_time = 0 ;
+ curr_Internal_WE_time = 0 ;
+ Program_Time_Byte = `AC_ProgramTime_Byte_50_12 ;
+ Block_Erase_Time = `AC_EraseTime_Block_50_12;
+ Set_LockBit_Time = `AC_Set_LockBit_50_12;
+ Clear_LockBit_Time = `AC_Clear_LockBit_50_12;
+ Program_Suspend_Time = `AC_Program_Suspend_50_12;
+ Erase_Suspend_Time = `AC_Erase_Suspend_50_12;
+
+ $readmemh(`BlockFileBegin,BlocksBegin);
+ $readmemh(`BlockFileEnd,BlocksEnd);
+
+ for (LoopCntr = 0; LoopCntr <= `NumberOfBlocks; LoopCntr = LoopCntr
+ + 1) begin
+ BlocksEraseCount [LoopCntr] = 0 ;
+ end
+
+ for (LoopCntr = 0; LoopCntr < `NumberOfBlocks; LoopCntr = LoopCntr
+ + 1) begin
+ BlockLockBit[LoopCntr] = `Unlocked;
+ end
+ //--------------------------------------------------------------------
+ // Array Init
+ //--------------------------------------------------------------------
+
+ //Constant condition expression: LoadOnPowerup == 1'b1
+ if (LoadOnPowerup)
+ LoadFromFile;
+ else begin
+ $display("Initializing Memory to 'hFF");
+ for (LoopCntr = 0; LoopCntr <= `MaxAddr; LoopCntr = LoopCntr + 1) begin
+ MainArray [LoopCntr] = 8'hFF ;
+ end
+ end
+ end //initial
+
+ //--------------------------------------------------------------------
+ // LoadFromFile
+ // This is used when the LoadOnPowerup parameter is set so that the
+ // Main array contains code at startup. Basically it loads the array
+ // from data in a file (LoadFileName).
+ //--------------------------------------------------------------------
+
+ task LoadFromFile ;
+ begin
+ $display("Loading from file %s",LoadFileName);
+ $readmemh(LoadFileName,MainArray, 1048576);
+ end
+ endtask
+
+ //--------------------------------------------------------------------
+ // StoreToFile
+ // This is used when the SaveOnPowerDown flag is set so that the Main
+ // Array stores code at powerdown. Basically it stores the array into
+ // a file (SaveFileName).
+ //--------------------------------------------------------------------
+
+ task StoreToFile;
+ reg [31:0] ArrayAddr ;
+ reg [31:0] outfile ;
+ begin
+ outfile = $fopen(SaveFileName) ;
+ if (outfile == 0)
+ $display("Error, cannot open output file %s",SaveFileName) ;
+ else
+ $display("Saving data to file %s",SaveFileName);
+ for (ArrayAddr = 0 ; ArrayAddr <= `MaxAddr; ArrayAddr = ArrayAddr
+ + 1) begin
+ $fdisplay(outfile,"%h",MainArray[ArrayAddr]);
+ end
+ end
+ endtask
+
+ //--------------------------------------------------------------------
+ // Program
+ // Description: Programs new values in to the array
+ //--------------------------------------------------------------------
+
+ task Program ;
+ inout [`Byte] TheArrayValue ;
+ input [`Byte] DataIn ;
+
+ reg [`Byte] OldData;
+ begin
+ OldData = TheArrayValue;
+ TheArrayValue = DataIn & OldData;
+ end
+ endtask
+
+ assign Internal_OE = !(ceb | oeb | !rpb) ;
+ assign Internal_OE2 = Internal_OE ;
+ assign Internal_OE3 = Internal_OE2 ;
+ assign Internal_RE = (((ReadyBusy == `Ready) || (ReadMode != `rdARRAY))
+ && !ceb && !Reset) ;
+ assign Internal_WE = !(ceb | web | !rpb) ;
+
+ // register definitions //
+
+ // Compatible Status Register
+ assign CSR [7] = ReadyBusy;
+ assign CSR [6] = EraseSuspended ;
+ assign CSR [5] = Erase_ClearLBError ;
+ assign CSR [4] = Program_SetLBError ;
+ assign CSR [3] = VppError ;
+ assign CSR [2] = WriteSuspended ;
+ assign CSR [1] = Protected ;
+ assign CSR [0] = 1'b0 ;
+
+ // Output Drivers //
+ assign dq[7:0] = (DriveOutputs == `TRUE) ? InternalOutput : 8'hz ;
+
+ always @(Reset) begin : Reset_process
+ if (Reset) begin
+ ClearVppFlag <= #1 `TRUE ;
+ ClearVppFlag <= #9 `FALSE ;
+ AlgDone = `FALSE ;
+ VppError = `FALSE ;
+ ReadMode = `rdARRAY;
+ ReadyBusy = `Ready ;
+ WriteSuspended = `FALSE ;
+ EraseSuspended = `FALSE ;
+ Suspend = `FALSE ;
+ Erase_ClearLBError = `FALSE ;
+ Program_SetLBError = `FALSE ;
+ Protected = `FALSE ;
+ AlgTime = 0 ;
+ CmdValid = `FALSE ;
+ WriteToPtr = `NewCmd ;
+ CSROut = 0 ;
+ IDOut = 0 ;
+ end
+ end
+
+
+ always @(Internal_RE or ReadMode or addr) begin : array_read
+ if (Internal_RE && ReadMode == `rdARRAY)
+ ArrayOut = MainArray[addr] ; // x8 outputs
+ end
+
+ always @(Internal_RE or ReadMode or addr or Internal_OE2) begin
+ // output mux
+ // Determine and generate the access time .
+ ToOut = 0;
+ if ($time > TAVQV) begin
+ last_addr_time = $time - curr_addr_time;
+ if ((last_addr_time < TAVQV) && ((TAVQV - last_addr_time) > ToOut))
+ ToOut = TAVQV - last_addr_time ;
+ last_oe_time = $time - curr_oe_time;
+ if ((last_oe_time < TGLQV) && ((TGLQV - last_oe_time) > ToOut))
+ ToOut = TGLQV - last_oe_time ;
+ last_ce_time = $time - curr_ce_time;
+ if ((last_ce_time < TELQV) && ((TELQV - last_ce_time) > ToOut))
+ ToOut = TELQV - last_ce_time ;
+ last_rp_time = $time - curr_rp_time;
+ if ((last_rp_time < TPHQV) && ((TPHQV - last_rp_time) > ToOut))
+ ToOut = TPHQV - last_rp_time ;
+ last_ReadMode_time = $time - curr_ReadMode_time;
+ if ((last_ReadMode_time < TAVQV) && ((TAVQV - last_ReadMode_time) >
+ ToOut))
+ ToOut = TAVQV - last_ReadMode_time ;
+ last_Internal_RE_time = $time - curr_Internal_RE_time ;
+ if ((last_Internal_RE_time < TAVQV) && ((TAVQV - last_Internal_RE_time)
+ > ToOut))
+ ToOut = TAVQV - last_Internal_RE_time ;
+ end // if
+
+ // Output Mux with timing
+ if (!StartUpFlag) begin
+ case (ReadMode)
+ `rdARRAY : begin
+ if ( (EraseSuspended == `TRUE) && (WriteSuspended == `FALSE)
+ && (addr >= BlocksBegin[Algorithm[`OpBlock]])
+ && (addr <= BlocksEnd[Algorithm[`OpBlock]]) && (oeb ==
+ `VIL) ) begin
+ $display("Error: Attempting to read from erase suspended block");
+ InternalOutput <= `MaxOutputs'hxx;
+ end
+ else if ( (EraseSuspended == `TRUE) && (WriteSuspended == `TRUE)
+ && (oeb == `VIL) && (addr >=
+ BlocksBegin[SuspendedAlg[`OpBlock]])
+ && (addr <= BlocksEnd[SuspendedAlg[`OpBlock]]) ) begin
+ $display("Error: Attempting to read from erase suspended block.");
+ InternalOutput <= `MaxOutputs'hxx;
+ end
+ else if ( (WriteSuspended == `TRUE) && (addr == Algorithm[`CmdAdd_1])
+ && (oeb == `VIL) ) begin
+ $display("Error: Attempting to read from write suspended address");
+ InternalOutput <= `MaxOutputs'hxx;
+ end
+ else
+ InternalOutput <= #ToOut ArrayOut ;
+ end
+ `rdCSR : begin
+ InternalOutput <= #ToOut CSROut ;
+ end
+ `rdID : begin
+ InternalOutput <= #ToOut IDOut ;
+ end
+ default : begin
+ $display("%t Error: illegal readmode", $time);
+ end
+ endcase
+ end // if
+ end // always
+
+ //
+ // other reads
+ //
+ always @(Internal_OE or addr) begin : other_read
+ if (!Reset) begin
+ if (ReadMode != `rdARRAY) begin
+ CSROut = CSR ;
+ if (addr[1:0] == 2'b00)
+ IDOut = `ID_ManufacturerB ;
+ else if (addr[1:0] == 2'b01)
+ IDOut = `ID_DeviceCodeB ;
+ else if (addr[1:0] == 2'b10) begin
+ for (LoopCntr = `NumberOfBlocks-1; LoopCntr >= 0; LoopCntr = LoopCntr
+ -
+ 1)
+ if (addr <= BlocksEnd[LoopCntr])
+ WhichBlock = LoopCntr;
+ IDOut = BlockLockBit[WhichBlock];
+ end
+ else
+ IDOut = MasterLock;
+ end
+ end
+ end
+
+ // Handle Write to Part
+
+ always @(negedge Internal_WE) begin : handle_write
+
+ reg [`Byte] temp ; // temporary variable needed for double
+ // indexing CmdData.
+ if (!Reset) begin
+ case (WriteToPtr) // Where are we writting to ?
+ `NewCmd : begin // This is a new command.
+ Cmd[`Cmd] = dq[7:0] ;
+ Cmd[`Add] = addr[`AddrSize-1:0] ;
+ CmdValid <= `TRUE ; // CmdValid sends it to the Predecode section
+ DataPtr <= -1 ;
+ end
+ `CmdField : begin // This is data used by another command
+ if (DataPtr == 1) begin
+ Cmd[`CmdData_1] = dq[`Byte];
+ Cmd[`CmdAdd_1] = addr [`AddrSize-1:0] ;
+ end
+ else if (DataPtr == 2) begin
+ Cmd[`CmdData_2] = dq[`Byte];
+ Cmd[`CmdAdd_2] = addr[`AddrSize-1:0] ;
+ end
+ else
+ $display("DataPtr out of range") ;
+ DataPtr <= #1 DataPtr - 1 ; // When DataPtr hits zero the command
+ end
+ default : begin
+ $display("Error: Write To ? Cmd");
+ end
+ endcase
+ end //if
+ end //always
+
+ //
+ // Predecode Command
+ //
+ always @(posedge CmdValid) begin : predecode
+ reg [`Byte] temp; // temporary variable needed for double
+ // indexing BSR.
+ if (!Reset) begin
+ // Set Defaults
+ Cmd [`OpType] = `Program ;
+ WriteToPtr = `NewCmd ;
+ DataPtr <= 0 ;
+ case (Cmd [`Cmd]) // Handle the basic read mode commands
+
+ // READ ARRAY COMMAND --
+
+ `ReadArrayCmd : begin // Read Flash Array
+ CmdValid <= `FALSE ;
+ if (ReadyBusy == `Busy) // Can not read array when running an algorithm
+ ReadMode <= `rdCSR ;
+ else
+ ReadMode <= `rdARRAY ;
+ end
+
+ // READ INTELLIGENT IDENTIFIER COMMAND --
+
+ `ReadIDCmd : begin // Read Intelligent ID
+ if ( (WriteSuspended == `TRUE) || (EraseSuspended == `TRUE) )
+ $display("Invalid read ID command during suspend");
+ else
+ ReadMode <= `rdID ;
+ CmdValid <= `FALSE ;
+ end
+
+ // READ COMPATIBLE STATUS REGISTER COMMAND --
+
+ `ReadCSRCmd : begin // Read CSR
+ ReadMode <= `rdCSR ;
+ CmdValid <= `FALSE ;
+ end
+ default : begin
+ Other = `TRUE ; // Other flag marks commands that are algorithms
+ Cmd [`Confirm] = `FALSE ; // Defaults
+ case (Cmd [`Cmd])
+
+ // PROGRAM BYTE COMMAND --
+
+ `ProgramCmd : begin // Program Byte
+ if (WriteSuspended == `TRUE) begin
+ $display("Error: Program Command during Write Suspend");
+ CmdValid <= `FALSE;
+ end
+ else begin
+ WriteToPtr = `CmdField ;
+ DataPtr <= 1 ;
+ if (EraseSuspended == `TRUE) begin
+ TimeLeft = AlgTime;
+ SuspendedAlg = Algorithm;
+ end
+ ToBeSuspended = `Program;
+ end
+ end
+
+ // PROGRAM BYTE COMMAND --
+
+ `Program2Cmd : begin // Program Byte
+ if (WriteSuspended == `TRUE) begin
+ $display("Error: Program Command during Write Suspend");
+ CmdValid <= `FALSE;
+ end
+ else begin
+ Cmd [`Cmd] = `ProgramCmd ;
+ WriteToPtr = `CmdField ;
+ DataPtr <= 1 ;
+ if (EraseSuspended == `TRUE) begin
+ TimeLeft = AlgTime;
+ SuspendedAlg = Algorithm;
+ end
+ ToBeSuspended = `Program;
+ end
+ end
+
+ // ERASE BLOCK COMMAND --
+
+ `EraseBlockCmd : begin // Single Block Erase
+ if ( (WriteSuspended == `TRUE) || (EraseSuspended == `TRUE) ) begin
+ $display("Attempted to erase block while suspended");
+ CmdValid <= `FALSE;
+ end
+ else begin
+ WriteToPtr = `CmdField ;
+ DataPtr <= 1 ;
+ Cmd [`OpType] = `Erase ;
+ Cmd [`Confirm] = `TRUE ;
+ ToBeSuspended = `Erase;
+ end
+ end
+
+ // LOCK BIT COMMAND
+
+ `LBSetupCmd : begin
+ if ( (WriteSuspended == `TRUE) || (EraseSuspended == `TRUE) ) begin
+ $display("Attempted to set lock-bit while suspended");
+ CmdValid <= `FALSE;
+ end
+ else begin
+ WriteToPtr = `CmdField ;
+ DataPtr <= 1 ;
+ Cmd [`OpType] = `Lock ;
+ end
+ end
+
+ default : begin // The remaining commands are complex
+ // non-algorithm commands
+ Other = `FALSE ;
+ CmdValid = `FALSE ;
+
+ // CLEAR STATUS REGISTER COMMAND
+
+ if (Cmd [`Cmd] == `ClearCSRCmd) begin
+ if (EraseSuspended | WriteSuspended)
+ ReadMode <= `rdARRAY ;
+ else if (ReadyBusy == `Busy)
+ ReadMode <= `rdCSR ;
+ else begin
+ Erase_ClearLBError <= `FALSE ;
+ Program_SetLBError <= `FALSE ;
+ VppError <= `FALSE ;
+ Protected <= `FALSE;
+ ReadMode <= `rdCSR ;
+ end
+ end
+
+ // RESUME COMMAND --
+
+ else if (Cmd [`Cmd] == `ResumeCmd) begin
+ if (WriteSuspended | EraseSuspended)
+ ReadMode <= `rdCSR ;
+ Suspend = `FALSE ;
+ if (ToBeSuspended == `Program)
+ WriteSuspended <= `FALSE ;
+ else
+ EraseSuspended <= `FALSE ;
+ ReadyBusy = `Busy;
+ end
+
+ // SUSPEND COMMAND --
+
+ else if (Cmd [`Cmd] == `SuspendCmd) begin
+ if (ReadyBusy == `Ready) begin
+ ReadMode <= `rdARRAY ;
+ $display("Algorithm finished; nothing to suspend");
+ end
+ else begin
+ ReadMode <= `rdCSR ;
+ Suspend = `TRUE ;
+ end
+ CmdValid <= `FALSE ;
+ end
+ else begin
+ CmdValid <= `FALSE ;
+ $display("Warning:Illegal Command");
+ end
+ end //default
+ endcase
+ end //default
+ endcase
+ end //if
+ end //always (predecode)
+
+ //
+ // Command Decode
+ //
+
+ always @(DataPtr) begin : command
+
+ integer BlockUsed;
+
+ if (!Reset && (DataPtr == 0) && (WriteToPtr != `NewCmd)) begin
+ // When DataPtr hits zero it means that all the
+ // additional data has been given to the current command
+ if (CmdValid && (WriteToPtr == `CmdField)) begin
+ WriteToPtr = `NewCmd;
+ // Just finish a multi-cycle command. Determine which block the command uses
+ BlockUsed = -1;
+ for (LoopCntr = `NumberOfBlocks-1; LoopCntr >= 0; LoopCntr =
+ LoopCntr - 1) begin
+ if (Cmd[`CmdAdd_1] <= BlocksEnd[LoopCntr])
+ BlockUsed = LoopCntr;
+ end
+ if (BlockUsed == -1)
+ $display("Error: Invalid Command Address");
+ else
+ Cmd [`OpBlock] = BlockUsed;
+ if (Cmd [`OpType] == `Erase )
+ Cmd [`Time] = Block_Erase_Time ;
+ else if (Cmd [`OpType] == `Program )
+ Cmd [`Time] = Program_Time_Byte;
+ else
+ Cmd [`Time] = 0;
+
+ // If this command needs a confirm
+ // (flaged at predecode) then check if confirm was received
+ if (Cmd [`Confirm]) begin
+ if (Cmd[`CmdData_1] == `ConfirmCmd) begin
+ // If the command is still valid put it in the queue and deactivate the array
+ Algorithm = Cmd;
+ AlgTime = Cmd [`Time] ;
+ CmdValid <= `FALSE;
+ if (!VppError)
+ ReadyBusy <= #1 `Busy ;
+ ReadMode <= `rdCSR;
+ end
+ else begin
+ ReadMode <= `rdCSR ;
+ Program_SetLBError <= `TRUE;
+ Erase_ClearLBError <= `TRUE;
+ CmdValid <= `FALSE;
+ end
+ end
+ else begin
+ Algorithm = Cmd;
+ AlgTime = Cmd [`Time] ;
+ CmdValid <= `FALSE;
+ if (!VppError)
+ ReadyBusy <= #1 `Busy ;
+ ReadMode <= `rdCSR;
+ end
+ end
+ end
+ end //always (command)
+
+ ///////////////
+ // Execution //
+ ///////////////
+ always @(posedge AlgDone) begin : execution
+ reg [`Byte] temp ; // temporary variable needed for double indexing BSR.
+ if (!Reset) begin
+ if (AlgDone) begin // When the algorithm finishes
+ // if chips is executing during an erase interrupt
+ // then execute out of queue slot 2
+ if (Algorithm [`OpType] == `Erase) begin
+
+ // ERASE COMMAND //
+ if (VppFlag) begin
+ $display("Vpp Error occured");
+ VppError <= `TRUE ;
+ Erase_ClearLBError <= `TRUE;
+ end
+ else begin
+ // Do ERASE to OpBlock
+ if ((BlockLockBit[Algorithm[`OpBlock]] == `Locked)
+ && (rpblevel != `rpb_vhh)) begin
+ $display("Error: Attempted to erase locked block");
+ Erase_ClearLBError <= `TRUE;
+ Protected <= `TRUE;
+ end
+ else begin
+ for (LoopCntr = BlocksBegin[Algorithm[`OpBlock]];
+ LoopCntr <= BlocksEnd[Algorithm[`OpBlock]]; LoopCntr
+ = LoopCntr + 1)
+ MainArray [LoopCntr] = 'hFF ;
+ BlocksEraseCount[Algorithm[`OpBlock]] =
+ BlocksEraseCount[Algorithm[
+ `OpBlock]] + 1;
+ $display("Block %d Erase Count: %d", Algorithm[`OpBlock],
+ BlocksEraseCount[Algorithm[`OpBlock]]);
+ end
+ end
+ end //ERASE COMMAND
+ else if (Algorithm [`OpType] == `Program) begin
+
+ // PROGRAM COMMAND //
+ $display("PROGRAM COMMAND:");
+ $display(" VppFlag=", VppFlag);
+ $display(" BlockLockBit=", BlockLockBit [Algorithm[`OpBlock]]);
+ $display(" rpblevel=",rpblevel);
+
+ if (VppFlag) begin
+ $display("VppFlag set, do program of byte aborted!");
+ Program_SetLBError <= `TRUE;
+ VppError <= `TRUE ;
+ end
+ else begin
+ if ((BlockLockBit [Algorithm[`OpBlock]] == `Locked)
+ && (rpblevel != `rpb_vhh)) begin
+ $display("Error: Attempted to program locked block.");
+ Program_SetLBError <= `TRUE;
+ Protected <= `TRUE;
+ end
+ else begin
+ $display("calling program task");
+ Program (MainArray[Algorithm [`CmdAdd_1]], Algorithm [`CmdData_1])
+ ;
+ if (EraseSuspended == `TRUE) begin
+ AlgTime = TimeLeft;
+ ToBeSuspended = `Erase;
+ Algorithm = SuspendedAlg;
+ end
+ end
+ end
+ end // PROGRAM COMMAND
+ else if (Algorithm [`OpType] == `Lock) begin
+
+ // LOCK BIT COMMANDS
+
+ if (Algorithm [`CmdData_1] == `SetBlockLBCmd) begin
+ if ( ((MasterLock == `Locked) && (rpblevel != `rpb_vhh)) ||
+ ((rpblevel != `rpb_vih) && (rpblevel != `rpb_vhh)) ) begin
+ Program_SetLBError = `TRUE;
+ Protected = `TRUE;
+ $display("Attempted to set locked block lock-bit");
+ end
+ else begin
+ #Set_LockBit_Time
+ BlockLockBit [Algorithm[`OpBlock]] = `Locked;
+ end
+ end
+ else if (Algorithm [`CmdData_1] == `SetMasterLBCmd) begin
+ if (rpblevel == `rpb_vhh)
+ MasterLock = `Locked;
+ else begin
+ Program_SetLBError = `TRUE;
+ Protected = `TRUE;
+ $display("Attempted to set master lock-bit with invalid RP# level");
+ end
+ end //SetMasterLBCmd
+ else if (Algorithm [`CmdData_1] == `ClearLBCmd) begin
+ if ( ((MasterLock == `Locked) && (rpblevel != `rpb_vhh)) ||
+ ((rpblevel != `rpb_vih) && (rpblevel != `rpb_vhh)) ) begin
+ Erase_ClearLBError = `TRUE;
+ Protected = `TRUE;
+ $display("Attempted to clear lock-bits while master lock-bit set");
+ end
+ else begin
+ #Clear_LockBit_Time
+ for (LoopCntr = 0; LoopCntr < `NumberOfBlocks; LoopCntr = LoopCntr + 1) begin
+ BlockLockBit[LoopCntr] = `Unlocked;
+ end
+ end
+ end //ClearLBCmd
+ else begin
+ $display("Invalid lock-bit configuration command sequence");
+ Erase_ClearLBError = `TRUE;
+ Program_SetLBError = `TRUE;
+ end
+ end //LOCK BIT COMMANDS
+ else
+ $display("Invalid algorithm operation type");
+ end //if (AlgDone)
+ ReadyBusy <= `Ready ;
+ end //if (!Reset)
+ end //always (execution)
+
+ always @(ReadyBusy) begin
+ if ((!Reset) && (ReadyBusy == `Busy)) begin // If the algorithm engine
+ // just started, start the clock
+
+ ClearVppFlag <= #1 `TRUE ;
+ ClearVppFlag <= #3 `FALSE ;
+ TimerClk <= #1 1'b1 ;
+ TimerClk <= #TimerPeriod 1'b0 ;
+ end
+ end
+
+ // record the time for addr changes from ADDR change to posedge CEB.
+ always @(addr or posedge ceb) begin
+ if ($time != 0 & flash_cycle & ceb) begin
+ if ((curr_addr_time + TAVAV) > $time) //Read/Write Cycle Time
+ $display("[",$time,"] Timing Violation: Read/Write Cycle Time (TAVAV), Last addr change: %d",curr_addr_time) ;
+ end
+ curr_addr_time = $time ;
+ flash_cycle = ~ceb;
+ end
+
+ // start of flash cycle
+ always @(negedge ceb) begin
+ flash_cycle = 1;
+ end
+
+ // record the time for oe changes .
+ always @(oeb) begin
+ if ($time != 0) begin
+ curr_oe_time = $time ;
+ end
+ end
+
+ // record the time for ce changes .
+ always @(ceb) begin
+ if ($time != 0) begin
+ curr_ce_time = $time ;
+ end
+ end
+
+ // record the time for rp changes .
+ always @(rpb) begin
+ if ($time != 0) begin
+ curr_rp_time = $time ;
+ end
+ end
+
+ // record the time for ReadMode changes .
+ always @(ReadMode) begin
+ if ($time != 0) begin
+ curr_ReadMode_time = $time ;
+ end
+ end
+
+ // record the time for Internal_RE changes .
+ always @(Internal_RE) begin
+ if ($time != 0) begin
+ curr_Internal_RE_time = $time ;
+ end
+ end
+
+ //always @(InternalBoot) begin
+ // InternalBoot_WE <= #TPHHWH InternalBoot;
+ //end
+
+ always @(TimerClk) begin
+ if ((!Reset) && (ReadyBusy == `Busy) && (TimerClk == 1'b0)) begin
+ // Reschedule clock and decrement algorithm count
+ TimerClk <= #1 1'b1 ;
+ TimerClk <= #TimerPeriod 1'b0 ;
+ if (Suspend) begin // Is the chip pending suspend? If so do it
+ Suspend = `FALSE;
+ if (ToBeSuspended == `Program) begin
+ WriteSuspended <= #Program_Suspend_Time `TRUE;
+ ReadyBusy <= #Program_Suspend_Time `Ready;
+ end
+ else begin
+ EraseSuspended <= #Erase_Suspend_Time `TRUE;
+ ReadyBusy <= #Erase_Suspend_Time `Ready;
+ end
+ end
+ if (ReadyBusy == `Busy) begin
+ AlgTime = AlgTime - 1;
+ if (AlgTime <= 0) begin // Check if the algorithm is done
+ AlgDone <= #1 `TRUE ;
+ AlgDone <= #10 `FALSE ;
+ end
+ end
+ end
+ end
+
+ //------------------------------------------------------------------------
+ // Reset Controller
+ //------------------------------------------------------------------------
+
+ always @(rpb or vcc) begin : ResetPowerdownMonitor
+ // Go into reset if reset powerdown pin is active or
+ // the vcc is too low
+ if ((rpb != `VIH) || (vcc < 2500)) begin // Low Vcc protection
+ Reset <= `TRUE ;
+ if (!((vcc >= 2500) || StartUpFlag))
+ $display ("Low Vcc: Chip Resetting") ;
+ end
+ else
+ // Coming out of reset takes time
+ Reset <= #TPHWL `FALSE ;
+ end
+
+ //------------------------------------------------------------------------
+ // VccMonitor
+ //------------------------------------------------------------------------
+
+ always @(Reset or vcc) begin : VccMonitor
+ // Save the array when chip is powered off
+ if ($time > 0) begin
+ if (vcc == 0 && SaveOnPowerdown)
+ StoreToFile;
+ if (vcc < 2700)
+ $display("Vcc is below minimum operating specs");
+ else if ((vcc >= 2700) && (vcc <= 3600)) begin
+ if ((vcc >= 3000) && (vcc <= 3600) && (`VccLevels & `Vcc3300)) begin
+ $display ("Vcc is in operating range for 3.3 volt mode") ;
+ ReadOnly = `FALSE ;
+ TAVAV = 121 ;
+ TAVAV = `TAVAV_33 ;
+ TPHQV = `TPHQV_33 ;
+ TELQV = `TELQV_33 ;
+ TGLQV = `TGLQV_33 ;
+ TAVQV = `TAVQV_33 ;
+ TGLQX = `TGLQX_33 ;
+ TGHQZ = `TGHQZ_33 ;
+ TEHQZ = `TEHQZ_33 ;
+ TOH = `TOH_33 ;
+ TWPH = `TWPH_33 ;
+ TWP = `TWP_33 ;
+ TPHWL = `TPHWL_33 ;
+ TPHHWH = `TPHHWH_33;
+ TAVWH = `TAVWH_33 ;
+ TDVWH = `TDVWH_33 ;
+ TWHDX = `TWHDX_33 ;
+ TWHAX = `TWHAX_33 ;
+ TimerPeriod = `TimerPeriod_ ;
+ if ((vpp <= 3600) && (vpp >= 3000)) begin
+ $display ("Vpp is in operating range for 3.3 volt mode") ;
+ Block_Erase_Time = `AC_EraseTime_Block_33_33;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_33;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_33;
+ Set_LockBit_Time = `AC_Set_LockBit_33_33;
+ Program_Suspend_Time = `AC_Program_Suspend_33_33;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_33;
+ end
+ else if ((vpp <= 5500) && (vpp >= 4500)) begin
+ $display ("Vpp is in operating range for 5.0 volt mode") ;
+ Block_Erase_Time = `AC_EraseTime_Block_33_5;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_5;
+ Set_LockBit_Time = `AC_Set_LockBit_33_5;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_5;
+ Program_Suspend_Time = `AC_Program_Suspend_33_5;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_5;
+ end
+ else begin
+ $display ("Vpp is in operating range for 12.0 volt mode") ;
+ Block_Erase_Time = `AC_EraseTime_Block_33_12;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_12;
+ Set_LockBit_Time = `AC_Set_LockBit_33_12;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_12;
+ Program_Suspend_Time = `AC_Program_Suspend_33_12;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_12;
+ end
+ end
+ else if (`VccLevels & `Vcc2700) begin
+ $display ("Vcc is in operating range for 2.7 volt mode -- read only")
+ ;
+ ReadOnly = `TRUE ;
+ TAVAV = `TAVAV_27 ;
+ TPHQV = `TPHQV_27 ;
+ TELQV = `TELQV_27 ;
+ TGLQV = `TGLQV_27 ;
+ TAVQV = `TAVQV_27 ;
+ TGLQX = `TGLQX_27 ;
+ TGHQZ = `TGHQZ_27 ;
+ TEHQZ = `TEHQZ_27 ;
+ TOH = `TOH_27 ;
+ TWPH = `TWPH_27 ;
+ TWP = `TWP_27 ;
+ TPHWL = `TPHWL_27 ;
+ TPHHWH = `TPHHWH_27;
+ TAVWH = `TAVWH_27 ;
+ TDVWH = `TDVWH_27 ;
+ TWHDX = `TWHDX_27 ;
+ TWHAX = `TWHAX_27 ;
+ TimerPeriod = `TimerPeriod_ ;
+ end
+ else
+ $display("Invalid Vcc Level");
+ end
+ else if ((vcc >= 4500) && (vcc <= 5500) && (`VccLevels & `Vcc5000)) begin
+ $display ("Vcc is in operating range for 5 volt mode") ;
+ ReadOnly = `FALSE ;
+ TAVAV = `TAVAV_50 ;
+ TPHQV = `TPHQV_50 ;
+ TELQV = `TELQV_50 ;
+ TGLQV = `TGLQV_50 ;
+ TAVQV = `TAVQV_50 ;
+ TGLQX = `TGLQX_50 ;
+ TGHQZ = `TGHQZ_50 ;
+ TEHQZ = `TEHQZ_50 ;
+ TOH = `TOH_50 ;
+ TWPH = `TWPH_50 ;
+ TWP = `TWP_50 ;
+ TPHWL = `TPHWL_50 ;
+ TPHHWH = `TPHHWH_50;
+ TAVWH = `TAVWH_50 ;
+ TDVWH = `TDVWH_50 ;
+ TWHDX = `TWHDX_50 ;
+ TWHAX = `TWHAX_50 ;
+ TimerPeriod = `TimerPeriod_ ;
+ if ((vpp <= 5500) && (vpp >= 4500)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_50_5;
+ Program_Time_Byte = `AC_ProgramTime_Byte_50_5;
+ Set_LockBit_Time = `AC_Set_LockBit_50_5;
+ Clear_LockBit_Time = `AC_Clear_LockBit_50_5;
+ Program_Suspend_Time = `AC_Program_Suspend_50_5;
+ Erase_Suspend_Time = `AC_Erase_Suspend_50_5;
+ end
+ else begin
+ Block_Erase_Time = `AC_EraseTime_Block_50_12;
+ Program_Time_Byte = `AC_ProgramTime_Byte_50_12;
+ Set_LockBit_Time = `AC_Set_LockBit_50_12;
+ Clear_LockBit_Time = `AC_Clear_LockBit_50_12;
+ Program_Suspend_Time = `AC_Program_Suspend_50_12;
+ Erase_Suspend_Time = `AC_Erase_Suspend_50_12;
+ end
+ end
+ else
+ $display ("Vcc is out of operating range") ;
+ end //$time
+ end //always (VccMonitor)
+
+ //------------------------------------------------------------------------
+ // VppMonitor
+ //------------------------------------------------------------------------
+ always @(VppFlag or ClearVppFlag or vpp) begin : VppMonitor
+ if (ClearVppFlag) begin
+ VppErrFlag = `FALSE ;
+ end
+ else
+ if (!( ((vpp <= 12600) && (vpp >= 11400)) || ((vpp <= 5500) &&
+ (vpp >= 4500))
+ || ((vpp <= 3600) && (vpp >= 3000)))) begin
+ VppErrFlag = `TRUE ;
+ end
+ if ((vpp <= 3600) && (vpp >= 3000)) begin
+ if ((vcc <= 3600) && (vcc >= 3000)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_33_33;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_33;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_33;
+ Set_LockBit_Time = `AC_Set_LockBit_33_33;
+ Program_Suspend_Time = `AC_Program_Suspend_33_33;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_33;
+ end
+ else
+ VppErrFlag = `TRUE;
+ end
+ else if ((vpp <= 5500) && (vpp >= 4500)) begin
+ if ((vcc <= 3600) && (vcc >= 3000)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_33_5;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_5;
+ Set_LockBit_Time = `AC_Set_LockBit_33_5;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_5;
+ Program_Suspend_Time = `AC_Program_Suspend_33_5;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_5;
+ end
+ else if ((vcc <= 5500) && (vcc >= 4500)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_50_5;
+ Program_Time_Byte = `AC_ProgramTime_Byte_50_5;
+ Set_LockBit_Time = `AC_Set_LockBit_50_5;
+ Clear_LockBit_Time = `AC_Clear_LockBit_50_5;
+ Program_Suspend_Time = `AC_Program_Suspend_50_5;
+ Erase_Suspend_Time = `AC_Erase_Suspend_50_5;
+ end
+ else
+ VppErrFlag = `TRUE;
+ end
+ else begin
+ if ((vcc <= 3600) && (vcc >= 3000)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_33_12;
+ Program_Time_Byte = `AC_ProgramTime_Byte_33_12;
+ Set_LockBit_Time = `AC_Set_LockBit_33_12;
+ Clear_LockBit_Time = `AC_Clear_LockBit_33_12;
+ Program_Suspend_Time = `AC_Program_Suspend_33_12;
+ Erase_Suspend_Time = `AC_Erase_Suspend_33_12;
+ end
+ else if ((vcc <= 5500) && (vcc >= 4500)) begin
+ Block_Erase_Time = `AC_EraseTime_Block_50_12;
+ Program_Time_Byte = `AC_ProgramTime_Byte_50_12;
+ Set_LockBit_Time = `AC_Set_LockBit_50_12;
+ Clear_LockBit_Time = `AC_Clear_LockBit_50_12;
+ Program_Suspend_Time = `AC_Program_Suspend_50_12;
+ Erase_Suspend_Time = `AC_Erase_Suspend_50_12;
+ end
+ else
+ VppErrFlag = `TRUE;
+ end
+
+ VppFlag <= VppErrFlag;
+ end //always (VppMonitor)
+
+
+ always @(StartUpFlag or Internal_OE3) begin : OEMonitor
+ // This section generated DriveOutputs which is the main signal that
+ // controls the state of the output drivers
+
+ if (!StartUpFlag) begin
+ WriteRecovery = 0 ;
+ last_Internal_WE_time = $time - curr_Internal_WE_time;
+ if (Internal_OE) begin
+ TempTime = WriteRecovery + TGLQX ;
+ DriveOutputs = `FALSE ;
+ WriteRecovery = WriteRecovery + TGLQV -TempTime;
+ DriveOutputs <= #WriteRecovery `TRUE ;
+ end
+ else begin
+ InternalOutput <= #TOH `MaxOutputs'hx;
+ if (oeb == `VIH)
+ WriteRecovery = WriteRecovery + TGHQZ;
+ else
+ WriteRecovery = WriteRecovery + TEHQZ;
+ DriveOutputs <= #WriteRecovery `FALSE ;
+ end
+ end
+ else
+ DriveOutputs <= `FALSE ;
+ end
+
+ /////// Timing Checks /////////////
+
+ always @(Internal_WE) begin : Timing_chk
+
+ if ($time > 0) begin
+
+ // pulse chk
+ if (Internal_WE) begin
+ if ((($time - curr_Internal_WE_time) < TWPH) && (TWPH > 0 )) begin
+ $display("[",$time,"] Timing Violation: Internal Write Enable Insufficient High Time") ;
+ end
+ end
+ else begin
+ // WEb controlled write
+ if ((curr_Internal_WE_time - curr_ce_time) >= 10) begin
+ if ((vcc <= 5500) && (vcc >= 4500)) begin
+ if (($time - curr_Internal_WE_time) < (TWP - 10)) begin
+ $display("[",$time,"] Timing Violation: Internal Write Enable Insufficient Low Time");
+ end
+ end
+ else begin
+ if (($time - curr_Internal_WE_time) < (TWP - 20))begin
+ $display("[",$time,"] Timing Violation: Interanal Write Enable Insufficient Low Time");
+ end
+ end
+ end
+ // CEb controlled write
+ else begin
+ if ((($time - curr_Internal_WE_time) < TWP) && (TWP > 0 )) begin
+ $display("[",$time,"] Timing Violation: Internal Write Enable Insufficient Low Time") ;
+ end
+ end
+ end
+ curr_Internal_WE_time = $time ;
+
+ // timing_chk - addr
+ last_dq_time = $time - curr_dq_time;
+ last_rpb_time = $time - curr_rpb_time;
+ last_addr_time = $time - curr_addr_time;
+
+ if (Internal_WE == 0) begin
+ if ((last_addr_time < TAVWH) && (last_addr_time > 0))
+ $display("[",$time,"] Timing Violation: Address setup time during write, Last Event %d",last_addr_time) ;
+ if ((last_rpb_time < TPHWL) && (last_rpb_time > 0))
+ $display("[",$time,"] Timing Violation: Writing while coming out of powerdown, Last Event %d",last_rpb_time) ;
+ if ((last_dq_time < TDVWH) && (last_dq_time > 0))
+ $display("[",$time,"] Timing Violation: Data setup time during write, Last Event %d",last_dq_time) ;
+ end
+ end
+ end
+
+ always @(addr) begin
+ last_Internal_WE_time = $time - curr_Internal_WE_time;
+ if (($time > 0) && !Internal_WE) begin //timing chk
+ if ((last_Internal_WE_time < TWHAX) && (last_Internal_WE_time > 0))
+ $display("[",$time,"] Timing Violation:Address hold time after write, Last Event %d",last_Internal_WE_time) ;
+ end
+ end
+
+ always @(rpb) begin
+ if ($time > 0) begin
+ curr_rpb_time = $time ;
+ end
+ end
+
+ always @(dq) begin
+ curr_dq_time = $time ;
+ last_Internal_WE_time = $time - curr_Internal_WE_time;
+ if (($time > 0) && !Internal_WE) begin
+ if ((last_Internal_WE_time < TWHDX) && (last_Internal_WE_time > 0))
+ $display("[",$time,"] Timing Violation:Data hold time after write, Last Event %d",last_Internal_WE_time) ;
+ end
+ end
+
+ endmodule
Index: models/28f016s3/dp016s3.v
===================================================================
--- models/28f016s3/dp016s3.v (nonexistent)
+++ models/28f016s3/dp016s3.v (revision 1765)
@@ -0,0 +1,256 @@
+/*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+*/
+
+//************************************************************************
+// This file contains the paramenters which define the part for the
+// Byte-Wide Smart 3 FlashFile(tm) memory model (bwsvff.v). The '3.3V
+// Vcc Timing' parameters are representative of
+// the 3.3V Vcc 28F016S3-120. These parameters need to be changed if the
+// 3.3V Vcc 28F016S3-150 is to be modeled. The '2.7V Vcc Timing' parameters
+// are representative of the 2.7V Vcc 28F016S3-150. These parameters need
+// to be changed if the 2.7V Vcc 28F016S3-170 is to be modeled. The
+// parameters were taken from the Byte-Wide SmartVoltage FlashFile Memory
+// Family datasheet (Order Number 290598).
+
+// This file must be loaded before the main model, as it contains
+// definitions required by the model.
+
+//28F016S3
+
+`define BlockFileBegin "../../bench/models/28f016s3/28f016s3.bkb" //starting addresses of each block
+`define BlockFileEnd "../../bench/models/28f016s3/28f016s3.bke" //ending addresses of each block
+
+//Available Vcc supported by the device.
+`define VccLevels 1 //Bit 0 - 5V, Bit 1 = 3.3V, Bit 2 = 2.7V
+
+`define AddrSize 21 //number of address pins
+`define MaxAddr `AddrSize'h1FFFFF // device ending address
+`define MainArraySize 0:`MaxAddr //array definition in bytes
+ //include A-1 for 8 bit mode)
+`define MaxOutputs 8 //number of output pins
+`define NumberOfBlocks 32 //number of blocks in the array
+
+`define ID_DeviceCodeB 'hAA //016 S3
+`define ID_ManufacturerB 'h89
+
+// Timing parameters. See the data sheet for definition
+// of the parameter.
+
+//5V Vcc Timing
+`define TAVAV_50 95
+`define TAVQV_50 95
+`define TELQV_50 95
+`define TPHQV_50 400
+`define TGLQV_50 40
+`define TGLQX_50 0 //TELQX also
+`define TGHQZ_50 10
+`define TEHQZ_50 55
+`define TOH_50 0
+`define TPHHWH_50 100
+`define TAVWH_50 40
+`define TDVWH_50 40
+`define TPHWL_50 1
+`define TWPH_50 25 //TWHWL, TEHEL, TWHEL, TEHWL
+`define TWP_50 50 //TWLWH, TELEH, TWLEH, TELWH
+`define TWHDX_50 5
+`define TWHAX_50 5
+
+
+//3.3V Vcc Timing
+`define TAVAV_33 120
+`define TAVQV_33 120
+`define TELQV_33 120
+`define TPHQV_33 600
+`define TGLQV_33 50
+`define TGLQX_33 0 //TELQX also
+`define TGHQZ_33 15
+`define TEHQZ_33 55
+`define TOH_33 0
+`define TPHHWH_33 100
+`define TAVWH_33 50
+`define TDVWH_33 50
+`define TPHWL_33 1
+`define TWPH_33 25 //TWHWL, TEHEL, TWHEL, TEHWL
+`define TWP_33 70 //TWLWH, TELEH, TWLEH, TELWH
+`define TWHDX_33 5
+`define TWHAX_33 5
+
+//2.7V Vcc Timing
+`define TAVAV_27 150
+`define TAVQV_27 150
+`define TELQV_27 150
+`define TPHQV_27 600
+`define TGLQV_27 55
+`define TGLQX_27 0 //TELQX also
+`define TGHQZ_27 20
+`define TEHQZ_27 55
+`define TOH_27 0
+`define TPHHWH_27 100
+`define TAVWH_27 50
+`define TDVWH_27 50
+`define TPHWL_27 1
+`define TWPH_27 25 //TWHWL, TEHEL, TWHEL, TEHWL
+`define TWP_27 70 //TWLWH, TELEH, TWLEH, TELWH
+`define TWHDX_27 5
+`define TWHAX_27 5
+
+//The following constants control how long it take an algorithm to run
+
+// To scale all times together (for making simulation run faster)
+// change the constant later listed as TimerPeriod. The actual delays
+// are TimerPeriod*xxx_Time, except for suspend latency times.
+
+`define TimerPeriod_ 1000 //1 usec = 1000ns requires for
+ //following times to be accurate
+
+//reducing the following will reduce simulation time
+
+//the times used below are the maximum (or typical if no maximum
+//time is given) values from the data sheet
+
+//5V Vcc, 12V Vpp
+`define AC_ProgramTime_Byte_50_12 6 //usecs
+`define AC_EraseTime_Block_50_12 1000000 //1 sec
+`define AC_Set_LockBit_50_12 10 //usecs
+`define AC_Clear_LockBit_50_12 1000000 //1 sec
+ //Latency times are NOT multiplied by TimerPeriod_
+`define AC_Program_Suspend_50_12 5000 //usecs
+`define AC_Erase_Suspend_50_12 12000 //usecs
+
+//3.3V Vcc, 12V Vpp
+`define AC_ProgramTime_Byte_33_12 8 //usecs 7.6us
+`define AC_EraseTime_Block_33_12 1100000 //1.1secs
+`define AC_Set_LockBit_33_12 12 //usecs 11.6us
+`define AC_Clear_LockBit_33_12 1100000 //1.1 sec
+ //Latency times are NOT multiplied by TimerPeriod_
+`define AC_Program_Suspend_33_12 6000 //usecs
+`define AC_Erase_Suspend_33_12 12000 //usecs
+
+//5V Vcc, 5V Vpp
+`define AC_ProgramTime_Byte_50_5 8 //usecs
+`define AC_EraseTime_Block_50_5 1100000 //1.1secs
+`define AC_Set_LockBit_50_5 12 //usecs
+`define AC_Clear_LockBit_50_5 1100000 //1.1 sec
+ //Latency times are NOT multiplied by TimerPeriod_
+`define AC_Program_Suspend_50_5 6000 //usecs
+`define AC_Erase_Suspend_50_5 12000 //usecs
+
+//3.3V Vcc, 5V Vpp
+`define AC_ProgramTime_Byte_33_5 10 //usecs 9.3us
+`define AC_EraseTime_Block_33_5 1200000 //1.2secs
+`define AC_Set_LockBit_33_5 14 //usecs 13.3us
+`define AC_Clear_LockBit_33_5 1200000 //1.2 sec
+ //Latency times are NOT multiplied by TimerPeriod_
+`define AC_Program_Suspend_33_5 7000 //usecs
+`define AC_Erase_Suspend_33_5 12000 //usecs
+
+//3.3V Vcc, 3.3V Vpp
+`define AC_ProgramTime_Byte_33_33 17 //usecs
+`define AC_EraseTime_Block_33_33 1800000 //1.8secs
+`define AC_Set_LockBit_33_33 21 //usecs
+`define AC_Clear_LockBit_33_33 1800000 //1.8 sec
+ //Latency times are NOT multiplied by TimerPeriod_
+`define AC_Program_Suspend_33_33 7000 //usecs
+`define AC_Erase_Suspend_33_33 20000 //usecs
Index: models/28f016s3/28f016s3.bkb
===================================================================
--- models/28f016s3/28f016s3.bkb (nonexistent)
+++ models/28f016s3/28f016s3.bkb (revision 1765)
@@ -0,0 +1,143 @@
+/*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+*/
+
+// This file contains the starting address of each block
+// numbered from block 0 to nn. The addresses are in hex.
+// The block addresses were taken from the Byte-Wide
+// Smart 3 FlashFile(tm) Memory Family datasheet
+// (Order Number 290598).
+
+000000
+010000
+020000
+030000
+040000
+050000
+060000
+070000
+080000
+090000
+0A0000
+0B0000
+0C0000
+0D0000
+0E0000
+0F0000
+100000
+110000
+120000
+130000
+140000
+150000
+160000
+170000
+180000
+190000
+1A0000
+1B0000
+1C0000
+1D0000
+1E0000
+1F0000
\ No newline at end of file
models/28f016s3/28f016s3.bkb
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: models/28f016s3/test_bad.v
===================================================================
--- models/28f016s3/test_bad.v (nonexistent)
+++ models/28f016s3/test_bad.v (revision 1765)
@@ -0,0 +1,849 @@
+/*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+*/
+
+
+`timescale 1ns/1ns
+
+
+module test28F016SC();
+
+reg [`AddrSize-1:0] address;
+
+reg [31:0] vcc,
+ vpp;
+
+reg ceb,
+ oeb,
+ web,
+ rpb;
+
+wire ryby;
+
+reg [1:0] rpblevel; // 00 = VIL
+ // 01 = VIH
+ // 10 = VHH
+
+reg [`MaxOutputs-1:0] dq_reg;
+wire [`MaxOutputs-1:0] dq = dq_reg;
+
+IntelSVFF IFlash (dq, address, ceb, oeb, web, rpb, ryby, vpp, vcc, rpblevel);
+
+initial
+ begin
+// $dumpfile("f008sc.dmp");
+// $dumpoff;
+// $dumpvars(???,dq,address,ceb,oeb,web,rpb);
+
+ dq_reg = `MaxOutputs'hz;
+ rpblevel = `rpb_vil;
+ powerup;
+ ReadID;
+ #100
+ oeb = `VIH;
+
+ ProgramData(`AddrSize'h2FFFF, `MaxOutputs'hAA);
+ ProgramData(`AddrSize'h60000, `MaxOutputs'h06);
+
+ begin: WriteTest
+ $display("rdARRAY DURING WRITE TEST");
+ #100
+ StartProgram(`AddrSize'h00000, `MaxOutputs'h00);
+ #150
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #(((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)-1000)
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h2FFFF);
+ #100
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #500
+ oeb = `VIL;
+ #500
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h00000);
+ #100
+ ReadData(`AddrSize'h2FFFF);
+ #100
+ oeb = `VIH;
+ end //WriteTest
+
+ begin: WriteSuspend
+ $display("WRITE SUSPEND TEST");
+ #100
+ StartProgram(`AddrSize'h10000, `MaxOutputs'h01);
+ #150
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #(((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)-1000)
+ Suspend;
+ #100
+ ClearCSRMode;
+ #100
+ ReadCSRMode;
+ #100
+ oeb = `VIH;
+ #300
+ Resume;
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #500
+ oeb = `VIL;
+ #500
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h10000);
+ #100
+ oeb = `VIH;
+ end //WriteSuspend
+
+ $display("SET BLOCK LOCK-BITS");
+ #100
+ SetBlockLockBit(`AddrSize'h75000);
+ #100
+ oeb = `VIH;
+
+ $display("ERASE BLOCK");
+ #100
+ EraseBlock(`AddrSize'h7000F);
+
+ $display("READ DATA, Loose Timing, Toggle Addr");
+ #100
+ SetReadMode;
+ #100
+ oeb = `VIL;
+ #100
+ address = `AddrSize'h70000;
+ #100
+ address = `AddrSize'h7FFFF;
+ #100
+ oeb = `VIH;
+
+ begin: BadErase
+ $display("BAD ERASE TEST");
+ #100
+ address = `AddrSize'h60000;
+ #100
+ dq_reg = `EraseBlockCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ReadArrayCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #1000
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ end //BadErase
+ #200
+ ReadCSRMode;
+ #200
+ ClearCSRMode;
+ #200
+ ReadCSRMode;
+ #200
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h60000);
+ #100
+ oeb = `VIH;
+
+ begin : BadLockBit
+ $display("BAD LOCK-BIT SEQUENCE TEST");
+ #100
+ address = `AddrSize'h40000;
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'h55;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #((`AC_Set_LockBit_50_12*`TimerPeriod_)-5000);
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+
+ $display("LOW Vpp OPERATION TEST");
+ #100
+ vpp =1300;
+ #100
+ ProgramData(`AddrSize'h33333, `MaxOutputs'h33);
+ #100
+ EraseBlock(`AddrSize'h6F000);
+ #100
+ vpp = 12000;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h33333);
+ #100
+ address = `AddrSize'h60000;
+ #100
+ oeb = `VIH;
+
+ #1000
+ powerdown;
+ #1000 $finish;
+ end
+
+always @(dq or address or ceb or rpb or oeb or web or vcc or vpp or rpblevel)
+ begin
+ $display(
+ "%d Addr = %h, Data = %h, CEb=%b, RPb=%b, OEb=%b, WEb=%d, vcc=%d, vpp = %d",
+ $time, address, dq, ceb, rpb, oeb, web, vcc, vpp);
+ end
+
+task powerup;
+ begin
+ $display(" POWERUP TASK");
+ rpb = `VIL; //reset
+ #100
+ address = 0;
+ #100
+ web = `VIH; //write enable high
+ #100
+ oeb = `VIH; //output ts
+ #100
+ ceb = `VIH; //disabled
+ #100
+ vcc = 5000; //power up vcc
+ #5000
+ vpp = 12000; //ramp up vpp
+ #5000
+ rpb = `VIH; //out of reset
+ rpblevel = `rpb_vih;
+ #100
+ oeb = `VIL; //enable outputs
+ #100
+ ceb = `VIL; //enable chip
+ end
+endtask
+
+
+task powerdown;
+ begin
+ $display(" POWERDOWN TASK");
+ address = 0;
+ #100
+ rpb = `VIL; //reset
+ #100
+ oeb = `VIH; //output ts
+ #100
+ web = `VIH; //we high
+ #100
+ ceb = `VIH; //disabled
+ #100
+ vpp = 0; //power down vpp
+ #5000
+ vcc = 0; //ramp down vcc
+ end
+endtask
+
+
+task ReadData;
+ input [`AddrSize-1:0] addr;
+
+ begin
+ $display(" READDATA TASK");
+ oeb = `VIH;
+ #100
+ address = addr;
+ #100
+ oeb = `VIL;
+ end
+endtask
+
+
+task SetReadMode;
+ begin
+ $display(" SETREADMODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ReadArrayCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ReadID;
+ begin
+ $display(" READID TASK");
+ oeb = `VIH;
+ #100
+ address = `AddrSize'h0;
+ #100
+ dq_reg[`Byte] = `ReadIDCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #100
+ address = `AddrSize'h1;
+ #100
+ address = `AddrSize'h3;
+ #100
+ address = `AddrSize'h2;
+ #100
+ address = `AddrSize'h10002;
+ end
+endtask
+
+
+task ReadCSRMode;
+ begin
+ $display(" READCSR MODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ReadCSRCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ end
+endtask
+
+
+task ClearCSRMode;
+ begin
+ $display(" CLEARCSRMODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ClearCSRCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task StartProgram;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" STARTPROGRAM TASK");
+ #100
+ address = addr;
+ #100
+ dq_reg[`Byte] = `Program2Cmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg[`Byte] = data;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ProgramData;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" PROGRAMDATA TASK");
+ StartProgram(addr, data);
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12*`TimerPeriod_)-500)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartProgram2;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" STARTPROGRAM2 TASK");
+ #100
+ address = addr;
+ #100
+ dq_reg[`Byte] = `Program2Cmd;
+ #100
+ web = `VIL;
+ #5
+ ceb = `VIL;
+ #100
+ ceb = `VIH;
+ #5
+ web = `VIH;
+ #100
+ dq_reg[`Byte] = data;
+ #100
+ web = `VIL;
+ #5
+ ceb = `VIL;
+ #100
+ ceb = `VIH;
+ #5
+ web = `VIH;
+ #100
+ ceb = `VIL;
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ProgramData2;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" PROGRAMDATA2 TASK");
+ ceb = `VIH;
+ StartProgram2(addr, data);
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12*`TimerPeriod_)-500)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+task StartErase;
+ input [`AddrSize-1:0] BlockAddr;
+ begin
+ $display(" STARTERASE TASK");
+ #100
+ address = BlockAddr;
+ #100
+ dq_reg = `EraseBlockCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ConfirmCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task EraseBlock;
+ input [`AddrSize-1:0] BlockAddr;
+ time EraseTime;
+ begin
+ $display(" ERASEBLOCK TASK");
+ StartErase(BlockAddr);
+ #100
+ oeb = `VIL;
+ EraseTime = ((`AC_EraseTime_Block_50_12*`TimerPeriod_)-5000);
+ #EraseTime
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartLockBit;
+ input [`AddrSize-1:0] BlockAddr;
+ begin
+ $display(" STARTLOCKBIT TASK");
+ #100
+ address = BlockAddr;
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `SetBlockLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task SetBlockLockBit;
+ input [`AddrSize-1:0] BlockAddr;
+ time LockBitTime;
+ begin
+ $display(" SETBLOCKLOCKBIT TASK");
+ StartLockBit(BlockAddr);
+ #100
+ oeb = `VIL;
+ LockBitTime = ((`AC_Set_LockBit_50_12*`TimerPeriod_)-5000);
+ #LockBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartClearBit;
+ begin
+ $display(" STARTCLEARBIT TASK");
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ClearLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ClearBlockLockBit;
+ time ClearBitTime;
+ begin
+ $display(" CLEARBLOCKLOCKBIT TASK");
+ StartClearBit;
+
+ #100
+ oeb = `VIL;
+ ClearBitTime = ((`AC_Clear_LockBit_50_12*`TimerPeriod_)-5000);
+ #ClearBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task SetMasterLockBit;
+ input [`AddrSize-1:0] DeviceAddr;
+ time LockBitTime;
+ begin
+ $display(" SETMASTERLOCKBIT TASK");
+ #100
+ address = DeviceAddr;
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `SetMasterLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ LockBitTime = ((`AC_Set_LockBit_50_12*`TimerPeriod_)-5000);
+ #LockBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+task Suspend;
+ begin
+ $display(" SUSPEND TASK");
+ #100
+ dq_reg = `SuspendCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #500
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ end
+endtask
+
+
+task Resume;
+ begin
+ $display(" RESUME TASK");
+ #100
+ dq_reg = `ResumeCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+endmodule
Index: models/28f016s3/test1s3.v
===================================================================
--- models/28f016s3/test1s3.v (nonexistent)
+++ models/28f016s3/test1s3.v (revision 1765)
@@ -0,0 +1,1068 @@
+/*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+*/
+
+
+`timescale 1ns/1ns
+
+
+module test28F016SC();
+
+reg [`AddrSize-1:0] address;
+
+reg [31:0] vcc,
+ vpp;
+
+reg ceb,
+ oeb,
+ web,
+ rpb;
+
+wire ryby;
+
+reg [1:0] rpblevel; // 00 = VIL
+ // 01 = VIH
+ // 10 = VHH
+
+reg [`MaxOutputs-1:0] dq_reg;
+wire [`MaxOutputs-1:0] dq = dq_reg;
+
+i28f016s3 IFlash (dq, address, ceb, oeb, web, rpb, ryby, vpp, vcc, rpblevel);
+
+initial
+ begin
+// $dumpfile("f008sc.dmp");
+// $dumpoff;
+// $dumpvars(???,dq,address,ceb,oeb,web,rpb);
+
+ dq_reg = `MaxOutputs'hz;
+ rpblevel = `rpb_vil;
+ powerup;
+ ReadID;
+ //Verify READS with loose timing (OE Toggling)
+ #100
+ SetReadMode;
+
+ $display("READ DATA, Loose Timing, toggle OE");
+ #100
+ ReadData(`AddrSize'h0);
+ #100
+ ReadData(`AddrSize'h10000);
+ #100
+ ReadData(`AddrSize'h1F0000);
+ #100
+ ReadData(`AddrSize'h1FFFFF);
+
+ $display("READ DATA, Loose Timing, toggle Addr");
+ //Verify Reads (OE LOW)
+ #100
+ address = `AddrSize'h3FFFF;
+ #100
+ address = `AddrSize'h4FFFF;
+ #100
+ address = `AddrSize'h5FFFF;
+ #100
+ oeb = `VIH;
+
+ $display("SET BLOCK LOCK-BITS");
+ #100
+ SetBlockLockBit(`AddrSize'h000000);
+ #100
+ SetBlockLockBit(`AddrSize'h010000);
+ #100
+ SetBlockLockBit(`AddrSize'h1F0000);
+ #100
+ ReadID;
+ #100
+ oeb = `VIH;
+
+ #100
+ $display("PROGRAM DATA, Loose Timing, Block Locked");
+ #100
+ ProgramData(`AddrSize'h000000, `MaxOutputs'h00);
+ #100
+ ProgramData(`AddrSize'h010000, `MaxOutputs'h01);
+ #100
+ ProgramData(`AddrSize'h1F0000, `MaxOutputs'h0F);
+ #100
+ ProgramData(`AddrSize'h1FFFFF, `MaxOutputs'h10);
+ #100
+ SetReadMode;
+ $display("READ DATA, Loose Timing, toggle OE");
+ #100
+ ReadData(`AddrSize'h000000);
+ #100
+ ReadData(`AddrSize'h010000);
+ $display("READ DATA, Loose Timing, toggle Addr");
+ //Verify Reads (OE LOW)
+ #100
+ address = `AddrSize'h1F0000;
+ #100
+ address = `AddrSize'h1FFFFF;
+ #100
+ oeb = `VIH;
+ $display("BLOCK LOCK-BIT OVERRIDE");
+ #100
+ rpblevel = `rpb_vhh;
+ #100
+ ProgramData(`AddrSize'h000000, `MaxOutputs'h00);
+ #100
+ rpblevel = `rpb_vih;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h000000);
+ #100
+ oeb = `VIH;
+
+ $display("CLEAR BLOCK LOCK-BITS");
+ #100
+ ClearBlockLockBit;
+ $display("PROGRAM DATA, Boot Unlocked");
+ #100
+ ProgramData(`AddrSize'h015000, `MaxOutputs'h51);
+ #100
+ ProgramData(`AddrSize'h015FFF, `MaxOutputs'h22);
+ #100
+ ProgramData(`AddrSize'h020000, `MaxOutputs'h02);
+ #100
+ ProgramData(`AddrSize'h04FFFF, `MaxOutputs'h11);
+ #100
+ ProgramData(`AddrSize'h050001, `MaxOutputs'h12);
+ #100
+ ProgramData(`AddrSize'h060000, `MaxOutputs'h06);
+ #100
+ ProgramData(`AddrSize'h06FFFF, `MaxOutputs'hF6);
+ #100
+ ProgramData(`AddrSize'h1F0000, `MaxOutputs'hAA);
+ #100
+ ProgramData2(`AddrSize'h1FFFFF, `MaxOutputs'h55);
+
+ $display("READ DATA, Loose Timing, Toggle OE");
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h015000);
+ #100
+ address = `AddrSize'h1F0000;
+ #100
+ address = `AddrSize'h1FFFFF;
+ #100
+ address = `AddrSize'h020000;
+ #100
+ address = `AddrSize'h0F0000;
+ #100
+ address = `AddrSize'h0FFFFF;
+ #100
+ oeb = `VIH;
+ $display("ERASE BLOCK");
+ #100
+ EraseBlock(`AddrSize'h1F000F);
+ $display("READ DATA, Loose Timing, Toggle Addr");
+ #100
+ SetReadMode;
+ #100
+ oeb = `VIL;
+ #100
+ address = `AddrSize'h1F0000;
+ #100
+ address = `AddrSize'h1FFFFF;
+ #100
+ address = `AddrSize'h015000;
+ #100
+ oeb = `VIH;
+ begin: WriteSuspend
+ $display("WRITE SUSPEND TEST");
+ #100
+ StartProgram(`AddrSize'h050000, `MaxOutputs'h05);
+ #150
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #(((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)-1000)
+ Suspend;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h04FFFF);
+ #100
+ ReadData(`AddrSize'h050000);
+ #100
+ ReadData(`AddrSize'h050001);
+ #100
+ oeb = `VIH;
+ #100
+ StartProgram(`AddrSize'h0AA000, `MaxOutputs'h66);
+ #300
+ Resume;
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #500
+ oeb = `VIL;
+ #500
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h050001);
+ #100
+ ReadData(`AddrSize'h050000);
+ #100
+ ReadData(`AddrSize'h0AA000);
+ #100
+ oeb = `VIH;
+ end //WriteSuspend
+ begin: BadErase
+ $display("BAD ERASE TEST");
+ #100
+ address = `AddrSize'h060000;
+ #100
+ dq_reg = `EraseBlockCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ReadArrayCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #1000
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ end //BadErase
+ #200
+ ReadCSRMode;
+ #200
+ ClearCSRMode;
+ #200
+ ReadCSRMode;
+ #200
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h060000);
+ #100
+ ReadData(`AddrSize'h06FFFF);
+ #100
+ oeb = `VIH;
+ begin: EraseSuspend
+ $display("ERASE SUSPEND TEST");
+ #100
+ StartErase(`AddrSize'h015000);
+ #1000
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #(((`AC_EraseTime_Block_50_12/2)*`TimerPeriod_)-1000)
+ Suspend;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h020000);
+ #100
+ ReadData(`AddrSize'h015FFF);
+ #100
+ oeb = `VIH;
+ #300
+ Resume;
+ #100
+ oeb = `VIL;
+ #(((`AC_EraseTime_Block_50_12/2)*`TimerPeriod_)-1000)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h010000);
+ #100
+ ReadData(`AddrSize'h015FFF);
+ #100
+ ReadData(`AddrSize'h020000);
+ #100
+ oeb = `VIH;
+ end //EraseSuspend
+ #300
+ $display("Embedded Suspend Mode");
+ begin: EraseSuspend_
+ #100
+ StartErase(`AddrSize'h065000);
+ #1000
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #(((`AC_EraseTime_Block_50_12/2)*`TimerPeriod_)-1000)
+ Suspend;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h050000);
+ #100
+ oeb = `VIH;
+ begin: WriteSuspend_
+ $display("EMBEDDED WRITE SUSPEND TEST");
+ #100
+ StartProgram(`AddrSize'h0FFFFF, `MaxOutputs'h77);
+ #150
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ oeb = `VIH;
+ #((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)
+ Suspend;
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h050001);
+ #100
+ ReadData(`AddrSize'h060000);
+ #100
+ oeb = `VIH;
+ #300
+ Resume; //Write Operation
+ #100
+ oeb = `VIL;
+ #500
+// #((`AC_ProgramTime_Byte_50_12/2)*`TimerPeriod_)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #500
+ oeb = `VIL;
+ #500
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h0FFFFF);
+ #100
+ oeb = `VIH;
+ end //WriteSuspend_
+ #300
+ Resume; //Erase Operation
+ #100
+ oeb = `VIL;
+ #(((`AC_EraseTime_Block_50_12/2)*`TimerPeriod_)-1000)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h06FFFF);
+ #100
+ ReadData(`AddrSize'h060000);
+ #100
+ ReadData(`AddrSize'h050000);
+ #100
+ oeb = `VIH;
+ end //EraseSuspend_
+ begin: MasterLockBitTest
+ $display("MASTER LOCK-BIT TEST");
+ SetMasterLockBit(`AddrSize'h0);
+ #100
+ rpblevel = `rpb_vhh;
+ #100
+ SetMasterLockBit(`AddrSize'h0);
+ #100
+ rpblevel = `rpb_vih;
+ #100
+ SetBlockLockBit(`AddrSize'h090000);
+ #100
+ rpblevel = `rpb_vhh;
+ #100
+ SetBlockLockBit(`AddrSize'h080000);
+ #100
+ SetBlockLockBit(`AddrSize'h070000);
+ #100
+ rpblevel = `rpb_vih;
+ #100
+ ProgramData(`AddrSize'h090000, `MaxOutputs'h09);
+ #100
+ ProgramData(`AddrSize'h080000, `MaxOutputs'h08);
+ #100
+ ProgramData(`AddrSize'h070000, `MaxOutputs'h07);
+ #200
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h070000);
+ #100
+ ReadData(`AddrSize'h080000);
+ #100
+ ReadData(`AddrSize'h090000);
+ #100
+ oeb = `VIH;
+ #100
+ ClearBlockLockBit;
+ #100
+ rpblevel = `rpb_vhh;
+ #100
+ ClearBlockLockBit;
+ #100
+ rpblevel = `rpb_vih;
+ #100
+ ProgramData(`AddrSize'h080000, `MaxOutputs'h08);
+ #100
+ ProgramData(`AddrSize'h070000, `MaxOutputs'h07);
+ #100
+ SetReadMode;
+ #100
+ ReadData(`AddrSize'h070000);
+ #100
+ ReadData(`AddrSize'h080000);
+ #100
+ oeb = `VIH;
+ end
+ #100
+ vcc = 3450;
+ #100
+ ReadData(`AddrSize'h000000);
+ #100
+ ReadData(`AddrSize'h0FFFFF);
+ #1000
+ powerdown;
+ #1000 $finish;
+ end
+
+always @(dq or address or ceb or rpb or oeb or web or vcc or vpp or rpblevel)
+ begin
+ $display(
+ "%d Addr = %h, Data = %h, CEb=%b, RPb=%b, OEb=%b, WEb=%d, vcc=%d, vpp = %d",
+ $time, address, dq, ceb, rpb, oeb, web, vcc, vpp);
+ end
+
+task powerup;
+ begin
+ $display(" POWERUP TASK");
+ rpb = `VIL; //reset
+ #100
+ address = 0;
+ #100
+ web = `VIH; //write enable high
+ #100
+ oeb = `VIH; //output ts
+ #100
+ ceb = `VIH; //disabled
+ #100
+ vcc = 5000; //power up vcc
+ #5000
+ vpp = 12000; //ramp up vpp
+ #5000
+ rpb = `VIH; //out of reset
+ rpblevel = `rpb_vih;
+ #100
+ oeb = `VIL; //enable outputs
+ #100
+ ceb = `VIL; //enable chip
+ end
+endtask
+
+
+task powerdown;
+ begin
+ $display(" POWERDOWN TASK");
+ address = 0;
+ #100
+ rpb = `VIL; //reset
+ #100
+ oeb = `VIH; //output ts
+ #100
+ web = `VIH; //we high
+ #100
+ ceb = `VIH; //disabled
+ #100
+ vpp = 0; //power down vpp
+ #5000
+ vcc = 0; //ramp down vcc
+ end
+endtask
+
+
+task ReadData;
+ input [`AddrSize-1:0] addr;
+
+ begin
+ $display(" READDATA TASK");
+ oeb = `VIH;
+ #100
+ address = addr;
+ #100
+ oeb = `VIL;
+ end
+endtask
+
+
+task SetReadMode;
+ begin
+ $display(" SETREADMODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ReadArrayCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ReadID;
+ begin
+ $display(" READID TASK");
+ oeb = `VIH;
+ #100
+ address = `AddrSize'h0;
+ #100
+ dq_reg[`Byte] = `ReadIDCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #100
+ address = `AddrSize'h1;
+ #100
+ address = `AddrSize'h3;
+ #100
+ address = `AddrSize'h2;
+ #100
+ address = `AddrSize'h10002;
+ end
+endtask
+
+
+task ReadCSRMode;
+ begin
+ $display(" READCSR MODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ReadCSRCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ end
+endtask
+
+
+task ClearCSRMode;
+ begin
+ $display(" CLEARCSRMODE TASK");
+ oeb = `VIH;
+ #100
+ dq_reg[`Byte] = `ClearCSRCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task StartProgram;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" STARTPROGRAM TASK");
+ #100
+ address = addr;
+ #100
+ dq_reg[`Byte] = `Program2Cmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg[`Byte] = data;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ProgramData;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" PROGRAMDATA TASK");
+ StartProgram(addr, data);
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12*`TimerPeriod_)-500)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartProgram2;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" STARTPROGRAM2 TASK");
+ #100
+ address = addr;
+ #100
+ dq_reg[`Byte] = `Program2Cmd;
+ #100
+ web = `VIL;
+ #5
+ ceb = `VIL;
+ #100
+ ceb = `VIH;
+ #5
+ web = `VIH;
+ #100
+ dq_reg[`Byte] = data;
+ #100
+ web = `VIL;
+ #5
+ ceb = `VIL;
+ #100
+ ceb = `VIH;
+ #5
+ web = `VIH;
+ #100
+ ceb = `VIL;
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ProgramData2;
+ input [`AddrSize-1:0] addr;
+ input [`MaxOutputs-1:0] data;
+ begin
+ $display(" PROGRAMDATA2 TASK");
+ ceb = `VIH;
+ StartProgram2(addr, data);
+ #100
+ oeb = `VIL;
+ #((`AC_ProgramTime_Byte_50_12*`TimerPeriod_)-500)
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+task StartErase;
+ input [`AddrSize-1:0] BlockAddr;
+ begin
+ $display(" STARTERASE TASK");
+ #100
+ address = BlockAddr;
+ #100
+ dq_reg = `EraseBlockCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ConfirmCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task EraseBlock;
+ input [`AddrSize-1:0] BlockAddr;
+ time EraseTime;
+ begin
+ $display(" ERASEBLOCK TASK");
+ StartErase(BlockAddr);
+ #100
+ oeb = `VIL;
+ EraseTime = ((`AC_EraseTime_Block_50_12*`TimerPeriod_)-5000);
+ #EraseTime
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartLockBit;
+ input [`AddrSize-1:0] BlockAddr;
+ begin
+ $display(" STARTLOCKBIT TASK");
+ #100
+ address = BlockAddr;
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `SetBlockLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task SetBlockLockBit;
+ input [`AddrSize-1:0] BlockAddr;
+ time LockBitTime;
+ begin
+ $display(" SETBLOCKLOCKBIT TASK");
+ StartLockBit(BlockAddr);
+ #100
+ oeb = `VIL;
+ LockBitTime = ((`AC_Set_LockBit_50_12*`TimerPeriod_)-5000);
+ #LockBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task StartClearBit;
+ begin
+ $display(" STARTCLEARBIT TASK");
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `ClearLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+
+task ClearBlockLockBit;
+ time ClearBitTime;
+ begin
+ $display(" CLEARBLOCKLOCKBIT TASK");
+ StartClearBit;
+
+ #100
+ oeb = `VIL;
+ ClearBitTime = ((`AC_Clear_LockBit_50_12*`TimerPeriod_)-5000);
+ #ClearBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+
+task SetMasterLockBit;
+ input [`AddrSize-1:0] DeviceAddr;
+ time LockBitTime;
+ begin
+ $display(" SETMASTERLOCKBIT TASK");
+ #100
+ address = DeviceAddr;
+ #100
+ dq_reg = `LBSetupCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `SetMasterLBCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ LockBitTime = ((`AC_Set_LockBit_50_12*`TimerPeriod_)-5000);
+ #LockBitTime
+ begin : Poll
+ forever
+ begin
+ oeb = `VIH;
+ #1000
+ oeb = `VIL;
+ #1000
+ if (dq[7] == `VIH)
+ disable Poll;
+ end //forever
+ end //Poll
+ #300
+ ClearCSRMode;
+ end
+endtask
+
+task Suspend;
+ begin
+ $display(" SUSPEND TASK");
+ #100
+ dq_reg = `SuspendCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ #100
+ oeb = `VIL;
+ #500
+ begin: Poll
+ forever
+ begin
+ oeb = `VIH;
+ #100
+ oeb = `VIL;
+ #100
+ if (dq[7] == `VIH)
+ disable Poll;
+ end
+ end
+ end
+endtask
+
+
+task Resume;
+ begin
+ $display(" RESUME TASK");
+ #100
+ dq_reg = `ResumeCmd;
+ #100
+ web = `VIL;
+ #100
+ web = `VIH;
+ #100
+ dq_reg = `MaxOutputs'hz;
+ end
+endtask
+
+endmodule
Index: models/28f016s3/read.me
===================================================================
--- models/28f016s3/read.me (nonexistent)
+++ models/28f016s3/read.me (revision 1765)
@@ -0,0 +1,120 @@
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+
+Intel's Byte-Wide SmartVoltage FlashFile(tm) flash memory verilog models
+consist of 4 files. One file, "bwsvff.v", contains the basic model for
+the flash memory family. The other files depend upon the device being
+modeled. One file is used to parametize the model (dp*.v) for the specific
+device. This file will call out other files to be loaded which include:
+
+ *.bkb block beginning addresses
+ *.bke block ending addresses
+
+The parameterization file must be loaded into the simulator before the main
+model file "bwsvff.v" as it contains definitions required for the model.
+
+A test file, test1s3.v, which illustrates the interaction between the
+microprocessor and the flash memory is also included. This test file can be
+changed to test different scenarios representative of specific applications.
+Another test file, test_bad.v, illustrates the different scenarios resulting
+in the status register signaling error conditions were encountered.
\ No newline at end of file
models/28f016s3/read.me
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: models/28f016s3/28f016s3.bke
===================================================================
--- models/28f016s3/28f016s3.bke (nonexistent)
+++ models/28f016s3/28f016s3.bke (revision 1765)
@@ -0,0 +1,143 @@
+/*
+ INTEL DEVELOPER'S SOFTWARE LICENSE AGREEMENT
+
+BY USING THIS SOFTWARE, YOU ARE AGREEING TO BE BOUND BY THE TERMS OF
+THIS AGREEMENT. DO NOT USE THE SOFTWARE UNTIL YOU HAVE CAREFULLY READ
+AND AGREED TO THE FOLLOWING TERMS AND CONDITIONS. IF YOU DO NOT AGREE
+TO THE TERMS OF THIS AGREEMENT, PROMPTLY RETURN THE SOFTWARE PACKAGE AND
+ANY ACCOMPANYING ITEMS.
+
+IF YOU USE THIS SOFTWARE, YOU WILL BE BOUND BY THE TERMS OF THIS
+AGREEMENT
+
+LICENSE: Intel Corporation ("Intel") grants you the non-exclusive right
+to use the enclosed software program ("Software"). You will not use,
+copy, modify, rent, sell or transfer the Software or any portion
+thereof, except as provided in this Agreement.
+
+System OEM Developers may:
+1. Copy the Software for support, backup or archival purposes;
+2. Install, use, or distribute Intel owned Software in object code
+ only;
+3. Modify and/or use Software source code that Intel directly makes
+ available to you as an OEM Developer;
+4. Install, use, modify, distribute, and/or make or have made
+ derivatives ("Derivatives") of Intel owned Software under the
+ terms and conditions in this Agreement, ONLY if you are a System
+ OEM Developer and NOT an end-user.
+
+RESTRICTIONS:
+
+YOU WILL NOT:
+1. Copy the Software, in whole or in part, except as provided for
+ in this Agreement;
+2. Decompile or reverse engineer any Software provided in object
+ code format;
+3. Distribute any Software or Derivative code to any end-users,
+ unless approved by Intel in a prior writing.
+
+TRANSFER: You may transfer the Software to another OEM Developer if the
+receiving party agrees to the terms of this Agreement at the sole risk
+of any receiving party.
+
+OWNERSHIP AND COPYRIGHT OF SOFTWARE: Title to the Software and all
+copies thereof remain with Intel or its vendors. The Software is
+copyrighted and is protected by United States and international
+copyright laws. You will not remove the copyright notice from the
+Software. You agree to prevent any unauthorized copying of the
+Software.
+
+DERIVATIVE WORK: OEM Developers that make or have made Derivatives will
+not be required to provide Intel with a copy of the source or object
+code. OEM Developers shall be authorized to use, market, sell, and/or
+distribute Derivatives to other OEM Developers at their own risk and
+expense. Title to Derivatives and all copies thereof shall be in the
+particular OEM Developer creating the Derivative. Such OEMs shall
+remove the Intel copyright notice from all Derivatives if such notice is
+contained in the Software source code.
+
+DUAL MEDIA SOFTWARE: If the Software package contains multiple media,
+you may only use the medium appropriate for your system.
+
+WARRANTY: Intel warrants that it has the right to license you to use,
+modify, or distribute the Software as provided in this Agreement. The
+Software is provided "AS IS". Intel makes no representations to
+upgrade, maintain, or support the Software at any time. Intel warrants
+that the media on which the Software is furnished will be free from
+defects in material and workmanship for a period of one (1) year from
+the date of purchase. Upon return of such defective media, Intel's
+entire liability and your exclusive remedy shall be the replacement of
+the Software.
+
+THE ABOVE WARRANTIES ARE THE ONLY WARRANTIES OF ANY KIND, EITHER EXPRESS
+OR IMPLIED, INCLUDING WARRANTIES OF MERCHANTABILITY OR FITNESS FOR ANY
+PARTICULAR PURPOSE.
+
+LIMITATION OF LIABILITY: NEITHER INTEL NOR ITS VENDORS OR AGENTS SHALL
+BE LIABLE FOR ANY LOSS OF PROFITS, LOSS OF USE, LOSS OF DATA,
+INTERRUPTION OF BUSINESS, NOR FOR INDIRECT, SPECIAL, INCIDENTAL OR
+CONSEQUENTIAL DAMAGES OF ANY KIND WHETHER UNDER THIS AGREEMENT OR
+OTHERWISE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
+
+TERMINATION OF THIS LICENSE: Intel reserves the right to conduct or have
+conducted audits to verify your compliance with this Agreement. Intel
+may terminate this Agreement at any time if you are in breach of any of
+its terms and conditions. Upon termination, you will immediately
+destroy, and certify in writing the destruction of, the Software or
+return all copies of the Software and documentation to Intel.
+
+U.S. GOVERNMENT RESTRICTED RIGHTS: The Software and documentation were
+developed at private expense and are provided with "RESTRICTED RIGHTS".
+Use, duplication or disclosure by the Government is subject to
+restrictions as set forth in FAR52.227-14 and DFAR252.227-7013 et seq.
+or its successor.
+
+EXPORT LAWS: You agree that the distribution and export/re-export of the
+Software is in compliance with the laws, regulations, orders or other
+restrictions of the U.S. Export Administration Regulations.
+
+APPLICABLE LAW: This Agreement is governed by the laws of the State of
+California and the United States, including patent and copyright laws.
+Any claim arising out of this Agreement will be brought in Santa Clara
+County, California.
+
+*/
+
+// This file contains the end address of each block
+// numbered from block 0 to nn. The addresses are in hex.
+// The block addresses were taken from the Byte-Wide
+// Smart 3 FlashFile(tm) Memory Family datasheet
+// (Order Number 290598).
+
+00FFFF
+01FFFF
+02FFFF
+03FFFF
+04FFFF
+05FFFF
+06FFFF
+07FFFF
+08FFFF
+09FFFF
+0AFFFF
+0BFFFF
+0CFFFF
+0DFFFF
+0EFFFF
+0FFFFF
+10FFFF
+11FFFF
+12FFFF
+13FFFF
+14FFFF
+15FFFF
+16FFFF
+17FFFF
+18FFFF
+19FFFF
+1AFFFF
+1BFFFF
+1CFFFF
+1DFFFF
+1EFFFF
+1FFFFF
models/28f016s3/28f016s3.bke
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: verilog/dbg_tb_defines.v
===================================================================
--- verilog/dbg_tb_defines.v (nonexistent)
+++ verilog/dbg_tb_defines.v (revision 1765)
@@ -0,0 +1,173 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// dbgTB_defines.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.2 2001/09/18 14:12:43 mohor
+// Trace fixed. Some registers changed, trace simplified.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+// Revision 1.3 2001/06/01 22:23:40 mohor
+// This is a backup. It is not a fully working version. Not for use, yet.
+//
+// Revision 1.2 2001/05/18 13:10:05 mohor
+// Headers changed. All additional information is now avaliable in the README.txt file.
+//
+// Revision 1.1.1.1 2001/05/18 06:35:12 mohor
+// Initial release
+//
+//
+
+// Following defines are used in the testbench only
+
+ // MODER register
+ `define ENABLE 32'h00010000
+ `define CONTIN 32'h00020000
+
+ // TSEL register
+ `define WPTRIG_0 32'h00000001
+ `define WPTRIG_1 32'h00000002
+ `define WPTRIG_2 32'h00000004
+ `define WPTRIG_3 32'h00000008
+ `define WPTRIG_4 32'h00000010
+ `define WPTRIG_5 32'h00000020
+ `define WPTRIG_6 32'h00000040
+ `define WPTRIG_7 32'h00000080
+ `define WPTRIG_8 32'h00000100
+ `define WPTRIG_9 32'h00000200
+ `define WPTRIG_10 32'h00000400
+ `define WPTRIGVALID 32'h00000800
+
+ `define BPTRIG 32'h00001000
+ `define BPTRIGVALID 32'h00002000
+
+ `define LSSTRIG_0 32'h00010000
+ `define LSSTRIG_1 32'h00020000
+ `define LSSTRIG_2 32'h00040000
+ `define LSSTRIG_3 32'h00080000
+ `define LSSTRIGVALID 32'h00100000
+
+ `define ISTRIGVALID 32'h00800000
+
+ `define TRIGOP_AND 32'hc0000000
+ `define TRIGOP_OR 32'h80000000
+
+ // QSEL register
+ `define WPQUALIF_0 32'h00000001
+ `define WPQUALIF_1 32'h00000002
+ `define WPQUALIF_2 32'h00000004
+ `define WPQUALIF_3 32'h00000008
+ `define WPQUALIF_4 32'h00000010
+ `define WPQUALIF_5 32'h00000020
+ `define WPQUALIF_6 32'h00000040
+ `define WPQUALIF_7 32'h00000080
+ `define WPQUALIF_8 32'h00000100
+ `define WPQUALIF_9 32'h00000200
+ `define WPQUALIF_10 32'h00000400
+ `define WPQUALIFVALID 32'h00000800
+
+ `define BPQUALIF 32'h00001000
+ `define BPQUALIFVALID 32'h00002000
+
+ `define LSSQUALIF_0 32'h00010000
+ `define LSSQUALIF_1 32'h00020000
+ `define LSSQUALIF_2 32'h00040000
+ `define LSSQUALIF_3 32'h00080000
+ `define LSSQUALIFVALID 32'h00100000
+
+ `define ISQUALIFVALID 32'h00800000
+
+ `define QUALIFOP_AND 32'hc0000000
+ `define QUALIFOP_OR 32'h80000000
+
+
+ // SSEL register
+ `define WPSTOP_0 32'h00000001
+ `define WPSTOP_1 32'h00000002
+ `define WPSTOP_2 32'h00000004
+ `define WPSTOP_3 32'h00000008
+ `define WPSTOP_4 32'h00000010
+ `define WPSTOP_5 32'h00000020
+ `define WPSTOP_6 32'h00000040
+ `define WPSTOP_7 32'h00000080
+ `define WPSTOP_8 32'h00000100
+ `define WPSTOP_9 32'h00000200
+ `define WPSTOP_10 32'h00000400
+ `define WPSTOPVALID 32'h00000800
+
+ `define BPSTOP 32'h00001000
+ `define BPSTOPVALID 32'h00002000
+
+ `define LSSSTOP_0 32'h00010000
+ `define LSSSTOP_1 32'h00020000
+ `define LSSSTOP_2 32'h00040000
+ `define LSSSTOP_3 32'h00080000
+ `define LSSSTOPVALID 32'h00100000
+
+ `define ISSTOPVALID 32'h00800000
+
+ `define STOPOP_AND 32'hc0000000
+ `define STOPOP_OR 32'h80000000
+
+ `define IS_NO_FETCH 32'h00000000
+ `define IS_FETCH 32'h00200000
+ `define IS_BRANCH 32'h00400000
+ `define IS_FETCH_DELAY 32'h00600000
+
+ `define LSS_NO_LOADSTORE 32'h00000000
+ `define LSS_LOADBYTE_ZEROEXT 32'h00020000
+ `define LSS_LOADBYTE_SIGNEXT 32'h00030000
+ `define LSS_LOADHALF_ZEROEXT 32'h00040000
+ `define LSS_LOADHALF_SIGNEXT 32'h00050000
+ `define LSS_LOADWORD_ZEROEXT 32'h00060000
+ `define LSS_LOADWORD_SIGNEXT 32'h00070000
+ `define LSS_STORE_BYTE 32'h000A0000
+ `define LSS_STORE_HALF 32'h000C0000
+
+// End: Following defines are used in the testbench only
+
+
Index: verilog/xcv_glbl.v
===================================================================
--- verilog/xcv_glbl.v (nonexistent)
+++ verilog/xcv_glbl.v (revision 1765)
@@ -0,0 +1,57 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MP3 demo Xilinx global signals ////
+//// ////
+//// This file is part of the MP3 demo application ////
+//// http://www.opencores.org/cores/or1k/mp3/ ////
+//// ////
+//// Description ////
+//// Some global signals used in Xilinx libraries. ////
+//// ////
+//// To Do: ////
+//// - nothing really ////
+//// ////
+//// Author(s): ////
+//// - Damjan Lampret, lampret@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`timescale 1 ns / 1 ps
+
+module glbl ();
+
+ wire GR;
+ wire GSR;
+ wire GTS;
+ wire PRLD;
+
+endmodule
Index: verilog/xess_top.v
===================================================================
--- verilog/xess_top.v (nonexistent)
+++ verilog/xess_top.v (revision 1765)
@@ -0,0 +1,375 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MP3 demo Test bench top level ////
+//// ////
+//// This file is part of the MP3 demo application ////
+//// http://www.opencores.org/cores/or1k/mp3/ ////
+//// ////
+//// Description ////
+//// Top level of MP3 demo test bench. ////
+//// ////
+//// To Do: ////
+//// - nothing really ////
+//// ////
+//// Author(s): ////
+//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+// Xess board - top bench module
+
+`include "timescale.v"
+`include "bench_define.v"
+
+module xess_top (
+);
+
+`ifdef SRAM_INIT
+sram_init sram_init1();
+`endif
+
+reg r_rstn;
+reg r_clk;
+reg r_clk2;
+wire rstn;
+wire clk;
+wire clk2;
+
+wire flash_rstn;
+wire flash_oen;
+wire flash_cen;
+wire flash_wen;
+wire flash_rdy;
+wire [7:0] flash_d;
+wire [20:0] flash_a;
+wire [31:0] flash_vpp; // Special flash inputs
+wire [31:0] flash_vcc; // Special flash inputs
+wire [1:0] flash_rpblevel; // Special flash inputs
+wire sram_r_cen;
+wire sram_r0_wen;
+wire sram_r1_wen;
+wire sram_r_oen;
+wire [18:0] sram_r_a;
+wire [15:0] sram_r_d;
+wire sram_l_cen;
+wire sram_l0_wen;
+wire sram_l1_wen;
+wire sram_l_oen;
+wire [18:0] sram_l_a;
+wire [15:0] sram_l_d;
+wire codec_mclk;
+wire codec_lrclk;
+wire codec_sclk;
+wire codec_sdin;
+wire codec_sdout;
+wire vga_hsyncn;
+wire vga_vsyncn;
+wire [1:0] vga_r;
+wire [1:0] vga_g;
+wire [1:0] vga_b;
+wire eth_tx_er;
+wire eth_tx_clk;
+wire eth_tx_en;
+wire [4:0] eth_txd;
+wire eth_rx_er;
+wire eth_rx_clk;
+wire eth_rx_dv;
+wire [4:0] eth_rxd;
+wire eth_col;
+wire eth_crs;
+wire eth_trste;
+wire eth_fds_mdint;
+wire eth_mdio;
+wire eth_mdc;
+wire [2:1] switch;
+wire USB_VPO;
+wire USB_VMO;
+wire gdb_tms;
+wire gdb_tck;
+wire gdb_trst;
+wire gdb_tdi;
+wire gdb_tdo;
+wire [6:3] pps;
+
+// Putting here the following blocks
+
+// The xfpga_top
+
+xfpga_top i_xess_fpga(
+ .clk( clk ),
+// .clk2(clk2),
+ .rstn( rstn ),
+
+ .flash_rstn( flash_rstn ),
+ .flash_cen( flash_cen ),
+ .flash_oen( flash_oen ),
+ .flash_wen( flash_wen ),
+ .flash_rdy( flash_rdy ),
+ .flash_d( flash_d ),
+ .flash_a( flash_a ),
+
+ .sram_r_cen( sram_r_cen ),
+ .sram_r_oen( sram_r_oen ),
+ .sram_r0_wen( sram_r0_wen ),
+ .sram_r1_wen( sram_r1_wen ),
+ .sram_r_d( sram_r_d ),
+ .sram_r_a( sram_r_a ),
+
+ .sram_l_cen( sram_l_cen ),
+ .sram_l_oen( sram_l_oen ),
+ .sram_l0_wen( sram_l0_wen ),
+ .sram_l1_wen( sram_l1_wen ),
+ .sram_l_d( sram_l_d ),
+ .sram_l_a( sram_l_a ),
+
+ .codec_mclk( codec_mclk ),
+ .codec_lrclk( codec_lrclk ),
+ .codec_sclk( codec_sclk ),
+ .codec_sdin( codec_sdin ),
+ .codec_sdout( codec_sdout ),
+
+ .vga_blank(),
+ .vga_pclk(),
+ .vga_hsyncn( vga_hsyncn ),
+ .vga_vsyncn( vga_vsyncn ),
+ .vga_r( vga_r ),
+ .vga_g( vga_g ),
+ .vga_b( vga_b ),
+
+ .eth_col( eth_col ),
+ .eth_crs( eth_crs ),
+ .eth_trste( eth_trste ),
+ .eth_tx_clk( eth_tx_clk ),
+ .eth_tx_en( eth_tx_en ),
+ .eth_tx_er( eth_tx_er ),
+ .eth_txd( eth_txd ),
+ .eth_rx_clk( eth_rx_clk ),
+ .eth_rx_dv( eth_rx_dv ),
+ .eth_rx_er( eth_rx_er ),
+ .eth_rxd( eth_rxd ),
+ .eth_fds_mdint( eth_fds_mdint ),
+ .eth_mdc( eth_mdc ),
+ .eth_mdio( eth_mdio ),
+
+ .sw( switch ),
+ .USB_VPO(USB_VPO),
+ .USB_VMO(USB_VMO),
+
+
+ .ps2_clk( ps2_clk ),
+ .ps2_data( ps2_data ),
+
+ .cpld_tdo(cpld_tdo)
+
+);
+
+// The Flash RAM
+
+assign flash_vpp = 32'h00002ee0;
+assign flash_vcc = 32'h00001388;
+assign flash_rpblevel = 2'b10;
+
+i28f016s3 Flash (
+ .rpb( flash_rstn ),
+ .ceb( flash_cen ),
+ .oeb( flash_oen ),
+ .web( flash_wen ),
+ .ryby( flash_rdy ),
+ .dq( flash_d ),
+ .addr( flash_a ),
+ .vpp( flash_vpp ),
+ .vcc( flash_vcc ),
+ .rpblevel( flash_rpblevel )
+);
+
+// The SRAM
+
+A512Kx8 Sram_r0 (
+ .CE_bar( sram_r_cen ),
+ .OE_bar( sram_r_oen ),
+ .WE_bar( sram_r0_wen ),
+ .dataIO( sram_r_d[7:0] ),
+ .Address( sram_r_a )
+);
+
+A512Kx8 Sram_r1 (
+ .CE_bar( sram_r_cen ),
+ .OE_bar( sram_r_oen ),
+ .WE_bar( sram_r1_wen ),
+ .dataIO( sram_r_d[15:8] ),
+ .Address( sram_r_a )
+);
+
+A512Kx8 Sram_l0 (
+ .CE_bar( sram_l_cen ),
+ .OE_bar( sram_l_oen ),
+ .WE_bar( sram_l0_wen ),
+ .dataIO( sram_l_d[7:0] ),
+ .Address( sram_l_a )
+);
+
+A512Kx8 Sram_l1 (
+ .CE_bar( sram_l_cen ),
+ .OE_bar( sram_l_oen ),
+ .WE_bar( sram_l1_wen ),
+ .dataIO( sram_l_d[15:8] ),
+ .Address( sram_l_a )
+);
+
+// The Codec
+
+codec_model codec (
+ .mclk( codec_mclk ),
+ .lrclk( codec_lrclk ),
+ .sclk( codec_sclk ),
+ .sdin( codec_sdin ),
+ .sdout( codec_sdout )
+);
+
+// The VGA
+
+vga_model VGA (
+ .pclk( clk ),
+ .hsyncn( vga_hsyncn ),
+ .vsyncn( vga_vsyncn ),
+ .r( vga_r ),
+ .g( vga_g ),
+ .b( vga_b )
+);
+
+// We simulate CPLD because it has GDB JTAG multiplexer that
+// works together with demultiplexer in FPGA to connect GDB to
+// the RISC
+`ifdef UNUSED
+config_gdb xcpld (
+ .clk(clk),
+ .a(flash_a),
+ .ceb(),
+ .oeb(),
+ .web(),
+ .resetb(),
+ .V_progb(),
+ .V_cclk(),
+ .V_csb(),
+ .V_wrb(),
+ .V_initb(cpld_tdo),
+ .V_dout(1'b0),
+ .V_done(1'b1),
+ .V_m(),
+
+ .ppd({2'b00, gdb_tms, gdb_tdi, gdb_trst, gdb_tck, 2'b00}),
+ .pps(pps),
+ .ppc(4'h0)
+);
+assign gdb_tdo = pps[4];
+`else
+/* SIMON */
+
+assign flash_a[6] = flash_cen ? gdb_tms : 1'bz;
+assign flash_a[7] = flash_cen ? gdb_tdi : 1'bz;
+assign flash_a[8] = flash_cen ? gdb_trst : 1'bz;
+assign flash_a[9] = flash_cen ? gdb_tck : 1'bz;
+assign gdb_tdo = cpld_tdo;
+/*
+assign flash_a[6] = gdb_tms;
+assign flash_a[7] = gdb_tdi;
+assign flash_a[8] = gdb_trst;
+assign flash_a[9] = gdb_tck;
+assign gdb_tdo = cpld_tdo;
+*/
+`endif
+
+// DBG i/f
+`ifdef DBG_IF_COMM
+dbg_comm dbg_comm(
+`else
+`ifdef DBG2_IF_COMM
+dbg_comm2 dbg_comm(
+ .P_TMS(gdb_tms),
+ .P_TCK(gdb_tck),
+ .P_TRST(gdb_trst),
+ .P_TDI(gdb_tdi),
+ .P_TDO(gdb_tdo)
+);
+`else
+assign gdb_tms = 1'b0;
+assign gdb_tck = 1'b0;
+assign gdb_trst = rstn;
+assign gdb_tdi = 1'b0;
+`endif
+`endif
+ assign eth_tx_clk = 1'b0;
+ assign eth_rx_er = 1'b0;
+ assign eth_rx_clk = 1'b0;
+ assign eth_rx_dv = 1'b0;
+ assign eth_rxd = 5'b0;
+ assign eth_col= 1'b0;
+ assign eth_crs = 1'b0;
+ assign eth_fds_mdint = 1'b0;
+ assign eth_mdio = 1'bZ;
+ assign switch = 2'b0;
+
+ assign ps2_clk = 1'b0;
+ assign ps2_data = 1'b0;
+
+initial
+begin
+ #0 r_rstn = 1;
+ #1 r_rstn = 0;
+`ifdef SRAM_INIT
+ sram_init1.init_sram;
+`endif
+ repeat (`RESET_TIME) @(negedge r_clk);
+ r_rstn = 1;
+end
+
+assign rstn = r_rstn;
+
+initial begin
+ r_clk = `INIT_CLK_VALUE;
+ r_clk2 = `INIT_CLK2_VALUE;
+end
+
+always
+begin
+ #`CLK_PERIOD_DIV2 r_clk <= ~r_clk;
+end
+
+always
+begin
+ #`CLK2_PERIOD_DIV2 r_clk2 <= ~r_clk2;
+end
+
+assign clk = r_clk;
+assign clk2 = r_clk2;
+
+endmodule
Index: verilog/sram_init.v
===================================================================
--- verilog/sram_init.v (nonexistent)
+++ verilog/sram_init.v (revision 1765)
@@ -0,0 +1,92 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MP3 demo SRAM init ////
+//// ////
+//// This file is part of the MP3 demo application ////
+//// http://www.opencores.org/cores/or1k/mp3/ ////
+//// ////
+//// Description ////
+//// Optional SRAM content initialization (for debugging ////
+//// purposes) ////
+//// ////
+//// To Do: ////
+//// - nothing really ////
+//// ////
+//// Author(s): ////
+//// - Damjan Lampret, lampret@opencores.org ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`ifdef SRAM_INIT
+
+module sram_init;
+
+reg [7:0] mem [135005:0];
+reg [31:0] tmp;
+
+task init_sram;
+integer i;
+begin
+ #1;
+
+ $display("Initializing SRAM ...");
+ $readmemh("../src/flash.in", mem);
+ for (i=0; i < 135000; i=i+4) begin
+ xess_top.Sram_r1.mem_array[i/4] = mem[i];
+ xess_top.Sram_r0.mem_array[i/4] = mem[i+1];
+ xess_top.Sram_l1.mem_array[i/4] = mem[i+2];
+ xess_top.Sram_l0.mem_array[i/4] = mem[i+3];
+ end
+
+`ifdef UNUSED
+
+ for (i=0; i < 135000; i=i+4) begin
+ tmp[31:24] = xess_top.Sram_r1.temp_array[i/4];
+ tmp[23:16] = xess_top.Sram_r0.temp_array[i/4];
+ tmp[15:8] = xess_top.Sram_l1.temp_array[i/4];
+ tmp[7:0] = xess_top.Sram_l0.temp_array[i/4];
+ $display("%h %h", i, tmp);
+ tmp[31:24] = xess_top.Sram_r1.mem_array[i/4];
+ tmp[23:16] = xess_top.Sram_r0.mem_array[i/4];
+ tmp[15:8] = xess_top.Sram_l1.mem_array[i/4];
+ tmp[7:0] = xess_top.Sram_l0.mem_array[i/4];
+ $display("%h %h", i, tmp);
+ end
+
+`endif
+
+end
+endtask
+
+endmodule
+
+`endif
Index: verilog/timescale.v
===================================================================
--- verilog/timescale.v (nonexistent)
+++ verilog/timescale.v (revision 1765)
@@ -0,0 +1,49 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MP3 demo test bench timescale ////
+//// ////
+//// This file is part of the MP3 demo application ////
+//// http://www.opencores.org/cores/or1k/mp3/ ////
+//// ////
+//// Description ////
+//// Test bench timescale. ////
+//// ////
+//// To Do: ////
+//// - nothing really ////
+//// ////
+//// Author(s): ////
+//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+
+`timescale 1ns/10ps
Index: verilog/dbg_comm.v
===================================================================
--- verilog/dbg_comm.v (nonexistent)
+++ verilog/dbg_comm.v (revision 1765)
@@ -0,0 +1,197 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// File_communication.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2001/09/24 14:06:13 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.2 2001/09/20 10:10:30 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+//
+//
+//
+//
+
+`ifdef DBG_IF_COMM
+
+`include "timescale.v"
+`include "dbg_defines.v"
+`include "dbg_tb_defines.v"
+
+`define GDB_IN "/projects/xess-damjan/sim/run/gdb_in.dat"
+`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
+//`define GDB_IN "/tmp/gdb_in.dat"
+//`define GDB_OUT "/tmp/gdb_out.dat"
+//`define GDB_IN "../src/gdb_in.dat"
+//`define GDB_OUT "../src/gdb_out.dat"
+
+module dbg_comm(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);
+
+parameter Tp = 1;
+
+output P_TMS;
+output P_TCK;
+output P_TRST;
+output P_TDI;
+input P_TDO;
+
+integer handle1, handle2;
+reg [4:0] memory[0:0];
+reg Mclk;
+reg wb_rst_i;
+
+reg alternator;
+
+reg StartTesting;
+wire P_TCK;
+wire P_TRST;
+wire P_TDI;
+wire P_TMS;
+wire P_TDO;
+
+reg [3:0] in_word_r;
+wire [4:0] in_word;
+wire [3:0] Temp;
+
+initial
+begin
+ alternator = 0;
+ StartTesting = 0;
+ wb_rst_i = 0;
+ #500;
+ wb_rst_i = 1;
+ #500;
+ wb_rst_i = 0;
+
+ #2000;
+ StartTesting = 1;
+ $display("StartTesting = 1");
+
+
+end
+
+initial
+begin
+ wait(StartTesting);
+ while(1)
+ begin
+ #1;
+ $readmemh(`GDB_OUT, memory);
+ //#1000;
+ if(!(memory[0] & 5'b10000))
+ begin
+ handle1 = $fopen(`GDB_OUT);
+ $fwrite(handle1, "%h", 5'b10000 | memory[0]); // To ack to jp1 that we read dgb_out.dat
+ $fclose(handle1);
+ end
+ end
+end
+
+assign in_word = memory[0];
+assign Temp = in_word_r;
+
+always @ (posedge in_word[4] or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ in_word_r<=#Tp 5'b0;
+ else
+ in_word_r<=#Tp in_word[3:0];
+end
+
+
+//always alternator = #100 ~alternator;
+
+always @ (posedge P_TCK or alternator)
+begin
+ handle2 = $fopen(`GDB_IN);
+ $fdisplay(handle2, "%b", P_TDO); // Vriting output data to file (TDO)
+ $fclose(handle2);
+end
+
+
+assign P_TCK = Temp[0];
+assign P_TRST = Temp[1];
+assign P_TDI = Temp[2];
+assign P_TMS = Temp[3];
+
+
+
+// Generating master clock (RISC clock) 10 MHz
+initial
+begin
+ Mclk<=#Tp 0;
+ #1 forever #`RISC_CLOCK Mclk<=~Mclk;
+end
+
+// Generating random number for use in DATAOUT_RISC[31:0]
+reg [31:0] RandNumb;
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RandNumb[31:0]<=#Tp 0;
+ else
+ RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
+end
+
+wire [31:0] DataIn = RandNumb;
+
+// Connecting dbgTAP module
+`ifdef UNUSED
+dbg_top dbg1 (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
+ .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
+ .risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
+ .opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
+ .risc_stall_o(), .reset_o()
+ );
+`endif
+
+endmodule // TAP
+
+`endif
Index: verilog/bench_define.v
===================================================================
--- verilog/bench_define.v (nonexistent)
+++ verilog/bench_define.v (revision 1765)
@@ -0,0 +1,53 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// MP3 demo test bench definitions ////
+//// ////
+//// This file is part of the MP3 demo application ////
+//// http://www.opencores.org/cores/or1k/mp3/ ////
+//// ////
+//// Description ////
+//// Definitions for the test bench. ////
+//// ////
+//// To Do: ////
+//// - nothing really ////
+//// ////
+//// Author(s): ////
+//// - Lior Shtram, lior.shtram@flextronicssemi.com ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+//
+`define RESET_TIME 10
+`define INIT_CLK_VALUE 1'b0
+`define CLK_PERIOD_DIV2 50
+
+`define INIT_CLK2_VALUE 1'b0
+`define CLK2_PERIOD_DIV2 50
Index: verilog/dbg_comm2.v
===================================================================
--- verilog/dbg_comm2.v (nonexistent)
+++ verilog/dbg_comm2.v (revision 1765)
@@ -0,0 +1,503 @@
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// File_communication.v ////
+//// ////
+//// ////
+//// This file is part of the SoC/OpenRISC Development Interface ////
+//// http://www.opencores.org/cores/DebugInterface/ ////
+//// ////
+//// ////
+//// Author(s): ////
+//// Igor Mohor ////
+//// igorm@opencores.org ////
+//// ////
+//// ////
+//// All additional information is avaliable in the README.txt ////
+//// file. ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2000,2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: not supported by cvs2svn $
+// Revision 1.3 2001/09/24 14:06:13 mohor
+// Changes connected to the OpenRISC access (SPR read, SPR write).
+//
+// Revision 1.2 2001/09/20 10:10:30 mohor
+// Working version. Few bugs fixed, comments added.
+//
+// Revision 1.1.1.1 2001/09/13 13:49:19 mohor
+// Initial official release.
+//
+//
+//
+//
+//
+
+`ifdef DBG_IF_COMM
+
+`include "dbg_timescale.v"
+`include "dbg_defines.v"
+//`include "dbg_tb_defines.v"
+
+
+
+`define GDB_IN "/projects/xess-damjan/sim/run/gdb_in.dat"
+`define GDB_OUT "/projects/xess-damjan/sim/run/gdb_out.dat"
+//`define GDB_IN "/tmp/gdb_in.dat"
+//`define GDB_OUT "/tmp/gdb_out.dat"
+//`define GDB_IN "../src/gdb_in.dat"
+//`define GDB_OUT "../src/gdb_out.dat"
+
+module dbg_comm2(P_TMS, P_TCK, P_TRST, P_TDI, P_TDO);
+
+parameter Tp = 1;
+parameter Tclk = 50; // Clock half period (Clok period = 100 ns => 10 MHz)
+
+output P_TMS;
+output P_TCK;
+output P_TRST;
+output P_TDI;
+input P_TDO;
+
+integer handle1, handle2;
+reg [87:0] memory[0:0];
+reg [87:0] file;
+reg Mclk;
+reg wb_rst_i;
+
+reg alternator;
+
+reg StartTesting;
+reg P_TCK;
+reg P_TRST;
+reg P_TDI;
+reg P_TMS;
+wire P_TDO;
+
+reg transition_detected;
+reg update_state;
+reg latchedbit;
+reg [31:0] data_out;
+
+
+initial
+begin
+ P_TCK = 0;
+ P_TMS = 0;
+ P_TDI = 0;
+ alternator = 0;
+ StartTesting = 0;
+ wb_rst_i = 0;
+ P_TRST = 1;
+ #500;
+ wb_rst_i = 1;
+ P_TRST = 0;
+ #500;
+ wb_rst_i = 0;
+ P_TRST = 1;
+
+ #2000;
+ StartTesting = 1;
+ $display("StartTesting = 1");
+
+
+end
+
+initial
+begin
+ wait(StartTesting);
+ while(1)
+ begin
+// while(~transition_detected)
+// begin
+ #1000;
+ $readmemh(`GDB_OUT, memory);
+// $readmemh(`GDB_OUT, file);
+// end
+// wait(update_state);
+ handle1 = $fopen(`GDB_OUT);
+// $fwrite(handle1, "%h", memory[0]); // To ack to jp1 that we read dgb_out.dat
+ $fwrite(handle1, "%h", {Temp[15:1], 1'b1}); // To ack to jp1 that we read dgb_out.dat
+ $fclose(handle1);
+// end
+ end
+end
+
+//always alternator = #100 ~alternator;
+
+//always @ (posedge P_TCK or alternator)
+always @ (posedge Mclk)
+begin
+ handle2 = $fopen(`GDB_IN);
+ wait(update_state);
+ $fdisplay(handle2, "%h", data_out); // Writing output data to file
+ $fclose(handle2);
+end
+
+wire [87:0]word = memory[0];
+
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ transition_detected <= 1'b0;
+ end
+ else if(!word[0])
+ begin
+ file = word;
+ transition_detected = 1'b1;
+ end
+ else
+ transition_detected = 1'b0;
+end
+
+wire [87:0]Temp = file;
+/*
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ transition_detected <= 1'b0;
+ latchedbit <= 1'b0;
+ end
+ else
+ if(~latchedbit & Temp[2])
+ transition_detected = 1'b1;
+ else
+ transition_detected = 1'b0;
+ latchedbit <= Temp[2];
+end
+*/
+
+
+
+reg [3:0] chain ;
+reg [7:0] chain_crc ;
+reg [31:0] address ;
+reg rw ;
+reg [31:0] data ;
+reg [7:0] data_crc ;
+
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ begin
+ chain = 'h0;
+ chain_crc = 'h0;
+ address = 'h0;
+ rw = 'h0;
+ data = 'h0;
+ data_crc = 'h0;
+ end
+ else
+ if(transition_detected)
+ begin
+ chain = Temp[87:84];
+ chain_crc = Temp[83:76];
+ address = Temp[75:44];
+ rw = Temp[43];
+ data = Temp[42:11];
+ data_crc = Temp[10:3];
+ end
+end
+
+
+
+
+// assign P_TCK = Temp[0];
+// assign P_TRST = Temp[1];
+// assign P_TDI = Temp[2];
+// assign P_TMS = Temp[3];
+
+
+
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ update_state <= 1'b0;
+ else
+ if(transition_detected)
+ begin
+ update_state <= 1'b0;
+ begin
+ SetInstruction(`CHAIN_SELECT);
+ ChainSelect(chain, chain_crc); // {chain, crc}
+ SetInstruction(`DEBUG);
+ if(rw)
+ begin
+ WriteRISCRegister(data, address, data_crc); // {data, addr, crc}
+ update_state <= 1'b1;
+ end
+ else
+ begin
+ ReadRISCRegister(address, data_crc, data_out); // {addr, crc, read_data}
+ ReadRISCRegister(address, data_crc, data_out); // {addr, crc, read_data}
+ update_state <= 1'b1;
+ end
+ end
+ end
+end
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+// Generating master clock (RISC clock) 10 MHz
+initial
+begin
+ Mclk<=#Tp 0;
+ #1 forever #`RISC_CLOCK Mclk<=~Mclk;
+end
+
+// Generating random number for use in DATAOUT_RISC[31:0]
+reg [31:0] RandNumb;
+always @ (posedge Mclk or posedge wb_rst_i)
+begin
+ if(wb_rst_i)
+ RandNumb[31:0]<=#Tp 0;
+ else
+ RandNumb[31:0]<=#Tp RandNumb[31:0] + 1;
+end
+
+wire [31:0] DataIn = RandNumb;
+
+// Connecting dbgTAP module
+`ifdef UNUSED
+dbg_top dbg1 (.tms_pad_i(P_TMS), .tck_pad_i(P_TCK), .trst_pad_i(P_TRST), .tdi_pad_i(P_TDI), .tdo_pad_o(P_TDO),
+ .wb_rst_i(wb_rst_i), .risc_clk_i(Mclk), .risc_addr_o(), .risc_data_i(DataIn),
+ .risc_data_o(), .wp_i(11'h0), .bp_i(1'b0),
+ .opselect_o(), .lsstatus_i(4'h0), .istatus_i(2'h0),
+ .risc_stall_o(), .reset_o()
+ );
+`endif
+
+
+
+// Generation of the TCLK signal
+task GenClk;
+ input [7:0] Number;
+ integer i;
+ begin
+ for(i=0; i