URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/or1k/tags/first/mp3/rtl
- from Rev 1765 to Rev 769
- ↔ Reverse comparison
Rev 1765 → Rev 769
/verilog/audio/audio_codec_if.v
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/verilog/audio/audio_top.v
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/verilog/audio/audio_wb_if.v
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/verilog/audio/fifo_empty_16.v
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/verilog/audio/fifo_4095_16.v
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/verilog/or1200.xcv/pic.v
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/verilog/or1200.xcv/pm.v
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/verilog/or1200.xcv/frz_logic.v
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/verilog/or1200.xcv/generic_tpram_32x32.v
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/verilog/or1200.xcv/generic_multp2_32x32.v
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/verilog/or1200.xcv/cfgr.v
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/verilog/or1200.xcv/dc_tag.v
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/verilog/or1200.xcv/or1200.v
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/verilog/or1200.xcv/generic_spram_64x14.v
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/verilog/or1200.xcv/dc_ram.v
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/verilog/or1200.xcv/dtlb.v
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/verilog/or1200.xcv/sprs.v
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/verilog/or1200.xcv/tt.v
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/verilog/or1200.xcv/generic_spram_64x37.v
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/verilog/or1200.xcv/ic.v
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/verilog/or1200.xcv/dc_fsm.v
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/verilog/or1200.xcv/id.v
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/verilog/or1200.xcv/mem2reg.v
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/verilog/or1200.xcv/reg2mem.v
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/verilog/or1200.xcv/mult_mac.v
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/verilog/or1200.xcv/lsu.v
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/verilog/or1200.xcv/immu.v
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/verilog/or1200.xcv/generic_spram_512x19.v
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/verilog/or1200.xcv/operandmuxes.v
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/verilog/or1200.xcv/generic_spram_2048x8.v
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/verilog/or1200.xcv/defines.v
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/verilog/or1200.xcv/alu.v
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/verilog/or1200.xcv/generic_spram_64x21.v
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/verilog/or1200.xcv/generic_spram_64x23.v
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/verilog/or1200.xcv/ic_tag.v
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/verilog/or1200.xcv/dc.v
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/verilog/or1200.xcv/cpu.v
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/verilog/or1200.xcv/except.v
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/verilog/or1200.xcv/generic_spram_2048x32.v
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/verilog/or1200.xcv/xcv_ram32x8d.v
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/verilog/or1200.xcv/itlb.v
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/verilog/or1200.xcv/ic_ram.v
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/verilog/or1200.xcv/generic_spram_512x20.v
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/verilog/or1200.xcv/ic_fsm.v
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/verilog/or1200.xcv/generic_dpram_32x32.v
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/verilog/or1200.xcv/ifetch.v
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/verilog/or1200.xcv/dmmu.v
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/verilog/or1200.xcv/wbmux.v
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/verilog/or1200.xcv/rf.v
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/verilog/or1200.xcv/wb_biu.v
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/verilog/or1200.xcv/du.v
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/verilog/ssvga/ssvga_wbs_if.v
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/verilog/ssvga/ssvga_crtc.v
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/verilog/ssvga/ssvga_defines.v
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\ No newline at end of file
/verilog/ssvga/crtc_iob.v
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\ No newline at end of file
/verilog/ssvga/ssvga_top.v
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/verilog/ssvga/ssvga_fifo.v
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/verilog/ssvga/ssvga_wbm_if.v
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/verilog/xfpga_defines.v
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/verilog/tcop_top.v
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/verilog/xfpga_top.v
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/verilog/dbg_interface/dbg_sync_clk1_clk2.v
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/verilog/dbg_interface/dbg_top.v
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/verilog/dbg_interface/dbg_crc8_d1.v
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/verilog/dbg_interface/dbg_register.v
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/verilog/dbg_interface/dbg_timescale.v
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/verilog/dbg_interface/dbg_registers.v
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/verilog/dbg_interface/timescale.v
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/verilog/dbg_interface/dbg_defines.v
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/verilog/dbg_interface/dbg_trace.v
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/verilog/mem_if/flash_top.v
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/verilog/mem_if/sram_top.v
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