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https://opencores.org/ocsvn/or1k/or1k/trunk
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- This comparison shows the changes necessary to convert path
/or1k/tags/first/mp3/syn/design_compiler
- from Rev 1765 to Rev 769
- ↔ Reverse comparison
Rev 1765 → Rev 769
/run/dodesign
File deleted
run/dodesign
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: out/README
===================================================================
--- out/README (revision 1765)
+++ out/README (nonexistent)
@@ -1 +0,0 @@
-This directory containts gate-level netlists.
Index: bin/cons_vs_umc18.inc
===================================================================
--- bin/cons_vs_umc18.inc (revision 1765)
+++ bin/cons_vs_umc18.inc (nonexistent)
@@ -1,50 +0,0 @@
-/* Constraints */
-CLK_UNCERTAINTY = 0.1 /* 100 ps */
-DFFPQ2_CKQ = 0.2 /* Clk to Q in technology time units */
-DFFPQ2_SETUP = 0.1 /* Setup time in technology time units */
-
-/* Clocks constraints */
-create_clock CLK -period CLK_PERIOD
-set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
-set_dont_touch_network all_clocks()
-
-/* Reset constraints */
-set_driving_cell -none RST
-set_drive 0 RST
-set_dont_touch_network RST
-
-/* All inputs except reset and clock */
-all_inputs_wo_rst_clk = all_inputs() - CLK - RST
-
-/* Set output delays and load for output signals
- *
- * All outputs are assumed to go directly into
- * external flip-flops for the purpose of this
- * synthesis
- */
-set_output_delay DFFPQ2_SETUP -clock CLK all_outputs()
-set_load load_of(umcl18u250t2_typ/DFFPQ2/D) * 4 all_outputs()
-
-/* Input delay and driving cell of all inputs
- *
- * All these signals are assumed to come directly from
- * flip-flops for the purpose of this synthesis
- *
- */
-set_input_delay DFFPQ2_CKQ -clock CLK all_inputs_wo_rst_clk
-set_driving_cell -cell DFFPQ2 -pin Q all_inputs_wo_rst_clk
-
-/* Set design fanout */
-/*
-set_max_fanout 10 TOPLEVEL
-*/
-
-/* Set area constraint */
-set_max_area MAX_AREA
-
-/* Optimize all near-critical paths to give extra slack for layout */
-c_range = CLK_PERIOD * 0.1
-group_path -critical_range c_range -name CLK -to CLK
-
-/* Operating conditions */
-set_operating_conditions TYPICAL
Index: bin/save_design.inc
===================================================================
--- bin/save_design.inc (revision 1765)
+++ bin/save_design.inc (nonexistent)
@@ -1,5 +0,0 @@
-/* Save current design using synopsys format */
-write -hierarchy -format db -output GATE_PATH + STAGE + _ + TOPLEVEL + .db
-
-/* Save current design using verilog format */
-write -hierarchy -format verilog -output GATE_PATH + STAGE + _ + TOPLEVEL + .v
Index: bin/tech_vs_umc18.inc
===================================================================
--- bin/tech_vs_umc18.inc (revision 1765)
+++ bin/tech_vs_umc18.inc (nonexistent)
@@ -1,16 +0,0 @@
-/* Set Virtual Silicon UMC 0.18u standard cell library */
-
-search_path = {. /libs/Virtual_silicon/UMCL18U250D2_2.1/design_compiler/ }
-snps = get_unix_variable("SYNOPSYS")
-synthetic_library = { \
- snps + "/libraries/syn/dw01.sldb" \
- snps + "/libraries/syn/dw02.sldb" \
- snps + "/libraries/syn/dw03.sldb" \
- snps + "/libraries/syn/dw04.sldb" \
- snps + "/libraries/syn/dw05.sldb" \
- snps + "/libraries/syn/dw06.sldb" \
- snps + "/libraries/syn/dw07.sldb" }
-target_library = { umcl18u250t2_typ.db }
-link_library = target_library + synthetic_library
-symbol_library = { umcl18u250t2.sdb }
-
Index: bin/reports.inc
===================================================================
--- bin/reports.inc (revision 1765)
+++ bin/reports.inc (nonexistent)
@@ -1,10 +0,0 @@
-/* Basic reports */
-report_area > LOG_PATH + STAGE + _ + TOPLEVEL + _area.log
-report_timing -nworst 10 > LOG_PATH + STAGE + _ + TOPLEVEL + _timing.log
-report_hierarchy > LOG_PATH + STAGE + _ + TOPLEVEL + _hierarchy.log
-report_resources > LOG_PATH + STAGE + _ + TOPLEVEL + _resources.log
-report_constraint > LOG_PATH + STAGE + _ + TOPLEVEL + _constraint.log
-/*
-report_power > LOG_PATH + STAGE + _ + TOPLEVEL + _power.log
-*/
-
Index: bin/top.scr
===================================================================
--- bin/top.scr (revision 1765)
+++ bin/top.scr (nonexistent)
@@ -1,64 +0,0 @@
-/*
- * User defines for synthesizing RTC IP core
- *
- */
-TOPLEVEL = xfpga_top
-include ../bin/select_tech.inc
-CLK = clk
-RST = rstn
-CLK_PERIOD = 5 /* 200 MHz */
-MAX_AREA = 0 /* Push hard */
-DO_UNGROUP = yes /* yes, no */
-DO_VERIFY = yes /* yes, no */
-
-/* Starting timestamp */
-sh date
-
-/* Set some basic variables related to environment */
-include ../bin/set_env.inc
-STAGE = final
-
-/* Load libraries */
-include ../bin/tech_ + TECH + .inc
-
-/* Load HDL source files */
-include ../bin/read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log
-
-/* Set design top */
-current_design TOPLEVEL
-
-/* Link all blocks and uniquify them */
-link
-uniquify
-check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
-
-/* Apply constraints */
-if (TECH == "vs_umc18") {
- include ../bin/cons_vs_umc18.inc
-} else if (TECH == "art_umc18") {
- include ../bin/cons_art_umc18.inc
-} else {
- echo "Error: Unsupported technology"
- exit
-}
-
-/* Lets do basic synthesis */
-if (DO_UNGROUP == "yes") {
- ungroup -all
-}
-compile -boundary_optimization -map_effort low
-
-/* Dump gate-level from incremental synthesis */
-include ../bin/save_design.inc
-
-/* Generate reports for incremental synthesis */
-include ../bin/reports.inc
-
-/* Verify design */
-if (DO_VERIFY == "yes") {
- compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
-}
-
-/* Finish */
-sh date
-exit
Index: bin/select_tech.inc
===================================================================
--- bin/select_tech.inc (revision 1765)
+++ bin/select_tech.inc (nonexistent)
@@ -1,5 +0,0 @@
-/* Defaults */
-
-TECH = vs_umc18 /* vs_umc18, art_umc18 */
-CLK_PERIOD = 5 /* 200 MHz */
-MAX_AREA = 0 /* Push hard */
Index: bin/set_env.inc
===================================================================
--- bin/set_env.inc (revision 1765)
+++ bin/set_env.inc (nonexistent)
@@ -1,20 +0,0 @@
-/* Enable Verilog HDL preprocessor */
-hdlin_enable_vpp = true
-
-/* Set log path */
-LOG_PATH = "../log/"
-
-/* Set gate-level netlist path */
-GATE_PATH = "../out/"
-
-/* Set RAMS_PATH */
-RAMS_PATH = "../../../lib/"
-
-/* Set RTL source path */
-RTL_PATH = { "../../../rtl/verilog/", "../../../rtl/verilog/audio/", \
- "../../../rtl/verilog/dbg_interface/", "../../../rtl/verilog/or1200/", \
- "../../../rtl/verilog/mem_if/", "../../../rtl/verilog/ssvga/" }
-
-/* Optimize adders */
-synlib_model_map_effort = high
-hlo_share_effort = medium
Index: bin/read_design.inc
===================================================================
--- bin/read_design.inc (revision 1765)
+++ bin/read_design.inc (nonexistent)
@@ -1,87 +0,0 @@
-/* Set search path for verilog include files */
-search_path = search_path + RTL_PATH + { GATE_PATH }
-
-/* Read verilog files of the RTC IP core */
-if (TOPLEVEL == "xfpga_top") {
- read -f verilog tcop_top.v
- read -f verilog xfpga_top.v
-
- read -f verilog audio_codec_if.v
- read -f verilog audio_top.v
- read -f verilog audio_wb_if.v
- read -f verilog fifo_4095_16.v
- read -f verilog fifo_empty_16.v
-
- read -f verilog dbg_crc8_d1.v
- read -f verilog dbg_defines.v
- read -f verilog dbg_register.v
- read -f verilog dbg_registers.v
- read -f verilog dbg_sync_clk1_clk2.v
- read -f verilog dbg_timescale.v
- read -f verilog dbg_top.v
- read -f verilog dbg_trace.v
-
- read -f verilog flash_top.v
- read -f verilog sram_top.v
-
- read -f verilog alu.v
- read -f verilog cfgr.v
- read -f verilog cpu.v
- read -f verilog dc.v
- read -f verilog dc_fsm.v
- read -f verilog dc_ram.v
- read -f verilog dc_tag.v
- read -f verilog defines.v
- read -f verilog dmmu.v
- read -f verilog dtlb.v
- read -f verilog du.v
- read -f verilog except.v
- read -f verilog frz_logic.v
- read -f verilog generic_dpram_32x32.v
- read -f verilog generic_multp2_32x32.v
- read -f verilog generic_spram_2048x32.v
- read -f verilog generic_spram_2048x8.v
- read -f verilog generic_spram_512x19.v
- read -f verilog generic_spram_512x20.v
- read -f verilog generic_spram_64x14.v
- read -f verilog generic_spram_64x21.v
- read -f verilog generic_spram_64x23.v
- read -f verilog generic_spram_64x37.v
- read -f verilog generic_tpram_32x32.v
- read -f verilog ic.v
- read -f verilog ic_fsm.v
- read -f verilog ic_ram.v
- read -f verilog ic_tag.v
- read -f verilog id.v
- read -f verilog ifetch.v
- read -f verilog immu.v
- read -f verilog itlb.v
- read -f verilog lsu.v
- read -f verilog mem2reg.v
- read -f verilog mult_mac.v
- read -f verilog operandmuxes.v
- read -f verilog or1200.v
- read -f verilog pic.v
- read -f verilog pm.v
- read -f verilog reg2mem.v
- read -f verilog rf.v
- read -f verilog sprs.v
- read -f verilog tt.v
- read -f verilog wb_biu.v
- read -f verilog wbmux.v
-
- read -f verilog xcv_ram32x8d.v
-
- read -f verilog crtc_iob.v
- read -f verilog ssvga_crtc.v
- read -f verilog ssvga_defines.v
- read -f verilog ssvga_fifo.v
- read -f verilog ssvga_top.v
- read -f verilog ssvga_wbm_if.v
- read -f verilog ssvga_wbs_if.v
-
-} else {
- echo "Non-existing top level."
- exit
-}
-
Index: bin/cons_art_umc18.inc
===================================================================
--- bin/cons_art_umc18.inc (revision 1765)
+++ bin/cons_art_umc18.inc (nonexistent)
@@ -1,50 +0,0 @@
-/* Constraints */
-CLK_UNCERTAINTY = 0.1 /* 100 ps */
-DFFHQX2_CKQ = 0.2 /* Clk to Q in technology time units */
-DFFHQX2_SETUP = 0.1 /* Setup time in technology time units */
-
-/* Clocks constraints */
-create_clock CLK -period CLK_PERIOD
-set_clock_skew all_clocks() -uncertainty CLK_UNCERTAINTY
-set_dont_touch_network all_clocks()
-
-/* Reset constraints */
-set_driving_cell -none RST
-set_drive 0 RST
-set_dont_touch_network RST
-
-/* All inputs except reset and clock */
-all_inputs_wo_rst_clk = all_inputs() - CLK - RST
-
-/* Set output delays and load for output signals
- *
- * All outputs are assumed to go directly into
- * external flip-flops for the purpose of this
- * synthesis
- */
-set_output_delay DFFHQX2_SETUP -clock CLK all_outputs()
-set_load load_of(typical/DFFHQX2/D) * 1 all_outputs()
-
-/* Input delay and driving cell of all inputs
- *
- * All these signals are assumed to come directly from
- * flip-flops for the purpose of this synthesis
- *
- */
-set_input_delay DFFHQX2_CKQ -clock CLK all_inputs_wo_rst_clk
-set_driving_cell -cell DFFHQX2 -pin Q all_inputs_wo_rst_clk
-
-/* Set design fanout */
-/*
-set_max_fanout 10 TOPLEVEL
-*/
-
-/* Set area constraint */
-set_max_area MAX_AREA
-
-/* Optimize all near-critical paths to give extra slack for layout */
-c_range = CLK_PERIOD * 0.05
-group_path -critical_range c_range -name CLK -to CLK
-
-/* Operating conditions */
-set_operating_conditions typical
Index: bin/tech_art_umc18.inc
===================================================================
--- bin/tech_art_umc18.inc (revision 1765)
+++ bin/tech_art_umc18.inc (nonexistent)
@@ -1,17 +0,0 @@
-/* Set Artisan Sage-X UMC 0.18u standard cell library */
-
-search_path = {. /libs/Artisan/aci/sc-x/synopsys/ } + \
- { /libs/Artisan/aci/sc-x/symbols/synopsys/ }
-snps = get_unix_variable("SYNOPSYS")
-synthetic_library = { \
- snps + "/libraries/syn/dw01.sldb" \
- snps + "/libraries/syn/dw02.sldb" \
- snps + "/libraries/syn/dw03.sldb" \
- snps + "/libraries/syn/dw04.sldb" \
- snps + "/libraries/syn/dw05.sldb" \
- snps + "/libraries/syn/dw06.sldb" \
- snps + "/libraries/syn/dw07.sldb" }
-target_library = { typical.db }
-link_library = target_library + synthetic_library
-symbol_library = { umc18.sdb }
-