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- This comparison shows the changes necessary to convert path
/or1k/tags/hello-uart_v1_0/hello-uart
- from Rev 1224 to Rev 1765
- ↔ Reverse comparison
Rev 1224 → Rev 1765
/uart.h
0,0 → 1,121
#ifndef _UART_H_ |
#define _UART_H_ |
|
#define UART_RX 0 /* In: Receive buffer (DLAB=0) */ |
#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ |
#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ |
#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ |
#define UART_IER 1 /* Out: Interrupt Enable Register */ |
#define UART_IIR 2 /* In: Interrupt ID Register */ |
#define UART_FCR 2 /* Out: FIFO Control Register */ |
#define UART_EFR 2 /* I/O: Extended Features Register */ |
/* (DLAB=1, 16C660 only) */ |
#define UART_LCR 3 /* Out: Line Control Register */ |
#define UART_MCR 4 /* Out: Modem Control Register */ |
#define UART_LSR 5 /* In: Line Status Register */ |
#define UART_MSR 6 /* In: Modem Status Register */ |
#define UART_SCR 7 /* I/O: Scratch Register */ |
|
/* |
* These are the definitions for the FIFO Control Register |
* (16650 only) |
*/ |
#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */ |
#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */ |
#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */ |
#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */ |
#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */ |
#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */ |
#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */ |
#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */ |
#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */ |
/* 16650 redefinitions */ |
#define UART_FCR6_R_TRIGGER_8 0x00 /* Mask for receive trigger set at 1 */ |
#define UART_FCR6_R_TRIGGER_16 0x40 /* Mask for receive trigger set at 4 */ |
#define UART_FCR6_R_TRIGGER_24 0x80 /* Mask for receive trigger set at 8 */ |
#define UART_FCR6_R_TRIGGER_28 0xC0 /* Mask for receive trigger set at 14 */ |
#define UART_FCR6_T_TRIGGER_16 0x00 /* Mask for transmit trigger set at 16 */ |
#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ |
#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ |
#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ |
|
/* |
* These are the definitions for the Line Control Register |
* |
* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting |
* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits. |
*/ |
#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */ |
#define UART_LCR_SBC 0x40 /* Set break control */ |
#define UART_LCR_SPAR 0x20 /* Stick parity (?) */ |
#define UART_LCR_EPAR 0x10 /* Even parity select */ |
#define UART_LCR_PARITY 0x08 /* Parity Enable */ |
#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */ |
#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */ |
#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */ |
#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */ |
#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */ |
|
/* |
* These are the definitions for the Line Status Register |
*/ |
#define UART_LSR_TEMT 0x40 /* Transmitter empty */ |
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ |
#define UART_LSR_BI 0x10 /* Break interrupt indicator */ |
#define UART_LSR_FE 0x08 /* Frame error indicator */ |
#define UART_LSR_PE 0x04 /* Parity error indicator */ |
#define UART_LSR_OE 0x02 /* Overrun error indicator */ |
#define UART_LSR_DR 0x01 /* Receiver data ready */ |
|
/* |
* These are the definitions for the Interrupt Identification Register |
*/ |
#define UART_IIR_NO_INT 0x01 /* No interrupts pending */ |
#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */ |
|
#define UART_IIR_MSI 0x00 /* Modem status interrupt */ |
#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */ |
#define UART_IIR_TOI 0x0c /* Receive time out interrupt */ |
#define UART_IIR_RDI 0x04 /* Receiver data interrupt */ |
#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */ |
|
/* |
* These are the definitions for the Interrupt Enable Register |
*/ |
#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */ |
#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */ |
#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */ |
#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */ |
|
/* |
* These are the definitions for the Modem Control Register |
*/ |
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ |
#define UART_MCR_OUT2 0x08 /* Out2 complement */ |
#define UART_MCR_OUT1 0x04 /* Out1 complement */ |
#define UART_MCR_RTS 0x02 /* RTS complement */ |
#define UART_MCR_DTR 0x01 /* DTR complement */ |
|
/* |
* These are the definitions for the Modem Status Register |
*/ |
#define UART_MSR_DCD 0x80 /* Data Carrier Detect */ |
#define UART_MSR_RI 0x40 /* Ring Indicator */ |
#define UART_MSR_DSR 0x20 /* Data Set Ready */ |
#define UART_MSR_CTS 0x10 /* Clear to Send */ |
#define UART_MSR_DDCD 0x08 /* Delta DCD */ |
#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */ |
#define UART_MSR_DDSR 0x02 /* Delta DSR */ |
#define UART_MSR_DCTS 0x01 /* Delta CTS */ |
#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */ |
|
/* |
* These are the definitions for the Extended Features Register |
* (StarTech 16C660 only, when DLAB=1) |
*/ |
#define UART_EFR_CTS 0x80 /* CTS flow control */ |
#define UART_EFR_RTS 0x40 /* RTS flow control */ |
#define UART_EFR_SCD 0x20 /* Special character detect */ |
#define UART_EFR_ENI 0x10 /* Enhanced Interrupt */ |
|
#endif /* _UART_H_ */ |
uart.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: reset.S
===================================================================
--- reset.S (nonexistent)
+++ reset.S (revision 1765)
@@ -0,0 +1,24 @@
+#include "board.h"
+#include "mc.h"
+
+ .global ___main
+ .section .stack, "aw", @nobits
+.space STACK_SIZE
+_stack:
+
+ .section .vectors, "ax"
+ .org 0x100
+_reset:
+ l.movhi r1,hi(_stack-4)
+ l.ori r1,r1,lo(_stack-4)
+ l.addi r2,r0,-3
+ l.and r1,r1,r2
+
+ l.movhi r2,hi(_main)
+ l.ori r2,r2,lo(_main)
+ l.jr r2
+ l.addi r2,r0,0
+
+___main:
+ l.jr r9
+ l.nop
reset.S
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart0.rx
===================================================================
--- uart0.rx (nonexistent)
+++ uart0.rx (revision 1765)
@@ -0,0 +1 @@
+abc
uart0.rx
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: hello.c
===================================================================
--- hello.c (nonexistent)
+++ hello.c (revision 1765)
@@ -0,0 +1,81 @@
+#include "board.h"
+#include "uart.h"
+
+#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
+
+#define WAIT_FOR_XMITR \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
+
+#define WAIT_FOR_THRE \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & UART_LSR_THRE) != UART_LSR_THRE)
+
+#define CHECK_FOR_CHAR (REG8(UART_BASE + UART_LSR) & UART_LSR_DR)
+
+#define WAIT_FOR_CHAR \
+ do { \
+ lsr = REG8(UART_BASE + UART_LSR); \
+ } while ((lsr & UART_LSR_DR) != UART_LSR_DR)
+
+void uart_init(void)
+{
+ int divisor;
+
+ /* Reset receiver and transmiter */
+ REG8(UART_BASE + UART_FCR) = UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | UART_FCR_TRIGGER_14;
+
+ /* Disable all interrupts */
+ REG8(UART_BASE + UART_IER) = 0x00;
+
+ /* Set 8 bit char, 1 stop bit, no parity */
+ REG8(UART_BASE + UART_LCR) = UART_LCR_WLEN8 & ~(UART_LCR_STOP | UART_LCR_PARITY);
+
+ /* Set baud rate */
+ divisor = IN_CLK/(16 * UART_BAUD_RATE);
+ REG8(UART_BASE + UART_LCR) |= UART_LCR_DLAB;
+ REG8(UART_BASE + UART_DLL) = divisor & 0x000000ff;
+ REG8(UART_BASE + UART_DLM) = (divisor >> 8) & 0x000000ff;
+ REG8(UART_BASE + UART_LCR) &= ~(UART_LCR_DLAB);
+}
+
+void uart_putc(char c)
+{
+ unsigned char lsr;
+
+ WAIT_FOR_THRE;
+ REG8(UART_BASE + UART_TX) = c;
+ if(c == '\n') {
+ WAIT_FOR_THRE;
+ REG8(UART_BASE + UART_TX) = '\r';
+ }
+ WAIT_FOR_XMITR;
+}
+
+char uart_getc(void)
+{
+ unsigned char lsr;
+ char c;
+
+ WAIT_FOR_CHAR;
+ c = REG8(UART_BASE + UART_RX);
+ return c;
+}
+
+char *str = "Hello world!!!\n";
+int main (void)
+{
+ char *s;
+
+ uart_init ();
+ for (s = str; *s; s++)
+ uart_putc (*s);
+
+ while (1)
+ uart_putc (uart_getc () + 1);
+
+ return 0;
+}
+
hello.c
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: mc.h
===================================================================
--- mc.h (nonexistent)
+++ mc.h (revision 1765)
@@ -0,0 +1,111 @@
+/* mc.h -- Simulation of Memory Controller
+ Copyright (C) 2001 by Marko Mlinar, markom@opencores.org
+
+ This file is part of OpenRISC 1000 Architectural Simulator.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+
+/* Prototypes */
+#ifndef __MC_H
+#define __MC_H
+
+#define N_CE (8)
+
+#define MC_CSR (0x00)
+#define MC_POC (0x04)
+#define MC_BA_MASK (0x08)
+#define MC_CSC(i) (0x10 + (i) * 8)
+#define MC_TMS(i) (0x14 + (i) * 8)
+
+#define MC_ADDR_SPACE (MC_CSC(N_CE))
+
+/* POC register field definition */
+#define MC_POC_EN_BW_OFFSET 0
+#define MC_POC_EN_BW_WIDTH 2
+#define MC_POC_EN_MEMTYPE_OFFSET 2
+#define MC_POC_EN_MEMTYPE_WIDTH 2
+
+/* CSC register field definition */
+#define MC_CSC_EN_OFFSET 0
+#define MC_CSC_MEMTYPE_OFFSET 1
+#define MC_CSC_MEMTYPE_WIDTH 2
+#define MC_CSC_BW_OFFSET 4
+#define MC_CSC_BW_WIDTH 2
+#define MC_CSC_MS_OFFSET 6
+#define MC_CSC_MS_WIDTH 2
+#define MC_CSC_WP_OFFSET 8
+#define MC_CSC_BAS_OFFSET 9
+#define MC_CSC_KRO_OFFSET 10
+#define MC_CSC_PEN_OFFSET 11
+#define MC_CSC_SEL_OFFSET 16
+#define MC_CSC_SEL_WIDTH 8
+
+#define MC_CSC_MEMTYPE_SDRAM 0
+#define MC_CSC_MEMTYPE_SSRAM 1
+#define MC_CSC_MEMTYPE_ASYNC 2
+#define MC_CSC_MEMTYPE_SYNC 3
+
+#define MC_CSR_VALID 0xFF000703LU
+#define MC_POC_VALID 0x0000000FLU
+#define MC_BA_MASK_VALID 0x000000FFLU
+#define MC_CSC_VALID 0x00FF0FFFLU
+#define MC_TMS_SDRAM_VALID 0x0FFF83FFLU
+#define MC_TMS_SSRAM_VALID 0x00000000LU
+#define MC_TMS_ASYNC_VALID 0x03FFFFFFLU
+#define MC_TMS_SYNC_VALID 0x01FFFFFFLU
+#define MC_TMS_VALID 0xFFFFFFFFLU /* reg test compat. */
+
+/* TMS register field definition SDRAM */
+#define MC_TMS_SDRAM_TRFC_OFFSET 24
+#define MC_TMS_SDRAM_TRFC_WIDTH 4
+#define MC_TMS_SDRAM_TRP_OFFSET 20
+#define MC_TMS_SDRAM_TRP_WIDTH 4
+#define MC_TMS_SDRAM_TRCD_OFFSET 17
+#define MC_TMS_SDRAM_TRCD_WIDTH 4
+#define MC_TMS_SDRAM_TWR_OFFSET 15
+#define MC_TMS_SDRAM_TWR_WIDTH 2
+#define MC_TMS_SDRAM_WBL_OFFSET 9
+#define MC_TMS_SDRAM_OM_OFFSET 7
+#define MC_TMS_SDRAM_OM_WIDTH 2
+#define MC_TMS_SDRAM_CL_OFFSET 4
+#define MC_TMS_SDRAM_CL_WIDTH 3
+#define MC_TMS_SDRAM_BT_OFFSET 3
+#define MC_TMS_SDRAM_BL_OFFSET 0
+#define MC_TMS_SDRAM_BL_WIDTH 3
+
+/* TMS register field definition ASYNC */
+#define MC_TMS_ASYNC_TWWD_OFFSET 20
+#define MC_TMS_ASYNC_TWWD_WIDTH 6
+#define MC_TMS_ASYNC_TWD_OFFSET 16
+#define MC_TMS_ASYNC_TWD_WIDTH 4
+#define MC_TMS_ASYNC_TWPW_OFFSET 12
+#define MC_TMS_ASYNC_TWPW_WIDTH 4
+#define MC_TMS_ASYNC_TRDZ_OFFSET 8
+#define MC_TMS_ASYNC_TRDZ_WIDTH 4
+#define MC_TMS_ASYNC_TRDV_OFFSET 0
+#define MC_TMS_ASYNC_TRDV_WIDTH 8
+
+/* TMS register field definition SYNC */
+#define MC_TMS_SYNC_TTO_OFFSET 16
+#define MC_TMS_SYNC_TTO_WIDTH 9
+#define MC_TMS_SYNC_TWR_OFFSET 12
+#define MC_TMS_SYNC_TWR_WIDTH 4
+#define MC_TMS_SYNC_TRDZ_OFFSET 8
+#define MC_TMS_SYNC_TRDZ_WIDTH 4
+#define MC_TMS_SYNC_TRDV_OFFSET 0
+#define MC_TMS_SYNC_TRDV_WIDTH 8
+
+#endif
mc.h
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: uart0.tx
===================================================================
--- uart0.tx (nonexistent)
+++ uart0.tx (revision 1765)
@@ -0,0 +1,5 @@
+Hello world!!!
+
+bcd Hello world!!!
+
+bcd
\ No newline at end of file
Index: sim.cfg
===================================================================
--- sim.cfg (nonexistent)
+++ sim.cfg (revision 1765)
@@ -0,0 +1,567 @@
+/* sim.cfg -- Simulator configuration script file
+ Copyright (C) 2001, Marko Mlinar, markom@opencores.org
+
+This file includes a lot of help about configurations and default one
+
+This file is part of OpenRISC 1000 Architectural Simulator.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
+
+
+/* INTRODUCTION
+
+ The or1ksim have various parameters, which can be set in configuration
+ files. Multiple configurations may be used and switched between at
+ or1ksim startup.
+ By default, or1ksim loads condfiguration file from './sim.cfg' and if not
+ found it checks '~/.or1k/sim.cfg'. If even this file is not found or
+ all parameters are not defined, default configuration is used.
+ Users should not rely on default configuration, but rather redefine all
+ critical settings, since default configuration may differ in newer
+ versions of the or1ksim.
+ If multiple configurations are used, user can switch between them by
+ supplying -f option when starting simulator.
+
+ This file may contain (standard C) only comments - no // support.
+
+ Like normal configuration file, this file is divided in sections,
+ where each section is described in detail also.
+
+ Some section also have subsections. One example of such subsection is
+ block:
+
+ device
+ instance specific parameters...
+ enddevice
+
+ which creates a device instance.
+*/
+
+
+/* MEMORY SECTION
+
+ This section specifies how is initial memory generated and which blocks
+ it consist of.
+
+ type = random/unknown/pattern
+ specifies the initial memory values. 'random' parameter generate
+ random memory using seed 'random_seed' parameter. 'pattern' parameter
+ fills memory with 'pattern' parameter and 'unknown' does not specify
+ how memory should be generated - the fastest option.
+
+ random_seed =
+ random seed for randomizer, used if type = random
+
+ pattern =
+ pattern to fill memory, used if type = pattern
+
+ nmemories =
+ number of memory instances connected
+
+ instance specific:
+ baseaddr =
+ memory start address
+
+ size =
+ memory size
+
+ name = ""
+ memory block name
+
+ ce =
+ chip enable index of the memory instance
+
+ delayr =
+ cycles, required for read access, -1 if instance does not support reading
+
+ delayw =
+ cycles, required for write access, -1 if instance does not support writing
+
+ 16550 = 0/1
+ 0, if this device is uart 16450 and 1, if it is 16550
+
+ log = ""
+ filename, where to log memory accesses to, no log, if log command is not specified
+*/
+
+section memory
+ /*random_seed = 12345
+ type = random*/
+ pattern = 0x00
+ type = unknown /* Fastest */
+
+ nmemories = 3
+ device 0
+ name = "FLASH"
+ ce = 0
+ baseaddr = 0x04000000
+ size = 0x00800000
+ delayr = 10
+ delayw = -1
+/* log = "flash.log"*/
+ enddevice
+
+ device 1
+ name = "RAM"
+ ce = 1
+ baseaddr = 0x00000000
+ size = 0x00400000
+ delayr = 1
+ delayw = 2
+/* log = "ram.log"*/
+ enddevice
+ device 2
+ name = "SRAM"
+ ce = 2
+ baseaddr = 0x08000000
+ size = 0x00400000
+ delayr = 1
+ delayw = 2
+/* log = "ram.log"*/
+ enddevice
+end
+
+/* IMMU SECTION
+
+ This section configures Instruction Memory Menangement Unit
+
+ enabled = 0/1
+ whether IMMU is enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of ITLB sets; must be power of two
+
+ nways =
+ number of ITLB ways
+
+ pagesize =
+ instruction page size; must be power of two
+
+ entrysize =
+ instruction entry size in bytes
+
+ ustates =
+ number of ITLB usage states (2, 3, 4 etc., max is 4)
+*/
+
+section immu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+end
+
+/* DMMU SECTION
+
+ This section configures Data Memory Menangement Unit
+
+ enabled = 0/1
+ whether DMMU is enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DTLB sets; must be power of two
+
+ nways =
+ number of DTLB ways
+
+ pagesize =
+ data page size; must be power of two
+
+ entrysize =
+ data entry size in bytes
+
+ ustates =
+ number of DTLB usage states (2, 3, 4 etc., max is 4)
+*/
+
+section dmmu
+ enabled = 1
+ nsets = 64
+ nways = 1
+ pagesize = 8192
+end
+
+
+/* IC SECTION
+
+ This section configures Instruction Cache
+
+ enabled = 0/1
+ whether IC is enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of IC sets; must be power of two
+
+ nways =
+ number of IC ways
+
+ blocksize =
+ IC block size in bytes; must be power of two
+
+ ustates =
+ number of IC usage states (2, 3, 4 etc., max is 4)
+*/
+
+section ic
+ enabled = 1
+ nsets = 256
+ nways = 1
+ blocksize = 16
+end
+
+/* DC SECTION
+
+ This section configures Data Cache
+
+ enabled = 0/1
+ whether DC is enabled
+ (NOTE: UPR bit is set)
+
+ nsets =
+ number of DC sets; must be power of two
+
+ nways =
+ number of DC ways
+
+ blocksize =
+ DC block size in bytes; must be power of two
+
+ ustates =
+ number of DC usage states (2, 3, 4 etc., max is 4)
+*/
+
+section dc
+ enabled = 1
+ nsets = 256
+ nways = 1
+ blocksize = 16
+end
+
+/* SIM SECTION
+
+ This section specifies how should sim behave.
+
+ verbose = 0/1
+ whether to print out extra messages
+
+ debug = 0-9
+ = 0 disabled debug messages
+ 1-9 level of sim debug information, greater the number more verbose is
+ the output
+
+ profile = 0/1
+ whether to generate profiling file 'sim.profile'
+
+ prof_fn = ""
+ filename, where to generate profiling info, used
+ only if 'profile' is set
+
+ history = 0/1
+ whether instruction execution flow is tracked for
+ display by simulator hist command. Useful for
+ back-trace debugging.
+
+ iprompt = 0/1
+ whether we strart in interactive prompt
+
+ exe_log = 0/1
+ whether execution log should be generated
+
+ exe_log_fn = ""
+ where to put execution log in, used only if 'exe_log'
+ is set
+
+ clkcycle = [ps|ns|us|ms]
+ specifies time measurement for one cycle
+*/
+
+section sim
+ verbose = 0
+ debug = 0
+ profile = 0
+ prof_fn = "sim.profile"
+
+ history = 0
+ /* iprompt = 0 */
+ exe_log = 0
+ exe_log_type = software
+ exe_log_start = 0
+/* exe_log_end = 20000000*/
+ exe_log_marker = 10000
+ exe_log_fn = "executed.log"
+end
+
+
+/* SECTION VAPI
+
+ This section configures Verification API, used for Advanced
+ Core Verification.
+
+ enabled = 0/1
+ whether to start VAPI server
+
+ server_port =
+ TCP/IP port to start VAPI server on
+
+ log_enabled = 0/1
+ whether logging of VAPI requests is enabled
+
+ vapi_fn =
+ specifies filename where to log into, if log_enabled is selected
+*/
+
+section VAPI
+ enabled = 0
+ server_port = 9998
+ log_enabled = 0
+ vapi_log_fn = "vapi.log"
+end
+
+
+/* CPU SECTION
+
+ This section specifies various CPU parameters.
+
+ ver =
+ rev =
+ specifies version and revision of the CPU used
+
+ upr =
+ changes the upr register
+
+ superscalar = 0/1
+ whether CPU is scalar or superscalar
+ (modify cpu/or32/execute.c to tune superscalar model)
+
+ hazards = 0/1
+ whether data hazards are tracked in superscalar CPU
+ and displayed by the simulator r command
+
+ dependstats = 0/1
+ whether inter-instruction dependencies are calculated
+ and displayed by simulator stats command.
+*/
+
+section cpu
+ ver = 0x1200
+ rev = 0x0001
+ /* upr = */
+ superscalar = 0
+ hazards = 0
+ dependstats = 0
+end
+
+
+/* DEBUG SECTION
+
+ This sections specifies how debug unit should behave.
+
+ enabled = 0/1
+ whether debug unit is enabled
+
+ gdb_enabled = 0/1
+ whether to start gdb server at 'server_port' port
+
+ server_port =
+ TCP/IP port to start gdb server on, used only if gdb_enabled
+ is set
+
+section debug
+ enabled = 1
+ gdb_enabled = 0
+ server_port = 9999
+end
+
+
+/* MC SECTION
+
+ This section configures the memory controller
+
+ enabled = 0/1
+ whether memory controller is enabled
+
+ baseaddr =
+ address of first MC register
+
+ POC =
+ Power On Configuration register
+*/
+
+section mc
+ enabled = 0
+ baseaddr = 0x60000000
+ POC = 0x00000008 /* Power on configuration register */
+end
+
+
+/* UART SECTION
+
+ This section configures UARTs
+
+ enabled = 0/1
+ whether uarts are enabled
+
+ nuarts =
+ make specified number of instances, configure each
+ instance within device - enddevice construct.
+
+ instance specific:
+ baseaddr =
+ address of first UART register for this device
+
+ rx_file = ""
+ filename, where to read data from
+
+ tx_file = ""
+ filename, where to write data to
+
+ irq =
+ irq number for this device
+
+ 16550 = 0/1
+ 0, if this device is uart 16450 and 1, if it is 16550
+
+ jitter =
+ in msecs... time to block, -1 to disable it
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section uart
+ nuarts = 1
+
+ device 0
+ baseaddr = 0x90000000
+ irq = 19
+ rxfile = "uart0.rx"
+ txfile = "uart0.tx"
+ jitter = -1 /* async behaviour */
+ 16550 = 1
+ enddevice
+end
+
+
+/* DMA SECTION
+
+ This section configures DMAs
+
+ ndmas =
+ make specified number of instances, configure each
+ instance within device - enddevice construct.
+
+ instance specific:
+ baseaddr =
+ address of first DMA register for this device
+
+ irq =
+ irq number for this device
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+/*
+section dma
+ ndmas = 0
+
+ device 0
+ baseaddr = 0xa0000000
+ irq = 4
+ enddevice
+end
+*/
+
+/* ETHERNET SECTION
+
+ This section configures ethernets
+
+ enabled = 0/1
+ whether ethernets are enabled
+
+ nethernets =
+ make specified number of instances, configure each
+ instance within device - enddevice construct.
+
+ instance specific:
+ baseaddr =
+ address of first ethernet register for this device
+
+ dma =
+ which controller is this ethernet "connected" to
+
+ rx_channel =
+ DMA channel used for RX
+
+ tx_channel =
+ DMA channel used for TX
+
+ rx_file = ""
+ filename, where to read data from
+
+ tx_file = ""
+ filename, where to write data to
+
+ vapi_id =
+ VAPI id of this instance
+*/
+
+section ethernet
+ nethernets = 1
+
+ device 0
+ baseaddr = 0xd0000000
+ dma = 0
+ irq = 15
+ rtx_type = 1
+ tx_channel = 0
+ rx_channel = 1
+ rxfile = "eth0.rx"
+ txfile = "eth0.tx"
+ sockif = "eth0"
+ enddevice
+end
+
+section fb
+ enabled = 1
+ baseaddr = 0xc0000000
+ refresh_rate = 1000000
+ filename = "primary"
+end
+
+/* KBD SECTION
+
+ This section configures PS/2 compatible keyboard
+
+ enabled = 0/1
+ whether keyboard is enabled
+
+ baseaddr =
+ base address of the keyboard device
+
+ rxfile = ""
+ filename, where to read data from
+*/
+
+section kbd
+ enabled = 1
+ irq = 12
+ baseaddr = 0x98000000
+ rxfile = "kbd.rx"
+end
+
sim.cfg
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: README.txt
===================================================================
--- README.txt (nonexistent)
+++ README.txt (revision 1765)
@@ -0,0 +1,112 @@
+ README hello-uart
+
+This directory originates from the hello-uart[1].tar.gz that was attached to the
+openrisc-forum message 2003/06/00075(http://www.opencores.org/forums/openrisc/2003/06/00075)
+The reason why I put it on the openrisc repository is because I'm experiencing troubles
+downloading the attachment. Also because in the past this program was a very
+good starting point for me to start programming the openrisc.
+
+ORIGINAL MESSAGE:
+
+From: "Damjan Lampret"
+Date: Sat, 14 Jun 2003 22:40:58 -0700
+Subject: Re: [openrisc] setting the stall bit using GDB
+
+Michael,
+
+try the following, source files attached (it should run on or1ksim or on
+your board assuming your SoC on the board uses addresses in board.h, change
+board.h as needed):
+
+First build the demo (see attached tgz). If you have all the tools installed
+you can build it using:
+
+
+make clean all
+
+
+File hello.or32 should be built. Now start jp1-xilinx utility:
+
+./jp1-xilinx 9999
+
+
+Instead of 9999, any other port address may be used. Then start GDB with our
+example:
+
+or32-rtems-gdb hello.or32
+
+
+Then load the hello.or32 file onto the board, using gdb:
+
+(gdb) target jtag jtag://localhost:9999
+(gdb) load
+
+
+Now program is loaded and we can start it. Before doing that we must connect
+serial port cable to our board, start serial port program (e.g. minicom) and
+set baud rates (default 9600 8N1 in board.h). OR1k has reset vector located
+at 0x100. We will simulate reset using:
+(gdb) set $pc=0x100
+(gdb) continue
+
+
+
+Hello World!!! should be printed on terminal. Instead of just continue
+command under gdb we can experiment more with next, step, nexti, stepi,
+break and others like print:
+
+(gdb) set $pc = 0x100
+(gdb) break uart_putc
+(gdb) c
+(gdb) next
+(gdb) print c
+
+
+Instead of using command line debugging with gdb we can also use Data
+Display Debugger. Start it with:
+
+ddd --debugger or32-uclinux-gdb hello.or32 &
+
+
+Same commands as above can be entered in console below. After program is
+loaded with:
+
+(gdb) target jtag jtag://localhost:9999
+(gdb) load
+(gdb) set $pc=0x100
+
+
+We can set breakpoint with mouse clicks and step using step/next buttons.
+Program can be run with continue button. We can set watchpoints, observe
+data in Data Display Window or simply by moving mouse over the variable.
+
+
+You can play a bit with hello.c file, e. g. by changing case of entered
+characters.
+
+regards,
+Damjan
+
+----- Original Message -----
+From:
+To:
+Sent: Tuesday, June 10, 2003 2:45 PM
+Subject: [openrisc] setting the stall bit using GDB
+
+
+> Can someone spare a minute to give a pointer for using GDB? My setup
+> includes the OR32 processor running on a Xilinx XCV1000, with some
+> SRAM and a UART attached to it. The Debug unit is compiled into the
+> core, and I am using a linux box as the host for GDB. We are using the
+> XIlinx Parallel-III JTAG cable, and it's attached to the TDI, TDO, TMS,
+> and TCK lines.
+>
+> So my question is, what GDB command do I use to send the stall/un-
+> stall commend to the TAP?
+>
+> Thanks,
+> Michael McAllister
+>
+>
+
+hello-uart[1].tar.gz
Index: Makefile
===================================================================
--- Makefile (nonexistent)
+++ Makefile (revision 1765)
@@ -0,0 +1,46 @@
+ifndef CROSS_COMPILE
+CROSS_COMPILE = or32-uclinux-
+CC = $(CROSS_COMPILE)gcc
+LD = $(CROSS_COMPILE)ld
+NM = $(CROSS_COMPILE)nm
+endif
+
+export CROSS_COMPILE
+
+all: hello.or32
+
+reset.o: reset.S Makefile
+ $(CC) -g -c -o $@ $< $(CFLAGS)
+
+hello.o: hello.c Makefile
+ $(CC) -g -c -o $@ $< $(CFLAGS)
+
+hello.or32: reset.o hello.o Makefile
+ $(LD) -Tram.ld -o $@ reset.o hello.o $(LIBS)
+
+
+System.map: hello.or32
+ @$(NM) $< | \
+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
+ sort > System.map
+
+#########################################################################
+clean:
+ find . -type f \
+ \( -name 'core' -o -name '*.bak' -o -name '*~' \
+ -o -name '*.o' -o -name '*.a' -o -name '*.tmp' \
+ -o -name '*.or32' -o -name '*.bin' -o -name '*.srec' \
+ -o -name '*.mem' -o -name '*.img' -o -name '*.out' \
+ -o -name '*.aux' -o -name '*.log' \) -print \
+ | xargs rm -f
+ rm -f System.map
+
+distclean: clean
+ find . -type f \
+ \( -name .depend -o -name '*.srec' -o -name '*.bin' \
+ -o -name '*.pdf' \) \
+ -print | xargs rm -f
+ rm -f $(OBJS) *.bak tags TAGS
+ rm -fr *.*~
+
+
Makefile
Property changes :
Added: svn:executable
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+*
\ No newline at end of property
Index: board.h
===================================================================
--- board.h (nonexistent)
+++ board.h (revision 1765)
@@ -0,0 +1,36 @@
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#define MC_ENABLED 1
+#define IC_ENABLE 0
+#define IC_SIZE 8192
+#define DC_ENABLE 0
+#define DC_SIZE 8192
+
+#define MC_CSR_VAL 0x0B000300
+#define MC_MASK_VAL 0x000000e0
+#define FLASH_BASE_ADDR 0x04000000
+#define FLASH_SIZE 0x02000000
+#define FLASH_BLOCK_SIZE 0x20000
+#define FLASH_TMS_VAL 0x00102102
+#define SDRAM_BASE_ADDR 0x00000000
+#define SDRAM_TMS_VAL 0x07248230
+
+#define IN_CLK 25000000
+#define TICKS_PER_SEC 100
+#define STACK_SIZE 0x10000
+#define UART_BAUD_RATE 9600 /* 115200 */
+
+#define UART_BASE 0x90000000
+#define UART_IRQ 19
+#define ETH_BASE 0xD0000000
+#define ETH_IRQ 15
+
+#define MC_BASE_ADDR 0x60000000
+
+/* Register access macros */
+#define REG8(add) *((volatile unsigned char *)(add))
+#define REG16(add) *((volatile unsigned short *)(add))
+#define REG32(add) *((volatile unsigned long *)(add))
+
+#endif
board.h
Property changes :
Added: svn:executable
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+*
\ No newline at end of property
Index: ram.ld
===================================================================
--- ram.ld (nonexistent)
+++ ram.ld (revision 1765)
@@ -0,0 +1,39 @@
+MEMORY
+ {
+ vectors : ORIGIN = 0x00000000, LENGTH = 0x00002000
+ ram : ORIGIN = 0x00002000, LENGTH = 0x00200000 - 0x00002000
+ }
+
+SECTIONS
+{
+ .vectors :
+ {
+ *(.vectors)
+ } > vectors
+
+ .text :
+ {
+ *(.text)
+ } > ram
+
+ .data :
+ {
+ *(.data)
+ } > ram
+
+ .rodata :
+ {
+ *(.rodata)
+ } > ram
+
+ .bss :
+ {
+ *(.bss)
+ } > ram
+
+ .stack :
+ {
+ *(.stack)
+ _src_addr = .;
+ } > ram
+}
ram.ld
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property