URL
https://opencores.org/ocsvn/or1k/or1k/trunk
Subversion Repositories or1k
Compare Revisions
- This comparison shows the changes necessary to convert path
/or1k/tags/nog_patch_65/or1ksim/cpu/or1k
- from Rev 1456 to Rev 1765
- ↔ Reverse comparison
Rev 1456 → Rev 1765
/sprs.c
0,0 → 1,221
/* sprs.c -- Simulation of OR1K special-purpose registers |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#include <stdlib.h> |
#include <stdio.h> |
#include <string.h> |
#include <errno.h> |
|
#include "config.h" |
|
#ifdef HAVE_INTTYPES_H |
#include <inttypes.h> |
#endif |
|
#include "port.h" |
#include "arch.h" |
#include "abstract.h" |
#include "sim-config.h" |
#include "except.h" |
#include "opcode/or32.h" |
#include "spr_defs.h" |
#include "execute.h" |
#include "sprs.h" |
#include "dcache_model.h" |
#include "icache_model.h" |
#include "debug.h" |
|
DECLARE_DEBUG_CHANNEL(immu); |
|
extern int flag; |
|
int audio_cnt = 0; |
|
static FILE *fo = 0; |
/* Set a specific SPR with a value. */ |
void |
mtspr(uint16_t regno, const sprword value) |
{ |
sprword prev_val; |
|
regno %= MAX_SPRS; |
prev_val = cpu_state.sprs[regno]; |
cpu_state.sprs[regno] = value; |
|
/* MM: Register hooks. */ |
switch (regno) { |
case SPR_TTCR: |
spr_write_ttcr (value); |
break; |
case SPR_TTMR: |
spr_write_ttmr (value); |
break; |
/* Data cache simulateing stuff */ |
case SPR_DCBPR: |
if(value) { |
dc_simulate_read(value, 4); |
cpu_state.sprs[SPR_DCBPR] = 0; |
} |
break; |
case SPR_DCBFR: |
if(value != -1) { |
dc_inv(value); |
cpu_state.sprs[SPR_DCBFR] = -1; |
} |
break; |
case SPR_DCBIR: |
if(value != 0) { |
dc_inv(value); |
cpu_state.sprs[SPR_DCBIR] = 0; |
} |
break; |
case SPR_DCBWR: |
cpu_state.sprs[SPR_DCBWR] = 0; |
break; |
case SPR_DCBLR: |
cpu_state.sprs[SPR_DCBLR] = 0; |
break; |
/* Instruction cache simulateing stuff */ |
case SPR_ICBPR: |
if(value) { |
ic_simulate_fetch(value); |
cpu_state.sprs[SPR_ICBPR] = 0; |
} |
break; |
case SPR_ICBIR: |
if(value) { |
ic_inv(value); |
cpu_state.sprs[SPR_ICBIR] = 0; |
} |
break; |
case SPR_ICBLR: |
cpu_state.sprs[SPR_ICBLR] = 0; |
break; |
case SPR_SR: |
/* Set internal flag also */ |
if(value & SPR_SR_F) flag = 1; |
else flag = 0; |
cpu_state.sprs[regno] |= SPR_SR_FO; |
#if DYNAMIC_EXECUTION |
if((value & SPR_SR_IME) && !(prev_val & SPR_SR_IME)) { |
TRACE_(immu)("IMMU just became enabled (%lli).\n", runtime.sim.cycles); |
recheck_immu(IMMU_GOT_ENABLED); |
} else if(!(value & SPR_SR_IME) && (prev_val & SPR_SR_IME)) { |
TRACE_(immu)("Remove counting of mmu hit delay with cycles (%lli)\n", |
runtime.sim.cycles); |
recheck_immu(IMMU_GOT_DISABLED); |
} |
#endif |
break; |
case SPR_NPC: |
{ |
/* The debugger has redirected us to a new address */ |
/* This is usually done to reissue an instruction |
which just caused a breakpoint exception. */ |
cpu_state.pc = value; |
|
if(!value && config.sim.verbose) |
PRINTF("WARNING: PC just set to 0!\n"); |
|
/* Clear any pending delay slot jumps also */ |
cpu_state.delay_insn = 0; |
pcnext = value + 4; |
} |
break; |
case 0xFFFD: |
fo = fopen ("audiosim.pcm", "wb+"); |
if (!fo) PRINTF("Cannot open audiosim.pcm\n"); |
PRINTF("Audio opened.\n"); |
break; |
case 0xFFFE: |
if (!fo) PRINTF("audiosim.pcm not opened\n"); |
fputc (value & 0xFF, fo); |
if ((audio_cnt % 1024) == 0) |
PRINTF("%i\n", audio_cnt); |
audio_cnt++; |
break; |
case 0xFFFF: |
fclose(fo); |
PRINTF("Audio closed.\n"); |
runtime.sim.cont_run = 0; |
break; |
case SPR_PMR: |
/* PMR[SDF] and PMR[DCGE] are ignored completely. */ |
if (value & SPR_PMR_SUME) { |
PRINTF ("SUSPEND: PMR[SUME] bit was set.\n"); |
runtime.sim.cont_run = 0; |
} |
break; |
default: |
/* Mask reseved bits in DTLBMR and DTLBMR registers */ |
if ( (regno >= SPR_DTLBMR_BASE(0)) && (regno < SPR_DTLBTR_LAST(3))) { |
if((regno & 0xff) < 0x80) |
cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | |
(value & (SPR_DTLBMR_V | SPR_DTLBMR_PL1 | SPR_DTLBMR_CID | SPR_DTLBMR_LRU)); |
else |
cpu_state.sprs[regno] = ((value / config.dmmu.pagesize) * config.dmmu.pagesize) | |
(value & (SPR_DTLBTR_CC | SPR_DTLBTR_CI | SPR_DTLBTR_WBC | SPR_DTLBTR_WOM | |
SPR_DTLBTR_A | SPR_DTLBTR_D | SPR_DTLBTR_URE | SPR_DTLBTR_UWE | SPR_DTLBTR_SRE | |
SPR_DTLBTR_SWE)); |
} |
|
/* Mask reseved bits in ITLBMR and ITLBMR registers */ |
if ( (regno >= SPR_ITLBMR_BASE(0)) && (regno < SPR_ITLBTR_LAST(3))) { |
TRACE_(immu)("Writting to an mmu way (reg: %"PRIx16", value: %"PRIx32")\n", |
regno, value); |
if((regno & 0xff) < 0x80) |
cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | |
(value & (SPR_ITLBMR_V | SPR_ITLBMR_PL1 | SPR_ITLBMR_CID | SPR_ITLBMR_LRU)); |
else |
cpu_state.sprs[regno] = ((value / config.immu.pagesize) * config.immu.pagesize) | |
(value & (SPR_ITLBTR_CC | SPR_ITLBTR_CI | SPR_ITLBTR_WBC | SPR_ITLBTR_WOM | |
SPR_ITLBTR_A | SPR_ITLBTR_D | SPR_ITLBTR_SXE | SPR_ITLBTR_UXE)); |
|
#if DYNAMIC_EXECUTION |
if(cpu_state.sprs[SPR_SR] & SPR_SR_IME) { |
/* The immu got reconfigured. Recheck if the current page in execution |
* is resident in the immu ways. This check would be done during the |
* instruction fetch but since the dynamic execution model does not do |
* instruction fetchs, do it now. */ |
recheck_immu(0); |
} |
#endif |
} |
|
/* Links to GPRS */ |
if(regno >= 0x0400 && regno < 0x0420) { |
cpu_state.reg[regno - 0x0400] = value; |
} |
break; |
} |
} |
|
/* Show status of important SPRs. */ |
void sprs_status() |
{ |
PRINTF("VR : 0x%.8lx UPR : 0x%.8lx\n", mfspr(SPR_VR), mfspr(SPR_UPR)); |
PRINTF("SR : 0x%.8lx\n", mfspr(SPR_SR)); |
PRINTF("MACLO: 0x%.8lx MACHI: 0x%.8lx\n", mfspr(SPR_MACLO), mfspr(SPR_MACHI)); |
PRINTF("EPCR0: 0x%.8lx EPCR1: 0x%.8lx\n", mfspr(SPR_EPCR_BASE), mfspr(SPR_EPCR_BASE+1)); |
PRINTF("EEAR0: 0x%.8lx EEAR1: 0x%.8lx\n", mfspr(SPR_EEAR_BASE), mfspr(SPR_EEAR_BASE+1)); |
PRINTF("ESR0 : 0x%.8lx ESR1 : 0x%.8lx\n", mfspr(SPR_ESR_BASE), mfspr(SPR_ESR_BASE+1)); |
PRINTF("TTMR : 0x%.8lx TTCR : 0x%.8lx\n", mfspr(SPR_TTMR), mfspr(SPR_TTCR)); |
PRINTF("PICMR: 0x%.8lx PICSR: 0x%.8lx\n", mfspr(SPR_PICMR), mfspr(SPR_PICSR)); |
PRINTF("PPC: 0x%.8lx NPC : 0x%.8lx\n", mfspr(SPR_PPC), mfspr(SPR_NPC)); |
} |
/except.c
0,0 → 1,214
/* except.c -- Simulation of OR1K exceptions |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#include <stdlib.h> |
#include <stdio.h> |
#include <string.h> |
|
#include "config.h" |
|
#ifdef HAVE_INTTYPES_H |
#include <inttypes.h> |
#endif |
|
#include "port.h" |
#include "arch.h" |
#include "abstract.h" |
#include "except.h" |
#include "sim-config.h" |
#include "debug_unit.h" |
#include "opcode/or32.h" |
#include "spr_defs.h" |
#include "execute.h" |
#include "sprs.h" |
|
#if DYNAMIC_EXECUTION |
#include "sched.h" |
#include "rec_i386.h" |
#include "op_support.h" |
#endif |
|
extern oraddr_t pcprev; |
|
int except_pending = 0; |
|
static const char *except_names[] = { |
NULL, |
"Reset", |
"Bus Error", |
"Data Page Fault", |
"Insn Page Fault", |
"Tick timer", |
"Alignment", |
"Illegal instruction", |
"Interrupt", |
"Data TLB Miss", |
"Insn TLB Miss", |
"Range", |
"System Call", |
"Trap" }; |
|
const char *except_name(oraddr_t except) |
{ |
return except_names[except >> 8]; |
} |
|
#if DYNAMIC_EXECUTION |
/* FIXME: Remove the need for this */ |
/* This is needed because immu_translate can be called from do_rfe and do_jump |
* in which case the scheduler does not need to get run. immu_translate can also |
* be called from mtspr in which case the exceptions that it generates happen |
* during an instruction and the scheduler needs to get run. */ |
int immu_ex_from_insn = 0; |
#endif |
|
/* Asserts OR1K exception. */ |
void except_handle(oraddr_t except, oraddr_t ea) |
{ |
oraddr_t except_vector; |
|
if(debug_ignore_exception (except)) |
return; |
|
#if !(DYNAMIC_EXECUTION) |
/* In the dynamic recompiler, this function never returns, so this is not |
* needed. Ofcourse we could set it anyway, but then all code that checks |
* this variable would break, since it is never reset */ |
except_pending = 1; |
#endif |
|
if (config.sim.verbose) |
PRINTF("Exception 0x%"PRIxADDR" (%s) at 0x%"PRIxADDR", EA: 0x%"PRIxADDR |
", ppc: 0x%"PRIxADDR", npc: 0x%"PRIxADDR", dpc: 0x%"PRIxADDR |
", cycles %lld, #%lld\n", |
except, except_name(except), pcprev, ea, cpu_state.pc, pcnext, |
cpu_state.pc_delay, runtime.sim.cycles, runtime.cpu.instructions); |
|
except_vector = except + (testsprbits (SPR_SR, SPR_SR_EPH) ? 0xf0000000 : 0x00000000); |
|
#if !(DYNAMIC_EXECUTION) |
pcnext = except_vector; |
#endif |
|
cpu_state.sprs[SPR_EEAR_BASE] = ea; |
cpu_state.sprs[SPR_ESR_BASE] = cpu_state.sprs[SPR_SR]; |
|
cpu_state.sprs[SPR_SR] &= ~SPR_SR_OVE; /* Disable overflow flag exception. */ |
|
cpu_state.sprs[SPR_SR] |= SPR_SR_SM; /* SUPV mode */ |
cpu_state.sprs[SPR_SR] &= ~(SPR_SR_IEE | SPR_SR_TEE); /* Disable interrupts. */ |
|
/* Address translation is always disabled when starting exception. */ |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_DME; |
|
#if DYNAMIC_EXECUTION |
/* If we were called from do_scheduler and there were more jobs scheduled to |
* run after this, they won't run unless the following call is made since this |
* function never returns. (If we weren't called from do_scheduler, then the |
* job at the head of the queue will still have some time remaining) */ |
if(scheduler.job_queue->time <= 0) |
do_scheduler(); |
#endif |
|
switch(except) { |
/* EPCR is irrelevent */ |
case EXCEPT_RESET: |
break; |
/* EPCR is loaded with address of instruction that caused the exception */ |
case EXCEPT_ITLBMISS: |
case EXCEPT_IPF: |
#if DYNAMIC_EXECUTION |
/* In immu_translate except_handle is called with except_handle(..., virtaddr) */ |
/* Add the immu miss delay to the cycle counter */ |
if(!immu_ex_from_insn) |
mtspr(SPR_EPCR_BASE, get_pc() - (cpu_state.delay_insn ? 4 : 0)); |
else |
/* This exception came from an l.mtspr instruction in which case the pc |
* points to the l.mtspr instruction when in acutal fact, it is the next |
* instruction that would have faulted/missed. ea is used instead of |
* cpu_state.pc + 4 because in the event that the l.mtspr instruction is |
* in the delay slot of a page local jump the fault must happen on the |
* instruction that was jumped to. This is handled in recheck_immu. */ |
mtspr(SPR_EPCR_BASE, ea); |
run_sched_out_of_line(immu_ex_from_insn); |
immu_ex_from_insn = 0; |
break; |
#endif |
/* All these exceptions happen during a simulated instruction */ |
case EXCEPT_BUSERR: |
case EXCEPT_DPF: |
case EXCEPT_ALIGN: |
case EXCEPT_ILLEGAL: |
case EXCEPT_DTLBMISS: |
case EXCEPT_RANGE: |
case EXCEPT_TRAP: |
#if DYNAMIC_EXECUTION |
/* Since these exceptions happen during a simulated instruction and this |
* function jumps out to the exception vector the scheduler would never have |
* a chance to run, therefore run it now */ |
run_sched_out_of_line(1); |
#endif |
mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0)); |
break; |
/* EPCR is loaded with address of next not-yet-executed instruction */ |
case EXCEPT_SYSCALL: |
mtspr(SPR_EPCR_BASE, (cpu_state.pc + 4) - (cpu_state.delay_insn ? 4 : 0)); |
break; |
/* These exceptions happen AFTER (or before) an instruction has been |
* simulated, therefore the pc already points to the *next* instruction */ |
case EXCEPT_TICK: |
case EXCEPT_INT: |
mtspr(SPR_EPCR_BASE, cpu_state.pc - (cpu_state.delay_insn ? 4 : 0)); |
#if !(DYNAMIC_EXECUTION) |
/* If we don't update the pc now, then it will only happen *after* the next |
* instruction (There would be serious problems if the next instruction just |
* happens to be a branch), when it should happen NOW. */ |
cpu_state.pc = pcnext; |
pcnext += 4; |
#else |
/* except_handle() mucks around with the temporaries, which are in the state |
* of the last instruction executed and not the next one, to which the pc |
* now points to */ |
cpu_state.pc -= 4; |
#endif |
break; |
} |
|
/* Address trnaslation is here because run_sched_out_of_line calls |
* eval_insn_direct which checks out the immu for the address translation but |
* if it would be disabled above then there would be not much point... */ |
cpu_state.sprs[SPR_SR] &= ~SPR_SR_IME; |
|
/* Complex/simple execution strictly don't need this because of the |
* next_delay_insn thingy but in the dynamic execution modell that doesn't |
* exist and thus cpu_state.insn_delay would stick in the exception handler |
* causeing grief if the first instruction of the exception handler is also in |
* the delay slot of the previous instruction */ |
cpu_state.delay_insn = 0; |
|
#if DYNAMIC_EXECUTION |
/* Save the registers that are in the temporaries */ |
if(!cpu_state.ts_current) |
upd_reg_from_t(cpu_state.pc); |
|
cpu_state.pc = except_vector; |
cpu_state.ts_current = 0; |
jump_dyn_code(except_vector); |
#endif |
} |
/opcode/or32.h
0,0 → 1,208
/* Table of opcodes for the OpenRISC 1000 ISA. |
Copyright 1990, 1991, 1992, 1993 Free Software Foundation, Inc. |
Contributed by Damjan Lampret (lampret@opencores.org). |
|
This file is part of or1k_gen_isa, or1ksim, GDB and GAS. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ |
|
/* We treat all letters the same in encode/decode routines so |
we need to assign some characteristics to them like signess etc.*/ |
|
#ifndef OR32_H_ISA |
#define OR32_H_ISA |
|
#define NUM_UNSIGNED (0) |
#define NUM_SIGNED (1) |
|
#ifndef PARAMS |
#define PARAMS(x) x |
#endif |
|
#ifndef CONST |
#define CONST const |
#endif |
|
#define MAX_GPRS 32 |
#define PAGE_SIZE 8192 |
#undef __HALF_WORD_INSN__ |
|
#define OPERAND_DELIM (',') |
|
#define OR32_IF_DELAY (1) |
#define OR32_W_FLAG (2) |
#define OR32_R_FLAG (4) |
|
#if defined(HAS_EXECUTION) |
# if SIMPLE_EXECUTION |
# include "simpl32_defs.h" |
# elif DYNAMIC_EXECUTION |
# include "dyn32_defs.h" |
# else |
extern void l_none PARAMS((void)); |
# endif |
#else |
extern void l_none PARAMS((void)); |
#endif |
|
|
struct or32_letter { |
char letter; |
int sign; |
/* int reloc; relocation per letter ??*/ |
}; |
|
enum insn_type { |
it_unknown, |
it_exception, |
it_arith, |
it_shift, |
it_compare, |
it_branch, |
it_jump, |
it_load, |
it_store, |
it_movimm, |
it_move, |
it_extend, |
it_nop, |
it_mac, |
it_float }; |
|
/* Main instruction specification array. */ |
struct or32_opcode { |
/* Name of the instruction. */ |
char *name; |
|
/* A string of characters which describe the operands. |
Valid characters are: |
,() Itself. Characters appears in the assembly code. |
rA Register operand. |
rB Register operand. |
rD Register operand (destination). |
I An immediate operand, range -32768 to 32767. |
J An immediate operand, range . (unused) |
K An immediate operand, range 0 to 65535. |
L An immediate operand, range 0 to 63. |
M An immediate operand, range . (unused) |
N An immediate operand, range -33554432 to 33554431. |
O An immediate operand, range . (unused) */ |
char *args; |
|
/* Opcode and operand encoding. */ |
char *encoding; |
|
#ifdef HAS_EXECUTION |
# if COMPLEX_EXECUTION |
char *function_name; |
# elif SIMPLE_EXECUTION |
void (*exec)(struct iqueue_entry *); |
# else /* DYNAMIC_EXECUTION */ |
void (*exec)(struct op_queue *opq, int param_t[3], orreg_t param[3], int); |
# endif |
#else /* HAS_EXECUTION */ |
void (*exec)(void); |
#endif |
|
unsigned int flags; |
enum insn_type func_unit; |
}; |
|
/* This operand is the last in the list */ |
#define OPTYPE_LAST (0x80000000) |
/* This operand marks the end of the operand sequence (for things like I(rD)) */ |
#define OPTYPE_OP (0x40000000) |
/* The operand specifies a register index */ |
#define OPTYPE_REG (0x20000000) |
/* The operand must be sign extended */ |
#define OPTYPE_SIG (0x10000000) |
/* Operand is a relative address, the `I' in `I(rD)' */ |
#define OPTYPE_DIS (0x08000000) |
/* The operand is a destination */ |
#define OPTYPE_DST (0x04000000) |
/* Which bit of the operand is the sign bit */ |
#define OPTYPE_SBIT (0x00001F00) |
/* Amount to shift the instruction word right to get the operand */ |
#define OPTYPE_SHR (0x0000001F) |
#define OPTYPE_SBIT_SHR (8) |
|
/* MM: Data how to decode operands. */ |
extern struct insn_op_struct { |
unsigned long type; |
unsigned long data; |
} **op_start; |
|
/* Leaf flag used in automata building */ |
#define LEAF_FLAG (0x80000000) |
|
struct temp_insn_struct |
{ |
unsigned long insn; |
unsigned long insn_mask; |
int in_pass; |
}; |
|
extern unsigned long *automata; |
extern struct temp_insn_struct *ti; |
|
extern CONST struct or32_letter or32_letters[]; |
|
extern CONST struct or32_opcode or32_opcodes[]; |
|
extern CONST int num_opcodes; |
|
/* Calculates instruction length in bytes. Always 4 for OR32. */ |
extern int insn_len PARAMS((int insn_index)); |
|
/* Is individual insn's operand signed or unsigned? */ |
extern int letter_signed PARAMS((char l)); |
|
/* Number of letters in the individual lettered operand. */ |
extern int letter_range PARAMS((char l)); |
|
/* MM: Returns index of given instruction name. */ |
extern int insn_index PARAMS((char *insn)); |
|
/* MM: Returns instruction name from index. */ |
extern CONST char *insn_name PARAMS ((int index)); |
|
/* MM: Constructs new FSM, based on or32_opcodes. */ |
extern void build_automata PARAMS ((void)); |
|
/* MM: Destructs FSM. */ |
extern void destruct_automata PARAMS ((void)); |
|
/* MM: Decodes instruction using FSM. Call build_automata first. */ |
extern int insn_decode PARAMS((unsigned int insn)); |
|
/* Disassemble one instruction from insn to disassemble. |
Return the size of the instruction. */ |
int disassemble_insn (unsigned long insn); |
|
/* Disassemble one instruction from insn index. |
Return the size of the instruction. */ |
int disassemble_index (unsigned long insn, int index); |
|
/* FOR INTERNAL USE ONLY */ |
/* Automatically does zero- or sign- extension and also finds correct |
sign bit position if sign extension is correct extension. Which extension |
is proper is figured out from letter description. */ |
unsigned long extend_imm(unsigned long imm, char l); |
|
/* Extracts value from opcode */ |
unsigned long or32_extract(char param_ch, char *enc_initial, unsigned long insn); |
|
#endif |
|
/except.h
0,0 → 1,52
/* except.h -- OR1K architecture specific exceptions |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#ifndef _EXCEPT_H_ |
#define _EXCEPT_H_ |
|
/* Define if you want pure virtual machine simulation (no exceptions etc.) */ |
#define ONLY_VIRTUAL_MACHINE 0 |
|
/* Definition of OR1K exceptions */ |
|
#define EXCEPT_RESET 0x0100 |
#define EXCEPT_BUSERR 0x0200 |
#define EXCEPT_DPF 0x0300 |
#define EXCEPT_IPF 0x0400 |
#define EXCEPT_TICK 0x0500 |
#define EXCEPT_ALIGN 0x0600 |
#define EXCEPT_ILLEGAL 0x0700 |
#define EXCEPT_INT 0x0800 |
#define EXCEPT_DTLBMISS 0x0900 |
#define EXCEPT_ITLBMISS 0x0a00 |
#define EXCEPT_RANGE 0x0b00 |
#define EXCEPT_SYSCALL 0x0c00 |
#define EXCEPT_TRAP 0x0e00 |
|
/* Non maskable exceptions */ |
#define IS_NME(E) ((E) == EXCEPT_RESET) |
|
/* Prototypes */ |
void except_handle(oraddr_t except, oraddr_t ea); |
const char *except_name(oraddr_t except); |
|
/* Has an exception been raised in this cycle ? */ |
extern int except_pending; |
|
#endif |
/sprs.h
0,0 → 1,132
/* sprs.h -- OR1K architecture specific special-purpose registers |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#include "spr_defs.h" |
|
typedef unsigned long sprword; |
|
/* Prototypes */ |
inline void mtspr(uint16_t regno, const sprword value); |
static inline sprword mfspr_(const uint16_t regno); |
extern sprword sprs[MAX_SPRS]; |
#define mfspr(regno) mfspr_(regno) |
|
static inline void setsprbit(const int regno, const int bitnum, const unsigned long bitvalue); |
static inline int getsprbit(const int regno, const int bitnum); |
void sprs_status(); |
|
#include "sim-config.h" |
#include "tick.h" |
|
/* Ugly, but fast */ |
/* Get a specific SPR. */ |
static inline sprword |
mfspr_(const uint16_t regno) |
{ |
extern oraddr_t pcprev; |
|
switch (regno) { |
case SPR_NPC: |
return cpu_state.pc; |
case SPR_PPC: |
return pcprev; |
case SPR_TTCR: |
return spr_read_ttcr(); |
default: |
/* Links to GPRS */ |
if(regno >= 0x0400 && regno < 0x0420) |
return cpu_state.reg[regno - 0x0400]; |
else if (regno < MAX_SPRS) |
return cpu_state.sprs[regno]; |
} |
if (config.sim.verbose) |
PRINTF ("WARNING: read out of SPR range %08X\n", regno); |
return 0; |
} |
|
/* Set specific SPR bit(s) identified by mask. */ |
static inline void |
setsprbits(const int regno, const unsigned long mask, const unsigned long value) |
{ |
sprword regvalue = cpu_state.sprs[regno]; |
sprword shifted = 0x0; |
int m, v = 0; |
|
/* m counts bits in valuemask */ |
/* v counts bits in value */ |
for (m = 0; m < 32; m++) |
if ((mask >> m) & 0x1) { |
shifted |= ((value >> v) & 0x1) << m; |
v++; |
} |
|
/* PRINTF("oldvalue %x setsprbits(%x, %x, %x) shifted %x", regvalue, regno, mask, value, shifted); */ |
cpu_state.sprs[regno] = (regvalue & ~mask) | shifted; |
} |
|
/* Get specific SPR bit(s) identified by mask. */ |
static inline unsigned long |
getsprbits(const int regno, const unsigned long mask) |
{ |
sprword regvalue = cpu_state.sprs[regno]; |
sprword shifted = 0x0; |
int m, v = 0; |
|
/* m counts bits in valuemask */ |
/* v counts bits in regvalue */ |
for (m = 0; m < 32; m++) |
if ((mask >> m) & 0x1) { |
shifted |= ((regvalue >> m) & 0x1) << v; |
v++; |
} |
|
return shifted; |
} |
|
/* Set a specific bit from SPR. LSB in a word is numbered zero. */ |
static inline void |
setsprbit(const int regno, const int bitnum, const unsigned long bitvalue) |
{ |
sprword mask; |
sprword regvalue = cpu_state.sprs[regno]; |
|
mask = ~(1 << bitnum); |
|
cpu_state.sprs[regno] = (regvalue & mask) | ((bitvalue & 0x1) << bitnum); |
|
return; |
} |
|
/* Get a specific bit from SPR. */ |
static inline int |
getsprbit(const int regno, const int bitnum) |
{ |
sprword regvalue = cpu_state.sprs[regno]; |
|
return (regvalue >> bitnum) & 0x1; |
} |
|
/* Get specific SPR bit(s) identified by mask. */ |
static inline unsigned long |
testsprbits(const int regno, const unsigned long mask) |
{ |
sprword regvalue = cpu_state.sprs[regno]; |
return regvalue & mask; |
} |
|
/spr_defs.h
0,0 → 1,486
/* spr_defs.h -- Defines OR1K architecture specific special-purpose registers |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
/* This file is also used by microkernel test bench. Among |
others it is also used in assembly file(s). */ |
|
/* Definition of special-purpose registers (SPRs) */ |
|
#define MAX_GRPS (32) |
#define MAX_SPRS_PER_GRP_BITS (11) |
#define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) |
#define MAX_SPRS (0x10000) |
|
/* Base addresses for the groups */ |
#define SPRGROUP_SYS (0<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DMMU (1<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IMMU (2<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_DC (3<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_IC (4<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_MAC (5<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_D (6<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PC (7<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PM (8<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_PIC (9<< MAX_SPRS_PER_GRP_BITS) |
#define SPRGROUP_TT (10<< MAX_SPRS_PER_GRP_BITS) |
|
/* System control and status group */ |
#define SPR_VR (SPRGROUP_SYS + 0) |
#define SPR_UPR (SPRGROUP_SYS + 1) |
#define SPR_CPUCFGR (SPRGROUP_SYS + 2) |
#define SPR_DMMUCFGR (SPRGROUP_SYS + 3) |
#define SPR_IMMUCFGR (SPRGROUP_SYS + 4) |
#define SPR_DCCFGR (SPRGROUP_SYS + 5) |
#define SPR_ICCFGR (SPRGROUP_SYS + 6) |
#define SPR_DCFGR (SPRGROUP_SYS + 7) |
#define SPR_PCCFGR (SPRGROUP_SYS + 8) |
#define SPR_NPC (SPRGROUP_SYS + 16) /* CZ 21/06/01 */ |
#define SPR_SR (SPRGROUP_SYS + 17) /* CZ 21/06/01 */ |
#define SPR_PPC (SPRGROUP_SYS + 18) /* CZ 21/06/01 */ |
#define SPR_EPCR_BASE (SPRGROUP_SYS + 32) /* CZ 21/06/01 */ |
#define SPR_EPCR_LAST (SPRGROUP_SYS + 47) /* CZ 21/06/01 */ |
#define SPR_EEAR_BASE (SPRGROUP_SYS + 48) |
#define SPR_EEAR_LAST (SPRGROUP_SYS + 63) |
#define SPR_ESR_BASE (SPRGROUP_SYS + 64) |
#define SPR_ESR_LAST (SPRGROUP_SYS + 79) |
|
/* Data MMU group */ |
#define SPR_DMMUCR (SPRGROUP_DMMU + 0) |
#define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) |
#define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) |
#define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) |
#define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) |
|
/* Instruction MMU group */ |
#define SPR_IMMUCR (SPRGROUP_IMMU + 0) |
#define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) |
#define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) |
#define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) |
#define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) |
|
/* Data cache group */ |
#define SPR_DCCR (SPRGROUP_DC + 0) |
#define SPR_DCBPR (SPRGROUP_DC + 1) |
#define SPR_DCBFR (SPRGROUP_DC + 2) |
#define SPR_DCBIR (SPRGROUP_DC + 3) |
#define SPR_DCBWR (SPRGROUP_DC + 4) |
#define SPR_DCBLR (SPRGROUP_DC + 5) |
#define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) |
#define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) |
|
/* Instruction cache group */ |
#define SPR_ICCR (SPRGROUP_IC + 0) |
#define SPR_ICBPR (SPRGROUP_IC + 1) |
#define SPR_ICBIR (SPRGROUP_IC + 2) |
#define SPR_ICBLR (SPRGROUP_IC + 3) |
#define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) |
#define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) |
|
/* MAC group */ |
#define SPR_MACLO (SPRGROUP_MAC + 1) |
#define SPR_MACHI (SPRGROUP_MAC + 2) |
|
/* Debug group */ |
#define SPR_DVR(N) (SPRGROUP_D + (N)) |
#define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) |
#define SPR_DMR1 (SPRGROUP_D + 16) |
#define SPR_DMR2 (SPRGROUP_D + 17) |
#define SPR_DWCR0 (SPRGROUP_D + 18) |
#define SPR_DWCR1 (SPRGROUP_D + 19) |
#define SPR_DSR (SPRGROUP_D + 20) |
#define SPR_DRR (SPRGROUP_D + 21) |
|
/* Performance counters group */ |
#define SPR_PCCR(N) (SPRGROUP_PC + (N)) |
#define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) |
|
/* Power management group */ |
#define SPR_PMR (SPRGROUP_PM + 0) |
|
/* PIC group */ |
#define SPR_PICMR (SPRGROUP_PIC + 0) |
#define SPR_PICPR (SPRGROUP_PIC + 1) |
#define SPR_PICSR (SPRGROUP_PIC + 2) |
|
/* Tick Timer group */ |
#define SPR_TTMR (SPRGROUP_TT + 0) |
#define SPR_TTCR (SPRGROUP_TT + 1) |
|
/* |
* Bit definitions for the Version Register |
* |
*/ |
#define SPR_VR_VER 0xffff0000 /* Processor version */ |
#define SPR_VR_REV 0x0000003f /* Processor revision */ |
|
/* |
* Bit definitions for the Unit Present Register |
* |
*/ |
#define SPR_UPR_UP 0x00000001 /* UPR present */ |
#define SPR_UPR_DCP 0x00000002 /* Data cache present */ |
#define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ |
#define SPR_UPR_DMP 0x00000008 /* Data MMU present */ |
#define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ |
#define SPR_UPR_OB32P 0x00000020 /* ORBIS32 present */ |
#define SPR_UPR_OB64P 0x00000040 /* ORBIS64 present */ |
#define SPR_UPR_OF32P 0x00000080 /* ORFPX32 present */ |
#define SPR_UPR_OF64P 0x00000100 /* ORFPX64 present */ |
#define SPR_UPR_OV32P 0x00000200 /* ORVDX32 present */ |
#define SPR_UPR_OV64P 0x00000400 /* ORVDX64 present */ |
#define SPR_UPR_DUP 0x00000800 /* Debug unit present */ |
#define SPR_UPR_PCUP 0x00001000 /* Performance counters unit present */ |
#define SPR_UPR_PMP 0x00002000 /* Power management present */ |
#define SPR_UPR_PICP 0x00004000 /* PIC present */ |
#define SPR_UPR_TTP 0x00008000 /* Tick timer present */ |
#define SPR_UPR_SRP 0x00010000 /* Shadow registers present */ |
#define SPR_UPR_RES 0x00fe0000 /* ORVDX32 present */ |
#define SPR_UPR_CUST 0xff000000 /* Custom units */ |
|
/* |
* Bit definitions for the Supervision Register |
* |
*/ |
#define SPR_SR_CID 0xf0000000 /* Context ID */ |
#define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ |
#define SPR_SR_FO 0x00008000 /* Fixed one */ |
#define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ |
#define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ |
#define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ |
#define SPR_SR_OV 0x00000800 /* Overflow flag */ |
#define SPR_SR_CY 0x00000400 /* Carry flag */ |
#define SPR_SR_F 0x00000200 /* Condition Flag */ |
#define SPR_SR_CE 0x00000100 /* CID Enable */ |
#define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ |
#define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ |
#define SPR_SR_DME 0x00000020 /* Data MMU Enable */ |
#define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ |
#define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ |
#define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ |
#define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ |
#define SPR_SR_SM 0x00000001 /* Supervisor Mode */ |
|
/* |
* Bit definitions for the Data MMU Control Register |
* |
*/ |
#define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
|
/* |
* Bit definitions for the Instruction MMU Control Register |
* |
*/ |
#define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ |
#define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ |
#define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ |
#define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ |
|
/* |
* Bit definitions for the Data TLB Match Register |
* |
*/ |
#define SPR_DTLBMR_V 0x00000001 /* Valid */ |
#define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_DTLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Data TLB Translate Register |
* |
*/ |
#define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_DTLBTR_A 0x00000010 /* Accessed */ |
#define SPR_DTLBTR_D 0x00000020 /* Dirty */ |
#define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ |
#define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ |
#define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ |
#define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ |
#define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Match Register |
* |
*/ |
#define SPR_ITLBMR_V 0x00000001 /* Valid */ |
#define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ |
#define SPR_ITLBMR_CID 0x0000003c /* Context ID */ |
#define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ |
#define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ |
|
/* |
* Bit definitions for the Instruction TLB Translate Register |
* |
*/ |
#define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ |
#define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ |
#define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ |
#define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ |
#define SPR_ITLBTR_A 0x00000010 /* Accessed */ |
#define SPR_ITLBTR_D 0x00000020 /* Dirty */ |
#define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ |
#define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ |
#define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ |
|
/* |
* Bit definitions for Data Cache Control register |
* |
*/ |
#define SPR_DCCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Insn Cache Control register |
* |
*/ |
#define SPR_ICCR_EW 0x000000ff /* Enable ways */ |
|
/* |
* Bit definitions for Data Cache Configuration Register |
* |
*/ |
|
#define SPR_DCCFGR_NCW 0x00000007 |
#define SPR_DCCFGR_NCS 0x00000078 |
#define SPR_DCCFGR_CBS 0x00000080 |
#define SPR_DCCFGR_CWS 0x00000100 |
#define SPR_DCCFGR_CCRI 0x00000200 |
#define SPR_DCCFGR_CBIRI 0x00000400 |
#define SPR_DCCFGR_CBPRI 0x00000800 |
#define SPR_DCCFGR_CBLRI 0x00001000 |
#define SPR_DCCFGR_CBFRI 0x00002000 |
#define SPR_DCCFGR_CBWBRI 0x00004000 |
|
/* |
* Bit definitions for Instruction Cache Configuration Register |
* |
*/ |
#define SPR_ICCFGR_NCW 0x00000007 |
#define SPR_ICCFGR_NCS 0x00000078 |
#define SPR_ICCFGR_CBS 0x00000080 |
#define SPR_ICCFGR_CCRI 0x00000200 |
#define SPR_ICCFGR_CBIRI 0x00000400 |
#define SPR_ICCFGR_CBPRI 0x00000800 |
#define SPR_ICCFGR_CBLRI 0x00001000 |
|
/* |
* Bit definitions for Data MMU Configuration Register |
* |
*/ |
|
#define SPR_DMMUCFGR_NTW 0x00000003 |
#define SPR_DMMUCFGR_NTS 0x0000001C |
#define SPR_DMMUCFGR_NAE 0x000000E0 |
#define SPR_DMMUCFGR_CRI 0x00000100 |
#define SPR_DMMUCFGR_PRI 0x00000200 |
#define SPR_DMMUCFGR_TEIRI 0x00000400 |
#define SPR_DMMUCFGR_HTR 0x00000800 |
|
/* |
* Bit definitions for Instruction MMU Configuration Register |
* |
*/ |
|
#define SPR_IMMUCFGR_NTW 0x00000003 |
#define SPR_IMMUCFGR_NTS 0x0000001C |
#define SPR_IMMUCFGR_NAE 0x000000E0 |
#define SPR_IMMUCFGR_CRI 0x00000100 |
#define SPR_IMMUCFGR_PRI 0x00000200 |
#define SPR_IMMUCFGR_TEIRI 0x00000400 |
#define SPR_IMMUCFGR_HTR 0x00000800 |
|
/* |
* Bit definitions for Debug Control registers |
* |
*/ |
#define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ |
#define SPR_DCR_CC 0x0000000e /* Compare condition */ |
#define SPR_DCR_SC 0x00000010 /* Signed compare */ |
#define SPR_DCR_CT 0x000000e0 /* Compare to */ |
|
/* Bit results with SPR_DCR_CC mask */ |
#define SPR_DCR_CC_MASKED 0x00000000 |
#define SPR_DCR_CC_EQUAL 0x00000002 |
#define SPR_DCR_CC_LESS 0x00000004 |
#define SPR_DCR_CC_LESSE 0x00000006 |
#define SPR_DCR_CC_GREAT 0x00000008 |
#define SPR_DCR_CC_GREATE 0x0000000a |
#define SPR_DCR_CC_NEQUAL 0x0000000c |
|
/* Bit results with SPR_DCR_CT mask */ |
#define SPR_DCR_CT_DISABLED 0x00000000 |
#define SPR_DCR_CT_IFEA 0x00000020 |
#define SPR_DCR_CT_LEA 0x00000040 |
#define SPR_DCR_CT_SEA 0x00000060 |
#define SPR_DCR_CT_LD 0x00000080 |
#define SPR_DCR_CT_SD 0x000000a0 |
#define SPR_DCR_CT_LSEA 0x000000c0 |
#define SPR_DCR_CT_LSD 0x000000e0 |
/* SPR_DCR_CT_LSD doesn't seem to be implemented anywhere in or1ksim. 2004-1-30 HP */ |
|
/* |
* Bit definitions for Debug Mode 1 register |
* |
*/ |
#define SPR_DMR1_CW0 0x00000003 /* Chain watchpoint 0 */ |
#define SPR_DMR1_CW1 0x0000000c /* Chain watchpoint 1 */ |
#define SPR_DMR1_CW2 0x00000030 /* Chain watchpoint 2 */ |
#define SPR_DMR1_CW3 0x000000c0 /* Chain watchpoint 3 */ |
#define SPR_DMR1_CW4 0x00000300 /* Chain watchpoint 4 */ |
#define SPR_DMR1_CW5 0x00000c00 /* Chain watchpoint 5 */ |
#define SPR_DMR1_CW6 0x00003000 /* Chain watchpoint 6 */ |
#define SPR_DMR1_CW7 0x0000c000 /* Chain watchpoint 7 */ |
#define SPR_DMR1_CW8 0x00030000 /* Chain watchpoint 8 */ |
#define SPR_DMR1_CW9 0x000c0000 /* Chain watchpoint 9 */ |
#define SPR_DMR1_CW10 0x00300000 /* Chain watchpoint 10 */ |
#define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ |
#define SPR_DMR1_BT 0x00800000 /* Branch trace */ |
#define SPR_DMR1_DXFW 0x01000000 /* Disable external force watchpoint */ |
|
/* |
* Bit definitions for Debug Mode 2 register |
* |
*/ |
#define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ |
#define SPR_DMR2_AWTC 0x00001ffc /* Assign watchpoints to counters */ |
#define SPR_DMR2_WGB 0x00ffe000 /* Watchpoints generating breakpoint */ |
|
/* |
* Bit definitions for Debug watchpoint counter registers |
* |
*/ |
#define SPR_DWCR_COUNT 0x0000ffff /* Count */ |
#define SPR_DWCR_MATCH 0xffff0000 /* Match */ |
|
/* |
* Bit definitions for Debug stop register |
* |
*/ |
#define SPR_DSR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DSR_TTE 0x00000010 /* iTick Timer exception */ |
#define SPR_DSR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DSR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DSR_RE 0x00000400 /* Range exception */ |
#define SPR_DSR_SCE 0x00000800 /* System call exception */ |
#define SPR_DSR_SSE 0x00001000 /* Single Step Exception */ |
#define SPR_DSR_TE 0x00002000 /* Trap exception */ |
|
/* |
* Bit definitions for Debug reason register |
* |
*/ |
#define SPR_DRR_RSTE 0x00000001 /* Reset exception */ |
#define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ |
#define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ |
#define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ |
#define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ |
#define SPR_DRR_AE 0x00000020 /* Alignment exception */ |
#define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ |
#define SPR_DRR_IE 0x00000080 /* Interrupt exception */ |
#define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ |
#define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ |
#define SPR_DRR_RE 0x00000400 /* Range exception */ |
#define SPR_DRR_SCE 0x00000800 /* System call exception */ |
#define SPR_DRR_TE 0x00001000 /* Trap exception */ |
|
/* |
* Bit definitions for Performance counters mode registers |
* |
*/ |
#define SPR_PCMR_CP 0x00000001 /* Counter present */ |
#define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ |
#define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ |
#define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ |
#define SPR_PCMR_LA 0x00000010 /* Load access event */ |
#define SPR_PCMR_SA 0x00000020 /* Store access event */ |
#define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ |
#define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ |
#define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ |
#define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ |
#define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ |
#define SPR_PCMR_BS 0x00000800 /* Branch stall event */ |
#define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ |
#define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ |
#define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ |
#define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ |
|
/* |
* Bit definitions for the Power management register |
* |
*/ |
#define SPR_PMR_SDF 0x0000000f /* Slow down factor */ |
#define SPR_PMR_DME 0x00000010 /* Doze mode enable */ |
#define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ |
#define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ |
#define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ |
|
/* |
* Bit definitions for PICMR |
* |
*/ |
#define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ |
|
/* |
* Bit definitions for PICPR |
* |
*/ |
#define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ |
|
/* |
* Bit definitions for PICSR |
* |
*/ |
#define SPR_PICSR_IS 0xffffffff /* Interrupt status */ |
|
/* |
* Bit definitions for Tick Timer Control Register |
* |
*/ |
#define SPR_TTCR_PERIOD 0x0fffffff /* Time Period */ |
#define SPR_TTMR_PERIOD SPR_TTCR_PERIOD |
#define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ |
#define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ |
#define SPR_TTMR_RT 0x40000000 /* Restart tick */ |
#define SPR_TTMR_SR 0x80000000 /* Single run */ |
#define SPR_TTMR_CR 0xc0000000 /* Continuous run */ |
#define SPR_TTMR_M 0xc0000000 /* Tick mode */ |
|
/* |
* l.nop constants |
* |
*/ |
#define NOP_NOP 0x0000 /* Normal nop instruction */ |
#define NOP_EXIT 0x0001 /* End of simulation */ |
#define NOP_REPORT 0x0002 /* Simple report */ |
#define NOP_PRINTF 0x0003 /* Simprintf instruction */ |
#define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ |
#define NOP_REPORT_FIRST 0x0400 /* Report with number */ |
#define NOP_REPORT_LAST 0x03ff /* Report with number */ |
/Makefile.in
0,0 → 1,332
# Makefile.in generated by automake 1.6.3 from Makefile.am. |
# @configure_input@ |
|
# Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 |
# Free Software Foundation, Inc. |
# This Makefile.in is free software; the Free Software Foundation |
# gives unlimited permission to copy and/or distribute it, |
# with or without modifications, as long as this notice is preserved. |
|
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY, to the extent permitted by law; without |
# even the implied warranty of MERCHANTABILITY or FITNESS FOR A |
# PARTICULAR PURPOSE. |
|
@SET_MAKE@ |
|
# Makefile -- Makefile for OR1K architecture dependent simulation |
# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 2 of the License, or |
# (at your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with this program; if not, write to the Free Software |
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
# |
SHELL = @SHELL@ |
|
srcdir = @srcdir@ |
top_srcdir = @top_srcdir@ |
VPATH = @srcdir@ |
prefix = @prefix@ |
exec_prefix = @exec_prefix@ |
|
bindir = @bindir@ |
sbindir = @sbindir@ |
libexecdir = @libexecdir@ |
datadir = @datadir@ |
sysconfdir = @sysconfdir@ |
sharedstatedir = @sharedstatedir@ |
localstatedir = @localstatedir@ |
libdir = @libdir@ |
infodir = @infodir@ |
mandir = @mandir@ |
includedir = @includedir@ |
oldincludedir = /usr/include |
pkgdatadir = $(datadir)/@PACKAGE@ |
pkglibdir = $(libdir)/@PACKAGE@ |
pkgincludedir = $(includedir)/@PACKAGE@ |
top_builddir = ../.. |
|
ACLOCAL = @ACLOCAL@ |
AUTOCONF = @AUTOCONF@ |
AUTOMAKE = @AUTOMAKE@ |
AUTOHEADER = @AUTOHEADER@ |
|
am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd |
INSTALL = @INSTALL@ |
INSTALL_PROGRAM = @INSTALL_PROGRAM@ |
INSTALL_DATA = @INSTALL_DATA@ |
install_sh_DATA = $(install_sh) -c -m 644 |
install_sh_PROGRAM = $(install_sh) -c |
install_sh_SCRIPT = $(install_sh) -c |
INSTALL_SCRIPT = @INSTALL_SCRIPT@ |
INSTALL_HEADER = $(INSTALL_DATA) |
transform = @program_transform_name@ |
NORMAL_INSTALL = : |
PRE_INSTALL = : |
POST_INSTALL = : |
NORMAL_UNINSTALL = : |
PRE_UNINSTALL = : |
POST_UNINSTALL = : |
build_alias = @build_alias@ |
build_triplet = @build@ |
host_alias = @host_alias@ |
host_triplet = @host@ |
target_alias = @target_alias@ |
target_triplet = @target@ |
|
EXEEXT = @EXEEXT@ |
OBJEXT = @OBJEXT@ |
PATH_SEPARATOR = @PATH_SEPARATOR@ |
AMTAR = @AMTAR@ |
AR = @AR@ |
ARFLAGS = @ARFLAGS@ |
AWK = @AWK@ |
BUILD_DIR = @BUILD_DIR@ |
CC = @CC@ |
CFLAGS = @CFLAGS@ |
CPU_ARCH = @CPU_ARCH@ |
DEPDIR = @DEPDIR@ |
INCLUDES = @INCLUDES@ |
INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ |
LOCAL_CFLAGS = @LOCAL_CFLAGS@ |
LOCAL_DEFS = @LOCAL_DEFS@ |
MAKE_SHELL = @MAKE_SHELL@ |
PACKAGE = @PACKAGE@ |
RANLIB = @RANLIB@ |
STRIP = @STRIP@ |
SUMVERSION = @SUMVERSION@ |
TERMCAP_LIB = @TERMCAP_LIB@ |
VERSION = @VERSION@ |
am__include = @am__include@ |
am__quote = @am__quote@ |
host = @host@ |
host_cpu = @host_cpu@ |
host_os = @host_os@ |
install_sh = @install_sh@ |
|
noinst_LIBRARIES = libor1k.a |
libor1k_a_SOURCES = sprs.c except.c |
subdir = cpu/or1k |
mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs |
CONFIG_HEADER = $(top_builddir)/config.h |
CONFIG_CLEAN_FILES = |
LIBRARIES = $(noinst_LIBRARIES) |
|
libor1k_a_AR = $(AR) cru |
libor1k_a_LIBADD = |
am_libor1k_a_OBJECTS = sprs.$(OBJEXT) except.$(OBJEXT) |
libor1k_a_OBJECTS = $(am_libor1k_a_OBJECTS) |
|
DEFS = @DEFS@ |
DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) |
CPPFLAGS = @CPPFLAGS@ |
LDFLAGS = @LDFLAGS@ |
LIBS = @LIBS@ |
depcomp = $(SHELL) $(top_srcdir)/depcomp |
am__depfiles_maybe = depfiles |
@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/except.Po ./$(DEPDIR)/sprs.Po |
COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ |
$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) |
CCLD = $(CC) |
LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ |
DIST_SOURCES = $(libor1k_a_SOURCES) |
DIST_COMMON = Makefile.am Makefile.in |
SOURCES = $(libor1k_a_SOURCES) |
|
all: all-am |
|
.SUFFIXES: |
.SUFFIXES: .c .o .obj |
$(srcdir)/Makefile.in: Makefile.am $(top_srcdir)/configure.in $(ACLOCAL_M4) |
cd $(top_srcdir) && \ |
$(AUTOMAKE) --gnu cpu/or1k/Makefile |
Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status |
cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe) |
|
clean-noinstLIBRARIES: |
-test -z "$(noinst_LIBRARIES)" || rm -f $(noinst_LIBRARIES) |
libor1k.a: $(libor1k_a_OBJECTS) $(libor1k_a_DEPENDENCIES) |
-rm -f libor1k.a |
$(libor1k_a_AR) libor1k.a $(libor1k_a_OBJECTS) $(libor1k_a_LIBADD) |
$(RANLIB) libor1k.a |
|
mostlyclean-compile: |
-rm -f *.$(OBJEXT) core *.core |
|
distclean-compile: |
-rm -f *.tab.c |
|
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/except.Po@am__quote@ |
@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sprs.Po@am__quote@ |
|
distclean-depend: |
-rm -rf ./$(DEPDIR) |
|
.c.o: |
@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ |
$(COMPILE) -c `test -f '$<' || echo '$(srcdir)/'`$< |
|
.c.obj: |
@AMDEP_TRUE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ depfile='$(DEPDIR)/$*.Po' tmpdepfile='$(DEPDIR)/$*.TPo' @AMDEPBACKSLASH@ |
@AMDEP_TRUE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ |
$(COMPILE) -c `cygpath -w $<` |
CCDEPMODE = @CCDEPMODE@ |
uninstall-info-am: |
|
ETAGS = etags |
ETAGSFLAGS = |
|
tags: TAGS |
|
ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) |
list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ |
unique=`for i in $$list; do \ |
if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ |
done | \ |
$(AWK) ' { files[$$0] = 1; } \ |
END { for (i in files) print i; }'`; \ |
mkid -fID $$unique |
|
TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ |
$(TAGS_FILES) $(LISP) |
tags=; \ |
here=`pwd`; \ |
list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ |
unique=`for i in $$list; do \ |
if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ |
done | \ |
$(AWK) ' { files[$$0] = 1; } \ |
END { for (i in files) print i; }'`; \ |
test -z "$(ETAGS_ARGS)$$tags$$unique" \ |
|| $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ |
$$tags $$unique |
|
GTAGS: |
here=`$(am__cd) $(top_builddir) && pwd` \ |
&& cd $(top_srcdir) \ |
&& gtags -i $(GTAGS_ARGS) $$here |
|
distclean-tags: |
-rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH |
DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) |
|
top_distdir = ../.. |
distdir = $(top_distdir)/$(PACKAGE)-$(VERSION) |
|
distdir: $(DISTFILES) |
@list='$(DISTFILES)'; for file in $$list; do \ |
if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ |
dir=`echo "$$file" | sed -e 's,/[^/]*$$,,'`; \ |
if test "$$dir" != "$$file" && test "$$dir" != "."; then \ |
dir="/$$dir"; \ |
$(mkinstalldirs) "$(distdir)$$dir"; \ |
else \ |
dir=''; \ |
fi; \ |
if test -d $$d/$$file; then \ |
if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ |
cp -pR $(srcdir)/$$file $(distdir)$$dir || exit 1; \ |
fi; \ |
cp -pR $$d/$$file $(distdir)$$dir || exit 1; \ |
else \ |
test -f $(distdir)/$$file \ |
|| cp -p $$d/$$file $(distdir)/$$file \ |
|| exit 1; \ |
fi; \ |
done |
check-am: all-am |
check: check-am |
all-am: Makefile $(LIBRARIES) |
|
installdirs: |
|
install: install-am |
install-exec: install-exec-am |
install-data: install-data-am |
uninstall: uninstall-am |
|
install-am: all-am |
@$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am |
|
installcheck: installcheck-am |
install-strip: |
$(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ |
INSTALL_STRIP_FLAG=-s \ |
`test -z '$(STRIP)' || \ |
echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install |
mostlyclean-generic: |
|
clean-generic: |
|
distclean-generic: |
-rm -f Makefile $(CONFIG_CLEAN_FILES) |
|
maintainer-clean-generic: |
@echo "This command is intended for maintainers to use" |
@echo "it deletes files that may require special tools to rebuild." |
clean: clean-am |
|
clean-am: clean-generic clean-noinstLIBRARIES mostlyclean-am |
|
distclean: distclean-am |
|
distclean-am: clean-am distclean-compile distclean-depend \ |
distclean-generic distclean-tags |
|
dvi: dvi-am |
|
dvi-am: |
|
info: info-am |
|
info-am: |
|
install-data-am: |
|
install-exec-am: |
|
install-info: install-info-am |
|
install-man: |
|
installcheck-am: |
|
maintainer-clean: maintainer-clean-am |
|
maintainer-clean-am: distclean-am maintainer-clean-generic |
|
mostlyclean: mostlyclean-am |
|
mostlyclean-am: mostlyclean-compile mostlyclean-generic |
|
uninstall-am: uninstall-info-am |
|
.PHONY: GTAGS all all-am check check-am clean clean-generic \ |
clean-noinstLIBRARIES distclean distclean-compile \ |
distclean-depend distclean-generic distclean-tags distdir dvi \ |
dvi-am info info-am install install-am install-data \ |
install-data-am install-exec install-exec-am install-info \ |
install-info-am install-man install-strip installcheck \ |
installcheck-am installdirs maintainer-clean \ |
maintainer-clean-generic mostlyclean mostlyclean-compile \ |
mostlyclean-generic tags uninstall uninstall-am \ |
uninstall-info-am |
|
# Tell versions [3.59,3.63) of GNU make to not export all variables. |
# Otherwise a system limit (for SysV at least) may be exceeded. |
.NOEXPORT: |
/arch.h
0,0 → 1,61
/* arch.h -- OR1K architecture specific macros |
Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
|
This file is part of OpenRISC 1000 Architectural Simulator. |
|
This program is free software; you can redistribute it and/or modify |
it under the terms of the GNU General Public License as published by |
the Free Software Foundation; either version 2 of the License, or |
(at your option) any later version. |
|
This program is distributed in the hope that it will be useful, |
but WITHOUT ANY WARRANTY; without even the implied warranty of |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
GNU General Public License for more details. |
|
You should have received a copy of the GNU General Public License |
along with this program; if not, write to the Free Software |
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ |
|
#define LINK_REG "r9" |
#define LINK_REGNO (9) |
#define STACK_REG "r1" |
#define STACK_REGNO (1) |
#define FRAME_REG "r2" |
#define FRAME_REGNO (2) |
#define RETURNV_REG "r11" |
#define RETURNV_REGNO (11) |
|
/* Basic types for openrisc */ |
typedef uint32_t oraddr_t; /* Address as addressed by openrisc */ |
typedef uint32_t uorreg_t; /* An unsigned register of openrisc */ |
typedef int32_t orreg_t; /* A signed register of openrisc */ |
|
#define PRIxADDR "08" PRIx32 /* How to print an openrisc address in hex */ |
#define PRIxREG "08" PRIx32 /* How to print an openrisc register in hex */ |
#define PRIdREG "08" PRId32 /* How to print an openrisc register in decimals */ |
|
#define ADDR_C(c) UINT32_C(c) |
#define REG_C(c) UINT32_C(c) |
|
/* Should args be passed on stack for simprintf |
* |
* FIXME: do not enable this since it causes problems |
* in some cases (an example beeing cbasic test |
* from orp testbench). the problems is in |
* |
* or1k/support/simprintf.c |
* |
* #if STACK_ARGS |
* arg = eval_mem32(argaddr,&breakpoint); |
* argaddr += 4; |
* #else |
* sprintf(regstr, "r%u", ++argaddr); |
* arg = evalsim_reg(atoi(regstr)); |
* #endif |
* |
* the access to memory should be without any |
* checks (ie not like or32 application accessed it) |
* |
*/ |
#define STACK_ARGS 0 |
/Makefile.am
0,0 → 1,23
# Makefile -- Makefile for OR1K architecture dependent simulation |
# Copyright (C) 1999 Damjan Lampret, lampret@opencores.org |
# |
# This file is part of OpenRISC 1000 Architectural Simulator. |
# |
# This program is free software; you can redistribute it and/or modify |
# it under the terms of the GNU General Public License as published by |
# the Free Software Foundation; either version 2 of the License, or |
# (at your option) any later version. |
# |
# This program is distributed in the hope that it will be useful, |
# but WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
# GNU General Public License for more details. |
# |
# You should have received a copy of the GNU General Public License |
# along with this program; if not, write to the Free Software |
# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
# |
|
noinst_LIBRARIES = libor1k.a |
libor1k_a_SOURCES = sprs.c except.c |
|
.
Property changes :
Added: svn:ignore
## -0,0 +1,2 ##
+Makefile
+.deps